Semiconductor device with improved matching properties of polysilicon resistor structures

Abstract

Semiconductor device (500a, 500b), comprising: a semiconductor substrate (200) having an active region (202) and a passive region (203) adjacent to the active region (202); a polysilicon resistor structure (250) disposed on an insulating structure (204) in the passive region (203); Dummy polysilicon resistor structures (260) on the insulating structure (204), each arranged outside opposite sides of the polysilicon resistor structure (250); and a polysilicon ring structure (270) disposed on the insulating structure (204) and surrounding the polysilicon resistor structure (250) and the dummy polysilicon resistor structures (260).

Description

BACKGROUND OF THE INVENTIONField of Invention

[0001] The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having improved matching characteristics of polysilicon resistor structures. Description of the state of the art

[0002] Integrated circuits are manufactured to include active devices such as diodes and transistors, and passive devices such as capacitors and resistive inductors. These active and passive devices are formed on a semiconductor substrate such as a silicon wafer and then interconnected in the desired manner.

[0003] Polysilicon resistors are commonly used in semiconductor applications such as digital and analog circuits, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), RC oscillators, RF end drivers, and complementary metal-oxide semiconductor devices. However, there are several steps in the manufacturing processes, such as the photolithography, patterning, and implantation process steps, where the resistance matching of the polysilicon resistors can suffer. US 2009 / 0 179 271 A1 discloses an integrated circuit including a diffusion layer, a first polysilicon layer, and a second polysilicon layer. The first polysilicon layer is located on the diffusion layer and forms a transistor. The second polysilicon comprises a first and a second portion. The first portion of the second polysilicon layer is located on the first polysilicon layer to form a capacitor.The second portion of the second polysilicon layer is located on the diffusion layer to form a resistor.

[0004] Therefore, a novel semiconductor device is desirable to improve the matching characteristics of polysilicon resistors. BRIEF SUMMARY OF THE INVENTION

[0005] One embodiment of the present invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a polysilicon resistor structure, dummy polysilicon resistor structures, and a polysilicon ring structure. The semiconductor substrate includes an active region and a passive region adjacent to the active region. The polysilicon resistor structure is disposed on an insulating structure in the passive region. The dummy polysilicon resistor structures are disposed on the insulating structure, each disposed outside opposite sides of the polysilicon resistor structure. The polysilicon ring structure is disposed on the insulating structure and surrounds the polysilicon resistor structure and the dummy polysilicon resistor structures.

[0006] One embodiment of the present invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a polysilicon resistor structure, dummy polysilicon resistor structures, and a polysilicon ring structure. The semiconductor substrate includes an active region and a passive region surrounded by the active region. The polysilicon resistor structure is disposed on an insulating structure in the passive region and extends in a first direction. The dummy polysilicon resistor structures are disposed along a second direction on the insulating structure and extend in the first direction. The polysilicon ring structure is disposed on the insulating structure and surrounds the polysilicon resistor structure, wherein the dummy polysilicon resistor structures are disposed along the second direction between the polysilicon resistor structure and the polysilicon ring structure.

[0007] Furthermore, an embodiment of the present invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate, dummy polysilicon resistor structures, a polysilicon resistor structure, and a polysilicon ring structure. The semiconductor substrate includes an active region and a passive region. The passive region is disposed adjacent to the active region. The dummy polysilicon resistor structures are disposed on an insulating structure in the passive region. The polysilicon resistor structure is disposed on the insulating structure, being arranged between the dummy polysilicon resistor structures along a width direction of the polysilicon resistor structure.The polysilicon ring structure is arranged on the insulating structure and surrounds the polysilicon resistor structure, wherein the dummy polysilicon resistor structures are arranged along the width direction of the polysilicon resistor structure between the polysilicon ring structure and the polysilicon resistor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention can be better understood by reading the following detailed description and examples with reference to the accompanying drawings, in which: Fig. 1 shows a layout of a semiconductor device according to some embodiments of the disclosure; Fig. 2A shows a cross-sectional view of the semiconductor device according to some embodiments, taken along the line AA' in Fig. 1 is shown; Fig. 2B shows a cross-sectional view of the semiconductor device according to some embodiments taken along line BB' in Fig. 1 is shown; Fig. 3 shows a layout of a semiconductor device according to some embodiments of the disclosure; Fig. 4A shows a cross-sectional view of the semiconductor device according to some embodiments, taken along the line AA' in Fig. 3 is shown; Fig. 4B shows a cross-sectional view of the semiconductor device according to some embodiments taken along line BB' in Fig. 3 is shown; Fig. 5 shows a schematic view illustrating a flow of developer and an exposed photoresist during a development process for patterning polysilicon resistor structures of a semiconductor device according to some embodiments of the disclosure; and Fig. 6 shows a diagram of a matching result comparison between a polysilicon resistor structure of a semiconductor device according to some embodiments of the disclosure and conventional polysilicon resistor structures. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following description is intended to illustrate the general principles according to some embodiments of the disclosure and should not be taken in a limiting sense. The scope according to some embodiments of the disclosure is best determined by reference to the appended claims.

[0010] The inventive concept will now be fully described with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The advantages and features of the inventive concept and methods for achieving the same will become apparent from the following exemplary embodiments, which will be described in more detail with reference to the accompanying drawings. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments and may be implemented in various forms. Accordingly, the exemplary embodiments are provided only to disclose the inventive concept and to enable those skilled in the art to recognize the scope of the inventive concept. Furthermore, the drawings shown are only schematic and non-limiting.In the drawings, the size of some elements may be exaggerated for descriptive purposes and not shown to scale. The dimensions and relative dimensions may not correspond to actual dimensions in practice, according to some embodiments of the disclosure.

[0011] Embodiments provide a semiconductor device having polysilicon resistor structures with improved resistance matching properties, which is achieved by disposing a polysilicon ring structure surrounding the polysilicon resistor structures. During the development process of photoresist structures for forming the polysilicon resistor structures and the polysilicon ring, the photoresist structure for patterning the polysilicon ring structure can block mechanical and chemical attack by the flow of developer, so that the photoresist structure for forming the adjacent polysilicon resistor structures can be developed with substantially identical development conditions. The resulting polysilicon resistor structures can have a similar geometric size and shape, resulting in the predetermined resistance value.Thus, the polysilicon resistor structures can exhibit improved resistance matching.

[0012] Fig. 1 shows a layout of a semiconductor device 500a according to some embodiments of the disclosure. Fig. 2A shows a cross-sectional view of the semiconductor device 500a according to some embodiments, taken along the line AA' in Fig. 1 is shown. Fig. 2B shows a cross-sectional view of the semiconductor device 500a according to some embodiments, taken along the line BB' in Fig. 1. In order to clearly show the arrangements of a protective layer 230a, a polysilicon resistor structure 250, dummy polysilicon resistor structures 260 and a polysilicon ring structure 270 of the semiconductor device 500a, Fig. 1 no salicide layers are shown. The semiconductor device 500a comprises, according to some embodiments, a semiconductor substrate 200, the polysilicon resistor structure 250, the dummy polysilicon resistor structures 260, and the polysilicon ring structure 270, as shown in the Fig. 1, Fig. 2A and Fig. 2B. In some embodiments, semiconductor substrate 200 may include silicon. In alternative embodiments, semiconductor substrate 200 may use SiGe, a bulk semiconductor, a strained semiconductor, a compound semiconductor, a semiconductor-on-insulator (SOI), and other commonly used semiconductor substrates. Semiconductor substrate 200 may have the desired conductivity type by implanting p-type or n-type impurities.

[0013] As in Fig. 1, the semiconductor substrate 200 includes an active region 202 and a passive region 203 adjacent to the active region 202. In some embodiments, the active region 202 may be arranged to surround the passive region 203. In some embodiments, the active region 202 may provide active electronic devices (not shown), such as field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOSs), bipolar transistors, high-voltage transistors, high-frequency transistors, memory cells, other suitable active devices, and / or combinations thereof, arranged therein.

[0014] As in Fig. 1, the active region 202 also provides a guard ring structure 280 disposed therein. The guard ring structure 280 includes a well region 208 and a doped region 222 disposed on the well region 208. The well region 208 and the doped region 222 of the guard ring structure 280 may both be electrically connected to a ground terminal GND (not shown). The well region 208 is formed in the active region 202 with a first conductivity type in some embodiments. The doped region 222 with the first conductivity type is formed on the well region 208 adjacent to a top surface 201 of the semiconductor substrate 200. In some embodiments, a dopant concentration of the doped region 222 is higher than that of the well region 208. Therefore, if the well region 208 functions as the n-well region 202, the doped region 222 would function as a heavily doped (n+-) n-region 222.Alternatively, if the well region 208 functions as the p-well region 202, the doped region 222 would function as the heavily doped (p+-) p-region 222.

[0015] In some embodiments, the semiconductor substrate 200 may have the first conductivity type, which is the same as the conductivity type of the well region 208 and the doped region 222. For example, the semiconductor substrate 200 functions as a p-type semiconductor substrate 200, the well region 208 functions as a p-well (PW) region 208, and the doped region 222 functions as a heavily doped (p+-) p-type region 222.

[0016] In some embodiments, the semiconductor substrate 200 may have a second conductivity type that differs from the conductivity type of the well region 208 and the doped region 222. For example, the semiconductor substrate 200 functions as a p-type semiconductor substrate 200, the well region 208 functions as an n-well (NW) region 208, and the doped region 222 functions as a heavily doped (n+-) n-type region 222.

[0017] In some embodiments, the passive region 203 surrounded by the active region 202 may include passive microelectronic devices disposed therein, such as resistors, capacitors, inductors, other suitable components, and / or combinations thereof. As shown in the Fig. 1, Fig. 2A and Fig. As shown in Figure 2B, the passive region 203 may include an isolation structure 204 disposed therein. Additionally, further isolation structures 204 may be disposed adjacent to the active region 202 (e.g., surrounding the active region 202) to define the active region 202 and electrically isolate it from other active regions (not shown) of the semiconductor substrate 200. In some embodiments, the isolation structure 204 may comprise shallow trench isolation (STI) or local oxidation of silicon (LOCOS).

[0018] As in the Fig. 1, Fig. 2A and Fig. As shown in Figure 2B, the polysilicon resistor structure 250 is arranged on the isolation structure 204 in the passive region 203 of the semiconductor substrate 200. Furthermore, the polysilicon resistor structure 250 is surrounded by the guard ring structure 280. The polysilicon resistor structures 250 may have a line shape, a stripe shape, a rectangular shape, or any other suitable shape and may extend in a first direction 402. Therefore, the first direction 402 may also function as the longitudinal direction of the polysilicon resistor structure 250. Furthermore, the polysilicon resistor structures 250 may be periodically arranged along a second direction 404, which is a different direction than the first direction 402. For example, the second direction 404 may be substantially vertical to the first direction 402. Therefore, the second direction 404 may also function as the width direction of the polysilicon resistor structure 250.The polysilicon resistor structures 250 may be arranged parallel to one another. Furthermore, the adjacent polysilicon resistor structures 250 may be spaced apart by a distance d1. According to the design rules, the distance d1 may be greater than or equal to the minimum distance between adjacent polysilicon layers. In further embodiments, the number of polysilicon resistor structures 250 is not limited. A single polysilicon resistor structure 250 may be arranged on the isolation structure 204.

[0019] As in the Fig. 2A and Fig. 2B, in some embodiments, the polysilicon resistor structure 250 may consist of a single-component structure or a multi-component structure. In some embodiments, the polysilicon resistor structure 250 may include a dielectric layer 210a, a polysilicon layer 212a, and spacers 214a. As shown in the Fig. 2A and Fig. 2B, the dielectric layer 210a is disposed on the isolation structure 204. The dielectric layer 210a may consist of a single layer or multiple layers formed from any suitable dielectric, any suitable high-k dielectric, and / or combinations thereof. The polysilicon layer 212a is disposed over the dielectric layer 210a. In some embodiments, the polysilicon layer 212a may consist of a single layer or multiple layers and may be doped with n-type or p-type impurities. The spacers 214a are disposed on opposite sides of the polysilicon layer 212a and opposite sides of the dielectric layer 210a. In some embodiments, the spacer 214a may include a dielectric such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, other suitable materials, or combinations thereof.In some embodiments, the polysilicon resistor structure 250 may be electrically connected to a power supply terminal (not shown).

[0020] As in the Fig. 1, Fig. 2A and Fig. As shown in Figure 2B, the dummy polysilicon resistor structures 260 are arranged on the isolation structure 204 in the passive region 203 of the semiconductor substrate 200. In some embodiments, the dummy polysilicon resistor structures 260 are each arranged outside of opposite sides 220 of the polysilicon resistor structure 250. Thus, at least one pair of dummy polysilicon resistor structures 260 may be arranged adjacent to the opposite sides 220 of the polysilicon resistor structure 250. Furthermore, the dummy polysilicon resistor structures 260 and the polysilicon resistor structure 250 may have a similar arrangement. For example, the dummy polysilicon resistor structures 260 may be arranged along the second direction 404 on the isolation structure 204 and extend in the first direction 402. The polysilicon resistor structure 250 may be arranged along the width direction of the polysilicon resistor structure 250 (iethe second direction 404) between the dummy polysilicon resistor structures 260. In some embodiments, the dummy polysilicon resistor structures 260 may be adjacent to the opposite sides 220 of the polysilicon resistor structure 250, parallel to the polysilicon resistor structure 250. In some embodiments, the polysilicon resistor structure 250 and the dummy polysilicon resistor structures 260 may have the same shape and size in a plan view, as in FIG. Fig. 1. For example, the dummy polysilicon resistor structures 260 may have a line shape, a stripe shape, a rectangular shape, or any other suitable shape and may extend in the first direction 402. In some embodiments, the dummy polysilicon resistor structure 260 is separated from the adjacent polysilicon resistor structure 250 by a distance d2 along the second direction 404 (i.e., the width direction of the polysilicon resistor structure 250). The distance d2 may be greater than or equal to the distance d1 between the adjacent polysilicon resistor structures 250 in the second direction 404.

[0021] As in the Fig. 2A and Fig. 2B, in some embodiments, the dummy polysilicon resistor structure 260 and the polysilicon resistor structure 250 may have a similar structure and may be formed simultaneously. Furthermore, the dummy polysilicon resistor structure 260 may consist of a single-component structure or a multi-component structure. In some embodiments, the dummy polysilicon resistor structure 260 may include a dielectric layer 210b, a polysilicon layer 212b, and spacers 214b. As shown in FIGS. Fig. 2A and Fig. 2B, the dielectric layer 210b is disposed on the isolation structure 204. The dielectric layer 210b may consist of a single layer or multiple layers formed from any suitable dielectric, any suitable high-k dielectric, and / or combinations thereof. The polysilicon layer 212b is disposed over the dielectric layer 210b. In some embodiments, the polysilicon layer 212b may consist of a single layer or multiple layers. In some embodiments, the polysilicon layer 212b may be doped or undoped with n-type or p-type impurities. The spacers 214b are disposed on opposite sides of the polysilicon layer 212b and opposite sides of the dielectric layer 210b.In some embodiments, the spacer 214b may include a dielectric such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, other suitable materials, or combinations thereof. In some embodiments, the dummy polysilicon resistor structures 260 are floating.

[0022] As in the Fig. 2A and Fig. 2B, in some embodiments, the polysilicon ring structure 270 is disposed on the isolation structure 204 and surrounds the polysilicon resistor structure 250 and a pair of dummy polysilicon resistor structures 260. In some embodiments, the polysilicon ring structure 270 is formed as a continuous ring structure surrounding the polysilicon resistor structure 250 and the dummy polysilicon resistor structures 260, as shown in Fig. 1. In some embodiments, the dummy polysilicon resistor structure 260 is arranged along the second direction 404 (i.e., the width direction of the polysilicon resistor structure 250) between the polysilicon resistor structure 250 and the polysilicon ring structure 270. Furthermore, the dummy polysilicon resistor structures 260 need not be arranged along the first direction 402 (i.e., the length direction of the polysilicon resistor structure 250) between the polysilicon ring structure 270 and the polysilicon resistor structure 250.

[0023] In some embodiments, the polysilicon ring structure 250 is separated from the adjacent dummy polysilicon resistor structure 260 along the second direction 404 (i.e., the width direction of the polysilicon resistor structure 250) by a distance d3. In some embodiments, the distance d3 along the second direction 404 may be greater than or equal to the distance d1 between the adjacent polysilicon resistor structures 250. In some embodiments, the distance d3 along the second direction 404 may be greater than or equal to the distance d2 between the adjacent polysilicon resistor structure 250 and the dummy polysilicon resistor structure 260.

[0024] As in the Fig. 1, Fig. 2A and Fig. 2B, the guard ring structure 280 arranged in the active area 202 may surround the polysilicon resistor structure 250, the dummy polysilicon resistor structures 260, and the polysilicon ring structure 270. In other words, the polysilicon ring structure 270 is arranged between the polysilicon resistor structure 250 and the guard ring structure 280. In some embodiments, the polysilicon ring structure 270 and the guard ring structure 280 have the same shape. For example, in the top view (as shown in Fig. 1) may have a rectangular ring shape or other suitable shape. Therefore, the guard ring structure 280 in the Fig. 1 shown plan view parallel to the polysilicon ring structure 270.

[0025] In some embodiments, the polysilicon ring structure 270, the polysilicon resistor structure 250, and the dummy polysilicon resistor structure 260 may have a similar structure and may be formed simultaneously, as shown in the Fig. 2A and Fig. 2B. Furthermore, the polysilicon ring structure 270 may be comprised of a single-component structure or a multi-component structure. In some embodiments, the polysilicon ring structure 270 may include a dielectric layer 210c, a polysilicon layer 212c, and spacers 214c. As shown in the Fig. 2A and Fig. 2B, the dielectric layer 210c is disposed on the isolation structure 204. The dielectric layer 210c may consist of a single layer or multiple layers formed from any suitable dielectric, any suitable high-k dielectric, and / or combinations thereof. The polysilicon layer 212c is disposed over the dielectric layer 210c. In some embodiments, the polysilicon layer 212c may consist of a single layer or multiple layers. In some embodiments, the polysilicon layer 212c may be doped or undoped with n- or p-type impurities. The spacers 214c are disposed on opposite sides of the polysilicon layer 212c and opposite sides of the dielectric layer 210c.In some embodiments, the spacer 214c may include a dielectric such as silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, other suitable materials, or combinations thereof. The polysilicon ring structure 270 may be formed as shown in FIGS. 1-6, according to some embodiments. Fig. 1, Fig. 2A and Fig. 2B may be electrically connected to a power supply terminal (not shown).

[0026] In some embodiments, the semiconductor device 500a further comprises a protection layer 230a arranged on the polysilicon resistor structure 250 and the dummy polysilicon resistor structures 260, as shown in the Fig. 1, Fig. 2A and Fig. 2B. In this embodiment, the protective layer 230a is formed such that it does not cover the polysilicon ring structure 270. In other words, the polysilicon ring structure 270 is arranged such that it is not covered by the protective layer 230a, so that the polysilicon ring structure 270 is exposed to a subsequent salicide process. As shown in the Fig. 1 and Fig. As shown in Figure 2B, the protection layer 230a may partially cover the polysilicon resistor structure 250 and the dummy polysilicon resistor structures 260 such that end portions (terminals) 250E of the polysilicon resistor structure 250 and end portions 260E of the dummy polysilicon resistor structures 260 are subjected to a subsequent salicide process. In further embodiments, the protection layer 230a may not cover the dummy polysilicon resistor structures 260. In some embodiments, the protection layer 230a may prevent a salicide layer from forming on the polysilicon resistor structure 250. Thus, the polysilicon resistor structure 250 covered by the protection layer 230a thereon may provide increased resistivity. In some embodiments, the protective layer 230a may include any suitable material.The protective layer 230a may comprise a resist protection oxide (RPO), such as an oxide layer, a nitride layer, an oxynitride layer, other suitable layers, and / or combinations thereof.

[0027] In some embodiments, the semiconductor device 500a further comprises salicide layers 218 covering portions of the polysilicon resistor structure 250, the dummy polysilicon resistor structures 260, and the polysilicon ring structure 270 exposed from the protection layer 230a, as shown in FIGS. Fig. 1, Fig. 2A and 2B. Furthermore, the salicide layers 218 may cover the upper surface 201 of the semiconductor substrate 200 in the guard ring structure 280, which is exposed by the protective layer 230a. More specifically, the salicide layers 218 may include salicide layers 218a, 218b, 218c, and 218d. The salicide layers 218a partially cover the polysilicon resistor structure 250, for example, the salicide layers 218a cover the end portions of the polysilicon layer 212a of the polysilicon resistor structure 250, as shown in Fig. 2B. Furthermore, the salicide layers 218b partially cover the dummy polysilicon resistor structures 260, for example, the salicide layers 218b cover the end portions of the polysilicon layers 212b of the dummy polysilicon resistor structures 260, as shown in Fig. 2B. Furthermore, the salicide layer 218c completely covers the polysilicon layers 212c of the polysilicon ring structure 270, as shown in the Fig. 2A and Fig. 2B. Furthermore, the salicide layer 218d covers the upper surface 201 of the semiconductor substrate 200 in the guard ring structure 280, as shown in Fig. 2A and Fig. 2B. In some embodiments, the protective layer 230a covering the central portions of the polysilicon resistor structure 250 and the dummy polysilicon resistor structures 260 is adjacent to the salicide layers 218a and 218b.

[0028] In some embodiments, the semiconductor device 500a further comprises conductive connection structures 224 arranged on the salicide layer 218, as shown in the Fig. 1, Fig. 2A and Fig. 2B. In some embodiments, the conductive interconnect structures 224 include conductive interconnect structures 224a, 224c, and 224d. More specifically, the conductive interconnect structures 224a are disposed on the salicide layers 218a and are electrically connected to the polysilicon resistor structure 250. Further, the conductive interconnect structures 224c are disposed on the salicide layer 218c and are electrically connected to the polysilicon ring structure 270. Furthermore, the conductive interconnect structures 224d are disposed on the salicide layer 218d and are electrically connected to the guard ring structure 280. Thus, the polysilicon resistor structure 250 and the polysilicon ring structure 270 may be electrically connected to the power supply terminals (not shown) through the respective salicide layers 218 and conductive interconnect structures 224.Because the dummy polysilicon resistor structures 260 are floating, no conductive interconnect structures 224 need to be disposed on the dummy polysilicon resistor structures 260. In some embodiments, the conductive interconnect structures 224 include contacts, vias, and metal lines formed over the semiconductor substrate 200. In some embodiments, the semiconductor device 500a is manufactured without forming the conductive interconnect structures 224c on the polysilicon ring structure 270. The polysilicon ring structure 270 may be floating.

[0029] Fig. 3 shows a layout of a semiconductor device 500b according to some embodiments of the disclosure. Fig. 4A shows a cross-sectional view of the semiconductor device 500b according to some embodiments, taken along the line AA' in Fig. 3 is shown. Fig. 4B shows a cross-sectional view of the semiconductor device 500b according to some embodiments, taken along the line BB' in Fig. 3. In order to clearly show the arrangement of a protective layer 230b, the polysilicon resistor structure 250, the dummy polysilicon resistor structures 260 and the polysilicon ring structure 270 of the semiconductor device 500b, Fig. 3 no salicide layers are shown. Elements of the following embodiments that are the same as or similar to those previously described with reference to the Fig. 1, Fig. 2A and Fig. 2B are not repeated for the sake of brevity.

[0030] The difference between the semiconductor device 500a and the semiconductor package 500b is that the semiconductor device 500b includes a protective layer 230b that partially covers the polysilicon resistor structure 250 and the dummy polysilicon resistor structures 260 and completely covers the polysilicon ring structure 270. Therefore, the subsequently formed salicide layers 218 cover the end portions 250E of the polysilicon resistor structure 250 and the end portions 260E of the dummy polysilicon resistor structures 260, but do not cover the polysilicon ring structure 270. Furthermore, the conductive connection structures 224 are not electrically connected to the polysilicon ring structure 270. Since no salicide layers 218 and conductive interconnect structures 224 are formed over the polysilicon ring structure 270, the polysilicon ring structure 270 is floating.In some embodiments, the semiconductor package 500b may provide another design option for the polysilicon ring structure 270.

[0031] In some embodiments, the polysilicon ring structure 270 configured to surround the polysilicon resistor structure 250 of the semiconductor devices 500a and 500b may reduce the occurrence of resistance mismatches of the adjacent polysilicon resistor structures by reducing the variations of the photoresist pattern for forming the polysilicon resistor structure 250. Fig. 5 shows a schematic view illustrating a flow of the developer and an exposed photoresist during a development process for patterning the polysilicon layers of the polysilicon resistor structure 250, the dummy polysilicon resistor structures 260, and the polysilicon ring structure 270 of the semiconductor devices 500a and 500b according to some embodiments of the disclosure. Fig. The development process shown in Figure 5 is used to develop photoresist structures 300a, 300b, and 300c (predetermined size and location of photoresist structures 300a, 300b, and 300c are shown in dashed lines). Photoresist structures 300a, 300b, and 300c may be used as masks for patterning a polysilicon layer 212 and a dielectric layer 210 to form polysilicon layers 212a and dielectric layer 210a of polysilicon resistor structure 250, polysilicon layer 212b and dielectric layer 210b of dummy polysilicon resistor structures 260, and polysilicon layer 212c and dielectric layer 210c of polysilicon ring structure 270.

[0032] During the development process, the photoresist structure 300c used to form the polysilicon layer 212c and the dielectric layer 210c of the polysilicon ring structure 270 surrounding the polysilicon resistor structure 250 is first directly exposed to a developer flow 350 to prevent mechanical and chemical attack by the developer flow 350, wherein the photoresist structures 300a and 300b used to form the polysilicon layers and the dielectric layers of the polysilicon resistor structure 250 and the dummy polysilicon resistor structures 260 surrounded by the polysilicon ring structure 270 are shielded from mechanical forces of the developer flow 350. Thus, the photoresist structure 300c (the right one in Fig. 5) narrower than the photoresist structures 300a and 300b, and the photoresist structures 300a and 300b may have a substantially identical size, as in Fig. 5. Furthermore, variations of the adjacent photoresist structures 300a may be further reduced. After the patterning process and the subsequent manufacturing processes, the adjacent polysilicon resistor structures 250 may have a substantially identical linewidth. The resistance variations of the adjacent polysilicon resistor structures 250 may be further eliminated. Therefore, the polysilicon resistor structures 250 of the semiconductor devices 500a and 500b may have improved resistance matching characteristics.

[0033] Fig. 6 shows a diagram of a matching result comparison between a polysilicon resistor structure 250 according to some embodiments of the disclosure, which is surrounded by the polysilicon ring structure 270 of the semiconductor devices 500a and 500b, and a conventional polysilicon resistor structure not surrounded by the polysilicon ring structure 270. In some embodiments, a polysilicon resistor structure 250 and a conventional polysilicon resistor structure with a width of about 0.5 μm and a length of about 30 μm are selected to measure the resistance variations (sigma (σ)). As shown in Fig.As shown in Figure 6, the polysilicon resistor structures 250 surrounded by the polysilicon ring structure 270 of the semiconductor devices 500a and 500b exhibit lower resistance variations (sigma (σ)) than the conventional polysilicon resistor structures not surrounded by the polysilicon ring structure 270. Compared to conventional polysilicon resistor structures not surrounded by the polysilicon ring structure, the polysilicon resistor structures 250 of the semiconductor devices 500a and 500b have improved resistance matching characteristics.

[0034] Embodiments provide semiconductor devices 500a and 500b. Semiconductor devices 500a and 500b include semiconductor substrate 200, polysilicon resistor structure 250, dummy polysilicon resistor structures 260, and polysilicon ring structure 270. Semiconductor substrate 200 includes an active region 202 and a passive region 203 adjacent to active region 202. Polysilicon resistor structure 250 is disposed on isolation structure 204 in passive region 203. Dummy polysilicon resistor structures 260 are disposed on isolation structure 204, each disposed outside opposite sides 220 of polysilicon resistor structure 250. The polysilicon ring structure 270 is arranged on the isolation structure 204 and surrounds the polysilicon resistor structure 250 and the dummy polysilicon resistor structures 260.In some embodiments, the passive region 203 is surrounded by the active region 202. In some embodiments, the polysilicon resistor structure 250 is arranged to extend in the first direction 402. In some embodiments, the dummy polysilicon resistor structures 260 are arranged along the second direction 404 on the isolation structure 204 and extend in the first direction 402. In some embodiments, the polysilicon resistor structure 250 is arranged between the dummy polysilicon resistor structures 260 along the width direction of the polysilicon resistor structure 250 (i.e., the second direction 404). In some embodiments, the dummy polysilicon resistor structures 260 are arranged along the width direction of the polysilicon resistor structure 250 (i.e., the second direction 404) between the polysilicon ring structure 270 and the polysilicon resistor structure 250.

[0035] Embodiments provide a semiconductor device having a polysilicon ring structure surrounding polysilicon resistor structures, such that the polysilicon resistor structures have improved resistance matching properties. During the development process for patterning the polysilicon layers of the polysilicon resistor structures, the dummy polysilicon resistor structure, and the polysilicon ring structure of the semiconductor device according to some embodiments of the disclosure, the photoresist pattern used to form the polysilicon layer of the polysilicon ring structure surrounding the polysilicon resistor structures is directly exposed to the developer flow to block mechanical and chemical attack by the developer flow, such that the resulting polysilicon resistor structures may have a substantially identical linewidth.Resistance fluctuations between adjacent polysilicon resistor structures can be further eliminated. Thus, the polysilicon resistor structures of semiconductor devices can exhibit improved resistance matching characteristics.

Claims

[1] A semiconductor device (500a, 500b) comprising: a semiconductor substrate (200) having an active region (202) and a passive region (203) adjacent to the active region (202); a polysilicon resistor structure (250) disposed on an insulating structure (204) in the passive region (203); Dummy polysilicon resistor structures (260) on the insulating structure (204), each arranged outside opposite sides of the polysilicon resistor structure (250); and a polysilicon ring structure (270) disposed on the insulating structure (204) and surrounding the polysilicon resistor structure (250) and the dummy polysilicon resistor structures (260). [2] The semiconductor device (500a, 500b) according to claim 1, further comprising: a guard ring structure (280) arranged in the active region (202) and the polysilicon ring structure (270), the polysilicon resistor structure (250) and surrounding the dummy polysilicon resistor structures (260), wherein the polysilicon ring structure (270) and the guard ring structure (280) preferably have the same shape in a plan view. [3] The semiconductor device (500a, 500b) according to any one of the preceding claims, wherein the polysilicon resistor structure (250) and the dummy polysilicon resistor structures (260) have the same shape in a plan view. [4] Semiconductor device (500a, 500b) according to one of the preceding claims, wherein the polysilicon ring structure (270) is floating and / or wherein the polysilicon ring structure (270) is undoped. [5] Semiconductor device (500a, 500b) according to one of the preceding claims, further comprising: a protective layer (230a, 230b) disposed on the polysilicon resistor structure (250) but not covering the polysilicon ring structure (270); and Salicide layers that completely cover the polysilicon ring structure (270) and partially covering the polysilicon resistor structure (250), or further comprising: a protective layer (230a, 230b) covering the polysilicon resistor structure (250) and the polysilicon ring structure (270) is covered; and Salicide layers covering end portions of the polysilicon resistor structure (250) but not covering the polysilicon ring structure (270). [6] A semiconductor device (500a, 500b) comprising: a semiconductor substrate (200) having an active region (202) and a passive region (203) surrounded by the active region (202); a polysilicon resistor structure (250) disposed on an insulating structure (204) in the passive region (203) and extending in a first direction (402); Dummy polysilicon resistor structures (260) arranged along a second direction (404) on the insulating structure (204) and extending in the first direction (402); and a polysilicon ring structure (270) arranged on the insulating structure (204) and surrounding the polysilicon resistor structure (250), wherein the dummy polysilicon resistor structures (260) are arranged along the second direction (404) between the polysilicon resistor structure (250) and the polysilicon ring structure (270). [7] The semiconductor device (500a, 500b) according to claim 6, further comprising: a first salicide layer partially covering the polysilicon resistor structure (250); and a first conductive connection structure arranged on the first salicide layer, the semiconductor device (500a, 500b) preferably further comprising: a protective layer (230a) covering the polysilicon resistor structure (250) and adjacent to the first salicide layer, but not overlapping with the polysilicon ring structure (270), or preferably further comprising: a protective layer (230b) covering the polysilicon resistor structure (250) and the polysilicon ring structure (270), or preferably further comprising a second salicide layer covering the polysilicon ring structure (270); and a second conductive interconnect structure disposed on the second salicide layer. [8] The semiconductor device (500a, 500b) of claim 6 or 7, wherein the dummy polysilicon resistor structures (260) are arranged adjacent to opposite sides of the polysilicon resistor structure (250), wherein the dummy polysilicon resistor structures (260) are floating, and / or wherein the first direction (402) is a longitudinal direction of the polysilicon resistor structure (250) and the second direction (404) is a width direction of the polysilicon resistor structure (250). [9] A semiconductor device (500a, 500b) according to any one of claims 6 to 8, further comprising: a guard ring structure (280) arranged in the active region (202) surrounding the polysilicon ring structure (270) and the polysilicon resistor structure (250), wherein the guard ring structure (280) is preferably parallel to the polysilicon ring structure (270) in a plan view. [10] A semiconductor device (500a, 500b) comprising: a semiconductor substrate (200) having an active region (202) and a passive region (203) adjacent to the active region (202); Dummy polysilicon resistor structures (260) on an insulating structure (204) in the passive region (203); a polysilicon resistor structure (250) arranged on the insulating structure (204) extending along a longitudinal direction (402) and arranged between the dummy polysilicon resistor structures (260) along a width direction (404) of the polysilicon resistor structure (250) perpendicular to the longitudinal direction (402); and a polysilicon ring structure (270) arranged on the insulating structure (204) and surrounding the polysilicon resistor structure (250), wherein the dummy polysilicon resistor structures (260) are arranged along the width direction of the polysilicon resistor structure (250) between the polysilicon ring structure (270) and the polysilicon resistor structure (250). [11] The semiconductor device (500a, 500b) according to claim 10, wherein the dummy polysilicon resistor structures (260) are not arranged between the polysilicon ring structure (270) and the polysilicon resistor structure (250) along the longitudinal direction of the polysilicon resistor structure (250), and / or wherein the dummy polysilicon resistor structures (260) and the polysilicon ring structure (270) are floating. [12] A semiconductor device (500a, 500b) according to claim 10 or 11, further comprising: a protective layer (230a, 230b) covering the polysilicon resistor structure (250) and covering the dummy polysilicon resistor structures (260), wherein the polysilicon ring structure (270) is arranged such that it is not covered by the protective layer (230a, 230b). [13] A semiconductor device (500a, 500b) according to any one of claims 10 to 12, further comprising: Salicide layers that completely cover the polysilicon ring structure (270), partially cover the polysilicon resistor structure (250) and partially cover the dummy polysilicon resistor structures (260), the semiconductor device (500a, 500b) preferably further comprising: a guard ring structure (280) arranged in the active region (202) and surrounding the polysilicon ring structure (270) and the polysilicon resistor structure (250), wherein the salicide layers cover the guard ring structure (280).

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