FLIP-FLOP CIRCUIT, INTEGRATED SEMICONDUCTOR CIRCUIT DEVICE AND VEHICLE

Abstract

Flip-flop circuit (105) comprising: a master latch (ML1E) with a first inverter (INV3) and a first tri-state inverter (TS1') configured such that an input terminal of the first tri-state inverter (TS1') is connected to an output terminal of the first inverter (INV3) and an output terminal of the first tri-state inverter (TS1') is connected to an input terminal of the first inverter (INV3), wherein the first tri-state inverter (TS1') comprises a first NMOS transistor (n5) configured to receive a clock signal into a gate of the first NMOS transistor (n5) and a first PMOS transistor (p6) configured to receive an inverted clock signal, which is an inversion of the clock signal, into the first PMOS transistor (p6);a slave latch (SL1E) with a second inverter (INV4) and a second tri-state inverter (TS2') configured such that an input terminal of the second tri-state inverter (TS2') is connected to an output terminal of the second inverter (INV4) and an output terminal of the second tri-state inverter (TS2') is connected to an input terminal of the second inverter (INV4), wherein the second tri-state inverter (TS2') comprises a second PMOS transistor (p10) configured to receive the clock signal into a gate of the second PMOS transistor (p10) and a second NMOS transistor (n9) configured to receive the inverted clock signal into the second NMOS transistor (n9);and at least a first wiring (L1) configured to connect a source of the first PMOS transistor (p6) and a source of the first NMOS transistor (n5), or a second wiring (L2) configured to connect a source of the second PMOS transistor (p10) and a source of the second NMOS transistor (n9), wherein the first tri-state inverter (TS1') comprises two NMOS transistors (n6, n12) directly connected together and configured to input an output signal of the first inverter (INV3) into the gates of the two NMOS transistors (n6, n12), wherein the flip-flop circuit (105) further comprises a third PMOS transistor (p12) connected in parallel to a PMOS transistor (p4) included in the first inverter (INV3), and configured to connect the output terminal of the The first tri-state inverter (TS1') is connected to a gate of the third PMOS transistor (p12).

Description

CROSS REFERENCE TO RELATED APPLICATIONThis application is based on and claims priority from Japanese Patent Application No. 2021-141436 filed on Aug. 31, 2021, the entire contents of which are incorporated herein by reference.TECHNICAL FIELDThe present disclosure relates to a flip-flop circuit, a semiconductor integrated circuit including the flip-flop circuit, and a vehicle.BACKGROUNDISO26262 has been standardized for the functional safety of electrical / electronic systems in motor vehicles and the requirements for the reliability of semiconductor integrated circuits in vehicles have been increasing.A soft error ("soft error") draws attention because it reduces the reliability of flip-flop circuits in semiconductor integrated circuits. This soft error occurs when radiation passes through or collides with a semiconductor integrated circuit and generates electron-hole pairs, and the holding values of memory elements are temporarily inverted.As a countermeasure against the soft error in the flip-flop circuits, a redundant flip-flop circuit having a configuration in which the flip-flop circuits are tripled and a majority decision circuit is connected to each flip-flop circuit is generally used. In the redundant flip-flop circuit, even if an output inversion occurs due to a soft error in one of the three flip-flop circuits, a correct signal is output by the majority decision of the majority decision circuit when the remaining two hold a correct output value.However, the redundant flip-flop circuit greatly increases the circuit area, the delay time, and the power consumption as compared with a single flip-flop circuit. That is, the redundant flip-flop circuit has a problem that the overhead of circuit area, delay time and power consumption is large.A conventional flip-flop circuit improves soft error resistance by generating output data of the flip-flop circuit by a majority decision based on an output data of one master latch circuit (master latch) and two output data of two slave latch circuits (slave latch). This flip-flop circuit can suppress the overhead of circuit area, delay time, and power consumption, as compared with the redundant flip-flop circuit described above. However, the flip-flop circuit is still capable of improvement in terms of suppressing overhead in terms of circuit area, delay time, and power consumption. In addition, the flip-flop circuit can detect and correct soft errors only in the clock stop state. US 2021 / 0 058 083 A1 relates to a circuit, a method for determining the size of an aspect ratio of transistors of a circuit and a circuit arrangement. JP 2017-41 675 A relates to an input-output circuit and a flip-flop circuit which aims to improve soft error resistance and to suppress the increase in delay time and power consumption.OVERVIEWAccording to an embodiment of the present invention, a flip-flop circuit includes: a master latch including a first inverter and a first tri-state inverter (tri-state inverter) configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor configured such that a clock signal is input to a gate of the first NMOS transistor and a first PMOS transistor configured such that an inverted clock signal that is an inversion of the clock signal is input to the first PMOS transistor; a slave latch having a second inverter and a second tri-state inverter configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, the second tri-state inverter including a second PMOS transistor configured such that the clock signal is input to a gate of the second PMOS transistor and a second NMOS transistor configured such that the inverted clock signal is input to the second NMOS transistor; and at least one first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor, or a second wiring, which is configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor, wherein the first tri-state inverter comprises two NMOS transistors directly connected to each other and configured to input the output signal of the first inverter to the gates of the two NMOS transistors, wherein the flip-flop circuit further comprises a third PMOS transistor connected in parallel to a PMOS transistor included in the first inverter and configured to connect the output terminal of the first tri-state inverter to a gate of the third PMOS transistor. By including the third PMOS transistor, the amount of current flowing into the output point of the master latch may be greater than the amount of current flowing into the output point of the master latch that does not include the third PMOS transistor. As a result, the soft error resistance of the flip-flop circuit including the third PMOS transistor is improved as compared with the flip-flop circuit not including the third PMOS transistor.According to an embodiment of the invention, a semiconductor integrated circuit comprises the flip-flop circuit.According to an embodiment of the present invention, a vehicle includes the semiconductor integrated circuit device.BRIEF DESCRIPTION OF THE DRAWING FIGURESFIG. 1 is a view showing a configuration example of a general flip-flop circuit according to the related art. FIG. 2 is a view showing the configuration of a flip-flop circuit according to a first non-claimed embodiment. FIG. 3A is a view showing the configuration of a flip-flop circuit according to a second non-claimed embodiment. FIG. 3B is a view showing an unclaimed configuration example of a circuit having a structure including a set. FIG. 4 is a view showing the configuration of a flip-flop circuit according to a third embodiment. FIG. 5 is a view showing the configuration of a flip-flop circuit according to a fourth non-claimed embodiment. FIG. 6 is a view showing the configuration of a flip-flop circuit according to a fifth embodiment. FIG. 7 is a view showing the schematic structure of a switching power supply. FIG. 8 is an external view of a vehicle.DETAILED DESCRIPTIONIn the present disclosure, a MOS transistor refers to a transistor whose gate structure is composed of at least three layers, namely, "a layer of a conductor or a semiconductor such as polysilicon having a low resistance value", an "insulating layer", and a "P-type, N-type, or intrinsic semiconductor layer". That is, the gate structure of the MOS transistor is not limited to the three-layered structure of metal, oxide and semiconductor.<Allgemeine Flip-Flop Circuit>Before describing embodiments of the present invention, a general flip-flop circuit will be described. FIG. 1 is a view showing a configuration example of the general flip-flop circuit.The general flip-flop circuit 100 (hereinafter referred to as "flip-flop circuit 100") illustrated in FIG. 1 is a D-type flip-flop circuit. The flip-flop circuit 100 includes inverters INV 0, INV 1, INV 2, and INV 5, transmission gates TG 1 and TG 2, a master latch ML 1, and a slave latch SL 1.The inverters INV 0 and INV 1 are connected in series in two stages to generate a clock signal CLK from an input clock signal CP and an inverted clock signal CLK that is an inversion of the clock signal CLK. The inverter INV 0 includes a PMOS transistor p 0 and an NMOS transistor n 0 connected in series from a power supply potential VC side to a reference potential GND side. The inverter INV 1 includes a PMOS transistor p 1 and an NMOS transistor n 1 connected in series from the power supply potential VC side to the reference potential side. The reference potential is lower than the power supply potential VC.The inverter INV 2 generates an inversion of a data signal D from the data signal D. The inverter INV 2 includes a PMOS transistor p 2 and an NMOS transistor n 2 connected in series from the supply potential VC side to the reference potential GND side.The inversion of the data signal D is supplied to an input terminal of the transmission gate TG1. An output terminal of the transmission gate TG 1 is connected to an input terminal of the master latch ML 1.The transmission gate TG 1 is a circuit that turns on when the clock signal CLK is at a LOW level and turns off when the clock signal CLK is at a HIGH level. The transfer gate TG1 includes a PMOS transistor p3 and an NMOS transistor n3. One of the source and drain of the PMOS transistor p3 is the input terminal of the transfer gate TG1, and the other is the output terminal of the transfer gate TG1. One of the source and drain of the NMOS transistor n3 is the input terminal of the transfer gate TG1, and the other is the output terminal of the transfer gate TG1.Details of the master latch ML 1 will be described later.An output terminal of the master latch ML1 is connected to an input terminal of the transmission gate TG2. An output terminal of the transmission gate TG 2 is connected to an input terminal of the slave latch SL 1.The transmission gate TG 2 is a circuit that turns on when the clock signal CLK is at the HIGH level and turns off when the clock signal CLK is at the LOW level. The transfer gate TG2 includes a PMOS transistor p7 and an NMOS transistor n7. One of the source and drain of the PMOS transistor p7 is the input terminal of the transfer gate TG2, and the other is the output terminal of the transfer gate TG2. One of the source and drain of the NMOS transistor n7 is the input terminal of the transfer gate TG2, and the other is the output terminal of the transfer gate TG2.Details of the slave latch SL 1 will be described later.The inverter INV 5 outputs a signal Q that is an inversion of an output signal of the slave latch SL 1. The inverter INV 5 includes a PMOS transistor p 11 and an NMOS transistor n 11 connected in series from the supply potential VC side to the reference potential GND side.The master latch ML 1 includes an inverter INV 3 and a tri-state inverter TS 1. The master latch ML 1 maintains a signal input to the master latch ML 1.An input terminal of the inverter INV 3 and an output terminal of the tri-state inverter TS 1 are input terminals of the master latch ML 1. An output terminal of the inverter INV 3 and an input terminal of the tri-state inverter TS 1 are output terminals of the master latch ML 1.The inverter INV 3 includes a PMOS transistor p 4 and an NMOS transistor n 4 connected in series from the supply potential VC side to the reference potential GND side.The tri-state inverter TS 1 outputs a signal that is an inversion of an output signal of the inverter INV 3 when the clock signal CLK is at the HIGH level, and is in a high impedance state when the clock signal CLK is at the LOW level. The tri-state inverter TS 1 includes a PMOS transistor p 5, a PMOS transistor p 6, an NMOS transistor n 5, and an NMOS transistor n 6 that are connected in series from the power supply potential VC side to the reference potential GND side. The output signal of the inverter INV3 is applied to each of the gates of the PMOS transistor p5 and the NMOS transistor n6, the inverted clock signal CLK is supplied to a gate of the PMOS transistor p6, and the clock signal CLK is supplied to a gate of the NMOS transistor n5.The slave latch SL 1 includes an inverter INV 4 and a tri-state inverter TS 2. The slave latch SL 1 maintains a signal input to the slave latch SL 1.An input terminal of the inverter INV 4 and an output terminal of the tri-state inverter TS 2 are input terminals of the slave latch SL 1. An output terminal of the inverter INV 4 and an input terminal of the tri-state inverter TS 2 are output terminals of the slave latch SL 1.The inverter INV 4 includes a PMOS transistor p 8 and an NMOS transistor n 8 connected in series from the supply potential VC side to the reference potential GND side.The tri-state inverter TS 2 outputs a signal that is an inversion of an output signal of the inverter INV 4 when the clock signal CLK is at the LOW level, and is in a high impedance state when the clock signal CLK is at the HIGH level. The tri-state inverter TS 2 includes a PMOS transistor p 9, a PMOS transistor p 10, an NMOS transistor n 9, and an NMOS transistor n 10 connected in series from the power supply potential VC side to the reference potential GND side. An output signal of the inverter INV 4 is supplied to each of the gates of the PMOS transistor p 9 and the NMOS transistor n 10, the clock signal CLK is supplied to a gate of the PMOS transistor p 10, and the inverted clock signal CLK is supplied to a gate of the NMOS transistor n 9.< Flop Circuit according to First Embodiment>FIG. 2 is a view showing a configuration example of a flip-flop circuit according to a first embodiment.The flip-flop circuit 101 according to the first embodiment shown in FIG. 2 (hereinafter referred to as "flip-flop circuit 101") is a D-type flip-flop circuit. The flip-flop circuit 101 has a configuration in which the master latch ML 1 in the flip-flop circuit 100 is replaced with a master latch ML 1A, and the slave latch SL 1 in the flip-flop circuit 100 is replaced with a slave latch SL 1A.The master latch ML 1A has a configuration in which a wiring L 1 is added to the tri-state inverter TS 1 in the master latch ML 1. The wiring L 1 is configured to connect a source of the PMOS transistor p 6 and a source of the NMOS transistor n 5. By adding the wiring L1 to the radiation-prone tri-state inverter TS1, the source of the PMOS transistor p6 and the source of the NMOS transistor n5 are connected in parallel such that the amount of current flowing to an output of the tri-state inverter TS1 increases. That is, addition of the wiring L 1 improves the driving force of the tri-state inverter TS 1. By improving the driving force of the tri-state inverter TS 1, susceptibility of the tri-state inverter TS 1 to radiation can be improved and the influence of the radiation on the master latch ML 1A can be suppressed.The slave latch SL 1A has a configuration in which a wiring L 2 is added to the tri-state inverter TS 2 in the slave latch SL 1. The wiring L 2 is configured to connect a source of the PMOS transistor p 10 and a source of the NMOS transistor n 9. By adding the wiring L2 to the radiation-prone tri-state inverter TS2, the source of the PMOS transistor p10 and the source of the NMOS transistor n9 are connected in parallel such that the amount of current flowing to an output of the tri-state inverter TS2 increases. That is, addition of the wiring L 2 improves the driving force of the tri-state inverter TS 2. By improving the driving force of the tri-state inverter TS 2, susceptibility of the tri-state inverter TS 2 to radiation can be improved and the influence of the radiation on the slave latch SL 1A can be suppressed.According to a circuit simulation, it has been confirmed that a critical charge amount Q crit at each of the output points of the tri-state inverters TS 1 and TS 2 of the flip-flop circuit 101 is larger than the critical charge amount Q crit at each of the output points of the tri-state inverters TS 1 and TS 2 of the flip-flop circuit 100. That is, the circuit simulation has confirmed that the addition of the wirings L 1 and L 2 improves the susceptibility of the tri-state inverters TS 1 and TS 2 to radiation.Since the flip-flop circuit 101 has a configuration in which the wirings L 1 and L 2 are added to the flip-flop circuit 100, additional areas, delay times, and power consumptions can be avoided compared with a redundant flip-flop circuit.The flip-flop circuit 101 has a configuration in which both wirings L 1 and L 2 are added to the flip-flop circuit 100, but the flip-flop circuit 101 may also have a configuration in which one of the wirings L 1 and L 2 is added to the flip-flop circuit 100. It is considered that soft error resistance (resistance) can be improved compared with the flip-flop circuit 100 even when one of the wirings L 1 and L 2 is added.< Flop Circuit according to Second Embodiment>FIG. 3A is a view showing a configuration example of a flip-flop circuit according to a second embodiment.The flip-flop circuit 102 according to the second embodiment shown in FIG. 3A (hereinafter referred to as "flip-flop circuit 102") is a D-type flip-flop circuit. The flip-flop circuit 102 has a configuration in which the master latch ML 1 in the flip-flop circuit 100 is replaced with a master latch ML 1B, and the slave latch SL 1 in the flip-flop circuit 100 is replaced with a slave latch SL 1B.The master latch ML 1B has a configuration in which the tri-state inverter TS 1 in the master latch ML 1 is replaced with a tri-state inverter TS 1'. The slave latch SL 1B has a configuration in which the tri-state inverter TS 2 in the slave latch SL 1 is replaced with a tri-state inverter TS 2'.The tri-state inverter TS1' has a configuration in which an NMOS transistor n12 is added to the tri-state inverter TS1. The NMOS transistor n12 is provided between the NMOS transistor n5 and the NMOS transistor n6. An output signal of the inverter INV3 is supplied to a gate of the NMOS transistor n12.The tri-state inverter TS2' has a configuration in which an NMOS transistor n13 is added to the tri-state inverter TS2. The NMOS transistor n13 is provided between the NMOS transistor n9 and the NMOS transistor n10. An output signal of the inverter INV4 is supplied to a gate of the NMOS transistor n13.Alpha radiation tests have shown that a circuit with a structure with set or reset is more resistant to soft error than a circuit with a structure without set and reset. An example of a circuit having a structure with a set or a reset may be a circuit having a structure with a set illustrated in FIG. 3B. The circuit shown in FIG. 3B includes PMOS transistors Q1 to Q3 and NMOS transistors Q4 to Q6. In the circuit shown in FIG. 3B, when an inverted set signal SET which is an inversion of a set signal SET is at a LOW level, the PMOS transistor Q2 is turned on and the NMOS transistor Q5 is turned off.Therefore, the flip-flop circuit 102 uses the series connection of the NMOS transistors included in the circuit having the set or reset structure to improve soft error resistance.By disposing the NMOS transistor n12 between the NMOS transistor n5 and the NMOS transistor n6, an output point of the tri-state inverter TS1' can be prevented from being directly conducted to the reference potential due to the parasitic bipolar effect. Therefore, it is considered that a soft error (soft error) due to the parasitic bipolar effect can be suppressed by disposing the NMOS transistor n12 between the NMOS transistor n5 and the NMOS transistor n6. Moreover, by disposing the NMOS transistor n13 between the NMOS transistor n9 and the NMOS transistor n10, an output point of the tri-state inverter TS2' can be prevented from being directly conducted to the reference potential due to the parasitic bipolar effect. Therefore, it is considered that a soft error (soft error) due to the parasitic bipolar effect can be suppressed by disposing the NMOS transistor n13 between the NMOS transistor n9 and the NMOS transistor n10.Since the flip-flop circuit 102 has a configuration in which the NMOS transistors n 12 and n 13 are added to the flip-flop circuit 100, the cost of circuit area, delay time, and power consumption is suppressed compared to a redundant flip-flop circuit.The flip-flop circuit 102 may have a configuration in which both of the NMOS transistors n 12 and n 13 are added to the flip-flop circuit 100, but the flip-flop circuit 102 may have a configuration in which one of the NMOS transistors n 12 and n 13 is added. It is considered that soft error resistance can be improved compared to the flip-flop circuit 100 even when (only) one of the NMOS transistors n 12 and n 13 is added.< Flop Circuit according to Third Embodiment>FIG. 4 is a view showing a configuration example of a flip-flop circuit according to a third embodiment.The flip-flop circuit 103 according to the third embodiment shown in FIG. 4 (hereinafter referred to as "flip-flop circuit 103") is a D-type flip-flop circuit. The flip-flop circuit 103 has a configuration in which the master latch ML 1B in the flip-flop circuit 102 is replaced with a master latch ML 1C, and the slave latch SL 1B in the flip-flop circuit 102 is replaced with a slave latch SL 1C.The master latch ML 1C has a configuration in which a PMOS transistor p 12 is added to the master latch ML 1B. The slave latch SL 1C has a configuration in which a PMOS transistor p 13 is added to the slave latch SL 1B.The PMOS transistor p 12 is connected in parallel with the PMOS transistor p 4. The gate of the PMOS transistor p12 is connected to the output terminal of the tri-state inverter TS1'. The PMOS transistor p13 is connected in parallel with the PMOS transistor p8. The gate of the PMOS transistor p13 is connected to the output terminal of the tri-state inverter TS2'.By adding the PMOS transistor p 12, the amount of current flowing into a starting point of the master latch ML 1C is larger than the amount of current flowing into a starting point of the master latch ML 1B. By adding the PMOS transistor p 13, the amount of current flowing into a starting point of the slave latch SL 1C is larger than the amount of current flowing into a starting point of the slave latch SL 1B. As a result, soft error resistance of the flip-flop circuit 103 is improved compared to soft error resistance of the flip-flop circuit 102.< Flop Circuit according to Fourth Embodiment>FIG. 5 is a view showing a configuration example of a flip-flop circuit according to a fourth embodiment.The flip-flop circuit 104 according to the fourth embodiment shown in FIG. 5 (hereinafter referred to as "flip-flop circuit 104") is a D-type flip-flop circuit. The flip-flop circuit 104 has a configuration in which the master latch ML 1 in the flip-flop circuit 100 is replaced with a master latch ML 1D, and the slave latch SL 1 in the flip-flop circuit 100 is replaced with a slave latch SL 1D.The master latch ML 1D has a configuration in which the master latch ML 1A of the first embodiment and the master latch of the second embodiment are combined.The slave latch SL 1D has a configuration in which the slave latch SL 1A of the first embodiment and the slave latch of the second embodiment are combined.The flip-flop circuit 104 is designed to further improve soft error (resistance) resistance (soft errors) as compared with the flip-flop circuit 101.< Flop Circuit according to Fifth Embodiment>FIG. 6 is a view showing a configuration example of a flip-flop circuit according to a fifth embodiment.The flip-flop circuit 105 according to the fifth embodiment shown in FIG. 6 (hereinafter referred to as "flip-flop circuit 105") is a D-type flip-flop circuit. The flip-flop circuit 105 has a configuration in which the master latch ML 1 in the flip-flop circuit 100 is replaced with a master latch ML 1E, and the slave latch SL 1 in the flip-flop circuit 100 is replaced with a slave latch SL 1E.The master latch ML 1E has a configuration in which the master latch ML 1A of the first embodiment and the master latch ML 1C of the third embodiment are combined.The slave latch SL 1E has a configuration in which the slave latch SL 1A of the first embodiment and the slave latch of the third embodiment are combined.The flip-flop circuit 105 is designed to further improve soft error resistance (soft errors) as compared to the flip-flop circuit 101.< Device and Vehicle>The flip-flop circuits described above can be used in, for example, a switching power supply device shown in FIG. 7. The switched mode power supply shown in FIG. 7 is a buck DC / DC converter with a ground detection set-time fixing system that steps down an input voltage Vin to produce a desired output voltage Vout.When the switching power supply device 200 shown in FIG. 7 determines that a feedback voltage Vfb falls to a reference voltage Vref, a driver 22 turns on an upper transistor Q 7 such that a switching voltage Vsw is at a high level by a predetermined on-time Ton, based on the output of an on-time setting circuit 23 that sets the predetermined on-time Ton. The driver 22 turns off the upper transistor Q 7 except for the predetermined on-time Ton. Further, the upper transistor Q 7 and a lower transistor Q 8 are complementarily switched by the driver 22.In the switching power supply device 200 shown in FIG. 7, the driver 22 performs a process corresponding to the output of a current sensor, a temperature sensor, or the like to realize an overcurrent protection function, an overheat protection function, or the like.The driver 22 is a power supply control circuit that controls a state of a bottom detection set-time fixing system switching power supply device, and the driver 22 includes the flip-flop circuits described above. A comparator 21 for comparing the feedback voltage Vfb and the reference voltage Vref, the driver 22, and the on-time setting circuit 23 are provided in a semiconductor integrated circuit device 24.The flip-flop circuits described above can also be used for a switching power supply device other than the ground detection on-time fixing system. Further, the flip-flop circuits described above can be used not only for a switching power supply device but also for a motor drive device, for example.Next, an application example of the switching power supply 200 described above will be described. FIG. 8 is an external view showing a configuration example of a vehicle equipped with on-board devices. The vehicle 300 of this configuration example is equipped with in-vehicle devices X 11 to X 17 and a battery (not illustrated) for supplying electric power to these in-vehicle devices X 11 to X 17.The on-board device X 11 is an electronic control device that performs engine-related controls (injection control, electronic throttle control, idle control, oxygen sensor heater control, automatic speed control, etc.).The on-board device X 12 is a lamp control device that controls the turning on and off of HID [High Intensity Discharged Lamp], DRL [Daytime Running Lamp], and so on.The on-board device X 13 is a transmission control device that performs transmission control.The on-board device X 14 is a body control device that controls the movement of the vehicle X (ABS [anti-lock brake system], EPS [electric power steering], electronic suspension control, etc.).The on-board device X 15 is a safety controller that performs control of a door lock, a safety alarm, and so on.The on-board device X 16 is an electronic device that is installed in the vehicle in series or as a special equipment of the manufacturer when the vehicle X is delivered, such as a wiper, an exterior electric mirror, an electric window, an electric sunroof, an electric seat, an air conditioner, etc.The on-board device X 17 is an electronic device mounted on the vehicle X, such as an on-board A / V device [audio / visual], an auto navigation system, an ETC system [electronic toll collection], etc."The switching power supply 200 described above may be incorporated into each of the on-board devices X 11 to X 17.<>In addition to the above-described embodiments, the configuration of the present invention can be modified in various ways without departing from the gist of the present invention. It is to be understood that the embodiments are exemplary and not restrictive in all respects, and the technical scope of the invention is defined by the claims rather than by the description of the embodiments and should be understood to include all changes which come within the meaning and scope of the appended claims.By increasing the gate width of the MOS transistor, the soft error resistance of the flip-flop circuit can be improved. However, if the gate widths of all the MOS transistors are increased, the efficiency of improving soft error resistance with respect to the size of the circuit area is not good.Among the electron-hole pairs generated by radiation passing through or colliding with a semiconductor integrated circuit, many electrons having high mobility are collected in an NMOS transistor. Therefore, a soft error (soft error) is likely to occur when the NMOS transistor is turned off. Therefore, soft fault resistance can be improved by increasing a current flowing when a PMOS transistor paired with the NMOS transistor is turned on, so that electrons accumulated in the NMOS transistor can be removed quickly.Therefore, it is possible to improve soft error resistance efficiently by making the gate width of a PMOS transistor included in a tri-state inverter in a master latch larger than the gate width of an NMOS transistor included in the tri-state inverter in the master latch. Similarly, it is possible to improve soft error resistance efficiently by making the gate width of a PMOS transistor included in a tri-state inverter in a slave latch larger than the gate width of an NMOS transistor included in the tri-state inverter in the slave latch.A flip-flop circuit (101, 104, 105) according to the above-described one aspect has a configuration (first configuration) including: a master latch (ML1A, ML1D, ML1E) including a first inverter (INV3) and a first tri-state inverter (TS1, TS1') configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, the first tri-state inverter including a first NMOS transistor (n5) configured such that a clock signal is input to a gate of the first NMOS transistor, and a first PMOS transistor (p6) configured to input an inverted clock signal, which is an inversion of the clock signal, to the first PMOS transistor; a slave latch (SL1A, SL1D, SL1E) comprising a second inverter (INV4) and a second tri-state inverter (TS2, TS2') configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter comprises a second PMOS transistor (p10) configured such that the clock signal is input to a gate of the second PMOS transistor and a second NMOS transistor (n9) configured such that the inverted clock signal is input to the second NMOS transistor; and at least one of a first wiring (L1) configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor, and a second wiring (L2) configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.The flip-flop circuit having the first configuration can improve soft error resistance while suppressing circuit area overhead, delay time, and power consumption.The flip-flop circuit of the first configuration may have a configuration (second configuration) in which the first tri-state inverter includes two NMOS transistors (n6, n12) directly connected to each other, and is configured so that the output signal of the first inverter is input to the gates of the two NMOS transistors.The flip-flop circuit having the second configuration can further improve soft error resistance (soft error resistances) as compared with the flip-flop circuit having the first configuration.The flip-flop circuit of the second configuration may have a configuration (third configuration) further comprising: a PMOS transistor (p 12) connected in parallel to the PMOS transistor (p 4) included in the first inverter and configured such that the output terminal of the first tri-state inverter is connected to a gate of the connected PMOS transistor.The flip-flop circuit having the third configuration can further improve soft error resistance compared to the flip-flop circuit having the second configuration.The flip-flop circuit of any one of the first to third configurations may have a configuration (fourth configuration) in which the second tri-state inverter includes two NMOS transistors (n10, n13) directly connected to each other, and is configured so that the output signal of the second inverter is input to the gates of the two NMOS transistors.The flip-flop circuit having the fourth configuration can further improve soft error resistance compared to the flip-flop circuit having the first configuration.The flip-flop circuit of the fourth configuration may have a configuration (fifth configuration) further comprising: a PMOS transistor (p 13) connected in parallel to the PMOS transistor (p 8) included in the second inverter, and configured such that the output terminal of the second tri-state inverter is connected to a gate of the PMOS transistor.The flip-flop circuit having the fifth configuration can further improve soft error resistance compared to the flip-flop circuit having the fourth configuration.A flip-flop circuit (102, 103) according to the above-described one aspect has a configuration (sixth configuration) including: a master latch (ML1B, ML1C) including a first inverter (INV3) and a first tri-state inverter (TS1') configured such that an input terminal of the first tri-state inverter is connected to an output terminal of the first inverter and an output terminal of the first tri-state inverter is connected to an input terminal of the first inverter, wherein the first tri-state inverter includes a first NMOS transistor (n5) configured such that a clock signal is input to a gate of the first NMOS transistor and a first PMOS transistor (p6), which is configured such that an inverted clock signal which is an inversion of the clock signal is input to the first PMOS transistor; and a slave latch (SL1B, SL1C) which comprises a second inverter (INV4) and a second tri-state inverter (TS2') which are configured such that an input terminal of the second tri-state inverter is connected to an output terminal of the second inverter and an output terminal of the second tri-state inverter is connected to an input terminal of the second inverter, wherein the second tri-state inverter comprises a second PMOS transistor (p10) which is configured such that the clock signal is input to a gate of the second PMOS transistor, and a second NMOS transistor (n9) configured to input the inverted clock signal to the second NMOS transistor, wherein the first tri-state inverter comprises two NMOS transistors (n6, n12) directly connected to each other and configured to input the output signal of the first inverter to the gates of the two NMOS transistors.The flip-flop circuit having the sixth configuration can improve soft error resistance while suppressing circuit area overhead, delay time, and power consumption.A semiconductor integrated circuit device ( 24) has a configuration (seventh configuration) including a flip-flop circuit of any one of the first to sixth configurations.The semiconductor integrated circuit having the seventh configuration can improve the soft fault resistance of the flip-flop circuit while suppressing the additional cost of circuit area, delay time, and power consumption of the flip-flop circuit.A vehicle ( 300) has a configuration (eighth configuration) including a semiconductor integrated circuit device of the seventh configuration.The vehicle having the eighth configuration can improve soft error resistance of the flip-flop circuit while suppressing overhead of circuit area, delay time, and power consumption of the flip-flop circuit.With the flip-flop circuit, the semiconductor integrated circuit, and the vehicle disclosed in the present invention, it is possible to improve soft fault resistance and, at the same time, to suppress the increased circuit area cost, delay time, and power consumption cost.Although certain embodiments have been described, these embodiments have been presented as examples and are not intended to limit the scope of the inventions. Indeed, the embodiments described herein may be embodied in a variety of other forms. Moreover, various omissions, substitutions, and changes in the form of the embodiments described herein may be made without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications as would fall within the spirit and scope of the invention.

Claims

A flip-flop circuit (105) comprising: a master latch (ML1E) having a first inverter (INV3) and a first tri-state inverter (TS1') configured such that an input terminal of the first tri-state inverter (TS1') is connected to an output terminal of the first inverter (INV3) and an output terminal of the first tri-state inverter (TS1') is connected to an input terminal of the first inverter (INV3), wherein the first tri-state inverter (TS1') includes a first NMOS transistor (n5) configured such that a clock signal is input to a gate of the first NMOS transistor (n5), and a first PMOS transistor (p6) configured such that an inverted clock signal which is an inversion of the clock signal is input to the first PMOS transistor (p6); a slave latch (SL1E) having a second inverter (INV4) and a second tri-state inverter (TS2') configured such that an input terminal of the second tri-state inverter (TS2') is connected to an output terminal of the second inverter (INV4) and an output terminal of the second tri-state inverter (TS2') is connected to an input terminal of the second inverter (INV4), wherein the second tri-state inverter (TS2') comprises a second PMOS transistor (p10) configured to input the clock signal to a gate of the second PMOS transistor (p10) and a second NMOS transistor (n9) configured to input the inverted clock signal to the second NMOS transistor (n9); and at least one first wiring (L1) configured to connect a source of the first PMOS transistor (p6) and a source of the first NMOS transistor (n5), or a second wiring (L2) configured to connect a source of the second PMOS transistor (p10) and a source of the second NMOS transistor (n9), wherein the first tri-state inverter (TS1') comprises two NMOS transistors (n6, n12) directly connected to each other and configured to input an output signal of the first inverter (INV3) to the gates of the two NMOS transistors (n6, n12), wherein the flip-flop circuit (105) further comprises a third PMOS transistor (p12) connected in parallel to a PMOS transistor (p4) included in the first inverter (INV3), and configured to connect the output terminal of the first tri-state inverter (TS1') to a gate of the third PMOS transistor (p12).The flip-flop circuit (105) according to claim 1, wherein the second tri-state inverter (TS2') comprises two NMOS transistors (n10, n13) directly connected to each other and arranged such that the output signal of the second inverter (INV4) is input to the gates of the two NMOS transistors (n10, n13).The flip-flop circuit (105) according to claim 2, further comprising a fourth PMOS transistor (p13) connected in parallel to a PMOS transistor (p8) included in the second inverter (INV4), and configured that the output terminal of the second tri-state inverter (TS2') is connected to a gate of the fourth PMOS transistor (p13).A flip-flop circuit (103) comprising: a master latch (ML1C) comprising a first inverter (INV3) and a first tri-state inverter (TS1') configured such that an input terminal of the first tri-state inverter (TS1') is connected to an output terminal of the first inverter (INV3) and an output terminal of the first tri-state inverter (TS1') is connected to an input terminal of the first inverter (INV3), wherein the first tri-state inverter (TS1') comprises a first NMOS transistor (n5) configured such that a clock signal is input to a gate of the first NMOS transistor (n5), and a first PMOS transistor (p6) configured such that an inverted clock signal which is an inversion of the clock signal is input to the first PMOS transistor (p6); and a slave latch (SL1C) including a second inverter (INV4) and a second tri-state inverter (TS2') configured such that an input terminal of the second tri-state inverter (TS2') is connected to an output terminal of the second inverter (INV4) and an output terminal of the second tri-state inverter (TS2') is connected to an input terminal of the second inverter (INV4), wherein the second tri-state inverter (TS2') includes a second PMOS transistor (p10) configured to input the clock signal to a gate of the second PMOS transistor (p10), and a second NMOS transistor (n9) configured to input the inverted clock signal to the second NMOS transistor (n9), wherein the first tri-state inverter (TS1') includes two NMOS transistors (n6, n12) directly connected to each other and configured to input an output signal of the first inverter (INV3) to the gates of the two NMOS transistors (n6, n12), and wherein the flip-flop circuit (103) further comprises a third PMOS transistor (p12) connected in parallel to a PMOS transistor (p4) included in the first inverter (INV3), and configured that the output terminal of the first tri-state inverter (TS1, TS1') is connected to a gate of the third PMOS transistor (p12).A semiconductor integrated circuit device (24) comprising the flip-flop circuit (103, 105) according to any one of claims 1 to 4.A vehicle (300) comprising the semiconductor integrated circuit device (24) according to claim 5.

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