Package with a thermoelectric cooler for dissipating heat from an optical unit and manufacturing process for it

Abstract

Procedure, comprehensive: Bonding a photonics unit to an interposer; Bonding a package component to the interposer, wherein the package component has a device die; Encapsulation of the package component and the photonics unit in an encapsulation material; Attaching a thermoelectronic cooler to the photonics unit; and Attaching a metal cover to the package component.

Description

BACKGROUND

[0001] With the rapidly increasing bandwidth requirements of high-performance data processing systems, high-speed optical input / output modules (I / O modules) are being used more and more. These optical I / O modules are often connected to light sources (lasers) that drive the circuits.

[0002] However, lasers have a low efficiency in converting optical signals into electrical signals, and more than 50% of the power can be dissipated as heat. This leads to a high temperature in the optical module that receives the laser signal, necessitating improved heat dissipation.

[0003] US 2019 / 0285804A1 discloses a fan-out package for photonic integrated circuits (PICs) and related methods for its fabrication. The PIC fan-out package comprises: an overmolded body; a PIC chip within the overmolded body containing electro-optical circuitry; multiple optical fiber stubs operationally connected to the electro-optical circuitry; an edge fiber coupling interface on one side of the overmolded body for coupling the multiple optical fiber stubs to external optical fibers via a connector; an accessory within the overmolded body; a redistribution wiring layer (RDL) interposer adjacent to the overmolded body and electrically connected to the PIC chip and the accessory; and a ball grid array (BGA) electrically connected to the PIC chip and the accessory via the RDL interposer. The BGA is configured to electrically connect the PIC chip and the accessory to a printed circuit board (PCB).

[0004] US 2017 / 0194308A1 discloses a photonic integrated circuit package comprising a photonic integrated circuit chip that includes multiple electrodes configured to receive the electrical signal, wherein at least one property of a segment of the active optical traveling wave element is modified based on the electrical signal received by a corresponding electrode of the multiple electrodes; a ground electrode; multiple bond contacts; and an interposer connected to at least a portion of the photonic integrated circuit chip, wherein the interposer includes a conductive trace formed on a surface of the interposer that is electrically connected to a source of the electrical signal; and a ground line.and several conductive vias electrically connected to the conductor track, each conductive via of the several conductive vias being connected to a corresponding bond contact of the several bond contacts of the photonic integrated circuit chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1 to 6 show cross-sectional views of intermediate stages in the formation of a package containing a thermo-electronic cooler (TEC) for dissipating heat from a photonics unit, with bond wires being used for current conduction in some embodiments. Fig. Figures 7 to 18 show cross-sectional views of the intermediate stages in the formation of a package containing a TEC for dissipating heat from a photonic unit, wherein, according to some embodiments, vias through silicon are used for current conduction. Fig. Figures 19 to 25 show cross-sectional views of the intermediate stages in the formation of a package containing a TEC for dissipating heat from a photonic unit, wherein, according to some embodiments, vias through molding compound are used for current conduction. Fig. 26 and Fig. Figure 27 shows cross-sectional views of intermediate steps in bonding and thinning a silicon-based interposer according to some embodiments. Fig. 28A and Fig. Figure 28B shows a cross-sectional view or a perspective view of a BiTe-based TEC according to some embodiments. Fig. Figure 29 shows a perspective view of a vertical TEC based on Si / SiGe according to some embodiments. Fig. Figure 30 shows a perspective view of a horizontal TEC based on Si / SiGe according to some embodiments. Fig. Figure 31 shows a cross-sectional view of a silicon-based interposer according to some embodiments. Fig. Figure 32 shows a cross-sectional view of an interposer with built-in local interconnect dies according to some embodiments. Fig. Figure 33 shows a process flow for forming a package with a TEC for cooling a photonic unit according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments and examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the following description of the formation of a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, terms describing spatial relationships, such as "underlying," "below," "lower," "above," and "upper," are used here, where necessary, for the sake of simplicity, to describe the relationship of an element or feature to one or more other elements or features, as illustrated in the figures. These spatial relationship terms are intended to encompass not only the orientation depicted in the figures but also other orientations of the device in application or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial relationship descriptions used here can be interpreted analogously.

[0008] A package comprising a photonics unit and a thermoelectronic cooler (TEC) for cooling the photonics unit is formed. The processes for forming the package are provided. According to some embodiments of the present disclosure, the cold side of a TEC is attached to a photonics unit, while the hot side is located away from the photonics unit. A current is passed through the TEC so that heat can be dissipated from the photonics unit via the TEC. Alternatively, a metal lid can be used to dissipate heat from other package components, such as memory stacks and logic dies within the package. The use of the TEC improves the heat dissipation efficiency of the photonics unit.The embodiments discussed herein are intended to serve as examples to enable the manufacture or use of the subject matter of this disclosure, and a person skilled in the art will readily understand that modifications can be made without departing from the scope of the various embodiments under consideration. In the different views and illustrative embodiments, the same reference numerals denote the same elements. Although embodiments relating to methods are described in a specific order, other embodiments can be carried out in any logical sequence.

[0009] Fig. Figures 1 to 6 show cross-sectional views of intermediate stages in the formation of a package with a TEC for cooling a photonic unit according to some embodiments of the present disclosure. The corresponding processes are also described in the Fig. The process flow shown in section 33 is shown schematically.

[0010] According to Fig. 1 will be an initial structure of a package 10 ( Fig. ). The initial structure can include a package component 12. According to some embodiments, the package component 12 has a plurality of interposers (intermediate elements) 12' and is referred to below as the interposer wafer 12. The interposer wafer 12 is shown schematically, and the structures are described in Fig. not shown in detail. The detailed structure of some examples for Interposer-Wafer 12 is described in the Fig. 26, Fig. 27, Fig. 31 and Fig. Figure 32 shows the interposer wafer 12 having electrical connections 14 that can electrically and signal-wise connect the elements on opposite sides of the interposer wafer 12. The schematically depicted connections 14 can represent redistribution lines (RDLs), vias, bond pads, metal pillars, and the like.

[0011] The interposer wafer 12 can be selected from any available structure, including, but not limited to, a silicon-based interposer, an organic interposer (also known as an RDL interposer), a local silicon interconnect interposer (LSI interposer) with one or more embedded LSI die(s), or the like. The silicon-based interposer may have a silicon substrate and through-silicon vias (TSVs, also known as through-vias (TVs)) that penetrate the silicon substrate. An example of a silicon-based interposer is shown in Fig. Figure 31 shows that the organic interposer features organic dielectric layers and RDLs that are built into the dielectric layers layer by layer. The LSI interposer can have one or more LSI dies that have built-in metal conductors connected to the LSI die. An example of an LSI die is shown in Figure 31. Fig. 32 is shown and is explained below.

[0012] As from Fig. As can be seen from Figure 1, in some embodiments the package components 16 (including package components 16A and 16B) are bonded to the interposer wafer 12. The corresponding process is described as process 202 in Figure 1. Fig. The process flow shown in Figure 33 illustrates the process flow. Each of the package components can be a device die, a package containing one or more device dies, a system-on-a-chip (SoC) die with a plurality of integrated circuits (or device dies) integrated as a system, or the like. The device dies in the package components can be logic dies, memory dies, input / output dies, integrated passive devices (IPDs), or combinations thereof. The logic device dies in the package components can be, for example, central processing unit (CPU) dies, graphics processing unit (GPU) dies, mobile application dies, microcontroller dies (MCU) dies, baseband dies (BB dies), application processor dies (AP dies), or the like.The memory dies in the package components 16 can be dies for static random-access memory (SRAM dies), dies for dynamic random-access memory (DRAM dies), or the like. The device dies in the package components 16 can have semiconductor substrates and interconnect structures.

[0013] In the following descriptions, according to some exemplary embodiments, package component 16A is a logic die, which may be an application-specific integrated circuit (ASIC). Package component 16B may be a memory stack, e.g., a high-performance memory (HBM) stack. Package component 16B may comprise memory dies 18, which form a die stack, and an encapsulation material 20 (e.g., a molding compound) that encapsulates the memory dies 18.

[0014] As in Fig. As shown in Figure 1, the package components 16 can be bonded to the underlying interposer wafer 12, for example by solder regions 22. According to some embodiments, bonding is carried out by a chip-on-wafer bonding process (CoW bonding process), in which package components 16, which are discrete chips / packages, are bonded to the interposer wafer 12, i.e. an unsawled wafer, to form a redesigned wafer.

[0015] The photonics unit 26 is also bonded to the interposer wafer 12. The corresponding process is also known as process 202 in the Fig. The process flow shown in Figure 33 illustrates the process flow 200. An underfill 24 is introduced into the gaps between the package components 16, the photonics unit 26, and the interposer wafer 12. The corresponding process is shown as process 204 in Figure 33. Fig. The process flow shown in Figure 33 illustrates the process flow 200. After the introduction of the underfill 24, the encapsulation material 28, which may be a molding compound, is applied to encapsulate the package components 16 and the photonic unit 26.

[0016] The photonics unit 26 can comprise a photonics die 30, an electronics die (E-die) 32, and a photonics component 34. The electronics die 32 and the photonics component 34 can be located above and bonded to the photonics die 30, and they can be encapsulated in a gap-filling region 36. According to some embodiments, the gap-filling region 36 is a dielectric region that can comprise a silicon nitride layer and, above the silicon nitride layer, an oxide layer.

[0017] According to some embodiments, the electronics die 32 includes the integrated circuits for interfacing with the photonics die 30, such as the circuits for controlling the operation of the photonics die 30. The electronics die 32 may, for example, include controllers, drivers, amplifiers, and / or the like, or combinations thereof, as well as serializers / deserializers (SerDes). The corresponding components in the electronics die 32 may function as parts of I / O interfaces between optical and electrical signals.

[0018] The photonic die 30 can have a substrate 40, which can be a dielectric substrate such as a silicon oxide substrate. The substrate 40 can also be a semiconductor substrate, for example, a silicon substrate. According to some embodiments, the photonic die 30 can have optical devices such as silicon waveguides, non-silicon waveguides, grating couplers, modulators, and / or the like. For example, according to some embodiments, modulators 46 (which can be germanium modulators) and silicon waveguides 44 are shown. Vias 42 are formed in the substrate 40. The photonic die 30 can, but need not, include photodiodes and / or electrical devices such as controllers, drivers, amplifiers, and / or the like, as well as combinations thereof.The interconnect structure 48 can be formed over the optical components and comprises a plurality of dielectric layers as well as metal conductors and vias in the plurality of dielectric layers. The interconnect structure 48 is electrically connected to the interposer wafer 12 via the vias 42.

[0019] A support substrate 60 is formed above the electronics die 32 and the photonics component 34. The support substrate 60 can be fusion-bonded to the gap-filling region 36 and the silicon substrate in the electronics die 32. For example, a silicon oxide layer (not shown) can (but need not) be formed as the bottom layer of the support substrate 60 for bonding to the underlying structures. According to some embodiments, the support substrate 60 is formed from a homogeneous material with high thermal conductivity. The support substrate 60 can, for example, be formed from or contain silicon or other transparent and thermally conductive materials. Alternatively, the support substrate 60 can also be formed from a metal such as copper, tungsten, or the like. If silicon is included, the support substrate 60 may not contain any metallic elements formed therein.A portion of the upper surface of the support substrate 60 can be curved to form a microlens 62. In some embodiments, the microlens 62 is recessed from the upper surface of the support substrate 60. In alternative embodiments, the microlens 62 protrudes from the support substrate 60. If recessed, the microlens 62 can be filled with a filler material 63, e.g., a polymer, as a protective layer. In alternative embodiments, the recess of the microlens 62 is not filled.

[0020] According to some embodiments, the photonic component 34 is or comprises a photodiode (e.g., a laser diode) which may be formed from or comprise a III-V semiconductor material. According to some embodiments, the photonic component 34 is configured to receive an electrical signal and emit a light beam (e.g., a laser beam) to the microlens 62. According to alternative embodiments, the photonic component 34 is configured to receive a light beam from the microlens 62 and convert the light into an electrical signal. The electrical signal in the photonic component 34 can be transmitted to or received from the photonic die 34.

[0021] According to some embodiments, the interposer wafer 12 already has electrical connections 14 at the time the package components 16 and the photonics unit 26 are bonded to the interposer wafer 12. These connections link the elements on the top side to the bottom side of the interposer wafer 12. According to alternative embodiments, in which the interposer wafer 12 has a silicon substrate, the interposer wafer 12 can be in Fig. 1 the in Fig. The structure shown in Figure 26 is present. The corresponding interposer wafer 12 can have vias 138 that extend into the silicon substrate 140 but do not penetrate it. The in Fig. The processes shown in Figure 27 are then carried out to complete the formation of the interposer wafer 12, with the vias 138 and the RDLs forming electrical connections 14 as shown in Figure 27. Fig. 1 shown form.

[0022] As in Fig. As shown in Figure 1, the encapsulation material 28, which can be a molding compound, a filler, an epoxy resin, a resin, or the like, is applied to encapsulate the package components 16 and the photonics unit 26. The corresponding process is described as process 206 in [reference missing]. Fig. The process flow shown in Figure 33 illustrates process 200. The recess of the microlens 62 can be filled with the encapsulation material 28 if no protective layer 63 is formed. Next, a planarization process is performed on the encapsulation material 28 to align its top surface with the top surfaces of the package components 16 and the support substrate 60. The corresponding process is shown as process 208 in Figure 33. Fig. The process flow shown in Figure 33 illustrates the process flow 200. The protective layer 63, or the portion of the encapsulation material 28 that fills the recess of the microlens 62, is then removed. The resulting structure is shown in Figure 33. Fig. 2 shown. In this way the redesigned wafer 67 is created.

[0023] As in Fig. As shown in Figure 2, the TEC 66 is attached to the support substrate 60 to promote the formation of the redesigned wafer 67. The corresponding process is described as process 210 in the Fig. The process flow shown in Figure 33 illustrates the process flow 200. In some embodiments, the attachment is effected by means of thermal interface material (TIM) 68, so that the heat can be transferred from the support substrate 60 to the TEC via the TIM 68. The TEC 66 is shown schematically, with the structure of the TEC 66 in Fig. 2 is not shown in detail. The detailed construction of some examples for TECs 66 is in the Fig. 28A, Fig. 28B, Fig. 29 and Fig. 30 shown.

[0024] The TEC 66 utilizes the Peltier effect to generate a heat flow at the interface between two different materials. A TEC is an active solid-state heat pump that transfers heat from one side of the device to the other. Electrical energy in the form of current is consumed for the heat transfer, and the direction of heat transfer depends on the current direction. According to some embodiments of the present disclosure, the TEC 66 is used for cooling the underlying photonics unit 26.

[0025] According to some embodiments, as in Fig. Figure 2 schematically depicts the TEC 66 as having a cold side 70C, a hot side 70H, a current input node 72, and a current output node 74. The cold side 70C is located on the side closer to the photonics unit 26, while the hot side 70H is located on the side furthest from the photonics unit 26. During operation of the TEC 66, heat is transferred from the cold side 70C to the hot side 70H, which is hotter than the cold side 70C. The hot side 70H may (but does not have to) be connected to a heat sink (not shown) to dissipate heat. Since the cold side 70C has a lower temperature than it would without a TEC 66, the heat dissipation efficiency from the photonics unit 26 to the TEC 66 is improved.

[0026] Fig. 28A, Fig. 28B, Fig. 29 and Fig. Figure 30 illustrates some examples of TECs 66 according to some embodiments. It is understood that the TECs 66 used in the embodiments may have further variants differing from the illustration, which are also included in the present disclosure.

[0027] Fig. 28A and Fig. Figure 28B shows a cross-sectional view and a perspective view of a portion of a BiTe-based TEC 66 according to some embodiments. The BiTe-based TEC 66 comprises a plurality of p-doped BiTe alloy blocks 110p and a plurality of n-doped BiTe alloy blocks 110n, arranged alternately. The adjacent BiTe alloy blocks 110p and 110n are electrically insulated from each other by insulating layers 112, which, according to some embodiments, may be ceramic layers. The BiTe alloy may contain Bi₂Te₃, which can be formed by sealing mixed bismuth and tellurium metal powders in a quartz tube under vacuum and heating the BiTe alloy to a high temperature, such as 800 °C, in a furnace.A plurality of metal plates 114 electrically connect adjacent BiTe alloy blocks 110p and 110n, such that the p-doped BiTe alloy blocks 110p and the n-doped BiTe alloy blocks 110n are connected in series. When a current I is fed into the current input node 72 and discharged from the current output node 74, the current I flows through the series-connected p-doped BiTe alloy blocks 110p and the n-doped BiTe alloy blocks 110n. Due to the Peltier effect, heat is transferred from the bottom to the top of the TEC 66. Accordingly, the bottom acts as the cold side 70C and the top as the hot side 70H.

[0028] Fig. Figure 29 shows a perspective view of a vertical TEC 66 based on Si / SiGe according to some embodiments. The vertical TEC 66 based on Si / SiGe has a Si / SiGe multilayer superlattice structure with a plurality of Si layers 120 and a plurality of SiGe layers 122, which are alternately stacked and arranged. The Si layers 120 and the SiGe layers 122 can be deposited, for example, by metal-organic chemical vapor deposition (MOCVD) or other suitable methods. The superlattice structure hinders phonon transfer (with reduced thermal conductivity) and increases electron / hole transfer (with increased electrical conductivity). Accordingly, the Seebeck coefficient is improved, and heat transfer is enhanced.When a current I is fed into the current input node 72 and discharged from the current output node 74, the current I flows from the bottom to the top, and the bottom becomes the cold side 70C, while the top becomes the hot side 70H.

[0029] Fig. Figure 30 shows a perspective view of a horizontal Si / SiGe-based TEC 66 according to some embodiments. The horizontal Si / SiGe-based TEC 66 has a plurality of SiGe layers 122' embedded in a Si region 120'. A current I can be applied to the current input node 72 and delivered to the current output node 74. When a current I flows from the left side to the right side, the left side becomes the cold side 70C, while the right side becomes the hot side 70H. A thermally conductive plate (designated 72) is placed under the SiGe region 122' and connected to the current input node 72, so that the underside becomes the cold side 70C. The metal plate of the current output node 74, located on the top side of the TEC, becomes the hot side 70H.

[0030] As in Fig. As shown in Figure 2, the redesigned wafer 67, after attachment of the TEC 66 to the photonics unit 26, can be separated to form a plurality of identical packages 67', each comprising a TEC 66 and a photonics unit 26, an interposer 12' in the interposer wafer 12, and several other components. The corresponding process is described as process 212 in the Fig. The process flow shown in section 33 illustrates the 200th process.

[0031] Next, as in Fig. Figure 3 shows that package 67' is bonded to package component 76. The corresponding process is shown as process 214 in the Fig. The process flow shown in Figure 33 is illustrated in Figure 200. According to some embodiments, the package component 76 is or comprises a package substrate, which may be a core substrate or a coreless substrate. The resulting package is thus a chip-on-wafer-on-substrate (CoWoS) substrate. According to other embodiments, the package component 76 may be a printed circuit board, a package, or the like.

[0032] As in Fig. As shown in Figure 4, electrical connections 78, which may be bond wires, are connected to the TEC 66 so that current can be supplied to the TEC 66 to perform the cooling function. According to some embodiments, the bond wires 78 are attached by wire bonding and connected to the current input node 72 and the current output node 74. According to some embodiments, the bond wires 78 can also be connected to the package component 76. The corresponding process is described as process 216 in [reference missing]. Fig. The process flow shown in section 33 illustrates the 200th process.

[0033] As in Fig. As shown in Figure 5, an optical fiber 80 is attached to the photonics unit 26 and aligned with the microlens 62. The attachment can be made using an optical adhesive 82, which fills the recess of the microlens 62. The corresponding process is described as process 218 in Figure 5. Fig. The process flow shown in section 33 illustrates the 200th process.

[0034] Fig. Figure 6 illustrates the attachment of the metal cover 84, which is attached to the package component 76 by means of an adhesive 86. The corresponding process is described as process 220 in the Fig. The process flow shown in Figure 33 illustrates the process flow 200. The TIM 87 is applied to the top of the package components 16 and connects the metal cover 84 to the package components 16. In this way, the package 10 is formed. The metal cover 84 has a left section on the left side of the package 67' and a right section on the right side of the package 67'. The illustrated left and right sides can be sections of a metal ring section 84R of the metal cover 84, with the metal ring section 84R forming a complete ring. Viewed from above, the metal cover 84 has a cover section 86C in which an opening is formed for ventilation and cooling as well as for the passage of the optical fiber 80.

[0035] According to some embodiments of the present disclosure, as in Fig. Figure 6 shows the photonics unit 26 cooled using the TEC 66. The photonics unit 26 can receive and operate laser light, which can have a low conversion efficiency when converted into and out of electrical signals, sometimes below 50%. This results in a considerable amount of energy being converted into heat within the photonics unit 26. To keep the temperature of the photonics unit 26 low and within a suitable range, a TEC 66 is used, which, due to the temperature difference between its cold and hot sides, dissipates heat more efficiently than a typical heat sink or metal cover.

[0036] However, the TEC 66 is powered by electrical current and therefore consumes power. Accordingly, package components 16, such as non-photonic logic dies and memory dies, which generate less heat than the photonic unit 26, can be cooled with the metal cover, thus reducing power consumption.

[0037] Fig. Figures 7 to 18 illustrate cross-sectional views of intermediate stages in the formation of a package according to alternative embodiments of the present disclosure. These embodiments are similar to those described in the Fig. In the embodiments shown in Figures 1 to 6, the exception is that instead of forming wire bonds to supply power to the TEC 66, vias (alternatively also referred to as through-holes) are formed through the dielectric and silicon, penetrating the gap-filling region 36 and the support substrate 60. The current for operating the TEC 66 is thus supplied through the support substrate 60. Unless otherwise specified, the materials, structures, and formation processes of the components of these embodiments (and those shown in the figures) are the same as those described in Figures 1 to 6. Fig. The embodiments shown in 19 to 25 are essentially the same as the components designated with the same reference numerals in the Fig. The preceding embodiments shown in 1 to 6 are described in detail below. Fig. 7 to 18 components shown (and the one in the Fig. The embodiments shown in Figures 19 to 25, according to further alternative embodiments, can therefore be taken from the descriptions of the preceding embodiments.

[0038] The Fig. Figures 7 to 12 illustrate the formation of a photonic unit 26 with through-holes in a support substrate according to some embodiments. Fig. 7 A photonic die 30 is formed. According to some embodiments, the photonic die 30 comprises a substrate 40, vias 42, waveguides 44, a Ge modulator 46, and an interconnect structure 48. According to some embodiments, the photonic die 30 is located in a wafer that has a plurality of photonic dies identical to the photonic die 30.

[0039] As in Fig. As can be seen in Figure 8, an electronics die 32 and a photonics component 34 are bonded to the photonics die 30. Subsequently, a gap-filling region 36 is formed to fill the gaps between the electronics die 32 and the photonics component 34.

[0040] In a subsequent process, as in Fig. Figure 9 shows vias 88 and bond pads 90 formed in the gap-filling region 36. Although only one via 88 is shown, two vias 88 can be formed above each photonic die 30, with the other via 88 located in a different plane not shown. The formation process can include etching the gap-filling region 36 to form openings and filling the openings with conductive materials, followed by a planarization process. According to some embodiments, the vias 88 and bond pads 90 can be made of or comprise Ti, TiN, Ta, TaN, tungsten, copper, alloys of these, and multiple layers of these. The vias 88 and bond pads 90 are electrically connected to metal pads in the interconnect structure 48. According to alternative embodiments, no bond pads 90 are formed, and the vias 88 extend to the top of the gap-filling region 36.

[0041] According to alternative embodiments, instead of forming the vias 42 prior to the formation of the interconnect structure 48, the vias 88 and the vias 42 are formed as integrated vias that extend continuously through the gap-filling region 36, the dielectric layers in the interconnect structure 48, and into the substrate 40. The corresponding vias also have straight edges extending from the top of the gap-filling region 36 into the substrate 40.

[0042] As in Fig. As shown in Figure 10, the support substrate 60 is bonded to the underlying structure, e.g., by hybrid bonding. According to some embodiments, the support substrate 60 is pre-formed and comprises a substrate 60S, which can be a silicon substrate or made of other thermally conductive materials. Furthermore, a bond layer 124 and bond pads 98 are formed on the underside. The bond layer 124 is bonded to the gap-filling region 36 and the silicon substrate in the electronic die 32 by fusion bonding, forming, for example, Si-O-Si bonds. The bond pads 98 are bonded to bond pads 90. Bond pads 96 and the corresponding dielectric layer 126 can be formed on the top side of the support substrate 60.Each of the vias 92 can have an inner conductive section and an outer insulating layer, the outer insulating layer electrically isolating the inner conductive section from the substrate 62S. The bond pads 96 and 98 are also electrically insulated from the substrate 60S, for example by the insulating layers.

[0043] According to Fig. In step 11, the substrate 40 in the photonic die 30 is diluted so that the vias 42 are exposed from below. In a subsequent process, as described in Fig. As shown in Figure 12, solder regions 128 are formed and electrically connected to the vias 42. A backside interconnect structure (not shown) can (but does not have to) also be formed, which may include dielectric layers and RDLs. The backside interconnect structure is formed between solder regions 128 and the vias 42 (and electrically connects them). In this way, the redesigned wafer 130 is created. Next, the redesigned wafer 130 is singulated to form a plurality of discrete photonic units 26, which are identical to each other.

[0044] According to Fig. 13. The package components 16 and the photonics unit 26 are bonded to the interposer wafer 12, e.g., via the solder regions 22. Next, as in Fig. Figure 14 shows that the underfill 24 is introduced into the gaps between the package components 16 and the photonics unit 26 and the respective underlying sections of the interposer wafer 12. Subsequently, the encapsulation material 28 is applied and cured and, according to some embodiments, may contain a molding compound.

[0045] As in Fig. As shown in Figure 15, the encapsulation material 28 is planarized to expose the top surfaces of the package components 16 and the support substrate 60. The bond pads 96 are also exposed. The recess of the microlens 62 is also cleared, e.g., by removing the materials filled into it (e.g., the protective layer 63 or the encapsulation material 28).

[0046] Next, as in Fig. Figure 16 shows that the TEC 66 is bonded to the support substrate 60, for example by hybrid bonding. According to some embodiments, the TEC 66 has a dielectric layer 134 and bond pads 132 in the dielectric layer 134, wherein the undersides of the dielectric layer 134 and the bond pads 132 are coplanar. The bond pads 132 can be electrically connected to the current input node 72 and the current output node 74 via the interconnects (e.g., metal pads 114, as shown in the Fig. 28A and Fig. 28B shown, or the metal pads in the Fig. 29 and Fig. 30) within the TEC 66.

[0047] According to some embodiments, two bond pads 132 are bonded to the respective bond pads 96, with one of the bond pads 132 being electrically connected to the current input node 72 ( Fig. 16) and the other is electrically connected to the current output node 74. According to other embodiments, a single bond pad 132 is formed and bonded to the corresponding bond pad 96. The single bond pad 132 can be connected either to the current input node 72 or the current output node 74. The other node (current input node 72 or current output node 74) can be connected via a via 136 ( Fig. 25) or via a bond wire 78 ( Fig. 6) electrically with the interposer 12' or the package component 76 ( Fig. 18) are connected. In this way, the reconstructed wafer 67 is created. The reconstructed wafer 67 is then separated into individual packages 67'.

[0048] As in Fig. As shown in Figure 17, the package 67' is connected to the package component 76, which can be a package substrate, a printed circuit board, another package, or the like. The optical fiber 80 is also attached to the carrier substrate 60 by means of optical adhesive 82 and aligned with the microlens 62.

[0049] Fig. Figure 18 illustrates the attachment of the metal cover 84 to the package component 76 by means of an adhesive 86. Furthermore, the metal cover 84 is attached to the top surfaces of the package components 16 via the TIM 87, so that the heat generated in the package components 16 can be dissipated into the metal cover 84. In this way, the package 10 is formed.

[0050] Fig. Figures 19 to 25 illustrate cross-sectional views of intermediate stages in the formation of a package according to some embodiments of the present disclosure. These embodiments are similar to those in the Fig. 1 to 6 embodiments shown, except that instead of wire bonds, vias are formed which penetrate the encapsulation material 28 to supply the current used by the TEC 66.

[0051] In Fig. The interposer wafer 12 is shown. Metal pins 136 are formed on the interposer wafer 12 and connected to the electrical connections 14. Even if only one metal pin 136 is formed, two metal pins 136 can be formed above each of the interposers 12' in the interposer wafer 12. According to some embodiments, the interposer wafer 12 has the following features at the time the metal pins 136 are formed: Fig. The structure shown in Figure 26 is characterized by an interposer wafer 12 comprising a silicon substrate 140 and conductive rods 138 extending into (but not penetrating) the silicon substrate 140. The interconnect structure 142 is formed over the substrate 140 and includes dielectric layers and redistribution lines (metal conductors and vias). The redistribution lines are electrically connected to the metal pins 138.

[0052] According to alternative embodiments, the interposer wafer 12 has, at the time of formation of the metal pins 136, the following properties: Fig. Structure shown in 31. In the Fig. In the structure shown in Figure 31, a back-side grinding process has already been carried out on the back of the substrate 140, and the metal pins 138 are exposed to form vias (also referred to as vias 138). Solder regions 144 can be formed at this time, but do not have to be. Since the interposer wafer 12 is thin, a support 146 can be used according to these embodiments ( Fig. 19) are placed under the interposer wafer 12 to provide mechanical support. A release liner 148, which may be an LTHC (light-to-heat conversion) layer, can bond the interposer wafer 12 to the carrier 146. The carrier 146 and the release liner 148 are shown with dashed lines to indicate that they may or may not be used when the metal pins 136 are formed.

[0053] According to Fig. 19 The formation of vias 136 can involve depositing a metal seed layer (not shown) on the interposer wafer 12, forming a structured plating mask (not shown), such as a structured photoresist, and plating metal pins 136 into the openings in the plating mask. The plating mask is then removed, followed by an etching process to remove the portions of the metal seed layer that were previously covered by the plating mask.

[0054] According to Fig. In step 20, the package components 16 and the photonics unit 26 are bonded to the interposer wafer. The underfill 24 is placed in the gaps between the package components 16 and the photonics unit 26 and the respective underlying sections of the interposer wafer 12. Next, as described in Fig. Figure 21 shows the encapsulation material 28 applied to form the package components 16 and the photonics unit 26, as well as the metal pins 136, within it. According to some embodiments, the encapsulation material 28 may contain a molding compound, a filler, a resin, an epoxy resin, or the like.

[0055] As in Fig. As shown in Figure 22, the encapsulation material 28 is planarized to expose the top surfaces of the package components 16 and the support substrate 60. The metal pins 136 are also exposed. Since the metal pins 136 now penetrate the encapsulation material 28, they are referred to in this description as vias or dielectric vias. The recess of the microlens 62 is also cleared, for example, by removing the materials filled into it (e.g., a protective layer 63 or the encapsulation material 28).

[0056] As already mentioned, if metal pins 136 are formed on the interposer wafer 12, as in Fig. Figure 31 shows that the carrier 146 and the separating film 148 are located beneath the interposer wafer 12. The carrier 146 can thus be unbonded, for example, by projecting a laser beam onto the separating film 148, thereby disintegrating the separating film 148. If, on the other hand, the interposer wafer 12 is located beneath the interposer wafer 12, the carrier 146 can be unbonded. Fig. The structure shown in 26 is characterized by the following: Fig. 26 and Fig. The processes shown in Figure 27 (as explained in the following sections) are carried out to complete the formation of the interposer wafer 12 and the electrical connections 14. In this way, the reconstructed wafer 67 is produced. A singulation process can be carried out to saw the reconstructed wafer 67 into discrete packages 67', as also shown in Figure 27. Fig. 22 shown.

[0057] As in Fig. As shown in Figure 23, the package 67' is connected to the package component 76, which may be a package substrate, a printed circuit board, another package, or the like. The optical fiber 80 is also attached to the carrier substrate 60 and aligned with the microlens 62 by means of the optical adhesive 82, as shown in Figure 23. Fig. 24 shown.

[0058] As also in Fig. As shown in Figure 24, the TEC 66 is bonded to the support substrate 60, for example by hybrid bonding. The bond pads in the TEC 66, which may be the current input node 72 and / or the current output node 74 (or additional bond pads electrically connected to the current input node 72 and / or the current output node 74), are connected to the vias 136. The current input node 72 and / or the current output node 74 are thus electrically connected to the vias 136. To bond the vias 136 to the TEC 66, the TEC 66 extends laterally beyond the edges of the photonics unit 26, with a section overlapping the encapsulation material 28.

[0059] Bonding of the TEC 66 to the vias 136 can be achieved via the bond pads formed on the base of the TEC 66. Alternatively, the current input node 72 and the current output node 74 can be bonded directly to the vias 136 if the current input node 72 and the current output node 74 extend to the base of the TEC 66. According to some embodiments, the vias 136 are bonded to the metal elements in the TEC 66 by direct metal-to-metal bonding. According to alternative embodiments, bonding can be achieved by hybrid bonding, which includes bonding the vias 136 to the metal elements in the TEC 66 by direct metal-to-metal bonding and bonding the support substrate 60 to a dielectric surface layer on the base of the TEC 66. The optical fiber 80 is also attached to the support substrate 60, for example, by the optical adhesive 82.

[0060] According to alternative embodiments, the bonding sequence of the TEC 66 and the package component 76 can be reversed.

[0061] According to some embodiments, two vias 136 are formed and bonded to the TEC 66, one of the vias 136 being electrically connected to the current input node 72 and the other electrically to the current output node 74. According to other embodiments, a single via 136 is formed and bonded to the respective metal element in the TEC 66. The single via 136 can be connected to either the current input node 72 or the current output node 74. The other node (current input node 72 or current output node) 74 ) can be connected via a through-hole 92 ( Fig. 18) or via a bond wire 78 ( Fig. 6) electrically connected to the interposer 12' or the package component 76 (Figure 124).

[0062] Fig. Figure 25 illustrates the attachment of the metal cover 84 to the package component 76 by means of an adhesive 86. Furthermore, the metal cover 84 is attached to the top surfaces of the package components 16 via the TIM 87, so that the heat generated in the package components 16 can be dissipated into the metal cover 84. In this way, the package 10 is formed.

[0063] The Fig. 26 and Fig. Figure 27 shows an embodiment in which the formation of the interposer wafer 12 is completed after the package components 16 and the photonic unit 26 have been bonded to the interposer wafer 12. Fig. 26 illustrates a structure that is in the Fig. 1, Fig. 14 or Fig. The process shown in section 21 can occur. As in Fig. As shown in Figure 26, the interposer wafer 12 has a semiconductor substrate 140, which can be a silicon substrate. The metal pins 138 in the interposer wafer 12 extend to an intermediate plane between a top and a bottom surface of the silicon substrate 140. Fig. Figure 26 shows the vias 136 in the encapsulation material 28, the vias 88 in the gap-filling region 36, and the vias 92 in the support substrate 60 with dashed lines to indicate that these vias can be arranged according to different embodiments, as shown in the Fig. 1, Fig. 14 and Fig. 21 shown, can be formed or not.

[0064] Fig. Figure 27 shows the thinning of the substrate 140 so that the vias 138 on the underside of the substrate 140 are exposed. Next, the solder regions 144 are formed to complete the formation of the interposer wafer 12. According to some embodiments, a backside interconnect structure (including RDLs, not shown) can be formed between the solder regions 144 and the vias 138, electrically connecting them.

[0065] The Fig. 31 and Fig. Figure 32 illustrates some example structures of the interposer 12' and the interposer wafer 12 according to some embodiments. Fig. Figure 31 illustrates a silicon-based interposer 12' which has a silicon substrate 140 and vias 138 penetrating the silicon substrate 140, as also shown in the Fig. 26 and Fig. 27 shown. Fig.Figure 32 illustrates an LSI interposer with LSI dies 150. Front-side RDLs 152A and rear-side RDLs 152B are formed on the front and rear sides of the LSI dies 150, respectively. The LSI dies 150 can be encapsulated in an encapsulation material 156. One or more vias 154 can be formed to penetrate the encapsulation material 156 and connect the front-side RDLs 152A and the rear-side RDLs 152B. Two package components (e.g., the package components 16A and 16B and the photonics unit 26) can be connected to each other via the metal traces within the LSI dies 150 and via the RDLs 152A.

[0066] In the embodiments described above, some processes and features according to some embodiments of the present disclosure are discussed for forming a three-dimensional (3D) package. Further features and processes may also be included. For example, test structures to support acceptance testing of the 3D packages or 3D circuit components may be included. The test structures may, for example, be test plates formed in a redistribution layer or on a substrate, which enables the testing of the 3D package or 3D circuit, the use of probes and / or probe cards, and the like. The acceptance test can be performed on intermediate structures as well as on the finished structure.In addition, the structures and methods disclosed herein can be used together with test methodologies that include intermediate tests of proven good dies to increase yield and reduce costs.

[0067] The embodiments of the present disclosure exhibit several advantageous features. By using a TEC for cooling photonic units, the cooling efficiency of photonic units, which generate a high amount of heat, is improved. On the other hand, logic and memory dies, which generate less heat than the photonic units, can be cooled with metal covers, thus optimizing the cooling requirements and reducing the power consumption for cooling.

[0068] According to some embodiments of the present disclosure, a method comprises bonding a photonic unit to an interposer; bonding a package component to the interposer, wherein the package component includes a device die; encapsulating the package component and the photonic unit in an encapsulation material; attaching a thermoelectronic cooler to the photonic unit; and attaching a metal lid to the package component. In one embodiment, the method further comprises performing a wire bonding process to connect a metal wire to the thermoelectronic cooler. In another embodiment, the method further comprises forming a via, wherein the encapsulation material further encapsulates the via and wherein the thermoelectronic cooler is electrically connected to the via.

[0069] In one embodiment, the photonics unit comprises a substrate having a via therein, wherein the thermoelectronic cooler is electrically connected to the via. In another embodiment, the method further comprises forming the photonics unit, including bonding an electronics die and a photonics component to a photonics die; and attaching the substrate to the electronics die and the photonics component, wherein the substrate has a microlens therein. In another embodiment, the method further comprises attaching an optical fiber to the microlens.In one embodiment, the method further comprises passing a current through the thermoelectronic cooler, wherein the thermoelectronic cooler has a cold side and a hot side in response to the current, wherein the cold side is attached to the photonics unit and wherein the hot side is located further away from the photonics unit than the cold side.

[0070] In one embodiment, the interposer comprises a silicon substrate and vias penetrating the silicon substrate. In another embodiment, the interposer comprises a local silicon interconnect (LSI) die and redistribution lines connected through the LSI die. In one embodiment, the attachment of the thermoelectronic cooler includes the attachment of a BiTe-based thermoelectronic cooler.

[0071] According to some embodiments of the present disclosure, a package comprises a photonic unit; a package component comprising a device die; an encapsulation material encapsulating the package component and the photonic unit; a thermoelectronic cooler attached to the photonic unit, wherein the thermoelectronic cooler has a current input node and a current output node, and wherein the thermoelectronic cooler has a cold side and a hot side, the cold side being located between the hot side and the photonic unit; a thermal paste; and a metal lid attached to the package component by means of the thermal paste. In one embodiment, the package further comprises a bond wire attached either to the current input node or to the current output node.

[0072] In one embodiment, the package further comprises a via that penetrates the encapsulation material, wherein the thermoelectronic cooler is electrically connected to the via. In another embodiment, the photonics unit comprises a support substrate, wherein the support substrate has a via therein, and wherein the thermoelectronic cooler is electrically connected to the via. In another embodiment, the photonics unit comprises a photonics die; an electronics die and a photonics component located above and bonded to the photonics die; and a support substrate located above and attached to the electronics die and the photonics component. In another embodiment, the support substrate comprises a microlens located therein, and the package further comprises an optical fiber attached to the microlens.

[0073] According to some embodiments of the present disclosure, a package comprises a package substrate; an interposer located above and bonded to the package substrate; a first package component located above and bonded to the interposer, wherein the first package component comprises a photonic die; an optical fiber configured to couple to the photonic die for signal transmission; a thermoelectronic cooler attached to the first package component, wherein the thermoelectronic cooler is configured to dissipate heat in the first package component; a second package component located above and bonded to the interposer; and a metal lid attached to the second package component, wherein the metal lid is configured to dissipate heat in the second package component.

[0074] In one embodiment, the thermoelectronic cooler is configured to have a cold side and a hot side, which are generated when it is energized, with the cold side attached to the first package component. In another embodiment, the first package component further comprises a support substrate over the photonic die, the support substrate containing a microlens. In yet another embodiment, the package further comprises a laser diode bonded to the photonic die, the support substrate being attached to the laser diode, and the optical fiber being optically coupled to the laser diode.

Claims

[1] Procedure, encompassing: Bonding a photonics unit to an interposer; Bonding a package component to the interposer, wherein the package component has a device die; Encapsulation of the package component and the photonics unit in an encapsulation material; Attaching a thermoelectronic cooler to the photonics unit; and Attaching a metal cover to the package component. [2] Method according to claim 1, further comprising carrying out a wire bonding process to connect a metal wire to the thermoelectronic cooler. [3] Method according to claim 1 or 2, further comprising: Forming a via, wherein the encapsulation material further encapsulates the via and wherein the thermoelectronic cooler is electrically connected to the via. [4] Method according to any of the preceding claims, wherein the photonics unit comprises: a support substrate having a via located therein, wherein the thermoelectronic cooler is electrically connected to the via. [5] Method according to claim 4, further comprising forming the photonics unit, comprising: Bonding an electronics die and a photonics component to a photonics die; and Attaching the support substrate to the electronics die and the photonics component, wherein the support substrate includes a microlens. [6] Method according to claim 5, further comprising attaching an optical fiber to the microlens. [7] Method according to any of the preceding claims, further comprising conducting a current through the thermoelectronic cooler, wherein the thermoelectronic cooler has a cold side and a hot side in response to the current, wherein the cold side is attached to the photonics unit and wherein the hot side is located further away from the photonics unit than the cold side. [8] Method according to any of the preceding claims, wherein the interposer comprises: a silicon substrate; and Vias that penetrate the silicon substrate. [9] Method according to any of the preceding claims, wherein the interposer comprises: a local silicon interconnect die; and Redistribution lines that are connected via the Local Silicon Interconnect Die. [10] Method according to any of the preceding claims, wherein the application of the thermoelectronic cooler comprises applying a BiTe-based thermoelectronic cooler. [11] Package, comprising: a photonics unit; a package component that includes a device die; an encapsulation material that encapsulates the package component and the photonics unit; a thermoelectronic cooler attached to the photonics unit, wherein the thermoelectronic cooler has a current input node and a current output node, and wherein the thermoelectronic cooler has a cold side and a hot side, the cold side being located between the hot side and the photonics unit; a thermal paste; and a metal cover that is attached to the package component via thermal paste. [12] Package according to claim 11, wherein the package further comprises a bond wire which is attached either to the current input node or to the current output node. [13] Package according to claim 11 or 12, further comprising: a via that penetrates the encapsulation material, wherein the thermoelectronic cooler is electrically connected to the via. [14] Package according to one of claims 11 to 13, wherein the photonic unit has a support substrate, wherein the support substrate has a via therein and wherein the thermoelectronic cooler is electrically connected to the via. [15] Package according to any one of claims 11 to 14, wherein the photonics unit comprises: a photonic die; an electronics die and a photonics component located above and bonded to the photonics die; and a carrier substrate that is located above and attached to the electronics die and the photonics component. [16] Package according to claim 15, wherein the carrier substrate has a microlens located therein and wherein the package further comprises an optical fiber attached to the microlens. [17] Package which includes the following: a package substrate; an interposer that is located above the package substrate and bonded to it; a first package component located above and bonded to the interposer, wherein the first package component comprises a photonic die; an optical fiber that is set up to couple signal-wise with the photonics die; a thermoelectronic cooler attached to the first package component, wherein the thermoelectronic cooler is configured to dissipate heat in the first package component; a second package component that sits above the interposer and is bonded to it; and a metal lid attached to the second package component, wherein the metal lid is configured to dissipate heat in the second package component. [18] Package according to claim 17, wherein the thermoelectronic cooler is configured to have a cold side and a hot side which are generated when it is powered on, and wherein the cold side is attached to the first package component. [19] Package according to claim 17 or 18, wherein the first package component further comprises a support substrate over the photonic die, the support substrate comprising a microlens therein. [20] Package according to claim 19, further comprising: a laser diode bonded to the photonic die, wherein the support substrate is attached to the laser diode and wherein the optical fiber is optically coupled to the laser diode.

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