OPTICAL DEVICE AND MANUFACTURING PROCESS

Abstract

A method for manufacturing an optical device, wherein the method comprises: Forming a first semiconductor device (700) as part of a first wafer, wherein the first semiconductor device (700) comprises a layer (705) of active devices and an interconnect structure (707); Forming a first opening (717) at least partially through the interconnect structure (707) and the layer (705) of active devices of the first semiconductor device (700); Filling the first opening (717); and Bonding of the first semiconductor device (700) to an optical interposer (100), while the first semiconductor device (700) remains part of the first wafer, wherein the filling of the first opening (717) comprises the deposition of an anti-reflective coating (1501) along side walls of the first opening (717).

Description

BACKGROUND

[0001] Electrical signal transmission and processing are among the techniques used for signal transmission and processing. Optical signal transmission and processing have been increasingly used in recent years, particularly thanks to the use of fiber optic applications for signal transmission.

[0002] Optical signaling and processing are typically combined with electrical signaling and processing to provide fully featured applications. For example, optical fibers can be used for long-distance signal transmission, while electrical signals can be used for short-distance signal transmission, processing, and control. Accordingly, devices are developed for converting between optical and electrical signals, as well as for processing both, integrating long-range optical components and short-range electrical components. These packages can therefore include both optical (photonic) dies with optical devices and electronic dies with electronic devices.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in DE 10 2020 107 271 A1, US 2022 / 0 187 536 A1, US 2020 / 0 166 720 A1 and US 2018 / 0 143 374 A1.

[0004] The invention is defined by the main claim and the dependent claim. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood by referring to the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figures 1-5 illustrate the formation of an optical interposer according to some embodiments. Fig. Figures 6A-6P illustrate the formation of a laser die according to some embodiments. Fig. Figures 7A-7G illustrate the formation of a first semiconductor device according to some embodiments. Fig. Figures 8-12 illustrate the formation of a first optical package according to some embodiments. Fig. Figures 13-14 illustrate the bonding of the first optical package to the interposer according to some embodiments. Fig. Figures 15A-15G illustrate an embodiment in which an opening in the first semiconductor device is filled, according to some embodiments. Fig. Figures 16A-16B illustrate a melt bonding process with wire bonding according to some embodiments. Fig. Figures 17A-17B illustrate a fusion bonding process with vias according to some embodiments. Fig. Figures 18A-18D illustrate the bonding of the optical interposer with a storage device according to some embodiments. Fig. Figures 19A-19D illustrate the arrangement of the storage device between the optical interposer and the first semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed.

[0007] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0008] Embodiments are now discussed in relation to specific configurations in which one or more laser dies are embedded in a first semiconductor device to form a “Compact Universal Photonic Engine” (COUPE), and the first semiconductor device is bonded to an optical interposer while still in wafer form. However, the embodiments presented here are intended only for illustration and are not meant to limit the configurations to the exact descriptions in the form discussed. Rather, the configurations discussed can be integrated into a wide variety of implementations, and all such implementations are intended to be fully included within the scope of these configurations.

[0009] We now turn Fig. 1 to, where an initial structure of an optical interposer 100 (see Fig. 5) is illustrated according to some embodiments. In the Fig. In the illustrated particular embodiment, the optical interposer 100 is a photonic integrated circuit (PIC) and at this stage comprises a first substrate 101, a first insulating layer 103 and a layer of material 105 for a first active layer 201 made of first optical components 203 (in Fig. 1 not illustrated separately, but further below in relation to Fig. (2 illustrated and discussed). In one embodiment, at the beginning of the manufacturing process of the optical interposer 100, the first substrate 101, the first insulating layer 103, and the layer of material 105 for the first active layer 201 of the first optical components 203 can together form part of a silicon-on-insulator (SOI) substrate. Let us first consider the first substrate 101. The first substrate 101 can be a semiconductor material such as silicon or germanium, a dielectric material such as glass, or any other suitable material that allows structural support for overlying devices.

[0010] The first insulating layer 103 can be a dielectric layer separating the first substrate 101 from the overlying first active layer 201, and in some embodiments can additionally serve as a section of plating material surrounding the subsequently fabricated first optical components 203 (as discussed further below). In one embodiment, the first insulating layer 103 can be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations thereof, or the like, formed by a process such as implantation (for example, to form a buried oxide layer (BOX layer)), or alternatively, it can be deposited onto the first substrate 101 by a deposition process such as chemical evaporation, atomic layer deposition, physical evaporation, combinations thereof, or the like.However, any suitable material and any suitable manufacturing process can be used.

[0011] The material 105 for the first active layer 201 is initially (before structuring) a conformal layer of material used to begin fabricating the first active layer 201 of the first optical components 203. In one embodiment, the material 105 for the first active layer 201 can be a translucent material that can be used as a core material for the desired first optical components 203, such as a semiconductor material like silicon, germanium, silicon-germanium, combinations thereof, or the like. In other embodiments, the material 105 for the first active layer 201 can be a dielectric material such as silicon nitride or the like, while in still other embodiments, the material 105 for the first active layer 201 can be III-V materials, lithium niobate materials, or polymers.In embodiments where the material 105 of the first active layer 201 is deposited, the material 105 for the first active layer 201 can be deposited by a process such as epitaxial growth, chemical evaporation, atomic layer deposition, physical evaporation, combinations thereof, or the like. In other embodiments where the first insulator layer 103 is formed using an implantation process, the material 105 of the first active layer 201 can initially be part of the first substrate 101—prior to the implantation process for forming the first insulator layer 103. However, any suitable materials and manufacturing processes can be used to form the material 105 of the first active layer 201.

[0012] Fig. Figure 2 illustrates that once the material 105 for the first active layer 201 is ready, the first optical components 203 for the first active layer 201 are fabricated using the material 105 for the first active layer 201. In embodiments, the first optical components 203 of the first active layer 201 can comprise components such as optical waveguides (for example, ribbed waveguides, finned waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (for example, grating couplers, edge couplers, etc.), directional couplers, optical modulators (for example, silicon photonic Mach-Zehnder switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, opto-electrical converters (for example, PN junctions), electro-optical converters, lasers, combinations thereof, or the like.However, any suitable first optical component 203 can be used.

[0013] To begin forming the first active layer 201 of the first optical components 203 from the initial material 105, the material 105 for the first active layer 201 can be structured into the desired shapes for the first active layer 201 of the first optical components 203. In one embodiment, the material 105 for the first active layer 201 can be structured, for example, using one or more photolithographic masking and etching processes. However, any suitable method for structuring the material 105 for the first active layer 201 can be used. For some of the first optical components 203, such as waveguides or edge couplers, the structuring process can constitute all or at least most of the fabrication used to form these first optical components 203.

[0014] Fig. Figure 3 illustrates that for those components that undergo further manufacturing processes, such as silicon photonic Mach-Zehnder switches that use resistance heating elements, additional processing can be performed either before or after structuring the material for the first active layer 201. For example, implantation processes, additional deposition and structuring processes for various materials (e.g., resistance heating elements, III-V materials for transducers), combinations of all these processes, or the like can be used to further support the fabrication of the various desired first optical components 203. In a particular embodiment, and as specifically shown in Figure 3, the following applies: Fig. As illustrated in Figure 3, in some embodiments, epitaxial deposition of a semiconductor material 301, such as germanium (which is used, for example, for the modulation and conversion of electrical / optical signals), can be carried out on a structured section of the material 105 of the first active layer 201. In such an embodiment, the semiconductor material 301 can be epitaxially grown to support the fabrication of, for example, a photodiode for an opto-electrical converter. All such fabrication processes can be used and all suitable first optical components 203 can be produced, and all such combinations are to be fully included within the scope of the embodiments.

[0015] Fig. Figure 4 illustrates that after the formation of the individual first optical components 203 of the first active layer 201, a second insulating layer 401 can be deposited to cover the first optical components 203 and to provide additional plating material. In one embodiment, the second insulating layer 401 can be a dielectric layer that separates the individual components of the first active layer 201 from each other and from the overlying structures, and can additionally serve as a further section of the plating material surrounding the first optical components 203. In one embodiment, the second insulating layer 401 can be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations thereof, or the like, formed by a deposition process such as chemical evaporation, atomic layer deposition, physical evaporation, combinations thereof, or the like.Once the material of the second insulating layer 401 has been deposited, it can be planarized, for example, using a chemical-mechanical polishing process, either to planarize a top surface of the second insulating layer 401 (in embodiments where the second insulating layer 401 is intended to completely cover the first optical components 203) or, alternatively, to planarize the second insulating layer 401 with top surfaces of the first optical components 203. However, any suitable material and any suitable manufacturing process can be used.

[0016] Fig. Figure 5 illustrates that once the first optical components 203 of the first active layer 201 have been manufactured and the second insulating layer 401 has been formed, first metallization layers 501 are formed to electrically connect the first active layer 201 of the first optical components 203 to a control circuit, to each other, and to subsequently attached devices (in Fig. 5 not illustrated, but further below with reference to Fig. (8 illustrated and described). In one embodiment, the first metallization layers 501 are formed from alternating layers of dielectric and conductive material and can be formed by any suitable processes (such as deposition, damascening, double damascening, etc.). In certain embodiments, several metallization layers can be used to connect the various first optical components 203, but the exact number of first metallization layers 501 depends on the design of the optical interposer 100.

[0017] Additionally, during the fabrication of the first metallization layers 501, one or more second optical components 503 can be formed as part of the first metallization layers 501. In some embodiments, the second optical components 503 of the first metallization layers 501 can comprise components such as couplers (for example, edge couplers, grating couplers, etc.) for connecting to external signals, optical waveguides (for example, ribbed waveguides, finned waveguides, buried channel waveguides, diffused waveguides, etc.), optical modulators (for example, silicon photonic Mach-Zehnder switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, opto-electrical converters (for example, PN junctions), electro-optical converters, lasers, combinations thereof, and the like.However, any suitable optical components can be used for the one or more second optical components 503.

[0018] In one embodiment, the one or more second optical components 503 can be formed by initially depositing a material for the one or more second optical components 503. In one embodiment, the material for the one or more second optical components 503 can be a dielectric material such as silicon nitride, silicon oxide, combinations thereof, or the like, or a semiconductor material such as silicon, deposited using a deposition method such as chemical evaporation, atomic layer deposition, physical evaporation, combinations thereof, or the like. However, any suitable material and any suitable deposition method can be used.

[0019] Once the material for the one or more second optical components 503 has been deposited or otherwise formed, it can be structured into the desired shapes for the one or more second optical components 503. In one embodiment, for example, the material of the one or more second optical components 503 can be structured using one or more photolithographic masking and etching techniques. However, any suitable method for structuring the material for the one or more second optical components 503 can be used.

[0020] For some of the one or more second optical components 503, such as waveguides or edge couplers, the structuring process can constitute all or at least the majority of the fabrication used to form these components. Additionally, for those components that undergo further fabrication processes, such as silicon photonic Mach-Zehnder switches that use resistance heating elements, further processing can be performed either before or after structuring the material for the one or more second optical components 503. For example, implantation processes, additional deposition and structuring processes for various materials, combinations of all these processes, or the like can be used to further facilitate the fabrication of the various desired second optical components 503.All such manufacturing processes can be used and all suitable second optical components 503 can be manufactured, and all such combinations are to be fully included within the scope of the embodiments.

[0021] Once one or more second optical components 503 of the first metallization layers 501 have been fabricated, a first bonding layer 505 is formed over the first metallization layers 501. In one embodiment, the first bonding layer 505 can be used for dielectric-to-dielectric and metal-to-metal bonding. According to some embodiments, the first bonding layer 505 is formed from a first dielectric material 509, such as silicon oxide, silicon nitride, or the like. The first dielectric material 509 can be deposited using any suitable method, such as CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD, atomic layer deposition (ALD), or the like. However, any suitable materials and deposition methods can be used.

[0022] Once the first dielectric material 509 has been formed, initial openings are created within it to expose conductive sections of the underlying layers in preparation for the formation of the first bond pads 507 within the first bonding layer 505. These openings can then be filled with a seed layer and plate metal to form the first bond pads 507 within the dielectric material 509. The seed layer can be deposited across the entire surface of the first dielectric material 509, the exposed conductive sections of the underlying layers, and the sidewalls of the openings. The seed layer can include a copper layer.The nucleation layer can be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), depending on the desired materials. The plate metal can be deposited over the nucleation layer by a plating process, such as electrical or chemical plating. The plate metal can comprise copper, a copper alloy, or the like. The plate metal can be a filler material. A barrier layer (not shown separately) can be deposited in front of the nucleation layer over the top surfaces of the first dielectric material 509 and the sidewalls of the openings and the second opening. The barrier layer can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0023] After the initial openings are filled, a planarization process, such as CMP, is performed to remove excess sections of the seed layer and plate metal, thereby forming the first bond pads 507 within the first bonding layer 505. In some embodiments, a bond pad via (not shown separately) can also be used to connect the first bond pads 507 to underlying conductive parts and, through these conductive parts, to connect the first bond pads 507 to the first metallization layers 501.

[0024] Additionally, the first bonding layer 505 can also include one or more third optical components 511 integrated into the first bonding layer 505 to serve as a bridge for incoming light (for example, from the laser die 600, which will be described further below). In such an embodiment, the one or more third optical components 511 can be fabricated prior to the deposition of the first dielectric material 509 using similar methods and materials as the one or more second optical components 503 (described above), such as being waveguides and other structures formed at least partially by a deposition and structuring process. However, any suitable structures, materials, and fabrication methods can be used.

[0025] Fig. Figures 6A-6P illustrate a fabrication process for forming a laser die 600, which is connected to the optical interposer 100. The laser die 600 is used to generate light to power the other optical components (for example, the first optical components 203, the second optical components 503, the third optical components 511, etc.) and can include light-generating structures such as a laser diode 602 (in Fig. 6A is not illustrated separately, but further below in relation to Fig. (6B illustrated and discussed). In certain embodiments, the laser diode 602 can be a Fabry-Perot diode and can be based on III-V materials, II-VI materials, or other suitable groups of materials.

[0026] In one embodiment, the formation of the laser die 600 can be initiated by forming a first contact 603, a first buffer layer 605, a first active diode layer 607, multiple quantum wells (MQWs), a second buffer layer 608, a bridge material 609, and a second contact 611 over a second substrate 601. In one embodiment, the second substrate 601 can be a material that can be used not only as a structural support but also as a seed material for the epitaxial growth of overlying materials and can, for example, be a 2-inch or 4-inch wafer made of material.In certain embodiments where the laser die 600 uses III-V materials to form the desired lasers, the second substrate 601 can be a material such as InP, GaAs, or GaSb, while in embodiments where the laser die 600 uses II-VI materials to form the desired lasers, the second substrate 601 can be a material such as GaAs, CdTe, or ZnSe. In further embodiments, the second substrate 601 can be sapphire or a semiconductor material. Any suitable materials can be used.

[0027] The first contact 603 is formed over the second substrate 601. The first contact 603 forms part of the laser diode 602, which is used to emit the desired laser. In an embodiment where the laser die 600 uses III-V compounds, the first contact 603 is a compound such as InP, GaN, InN, AlN, AlxGa(1-x)N, AlxIn(1-x)N, AlxInyGa(1-xy)N, combinations thereof, or the like. Additionally, in embodiments where the laser die 600 uses II-VI compounds, the first contact 603 can also be a III-V material such as GaAs, InP, GaSb, combinations thereof, or the like.

[0028] Additionally, the first contact 603 can be doped with a dopant to support the formation of the laser diode 602 (for example, the np-diode) to generate the desired laser. In embodiments where n-type conductivity is desired for the first contact 603, it can be doped with an n-type dopant such as phosphorus, arsenic, antimony, bismuth, lithium, combinations of these substances, or the like. In other embodiments where p-type conductivity is desired for the first contact 603, it can be doped with p-type dopants such as boron, aluminum, gallium, indium, combinations thereof, or the like. However, any suitable dopant can be used.

[0029] In some embodiments, the first contact 603 is formed, for example, by an epitaxial growth process such as molecular beam epitaxy (MBE), although other processes, such as hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), or the like, can also be used. The first contact 603 is preferably doped in situ during its formation, although other processes, such as ion implantation or diffusion, can also be used.

[0030] The first buffer layer 605 is formed over the first contact 603 and is used to facilitate the epitaxial growth of overlying layers (for example, the first active diode layer 607) from the material of the first contact 603 to the material of the layer above it. In an embodiment where the laser die 600 uses III-V compounds, the first buffer layer 605 is a compound such as InGaAsP, InGaAlAs, InGaAs, combinations thereof, or the like. Additionally, in embodiments where the laser die 600 uses II-VI compounds, the first buffer layer 605 can be a II-VI material such as BeMgZnSe, BeZnCdSe, BeTe, combinations thereof, or the like.Additionally, the first buffer layer 605 can be deposited using an epitaxial growth process such as molecular beam epitaxy (MBE), although other processes such as hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), or the like may also be used, and can be doped in a similar manner to the first contact 603. However, any suitable material and any suitable deposition method may be used.

[0031] The first active diode layer 607 is formed above the first buffer layer 605. The first active diode layer 607 is designed, among other things, to control the generation of light at desired wavelengths. For example, by adjusting and controlling the proportional composition of the elements in the first active diode layer 607, the band gap of the materials in the first active diode layer 607 can be adjusted, thereby setting the wavelength of the light that is ultimately emitted.

[0032] The first active diode layer 607 comprises multiple quantum wells (MQWs). MQW structures in the first active diode layer 607 in embodiments using III-V materials can, for example, be layers of InAlGaAs, InGaN, GaN, AlxInyGa (1-x-y)N (where 0<=x<=1) or the like, while in embodiments using II-VI-based materials, the first active diode layer 607 can comprise materials such as BeZnCdSe. The first active diode layer 607 can comprise any number of quantum wells, such as 5 to 20 quantum wells. The MQWs are preferably epitaxially grown using the first buffer layer 605 as a nucleation layer by metal-organic chemical vapor deposition (MOCVD), although other processes, such as MBE, HVPE, LPE, or the like, can also be used.

[0033] The second buffer layer 608 is optionally formed above the first active diode layer 607 and is used to facilitate the epitaxial growth of overlying layers (for example, the bridge material 609) from the material of the first active diode layer 607 to the material of the layer above it. In an embodiment where the laser die 600 uses III-V compounds, the second buffer layer 608 is a compound such as InGaAsP, InGaAlAs, InGaAs, combinations thereof, or the like. Additionally, in embodiments where the laser die 600 uses II-VI compounds, the second buffer layer 608 can be a II-VI material such as BeMgZnSe, BeZnCdSe, BeTe, combinations thereof, or the like.Additionally, the second buffer layer 608 can be deposited using an epitaxial growth process such as molecular beam epitaxy (MBE), although other processes such as hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), or the like may also be used, and can be doped in a manner opposite to that of the first contact 603, for example, by being doped to a p-type conductivity while the first contact 603 is doped to an n-type conductivity. However, any suitable material and any suitable deposition method may be used.

[0034] The bridge material 609 is formed to facilitate the epitaxial growth of an overlying layer (for example, the second contact 611) from the material of the second buffer layer 608 to the material of the overlying layer. In an embodiment where the laser die 600 uses III-V compounds, the bridge material 609 is a compound such as InP or the like. Additionally, in embodiments where the laser die 600 uses II-VI compounds, the bridge material 609 can be a II-VI material such as BeMgZnSe, BeZnCdSe, BeTe, combinations thereof, or the like. Furthermore, the bridge material 609 can be doped using dopants whose conductivity is opposite to that of the first contact 603, for example, by doping it to a p-type conductivity when the first contact 603 is doped to an n-type conductivity.The web material 609 can be one or more layers and can be deposited using an epitaxial growth process such as molecular beam epitaxy (MBE), although other processes such as hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), or the like may also be used. However, any suitable material and any suitable deposition method can be used.

[0035] The second contact 611 is formed above the bridge material 609. The second contact 611 forms the second part of the laser diode 602, which is used to emit light in conjunction with the first contact 603. In an embodiment in which the laser die 600 is based on III-V materials, the second contact 611 comprises a III-V compound, such as InAlAs, GaN, InN, AlN, AlxGa(1-x)N, AlxIn(1-x)N, AlxInyGa(1-xy)N, combinations thereof, or the like, doped with a dopant of a second conductivity type (for example, p-GaN) that is opposite to the first conductivity type in the first contact 603. In another embodiment, where the laser die 600 is based on II-VI materials, the second contact 611 can be a II-VI material such as BeTe, BeMgZnSe, BeZnCdSe, combinations thereof, or the like. The second contact 611 can be formed, for example, by an epitaxial growth process such as MOCVD.However, any suitable materials and any other suitable processes, such as HVPE, LPE, MBE or the like, can be used.

[0036] Fig. Figure 6B illustrates the structuring of the second contact 611, the bridge material 609, the second buffer layer 608, the first active diode layer 607, the first buffer layer 605, and the first contact 603 to form the layered structure of the desired laser diode 602. In one embodiment, the second contact 611 and the bridge material 609 can be structured, for example, using a first photolithographic masking and etching process. Once the second contact 611 and the section of the bridge material 609 have been structured, the second buffer layer 608, the first active diode layer 607, and the first buffer layer 605 can be structured, for example, using a second photolithographic masking and etching process.Finally, the first contact 603 can be structured, for example, using a third photolithographic masking and etching process to achieve adiabatic tapering, thus facilitating evanescent coupling with underlying layers. However, any suitable structuring process and any number of structuring processes can be used to obtain a desired structure for the laser.

[0037] Fig. Figure 6B further illustrates the deposition of a first passivation layer 613 over the structure. In one embodiment, the first passivation layer 613 is formed from a material used for electrical insulation and to protect the structure from overlying structures. This material can be, for example, silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. It can be deposited using a chemical evaporation process, an atomic layer deposition process, a physical evaporation process, combinations thereof, or the like. However, any suitable materials and any suitable deposition methods can be used.

[0038] Fig. Figure 6C illustrates structuring the first passivation layer 613 to form through-holes via the first passivation layer 613 and expose the first contact 603 and the second contact 611. In one embodiment, the structuring can be carried out, for example, using a photolithographic masking and etching process. However, any suitable structuring process can be used.

[0039] Fig. Figure 6C further illustrates the deposition of contacts 615 through the via openings and in electrical connection with the first contact 603 and the second contact 611. In one embodiment, the contacts 615 can be a conductive material such as copper, aluminum, gold, tungsten, combinations thereof, or the like, deposited using a process such as chemical evaporation, atomic layer deposition, physical evaporation, plating, combinations thereof, or the like. However, any suitable material and any suitable manufacturing process can be used.

[0040] Fig. Figure 6D illustrates the deposition of a second passivation layer 617 and a third passivation layer 619 over the contacts 615. In one embodiment, the second passivation layer 617 can be an insulating and protective material such as silicon dioxide (SiO2), silicon nitride, silicon oxynitride, combinations thereof, or the like, deposited using a deposition process such as chemical evaporation, atomic layer deposition, physical evaporation, combinations thereof, or the like. However, any suitable material and any suitable manufacturing process can be used.

[0041] The third passivation layer 619 is deposited over the second passivation layer 617 to help protect sections of the second passivation layer 617 during subsequent structuring processes. In one embodiment, the third passivation layer 619 can be an insulating and protective material different from the second passivation layer 617, such as silicon oxide, silicon oxynitride, combinations thereof, or the like, deposited using a deposition process such as chemical evaporation, atomic layer deposition, physical evaporation, combinations thereof, or the like. However, any suitable material and any suitable manufacturing process can be used.

[0042] Fig. Figure 6E illustrates a structuring of the second passivation layer 617 and the third passivation layer 619 to form contact via openings through the second passivation layer 617 and the third passivation layer 619 and to expose the contacts 615. In one embodiment, the structuring can be carried out, for example, using a photolithographic masking and etching process. However, any suitable structuring process can be used.

[0043] Fig. Figure 6E further illustrates the deposition of conductive protective layers 621 through the contact via openings and in electrical connection with the contacts 615. In one embodiment, the conductive protective layers 621 can be one or more layers of conductive materials that support etch selectivity and can also help to facilitate subsequently formed conductive extensions 623 (which are in Fig. 6E are not illustrated, but further below in relation to Fig. 6F illustrated and discussed) to seal (for example, against moisture) to help prevent process damage to the conductive extensions 623. In certain embodiments, the conductive protective layers 621 can be materials such as tantalum, titanium, tantalum nitride, titanium nitride, combinations thereof, or the like, deposited using a process such as chemical evaporation, atomic layer deposition, physical evaporation, plating, combinations thereof, or the like. However, any suitable material and any suitable manufacturing process may be used.

[0044] Fig. Figure 6F illustrates the formation of the conductive extensions 623, which make contact with the conductive protective layers 621. In one embodiment, the conductive extensions 623 can be a conductive material, such as a metal like aluminum, copper, germanium, combinations thereof, or the like, deposited using a deposition process such as plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, plating, combinations thereof, or the like. However, any suitable material and any suitable manufacturing process can be used.

[0045] Fig. Figure 6F further illustrates that the conductive extensions 623 are structured. In one embodiment where the conductive extensions 623 are plated, they can be structured during the deposition process, while in other processes, they can be structured after deposition, for example, using a photolithographic masking and etching process. However, any suitable process can be used.

[0046] Fig. Figure 6G illustrates the deposition of a fourth passivation layer 625 over the conductive extensions 623. In one embodiment, the fourth passivation layer 625 is a protective dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, deposited using a deposition process such as chemical evaporation, atomic layer deposition, physical evaporation, combinations thereof, or the like. However, any suitable materials and processes may be used to form the fourth passivation layer 625.

[0047] Fig. Figure 6H illustrates that once the fourth passivation layer 625 has been formed, several of the laser diodes 602 (where in Fig. 6H (multiple structures on every second substrate 601 are illustrated) can be bonded to a semiconductor substrate 626 to form a reconstituted wafer 628. In one embodiment, the semiconductor substrate 626 can be a semiconductor material used for structural support during subsequent processing and as a heat sink to assist in the event of laser overheating problems, and can be, for example, a silicon wafer, a silicon-germanium wafer, a silicon-on-insulator wafer, or the like. In some embodiments, the semiconductor substrate 626 is a 12-inch wafer, although any suitable size and material can be used.

[0048] In one embodiment, the multiple laser diodes 602 can be bonded to the semiconductor substrate 626, for example, using a fusion bonding process. In some embodiments, for instance, the fusion bonding process can activate areas of the fourth passivation layer 625 and the semiconductor substrate 626, and then the fourth passivation layer 625 and the semiconductor substrate 626 are brought into physical contact to initiate the bonding process. This can further strengthen the bond. However, any other suitable attachment process, including the use of an adhesive, can also be used.

[0049] Fig. Figure 6I illustrates a top view of the reconstituted wafer 628, wherein Fig. 6H a cross-sectional view of the reconstituted wafer 628 along line HH' in Fig. Figure 6I illustrates this. As can be seen in this top view, the reconstituted wafer 628 comprises several of the individual laser diodes 602 attached to the semiconductor substrate 626. Fig. Figure 6I illustrates ten individual laser diodes 600, but any suitable number of laser diodes 600 can be attached to the semiconductor substrate 626.

[0050] Fig. Figure 6J illustrates the removal of the second substrate 601 to expose the first contacts 603 of the laser dies 600. In one embodiment, the second substrate 601 can be removed using a planarization process, such as a chemical-mechanical polishing process, a grinding process, or the like. In other embodiments, the second substrate 601 can be removed using one or more etching processes to expose the first contacts 603. Any suitable method can be used.

[0051] Fig. Figure 6K illustrates that once the first contacts 603 have been exposed, a gap-filling material 627 is deposited to fill the regions between the individual laser dies 600 and to re-cover the now exposed first contacts 603. In one embodiment, the gap-filling material 627 can be a dielectric material, which can also serve as a bottom-side plating material. In a particular embodiment, the gap-filling material 627 can be silicon oxide, silicon nitride, spin-on glass, combinations thereof, or the like, deposited using a process such as chemical evaporation, physical evaporation, atomic layer deposition, combinations thereof, or the like. However, any suitable material and any suitable deposition process can be used.

[0052] Fig. Figure 6K further illustrates that the gap-filling material 627, once deposited, can be planarized and thinned. In one embodiment, the gap-filling material 627 can be planarized, for example, using a chemical-mechanical planarization process, a grinding process, or the like. In some embodiments, the gap-filling material 627 can be planarized such that it has a thickness over the first contacts 603 suitable for optical coupling between the first contact 603 and subsequently placed devices. In one particular embodiment, the gap-filling material 627 can be formed to have a thickness between about 5 µm and about 8 µm. However, any suitable material, any suitable deposition method, and any suitable thickness can be used.

[0053] Fig. Figure 6L illustrates the formation of a dielectric layer 629 over the gap-filling material 627 once the gap-filling material 627 has been deposited and planarized. In one embodiment, the dielectric layer 629 can be one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, deposited using a deposition process such as chemical evaporation, atomic layer deposition, physical evaporation, combinations thereof, or the like. In a particular embodiment, the dielectric layer 629 can be a triple layer of materials, such as a first layer of silicon nitride, a second layer of silicon oxide, and a third layer of silicon nitride. However, any suitable number of layers and any suitable materials can be used.

[0054] Fig. Figure 6M illustrates that once the gap-filling material 627 has been deposited and planarized, and the dielectric layer 629 has been deposited, conductive vias 635 can be formed to establish electrical contact with the conductive extensions 623. In one embodiment, the conductive vias 635 can be formed by initially depositing and structuring a photoresist and creating openings through the dielectric layer 629 and the second passivation layer 617. Once the openings have been formed, they are then filled with a conductive material, such as copper, using a seed layer and a plating process to fill the openings. Once the openings have been filled, the photoresist is removed, leaving the conductive vias 635 extending out from the dielectric layer 629.However, any suitable manufacturing process can be used.

[0055] Fig. Figure 6N illustrates the deposition of a second dielectric layer 637 to cover and submerge the conductive vias 635 to protect them until further processing. In one embodiment, the second dielectric layer 637 is a dielectric material such as silicon oxide, BCB, SiNC, combinations thereof, or the like, deposited using a deposition process such as chemical evaporation, atomic layer deposition, physical evaporation, or the like. However, any suitable material and deposition process may be used.

[0056] Fig. Figure 6O illustrates the beginning of a singulation process that can be used to singulate the individual laser dies 600. In one embodiment, and as shown in Fig. As illustrated in Figure 60, the singulation process is initiated by etching openings between the individual laser dies 600 and at least partially, but not completely, into the semiconductor substrate 626. However, any suitable method for partially separating the laser dies 600 can also be used, such as a laser dicing process.

[0057] Fig. Figure 6P illustrates that once the laser dies 600 have been partially separated, the semiconductor substrate 626 can be thinned to expose the openings and complete the singulation. In one embodiment, the thinning can be carried out, for example, using a planarization process such as a grinding process, a chemical-mechanical polishing process, a combination thereof, or the like. However, any suitable thinning process can be used.

[0058] Fig. Figure 7A illustrates a first semiconductor device 700, which is bonded to the optical interposer 100 together with the laser die 600. In some embodiments, the first semiconductor device 700 is an electronic integrated circuit (EIC – for example, a device without optical devices) and may comprise a semiconductor substrate 703, a layer of active devices 705, and an overlying interconnect structure 707. In one embodiment, the semiconductor substrate 703 may resemble the first substrate 101 (for example, a semiconductor material such as silicon or silicon-germanium in a wafer form), the active devices 705 may be transistors, capacitors, resistors, and the like formed over the semiconductor substrate 703, and the interconnect structure 707 may resemble the first metallization layers 501 (without optical components).However, any suitable device can be used.

[0059] In one embodiment, the first semiconductor device 700 can be configured to cooperate with the optical interposer 100 for a desired functionality. In some embodiments, the first semiconductor device 700 can be a logic die, a high-bandwidth memory module (HBM module), an xPU, a 3DIC die, a CPU, a GPU, a SoC die, a MEMS die, combinations thereof, or the like. Any suitable device with any suitable functionality can be used, and all such devices are intended to fall fully within the scope of the embodiments.

[0060] Fig. Figure 7A also illustrates that as part of the fabrication of the first semiconductor device 700, a first region 709 (in Fig. 7A (highlighted by the dashed box) is formed within the layer of active devices 705 and the overlying interconnect structure 707. In one embodiment, the first region 709 is a location where the laser die 600 is subsequently embedded into the first semiconductor device 700 to make the first semiconductor device 700 a light-emitting wafer module. The first region 709 is formed by not placing any functional devices (for example, transistors or conductive routings) in the first region 709 during the fabrication of the layer of active devices 705 and the interconnect structure 707. However, any suitable fabrication method may be used.

[0061] Fig. Figure 7B illustrates a top view of a sealing ring 702 that can enclose the functional structures of the first semiconductor device 700 (for example, the layer of active devices 705 and the overlying interconnect structure 707) and separate the first region 709 from the remainder of the first semiconductor device 700. In some embodiments, the sealing ring 702 incorporates metal conductors and vias in the dielectric layers of the interconnect structure 707. The sealing ring 702 can be fabricated concurrently with the conductive elements of the interconnect structure 707, for example, using damascening and / or dual-damascening processes. However, any suitable fabrication process can be used.

[0062] We now return to Fig. 7A back. Fig. Figure 7A also illustrates the attachment of a support substrate 711. In one embodiment, the support substrate 711 can be a support material that is transparent to the wavelength of the light whose use is desired, such as silicon, and can be attached, for example, using an adhesive (in Fig. (7A not illustrated separately). In other embodiments, however, the support substrate 711 can be bonded, for example, using a bonding process. Any suitable method for attaching the support substrate 711 can be used.

[0063] Fig. Figure 7C illustrates the formation of a lens 713 within the support substrate 711. In one embodiment, a photosensitive material (in Fig. (7C not illustrated separately) are deposited, exposed, developed, and melted to form the desired shape for lens 713 within a mask. Once the mask is present, the formation of lens 713 can be carried out, for example, using an anisotropic etching process, such as a reactive ion etching process, which uses the mask as a sacrificial mask. Specifically, as the etching process progresses to etching the support substrate 711, it also etches the mask material. As the thinner sections of the mask are removed, additional sections of the support substrate 711 are exposed to the etching process until the mask is partially, mostly, or completely consumed. In this way, the shape of the mask is transferred to the support substrate 711, thereby forming lens 713 within the support substrate 711. However, any suitable process can be used.

[0064] Fig. Figure 7C further illustrates the formation of an anti-reflective coating (ARC) 715 over the lens 713. In one embodiment, the ARC 715 can be one or more layers of materials that help prevent unwanted reflections when light is focused through the lens 713. In a particular embodiment, the one or more layers can be materials such as silicon oxide, silicon nitride, combinations thereof, or the like, formed using processes such as chemical evaporation, atomic layer deposition, physical evaporation, oxidation, nitridation, combinations thereof, or the like.

[0065] In one particular embodiment, the ARC 715 can be formed using a first layer of silicon oxide and a first layer of silicon nitride deposited over the first silicon oxide layer. A second layer of silicon oxide and a second layer of silicon nitride are deposited over the first silicon oxide and first silicon nitride layers, forming an alternating stack of silicon oxide and silicon nitride. However, any suitable combination of materials can be used.

[0066] Fig. Figure 7D illustrates the removal of material from the first region 709 to form a first opening 717 and provide space for the placement of the laser die 600. In one embodiment, the material removal can be carried out, for example, using one or more anisotropic etching processes, such as one or more reactive ion etching processes. However, any suitable ablation process or combination of ablation processes can be used.

[0067] In one embodiment, the first opening 717 can be formed with dimensions such that the laser die 600 fits precisely into the first opening 717. Therefore, the exact dimensions of the first opening 717 are based at least partially on the dimensions of the laser die 600. In some embodiments, however, the first opening 717 can be formed such that it has a first width W1 between approximately 1 mm and approximately 4 mm and a first depth D1 between approximately 4 µm and approximately 8 µm. However, any suitable dimensions can be used.

[0068] Furthermore, it illustrates Fig. Although Figure 7D shows that the first opening 717 is formed such that it extends through the interconnect structure 707 and the layer of active devices 705, this is for illustrative purposes only and is not intended to limit the embodiments. Rather, the first opening 717 can be formed such that it extends through any suitable number of layers, for example, also through the semiconductor substrate 703 and into the support substrate 711. Any suitable depth can be used.

[0069] Fig. Figure 7E illustrates the embedding of one or more laser dies 600 (where only a single laser die 600 is illustrated) into the first opening 717 of the first semiconductor device 700. In one embodiment, the one or more laser dies 600 can be embedded by, for example, inserting the laser die 600 into the first opening 717 using a pick-and-place process. If desired, the laser die 600 can also be bonded to the exposed surface of the semiconductor substrate 703. However, any suitable process can be used.

[0070] Once the laser die 600 has been inserted into the first opening 717, it can either be planar with the first semiconductor device 700 or extend out of it. In such an embodiment, the laser die 600 can extend out of the first semiconductor chip 700 by a first height H1 of between approximately 0.1 µm and approximately 3 µm. However, any suitable dimensions can be used.

[0071] Fig. Figure 7F illustrates that once the laser die 600 has been inserted into the first opening 717, a sealing material 719 can be deposited to fill and seal the remainder of the first opening 717 and to anchor the laser die 600 in place. In one embodiment, the sealing material 719 can be an oxide such as silicon dioxide or a polymer such as BCB or SiNC, although any suitable material may be used. In one embodiment, the sealing material 719 can be deposited using a process such as chemical evaporation, atomic layer deposition, flowable chemical evaporation, spin deposition, combinations thereof, or the like, followed by a structuring process. However, any suitable deposition process may be used.

[0072] Fig. Figure 7G illustrates a planarization process used to planarize the laser die 600 with the interconnect structure 707. In one embodiment, the planarization process can be a chemical-mechanical polishing process, using etchants and abrasives to remove exposed material. However, any suitable planarization process, such as grinding or even one or more etching processes, can be used.

[0073] Fig. Figure 7G further illustrates the simultaneous formation of two bond pads 723 in the interconnect structure 707 and the second dielectric layer 637, thereby forming a second bond layer 721 within the interconnect structure 707 to provide points for an electrical connection between the interconnect structure 707 and the laser die 600. In one embodiment, the second bond pads 723 can resemble the first bond pads 507. However, any suitable devices can be used.

[0074] Furthermore, it illustrates Fig. Although it is shown that the laser die 600 extends only through the interconnect structure 707 and the layer of active devices 705, this is for illustrative purposes only and is not intended to limit the presented embodiments to this example alone. Rather, the laser die 600 can also be embedded in such a way that it extends into or through the semiconductor substrate 703 and the support substrate 711. Any suitable depth can be used.

[0075] Fig. Figure 8 illustrates bonding the first semiconductor device 700 (while the first semiconductor device 700 remains part of a wafer) together with the embedded laser die 600 (illustrated in simplified form for clarity) to the first bonding layer 505 of the optical interposer 100 (which remains part of a wafer). In one particular embodiment, the first semiconductor device 700, the laser die 600, and the first bonding layer 505 can be bonded using a dielectric-to-dielectric and metal-to-metal bonding process. However, any suitable bonding process can be used.

[0076] In a particular embodiment employing a dielectric-to-dielectric and metal-to-metal bonding process, the process can be initiated by activating the surfaces of the first semiconductor device 700, the laser die 600, and the surfaces of the first bonding layer 505. Activating the top surfaces of the first bonding layer 505, the first semiconductor device 700, and the laser die 600 can, for example, include dry treatment, wet treatment, plasma treatment, contact with an inert gas plasma, contact with H₂, contact with N₂, contact with O₂, combinations thereof, or the like. In embodiments employing wet treatment, for example, RCA cleaning can be used. In another embodiment, the activation process can include other types of treatment.The activation process supports the bonding of the first bonding layer 505, the first semiconductor device 700 and the laser die 600.

[0077] After the activation process, the optical interposer 100, the first semiconductor device 700, and the laser die 600 can be cleaned, for example, using a chemical rinse. Then, the laser die 600 and the first semiconductor device 700 are aligned in a wafer-to-wafer alignment process and brought into physical contact with the optical interposer 100. The optical interposer 100, the first semiconductor device 700, and the laser die 600 are then subjected to heat treatment and contact pressure to bond them. For example, the optical interposer 100, the first semiconductor device 700 and the laser die 600 can be subjected to a pressure of about 200 kPa or less and a temperature between about 25°C and about 250°C to fuse the optical interposer 100, the first semiconductor device 700 and the laser die 600.The optical interposer 100, the first semiconductor device 700, and the laser die 600 can then be exposed to a temperature at or above the eutectic point for the material of the first bond pads 507 and the second bond pads 723, for example, between about 150°C and about 650°C, to fuse the metal. In this way, the optical interposer 100, the first semiconductor device 700, and the laser die 600 form a dielectric-to-dielectric and metal-to-metal bonded device. In some embodiments, the bonded devices are subsequently baked, annealed, pressed, or otherwise treated to strengthen or complete the bond.

[0078] Furthermore, although the above description describes a dielectric-to-dielectric and metal-to-metal bonding process, this is for illustrative purposes only and should not be interpreted as limiting. In other embodiments, the optical interposer 100 can be bonded to the first semiconductor device 700 and the laser die 600 by metal-to-metal bonding or another bonding process. For example, the first semiconductor device 700, the laser die 600, and the optical interposer 100 can be bonded by metal-to-metal bonding achieved by fusing conductive elements. Any suitable bonding process can be used, and all such methods are fully covered by the scope of these embodiments.

[0079] Fig. Figure 9 illustrates the removal of the first substrate 101 and, optionally, the first insulating layer 103, thereby exposing the first active layer 201 of the first optical components 203. In one embodiment, the first substrate 101 and the first insulating layer 103 can be removed using a planarization process, such as a chemical-mechanical polishing process, a grinding process, one or more etching processes, combinations thereof, or the like. However, any suitable process can be used to remove the first substrate 101 and / or the first insulating layer 103.

[0080] Once the first substrate 101 and the first insulating layer 103 have been removed, a second active layer 901 can be formed from fourth optical components 903 on a back side of the first active layer 201. In one embodiment, the second active layer 901 can be formed from fourth optical components 903 using similar materials and processes as the second optical components 503 of the first metallization layers 501 (above in relation to Fig. 5 described). For example, the second active layer 901 can be formed from fourth optical components 903 from alternating layers of a plating material such as silicon oxide and a core material such as silicon nitride, which are formed using deposition and structuring processes to form optical components such as waveguides and the like.

[0081] Fig. Figure 10 illustrates the formation of first device vias (TDVs) 1001. In one embodiment, the first device vias 1001 extend through the second active layer 901 and the first active layer 201 to enable rapid transmission of power, data, and ground through the optical interposer 100. In another embodiment, the first device vias 1001 can be formed by initially creating device via openings into the second active layer 901 and the optical interposer 100. The device via openings can be formed by depositing and developing a suitable photoresist (not shown) and removing exposed portions of the second active layer 901 and the optical interposer 100.

[0082] Once the device vias have been formed within the optical interposer 100, the device vias can be lined with a lining (in Fig. (10 not illustrated separately). The lining can be, for example, an oxide formed from tetraethyl orthosilicate (TEOS) or silicon nitride, although alternatively any suitable dielectric material can be used. The lining can be formed using plasma-enhanced chemical vapor deposition (PECVD), although alternatively other suitable processes, such as physical vapor deposition or a thermal process, can be used.

[0083] Once the lining has formed along the sidewalls and bottom of the device via holes, a barrier layer (also not shown independently) can be formed, and the remainder of the device via holes can be filled with initial conductive material. The initial conductive material can include copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like may be used. The initial conductive material can be formed by electroplating copper onto a seed layer (not shown), filling, and overfilling the device via holes.Once the device via holes have been filled, excess lining, barrier layer, nucleation layer and excess first conductive material outside the device via holes can be removed by a planarization process, such as chemical-mechanical polishing (CMP), although any suitable ablation process may be used.

[0084] Optionally, in some embodiments, once the first device vias 1001 have been formed, second metallization layers (in Fig. (10 not illustrated separately) are formed in electrical connection with the first device vias 1001. In one embodiment, the second metallization layers can be formed as described above with respect to the first metallization layers 501—for example, as alternating layers of dielectric and conductive materials—using damascening processes, dual damascening processes, or the like. In other embodiments, the second metallization layers can be formed using a plating process to form and shape conductive material and then cover the conductive material with a dielectric material. However, any suitable structures and manufacturing processes can be used.

[0085] Fig. Figure 11 illustrates the formation of third bond pads 1103. The third bond pads 1103 can be formed to provide conductive regions for contact between the first device vias 1001 and other external devices. In one embodiment, the third bond pads 1103 can be formed in a similar manner and using similar materials as the first bond pads 507, or alternatively, they can be formed using a deposition and structuring process. However, any suitable material and any suitable fabrication method can be used.

[0086] Fig. Figure 12 illustrates that once the third bond pads 1103 have been formed, a second interconnect structure 1201, solder metallization layers 1203, and external connections 1205 can be formed to complete an embodiment of a first optical package 1200. In one embodiment, the second interconnect structure 1201 can be formed using methods and materials similar to those used to form the first metallization layer 501. However, any suitable methods and materials can be used.

[0087] The solder metallization layers 1203 can comprise three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, the person skilled in the art will recognize that there are many suitable arrangements of materials and layers, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement, that are suitable for forming the solder metallization layers. Any suitable materials or layers of material that can be used for the solder metallization layers 1203 are to fall entirely within the scope of the embodiments.

[0088] In one embodiment, the solder metallization layers 1203 are produced by forming each layer over the second interconnect structure 1201. The formation of each layer can be carried out using a plating process, such as electrochemical plating, although, depending on the desired materials, other formation processes, such as sputtering, evaporation, or a PECVD process, can also be used. The solder metallization layers 1203 can be formed to have a thickness between approximately 0.7 µm and approximately 10 µm, for example, approximately 5 µm.

[0089] In one embodiment, the external connections 1205 can be placed on the solder metallization layers 1203 and can, for example, be a ball grid array (BGA) comprising a eutectic material such as solder, although any suitable material can be used. In one embodiment, where the external connections 1205 are solder bumps, the external connections 1205 can be formed using a ball-drop process, such as a direct ball-drop process. In another embodiment, the solder bumps can be formed by initially forming a layer of tin by any suitable method, such as evaporation, electroplating, printing, or solder transfer, and then melting to bring the material into the desired bump shape.Once the external connections 1205 have been formed, a test can be carried out to ensure that the structure is suitable for further processing.

[0090] Fig. Figure 13 illustrates that the first optical package 1200, once formed, can be attached to an intermediate substrate 1301, which is used to couple the first optical package 1200 with other devices, for example to form a chip-on-wafer-on-substrate (CoWoS) ®). In one embodiment, the interposer substrate 1301 comprises a semiconductor substrate 1303, third metallization layers 1305, second device vias (TDVs) 1307, and second external terminals 1309. The semiconductor substrate 1303 can comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon-germanium, SOI, silicon-germanium on insulator (SGOI), or combinations thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0091] Optionally, first active devices (not illustrated separately) can be added to the semiconductor substrate 1303. The first active devices comprise a wide variety of different active and passive devices, such as capacitors, resistors, inductors, and the like, which can be used to generate the desired structural and functional design requirements for the semiconductor substrate 1303. The first active devices can be formed either within or on the semiconductor substrate 1303 using any suitable method.

[0092] The third metallization layers 1305 are formed over the semiconductor substrate 1303 and the first active devices and serve to connect the various active devices to form a functional circuit. In one embodiment, the third metallization layers 1305 are formed from alternating layers of dielectric material (for example, dielectric materials with a low k-value, dielectric materials with an extremely low k-value, dielectric materials with an ultra-low k-value, combinations thereof, or the like) and conductive material and can be formed by any suitable process (such as deposition, damascening, dual damascening, etc.). However, any suitable materials and processes can be used.

[0093] Additionally, at any desired point in the manufacturing process, the second TDVs 1307 can be formed within the semiconductor substrate 1303 and, if desired, one or more layers of the third metallization layers 1305 to provide electrical connectivity from a front side of the semiconductor substrate 1303 to a back side of the semiconductor substrate 1303. In one embodiment, the second TDVs 1307 can be formed using similar processes and materials as the first device vias 1001 described above. Fig. The methods described in section 10 can be used. However, any suitable methods and materials can be used.

[0094] In one embodiment, the second external connectors 1309 can be placed on the semiconductor substrate 1303 in electrical connection with the second TDVs 1307 and can, for example, be a ball grid array (BGA) comprising a eutectic material such as solder, although any suitable material can be used. Optionally, a solder metallization or additional metallization layers (in Fig. (Figure 13 not illustrated separately). In one embodiment, in which the second external connectors 1309 are solder bumps, the second external connectors 1309 can be formed using a ball-drop process, such as a direct ball-drop process. In another embodiment, the solder bumps can be formed by initially forming a tin layer by any suitable method, such as evaporation, electroplating, printing, or solder transfer, and then melting to bring the material into the desired bump shape. Once the external connectors 1309 have been formed, a test can be performed to ensure that the structure is suitable for further processing.

[0095] Once the interposer substrate 1301 has been formed, the first optical package 1200 can be attached to the interposer substrate 1301. In one embodiment, the first optical package 1200 can be attached to the interposer substrate 1301 by aligning the external connections 1205 with conductive sections of the interposer substrate 1301. Once the external connections 1205 have been aligned and brought into physical contact, they are melted by increasing the temperature of the external connections 1205 beyond a eutectic point, thereby transitioning the material of the external connections 1205 into a liquid phase. After melting, the temperature is lowered to return the material of the external connections 1205 to a solid phase, thereby bonding the first optical package 1200 to the interposer substrate 1301.

[0096] Fig. Figure 13 further illustrates the bonding of a second semiconductor device 1311 and a third semiconductor device 1313 to the semiconductor substrate 1303. In some embodiments, the second semiconductor device 1311 is an electronic integrated circuit (EIC), such as a stacked device comprising multiple interconnected semiconductor substrates. For example, the second semiconductor device 1311 may be a memory device, such as a high-bandwidth memory module (HBM module), a hybrid memory cube module (HMC module), or the like, comprising multiple stacked memory dies. In such embodiments, the second semiconductor device 1311 comprises multiple semiconductor substrates interconnected by device through-device vias (TDVs).Each of the semiconductor substrates may optionally include a layer of active devices and an overlying interconnect structure, a bond layer and associated bond pads to connect the multiple devices within the second semiconductor device 1311.

[0097] While the second semiconductor device 1311 is an HBM module in one embodiment, the embodiments are naturally not limited to the second semiconductor device 1311 being an HBM module. Rather, the second semiconductor device 1311 can be any suitable semiconductor device, such as a processor die or any other type of functional die. In certain embodiments, the second semiconductor device 1311 can be an xPU, a logic die, a 3DIC die, a CPU, a GPU, a SoC die, a MEMS die, combinations thereof, or the like. Any suitable device with any suitable functionality can be used, and all such devices are intended to fall fully within the scope of the embodiments.

[0098] The third semiconductor device 1313 can be another EIC intended to work together with both the first optical package 1200 and the second semiconductor device 1311. In some embodiments, the third semiconductor device 1313 can be any suitable type of device (for example, an xPU, a logic die, a 3DIC die, a CPU, a GPU, a SoC die, a MEMS die, combinations thereof, or the like) and can have different functionality than the second semiconductor device 1311, such as that of an application-specific integrated circuit (ASIC), or it can have the same functionality as the second semiconductor device 1311, such as that of another high-bandwidth memory device. Any suitable device can be used.

[0099] In one embodiment, both the second semiconductor device 1311 and the third semiconductor device 1313 can be bonded to the interposer substrate 1301, for example, using third external connections 1315. The third external connections 1315 can be conductive bumps (for example, ball grid arrays, micro-bumps, etc.) or conductive pillars using materials such as solder and copper. In an embodiment where the third external connections 1315 are contact bumps, the third external connections 1315 can comprise a material such as tin or other suitable materials such as silver, lead-free tin, or copper.In an embodiment where the third external connections are tin solder bumps, the third external connections 1315 can be formed by initially forming a layer of tin by such commonly used methods as evaporation, electroplating, printing, solder transfer, bead placement, etc. Once a layer of tin has been formed on the structure, melting can be carried out to bring the material into the desired bump shape.

[0100] Once the third external connections 1315 have been placed, the second semiconductor device 1311 and the third semiconductor device 1313 are additionally aligned onto the interposer substrate 1301. Once the third external connections 1315 are aligned and in physical contact, they are melted by increasing the temperature of the third external connections 1315 beyond a eutectic point, thereby transitioning the material of the third external connections 1315 into a liquid phase. After melting, the temperature is lowered to return the material of the third external connections 1315 to a solid phase, thereby bonding the second semiconductor device 1311 and the third semiconductor device 1313 to the interposer substrate 1301.

[0101] Once the second semiconductor device 1311 and the third semiconductor device 1313 have been bonded, a backer rod 1317 can be placed. The backer rod 1317 can reduce stress and protect the connections created by the melting of the third external connections 1315 and the external connections 1205. The backer rod 1317 can be formed by a capillary flow process after the first optical package 1200, the second semiconductor device 1311, and the third semiconductor device 1313 have been attached.

[0102] After the underfill material 1317 has been placed, the second semiconductor device 1311, the third semiconductor device 1313, and the first optical package 1200 are encapsulated with an encapsulation material 1319. In one embodiment, the encapsulation material 1319 can be a potting compound, an epoxy resin, or the like. The encapsulation material 1319 can be applied by compression molding, injection molding, or the like. The encapsulation material 1319 is further placed in gap regions between the second semiconductor device 1311, the third semiconductor device 1313, and the first optical package 1200. The encapsulation material 1319 can be applied in liquid or semi-liquid form and subsequently cured.

[0103] Once the encapsulation material 1319 has been placed, a planarization process is performed on the encapsulation material 1319. After planarization, the top surfaces of the encapsulation material 1319, the second semiconductor device 1311, the third semiconductor device 1313, and the first optical package 1200 are essentially coplanar, depending on the process variation. The planarization process can be, for example, chemical-mechanical polishing (CMP), grinding, or the like. In some embodiments, the planarization can be omitted.

[0104] Once the second semiconductor device 1311, the third semiconductor device 1313, and the first optical package 1200 have been bonded to the interposer substrate 1301, the interposer substrate 1301 can be bonded to a second substrate 1321, for example, by means of the second external connectors 1309. In one embodiment, the second substrate 1321 can be a package substrate, which may be a printed circuit board (PCB) or the like. The second substrate 1321 can have one or more dielectric layers and electrically conductive structural elements, such as traces and vias. In some embodiments, the second substrate 1321 can have vias, active devices, passive devices, and the like. The second substrate 1321 can also have conductive pads formed on the top and bottom surfaces of the second substrate 1321.

[0105] The second external connectors 1309 can be aligned with corresponding conductive connections on the second substrate 1321. After alignment, the second external connectors 1309 can then be melted to bond the second substrate 1321 to the interposer substrate 1301. However, any suitable bonding process can be used to connect the interposer substrate 1301 to the second substrate 1321.

[0106] Additionally, the second substrate 1321 can be prepared for further processing by forming fourth external connections 1323 on a side of the second substrate 1321 opposite the first optical package 1200. In one embodiment, the fourth external connections 1323 can be formed using similar processes and materials as the second external connections 1309. However, any suitable materials and processes can be used.

[0107] Fig. Figure 13 further illustrates the placement of an optical fiber 1325, which is used as an optical input / output port for the optical interposer 100. In one embodiment, the optical fiber 1325 is placed such that it is optically connected to an optical input, such as a grating coupler (in Fig. (Figure 13 not shown separately), which is located inside the optical interposer 100, is coupled. By positioning the optical fiber 1325 in optical contact with the grating coupler, optical signals leaving the optical fiber 1325 are directed into the optical components of the optical interposer. Similarly, the optical fiber 1325 is positioned so that optical signals leaving the optical interposer 100 are directed into the optical fiber 1325 for transmission. However, any suitable location can be used.

[0108] The optical fiber 1325 can, for example, be held in place using an optical adhesive 1327. In some embodiments, the optical adhesive 1327 comprises a polymer material such as epoxy acrylate oligomers and can have a refractive index between about 1 and about 3. However, any suitable material can be used.

[0109] Embedding the laser die 600 into the first semiconductor device 700 saves space that would otherwise be used to integrate a bulky and complexly encapsulated external laser, while the first semiconductor device 700 remains large enough to provide high drive power for underlying circuitry. Furthermore, integrating the laser die 600 into the first semiconductor device 700 while the first semiconductor device 700 is still part of a wafer allows both the first semiconductor device 700 and the laser die 600 to be bonded to the optical interposer 100 while the optical interposer 100 is still in wafer form. This eliminates the need for separate die / chip bonding and significantly reduces bonding costs.Thus, laser integration remains a cost-effective option and is not hindered by the complete coverage of the wafer.

[0110] Fig. Figure 14 illustrates a variation in which the first optical package 1200, the second semiconductor device 1311, and the third semiconductor device 1313 are bonded to an integrated fan-out substrate 1400, for example, by means of local silicon interposers. In this embodiment, InFO-TDVs 1401 are initially formed (for example, using a photolithographic masking and plating process) on a substrate (not shown separately) alongside fourth semiconductor devices 1403, which may be local silicon interposers or otherwise resemble the second semiconductor device 1311 and / or the third semiconductor device 1313.Once the InFO-TDVs 1401 and the fourth semiconductor devices 1403 are in place, they are encapsulated with a second encapsulation material 1407 (for example, an organic layer similar to the encapsulation material 1319), and fourth metallization layers 1409 (similar to the first metallization layers 501) can be formed. The substrate can then be removed, and fifth metallization layers 1411 can be formed on an opposite side of the InFO-TDVs 1401.

[0111] Once the InFO package 1400 has been formed, the second semiconductor device 1311 and the third semiconductor device 1313 can be bonded to the InFO package 1400 using the third external connections 1315, and the first optical package 1200 is attached using the external connections 1205. Additionally, the InFO package 1400 can be bonded to the second substrate 1321, for example, using the second external connectors 1309, and the fourth external connectors 1323 are formed on the second substrate 1321. However, any suitable processes and structures can be used.

[0112] Fig. Figures 15A-15E illustrate another use of the first semiconductor device 700, wherein the first opening 717 is formed, but the laser die 600 is not subsequently placed in the first opening 717 and can be separated from the first semiconductor device 700. Rather, in this embodiment, the first opening 717 is filled with one or more materials to help signals arriving through the lens 713 to pass through the first semiconductor device 700.

[0113] Let's look first Fig. 15A on. Fig. 15A illustrates the structure of Fig. 7D, wherein the first opening 717 has already been formed within the first semiconductor device 700. In this embodiment, however, the laser die 600 is not placed in the first opening 717, but the process continues with the deposition of an antireflection coating 1501 on the side walls and bottom surfaces of the first opening 717. In one embodiment, the antireflection coating 1501 can be any one or more materials or a combination of materials that help prevent unwanted reflections of incoming or outgoing light, such as titanium oxide, aluminum oxide, silicon oxide, silicon nitride, silicon, combinations thereof, or the like. Additionally, the antireflection coating 1501 can be deposited using a deposition method such as chemical evaporation, atomic layer deposition, physical evaporation, combinations thereof, or the like.

[0114] Fig. Figure 15B illustrates an enlarged view of the first region 709 and the antireflective coating 1501, wherein the antireflective coating 1501 comprises several layers of different materials. In this particular embodiment, the antireflective coating 1501 comprises three sets of alternating material layers, such that a total of six layers are obtained. In each set of alternating materials, there is a first layer 1502 of a first material, such as silicon nitride, and a second layer 1504 of a second material, such as silicon oxide. However, any suitable materials and any suitable number of layers of different materials may be used.

[0115] Fig. Figure 15C illustrates the deposition of a first filler material 1503 for filling and / or overfilling the first opening 717. In one embodiment, the first filler material 1503 is another material that assists incoming and outgoing light in passing through the first semiconductor device 700, such as silicon dioxide, BCB, SiON, combinations thereof, or the like, deposited using a process such as chemical evaporation, atomic layer deposition, physical evaporation, flowable chemical evaporation, combinations thereof, or the like. However, any suitable material and any suitable deposition process may be used.

[0116] Once the first filler material 1503 has been deposited to fill and / or overfill the first opening 717, the first filler material 1503 can be planarized to remove unwanted materials of the antireflection layer 1501 and the first filler material 1503 from outside the first opening 717. In one embodiment, the planarization process can be a chemical-mechanical polishing process. However, any suitable planarization process, such as a grinding process or even a series of one or more etching processes, can be used.

[0117] Fig. Figure 15C also illustrates that the planarization process can cause undesirable damage because it can erode different materials at different rates. For example, in some embodiments where the planarization process erodes the first filler material 1503 at a higher rate than the exposed materials of the interconnect structure 707, a recess or cup-shaped depression may form within the first filler material 1503 during the planarization process.

[0118] Fig. Figure 15D illustrates filling the recess or cup-shaped depression to form a planar surface for subsequent fabrication processes. In one embodiment, the recess can be filled with a second filler material 1505, which both fills the recess and allows light to pass through the first semiconductor device 700. This second filler material can be a dielectric material such as SiN, SiON, or BCB. The second filler material 1505 can be deposited using a chemical evaporation process, an atomic layer deposition process, a physical evaporation process, a combination thereof, or the like. The second filler material 1505 can then be planarized with the interconnect structure 707. However, any suitable methods and materials can be used.

[0119] In one embodiment, once the second filler material 1505 has been planarized with the rest of the first semiconductor device 700, it has a second depth D2 sufficient to fill the cavity formed by the deposition of the first filler material 1503. In one embodiment, the second depth D2 can be between about 0.1 µm and about 1 µm. However, any suitable depth can be used.

[0120] Fig. Figure 15D further illustrates that once the second filler material 1505 has been formed, the second bond pads 723 can be formed. In one embodiment, the second bond pads 723 can be formed as above with respect to Fig. The 7G described above can be formed. However, any suitable formation method can be used.

[0121] Fig. Figure 15E illustrates bonding the first semiconductor device 700 (without the laser die 600, but with the second filler material 1505) to the optical interposer 100 and forming the second active layer 901 to create this embodiment of the first optical package 1200. In one embodiment, the first semiconductor device 700 can be bonded to the optical interposer 100 as shown above with respect to Fig. 8 described, bonding can be carried out, for example using a dielectric-to-dielectric and a metal-to-metal bonding process, and further processing can be carried out as above with respect to the Fig. The procedures described in sections 9-12 can be carried out. However, any suitable manufacturing process can be used.

[0122] Fig. Figures 15F-15G illustrate the bonding of the first optical package 1200 to the interposer substrate 1301 (in Fig. 15F) and the Info Package 1400 (in Fig. 15G). In one embodiment, the first optical package 1200 can be configured as above with respect to the Fig. The bonding described in sections 13 and 14 is possible. However, any suitable methods or structures can be used.

[0123] Fig. Figure 16A illustrates another embodiment in which the first opening 717 is filled with the first filling material 1503, but in which the first optical package 1200 is attached to the interposer substrate 1301 (see Fig. 16B) is bonded with a fusion bond instead of a dielectric-to-dielectric and metal-to-metal connection. In this embodiment, the first optical package 1200 can be largely as described above with respect to the Fig. 1-12 are described. In this embodiment, however, the lens 713, the antireflection coating 715, the first device vias 1001 and the external connections 1205 are not formed in or on the support substrate 711.

[0124] Rather, a bonding layer 1601 is formed along the back side of the support substrate 711 at any suitable point in the process. In one embodiment, the bonding layer 1601 can be a material such as silicon dioxide, SiN, SiNC, combinations thereof, or the like, formed using a process such as chemical evaporation, atomic layer deposition, physical evaporation, oxidation, combinations thereof, or the like. However, any suitable process and any suitable materials can be used.

[0125] Because the external connections 1205, as above in relation to Fig. As described in Figure 12, fourth bond pads 1603 are formed in this embodiment to provide electrical connections. In such an embodiment, the fourth bond pads 1603 can be formed using similar materials and processes as the first bond pads 507 described above. Fig. The methods described in section 5 can be used. However, any suitable methods and materials can be used.

[0126] Fig. Figure 16B illustrates that once the bonding layer 1601 has been formed, the first optical package 1200 can be bonded to the interposer substrate 1301 using the bonding layer 1601, along with bonding the second semiconductor device 1311 and the third semiconductor device 1313. For example, in some embodiments, the fusion bonding process can activate areas of the bonding layer 1601 and dielectric sections of the third metallization layers 1305, and then the bonding layer 1601 and dielectric sections of the third metallization layers 1305 are brought into physical contact to initiate the bonding process, and further bond strengthening can be performed. However, any other suitable attachment process, including the use of an adhesive, can also be used.

[0127] Once the first optical package 1200 has been bonded to the interposer substrate 1301, the second semiconductor device 1311 and the third semiconductor device 1313 can also be bonded to the interposer substrate 1301. In one embodiment, the bonding can be carried out as described above with respect to Fig. The bonding process described in section 13 can be carried out, for example, using a dielectric-to-dielectric and metal-to-metal bonding process. However, any suitable bonding process can be used.

[0128] Fig. Figure 16B further illustrates bonding the laser die 600 to the fourth bond pads 1603. In one embodiment, the laser die 600 can be bonded to some (but not all) of the fourth bond pads 1603, for example, using a dielectric-to-dielectric and metal-to-metal process, as described above in relation to Fig. 8 described. However, any suitable bonding process can be used.

[0129] Fig. Figure 16B also illustrates a wire bond 1605 that can be used to electrically connect the first optical package 1200 to the second substrate 1321 via the fourth bond pads 1603. In one embodiment, an electronic flame-off (EFO) device can be used to control the temperature of a gold wire (in Fig. 16B not individually illustrated) within a capillary, which is held in place by a wire clamp (in Fig. (16B also not individually illustrated) is controlled. Once the temperature of the gold wire has risen to between approximately 150°C and approximately 250°C, the gold wire is brought into contact with the fourth bond pads 1603 to form a first bond, and then the gold wire is moved to the second substrate 1321 to form a second bond. After bonding, the remaining gold wire is separated from the bonded sections to form the wire bonds 1605. The bonding process can be repeated to form as many bonds as desired.

[0130] Fig. Figures 17A-17B illustrate another embodiment in which the laser die 600 is connected to the fourth bond pads 1603 (in Fig. 17A not illustrated, but in Fig. (illustrated in Figure 17B). In this embodiment, however, the electrical connections are not provided using the wire bond 1605, but are provided using third device vias 1701 extending through the support substrate 711 and the bonding layer 1601. In one embodiment, the third device vias 1701 can be arranged as above with respect to the first device vias 1001 in Fig. 10 can be described. However, any suitable methods and materials can be used.

[0131] Fig. Figure 17B illustrates that once the third device vias 1701 have been formed, the first optical package 1200 can be bonded to the interposer substrate 1301. However, in this embodiment, the first optical package 1200 is not bonded using a fusion bonding process (as described above in relation to Fig. 16B) bonded to the interposer substrate 1301, but using a dielectric-to-dielectric and metal-to-metal bonding process, whereby the third device vias 1701 electrically connect the third metallization layers 1305 to the rest of the first optical package 1200.

[0132] Fig. Figure 17B further illustrates bonding the laser die 600 to the fourth bond pads 1603 and bonding the second semiconductor device 1311 and the third semiconductor device 1313 to the interposer substrate 1301. In one embodiment, the laser die 600 can be bonded as above with respect to Fig. 16B are bonded, while the second semiconductor device 1311 and the third semiconductor device 1313 are bonded as described above with respect to Fig. 13 can be bonded. However, any suitable bonding process can be used.

[0133] Fig. Figures 18A-18B illustrate another embodiment in which the first optical package 1200, instead of being bonded to the second semiconductor device 1311 via the interposer substrate 1301, for example, is bonded directly to the second semiconductor device 1311 in an optical stack. In this embodiment, the first optical package 1200 is bonded as above with respect to Fig. 15E described, manufactured, but without the formation of the third bond pads 1103 by the external connections 1205.

[0134] After the first optical package 1200 has been fabricated, it can be physically and electrically connected to the second semiconductor device 1311. In one embodiment, for example, the first optical package 1200 can be bonded to the second semiconductor device 1311 using dielectric-to-dielectric and metal-to-metal bonding, whereby dielectric material of the second active layer 901 is bonded to dielectric material of the second semiconductor device 1311, and the first device vias 1001 are bonded to conductive sections of the second semiconductor device 1311. However, any suitable bonding process can be used.

[0135] Fig. Figure 18B illustrates that once the first optical package 1200 has been bonded to the second semiconductor device 1311, the third bond pads 1103, the second interconnect structure 1201, the solder metallization layers 1203, and the external connections 1205 can be formed. In one embodiment, the third bond pads 1103, the second interconnect structure 1201, the solder metallization layers 1203, and the external connections 1205 can be formed as above with respect to the Fig. 11 and Fig. 12 can be described as being manufactured. However, any suitable manufacturing process can be used.

[0136] Fig. 18C and Fig. Figure 18D illustrates the bonding of the second semiconductor device 1311 (with the first optical package 1200 bonded to it) and the third semiconductor device 1313 to the interposer substrate 1301 (in Fig. 18C) and the InFO package 1400 (in Fig. 18D). In one embodiment, the second semiconductor device 1311 can be configured as above with respect to the Fig. The bonding described in sections 13 and 14 is possible. However, any suitable methods or structures can be used.

[0137] Fig. Figures 19A-19D illustrate another embodiment comprising the optical interposer 100, the first semiconductor device 700, and the second semiconductor device 1311. In this embodiment, however, the second semiconductor device 1311 is located between the optical interposer 100 and the first semiconductor device 700.

[0138] Let's look first Fig. 19A. The first semiconductor device 700 can be used as above with regard to Fig. The first semiconductor device 700 is manufactured as described in Figure 15D. In this embodiment, however, the first semiconductor device 700 is bonded not to the optical interposer 100, but to the second semiconductor device 1311. For example, the first semiconductor device 700 can be bonded to the second semiconductor device 1311 using a dielectric-to-dielectric and metal-to-metal bonding process. However, any suitable bonding process can be used.

[0139] Fig. Figure 19B illustrates that once the first semiconductor device 700 has been bonded to the second semiconductor device 1311, the second semiconductor device 1311 can be bonded to the optical interposer 100. In one embodiment, the second semiconductor device 1311 can be bonded to the optical interposer 100 using a dielectric-to-dielectric and metal-to-metal bonding process. However, any suitable bonding process can be used.

[0140] Fig. Figure 19B further illustrates that, after the second semiconductor device 1311 has been bonded to the optical interposer 100, the first substrate 101 can be removed and the second active layer 901, the first device vias 1001 and the fourth bond pads 1603 can be formed. However, any suitable structures can be used.

[0141] Fig. Figure 19C illustrates that once the optical interposer 100 has been bonded to the second semiconductor device 1311, the first semiconductor device 700 (and thus the second semiconductor device 1311 and the optical interposer 100) can be bonded to the interposer substrate 1301 (for example, using fusion bonding, as above in relation to Fig. 16B), the laser die 600 can be bonded to the optical interposer 100 (as described above in relation to Fig. 16B), the third semiconductor device 1313 can be bonded to the interposer substrate 1301 (as described above in relation to Fig. 13), the interposer substrate 1301 can be bonded to the second substrate 1321 (as described above in relation to Fig. 13), and the wire bond 1605 can be used to connect the second substrate 1321 and the first optical package 1200 (as described above in relation to Fig. 16). However, any suitable method may be used.

[0142] Fig. Figure 19D illustrates another embodiment in which the second semiconductor device 1311 is arranged between the first semiconductor device 700 and the optical interposer 100. In this embodiment, however, the wire bond 1605 is not used to provide electrical connections, but the third device vias 1701 are formed such that they extend through the support substrate 711 and the semiconductor substrate 703 (as above in relation to Fig. 17A described). That is, once the first semiconductor device 700 has been bonded, the third device vias 1701 provide the electrical connections between the first semiconductor device 700 and the interposer substrate 1301.

[0143] Although a number of configurations have been presented in the descriptions above, these specific configurations are, of course, only for illustrative purposes and are not intended to limit the embodiments to these specific configurations. Rather, any suitable configuration is possible, such as a stack of the first semiconductor device 700, the optical interposer 100, and the second semiconductor device 1311 (where the first semiconductor device 700 is bonded to the interposer substrate 1301), or another stack of the optical interposer 100, the first semiconductor device 700, and the second semiconductor device 1311 (where the optical interposer 100 is bonded to the interposer substrate 1301). Any suitable configuration may be used, and all such configurations are intended to fall fully within the scope of the embodiments.

[0144] Integrating the second semiconductor device 1311 into an optical stack with the optical interposer 100 and the first semiconductor device 700 results in a more efficient device. Specifically, signals between the optical interposer 100, the first semiconductor device 700, and the second semiconductor device 1311 need to travel a shorter distance. By reducing the distance required for communication, faster transmission with less power can be achieved.

[0145] In one embodiment, a method for fabricating an optical device comprises: forming a first semiconductor device as part of a first wafer, the first semiconductor device comprising a layer of active devices and an interconnect structure; forming a first opening at least partially through the interconnect structure and the layer of active devices of the first semiconductor device; filling the first opening; and bonding the first semiconductor device to an optical interposer, while the first semiconductor device remains part of the first wafer. In one embodiment, filling the first opening comprises embedding a laser die in the first opening. In another embodiment, filling the first opening further comprises depositing a sealing material around the laser die within the first opening.In one embodiment, filling the first opening further comprises planarizing the laser die with the interconnect structure. In another embodiment, filling the first opening comprises depositing an antireflection coating along the sidewalls of the first opening. In another embodiment, filling the first opening comprises depositing a filler material, wherein, after deposition of the filler material, the filler material has a cup-shaped depression. In another embodiment, filling the first opening further comprises: depositing a dielectric material adjacent to the cup-shaped depression; and planarizing the dielectric material with the interconnect structure.

[0146] In another embodiment, a method for manufacturing an optical device comprises: receiving a first semiconductor device; embedding a laser die in the first semiconductor device; and simultaneously bonding the first semiconductor device and the laser die to a first optical interposer. In one embodiment, the method further comprises bonding the first optical interposer to a silicon interposer. In another embodiment, the method further comprises bonding a second semiconductor device and a third semiconductor device to the silicon interposer. In another embodiment, the method further comprises bonding the first optical interposer to a local silicon interposer.In one embodiment, embedding the laser die comprises: placing the laser die within a first opening of the first semiconductor device; depositing a sealing material around the laser die; and planarizing the laser die and the sealing material with the first semiconductor device. In another embodiment, the method further comprises simultaneously forming contact pads that are electrically connected via an interconnect between the first semiconductor device and the laser die. In yet another embodiment, the method further comprises: forming first optical components on a side of the first optical interposer opposite the laser die; and forming vias through the first optical components.

[0147] In another embodiment, an optical device comprises: an optical stack comprising: a first optical interposer; a memory stack; and a first semiconductor device; and an interposer bonded to the optical stack. In one embodiment, the memory stack is located between the first optical interposer and the first semiconductor device. In another embodiment, the first semiconductor device is bonded to the interposer. In yet another embodiment, the optical device further comprises a wire bond connecting the optical stack to a second substrate, the second substrate being located on a side of the interposer opposite the optical stack.In one embodiment, the optical device further comprises vias that extend through the first semiconductor device.

Claims

[1] Method for manufacturing an optical device, wherein the method comprises: Forming a first semiconductor device (700) as part of a first wafer, wherein the first semiconductor device (700) comprises a layer (705) of active devices and an interconnect structure (707); Forming a first opening (717) at least partially through the interconnect structure (707) and the layer (705) of active devices of the first semiconductor device (700); Filling the first opening (717); and Bonding of the first semiconductor device (700) to an optical interposer (100), while the first semiconductor device (700) remains part of the first wafer, wherein the filling of the first opening (717) comprises the deposition of an anti-reflective coating (1501) along side walls of the first opening (717). [2] Method according to claim 1, wherein filling the first opening (717) comprises depositing a filling material (1503), wherein after depositing the filling material (1503) the filling material (1503) has a cup-shaped recessed surface. [3] Method according to claim 2, wherein the filling of the first opening (717) further comprises: Deposition of a dielectric material (1505) next to the cup-shaped depression; and Planarizing the dielectric material (1505) with the interconnect structure (707). [4] Optical device comprising: an optical stack that exhibits: a first optical interposer (100); a memory stack (1311); and a first semiconductor device (700); and an interposer (1301, 1400) bonded to the optical stack, wherein the first semiconductor device (700) comprises a layer (705) of active devices and an interconnect structure (707) located on the layer (705) of active devices, wherein the first semiconductor device (700) has an antireflection coating (1501) on side walls and bottom surfaces of an opening (717) located within the layer (705) of active devices and the interconnect structure (707) above it. [5] Optical device according to claim 4, wherein the memory stack (1311) is located between the first optical interposer (100) and the interposer (1301, 1400). [6] Optical device according to claim 4, wherein the memory stack (1311) is located between the first optical interposer (100) and the first semiconductor device (700). [7] Optical device according to claim 6, wherein the first semiconductor device (700) is bonded to the interposer (1301, 1400). [8] Optical device according to claim 7, which further comprises a wire bond connecting the optical stack to a second substrate (1321), wherein the second substrate (1321) is located on a side of the interposer (1301, 1400) opposite the optical stack. [9] Optical device according to any one of the preceding claims 4 to 8, which further comprises vias (1701) extending through the first semiconductor device (700).

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