First power semiconductor module for a first sub-circuit, second power semiconductor module for a second sub-circuit and arrangement thereof

Abstract

A first power semiconductor module for a first sub-circuit of a T-MLI circuit arrangement and a second power semiconductor module for a second sub-circuit of a T-MLI circuit arrangement are presented, wherein the T-MLI circuit arrangement has a DC branch with an upper first power semiconductor switch whose power input is connected to a positive potential of a DC voltage source and a first antiparallel connected power diode.comprising a lower fourth power semiconductor switch whose power output is connected to a negative potential of a DC voltage source and a fourth antiparallel connected power diode, and comprising a center tap and a T-branch comprising a second power semiconductor switch whose power input is directly or indirectly connected to ground potential and a second antiparallel connected power diode, and comprising a third power semiconductor switch whose power input is directly or indirectly connected to the center tap and a third antiparallel connected power diode, and comprising wherein the second and third power semiconductor switches are electrically connected in series, as well as an arrangement with a first and a second power semiconductor module.

Description

[0001] The invention describes a first power semiconductor module for a first subcircuit of a T-MLI circuit arrangement, a second power semiconductor module for a second subcircuit of a T-MLI circuit arrangement and an arrangement therewith.

[0002] DE 10 2013104081 B3 discloses a 3-level power converter half-bridge with a first substrate and a second substrate arranged separately from the first substrate, wherein the power semiconductor switches and diodes of the 3-level power converter half-bridge are divided between a first substrate and a second substrate in such a way that during preferred operation of the 3-level power converter half-bridge with a high power factor, no or only rarely current commutations occur between the power semiconductor switches and diodes arranged on the first substrate and the power semiconductor switches and diodes arranged on the second substrate.

[0003] The invention is based on the object of combining a first and second power semiconductor module with a first and second subcircuit to form an arrangement with an optimized commutation.

[0004] This object is achieved according to the invention by a first power semiconductor module for a first subcircuit of a T-MLI circuit arrangement, wherein the T-MLI circuit arrangement comprises a DC branch with an upper first power semiconductor switch whose power input is connected to a positive potential of a DC voltage source and a first antiparallel connected power diode, with a lower fourth power semiconductor switch whose power output is connected to a negative potential of a DC voltage source and a fourth antiparallel connected power diode and with a center tap and a T-branch with a second power semiconductor switch whose power input is directly or indirectly connected to ground potential and a second anti-parallel connected power diode and with a third power semiconductor switch whose power input is directly or indirectly connected to the center tap and with a third anti-parallel connected power diode, and wherein the second and third power semiconductor switches are connected in series and wherein the first subcircuit comprises the first and second power semiconductor switches and the second, third and fourth power diodes.

[0005] In a preferred embodiment, the first subcircuit is arranged in a first housing with load connection elements, wherein these load connection elements have four different polarities.

[0006] It may be advantageous if the first and second power semiconductor switches of the first subcircuit are designed as a power semiconductor component or as a group of parallel-connected power semiconductor components, wherein the respective power semiconductor component is designed as an IGBT or a MOS-FET, in particular as a SiC-MOS-FET, or as a HEMT, in particular as a GaN-HEMT.

[0007] The object is further achieved by a second power semiconductor module for a second subcircuit of a T-MLI circuit arrangement, wherein the T-MLI circuit arrangement comprises a DC branch with an upper first power semiconductor switch whose power input is connected to a positive potential of a DC voltage source and a first antiparallel connected power diode, with a lower fourth power semiconductor switch whose power output is connected to a negative potential of a DC voltage source and a fourth antiparallel connected power diode and with a center tap and a T-branch with a second power semiconductor switch whose power input is directly or indirectly connected to ground potential and a second anti-parallel connected power diode and with a third power semiconductor switch whose power input is directly or indirectly connected to the center tap and with a third anti-parallel connected power diode, and wherein the power outputs of the second and third power semiconductor switches are connected in series and wherein the second subcircuit comprises the third and fourth power semiconductor switches, the first, second and third power diodes.

[0008] It may be preferred that the second subcircuit is arranged in a second housing with load connection elements, wherein these load connection elements have four different polarities.

[0009] It may be advantageous if the third and fourth power semiconductor switches of the second subcircuit are designed as a power semiconductor component or as a group of parallel-connected power semiconductor components, wherein the respective power semiconductor component is designed as an IGBT or a MOS-FET, in particular as a SiC-MOS-FET, or as a HEMT, in particular as a GaN-HEMT.

[0010] The object is further achieved by an arrangement with a first power semiconductor module described above and a second power semiconductor module described above.

[0011] It may be advantageous if the first and second power semiconductor modules are arranged such that the load connection elements of the same polarity have a short connection path for connection to one another.

[0012] It may also be advantageous if the second and third power diodes are present in the first and second power semiconductor modules, respectively.

[0013] Of course, unless this is explicitly or per se excluded or contradicts the idea of ​​the invention, the features mentioned in the singular can be present multiple times in the power semiconductor modules according to the invention and in particular in the arrangement according to the invention.

[0014] It is understood that the various embodiments of the invention, whether implemented individually or in any combination, can be used to achieve improvements. In particular, the features mentioned and explained above and below can be used not only in the specified combinations, but also in other combinations or on their own, without departing from the scope of the present invention.

[0015] Further explanations of the invention, advantageous details and features, emerge from the following description of the Fig. 1 to 8 schematically illustrated embodiments of the invention, or of respective parts thereof. Fig. 1 shows an embodiment of a TMLI circuit arrangement of an arrangement according to the invention. Fig. 2 and Fig. 3 show two embodiments of a first subcircuit of a T-MLI circuit arrangement of a first power semiconductor module according to the invention. Fig. 4 and Fig. 5 show two embodiments of a second subcircuit of a T-MLI circuit arrangement of a second power semiconductor module according to the invention. Fig. 6 to 8 show three embodiments in schematic representation of an arrangement according to the invention with a first and second power semiconductor module.

[0016] Fig. 1 shows in conjunction with the Fig. 2 to 5 show an embodiment of a T-MLI (T-type multi-level inverter) circuit arrangement, in particular a 3-level converter half-bridge, of an arrangement 10 according to the invention with a first and second subcircuit of a first and a second power semiconductor module 12, 14. The circuit arrangement has a DC branch with an upper first power semiconductor switch T1 with an anti-parallel connected power diode D1, wherein the power input of the first power semiconductor switch T1 is connected to a positive potential of a DC voltage source, here to a first DC voltage terminal DC+. The DC branch further has a lower fourth power semiconductor switch T4 with a fourth anti-parallel connected power diode D4, wherein the power output of the fourth power semiconductor switch T4 is connected to a negative potential of a DC voltage source, here to a second DC voltage terminal DC.The half-bridge circuit has a center tap between the first and fourth power semiconductor switches T1, T4. The center tap is connected to an AC voltage terminal, which has an alternating potential during operation. Fig. 1 also shows a T-branch with a second power semiconductor switch T2 and a second antiparallel-connected power diode D2. The power input of the second power semiconductor switch T2 is directly connected to a neutral terminal N, i.e., the ground potential, as an example. The T-branch also has a third power semiconductor switch T3 with a third antiparallel-connected power diode D3. The power input of the third power semiconductor switch T3 is directly connected to the center tap. The power output of the second power semiconductor switch T2 and the power output of the third power semiconductor switch T3 are electrically connected to one another.

[0017] The arrangement 10 here, for example, has only a second and a third power diode D2, D3. However, the first and second power semiconductor modules 12, 14 of the arrangement 10 can alternatively also each have a second and third power diode D2, D3, see FIG. Fig. 2 to 5.

[0018] The first, second, third, and fourth power semiconductor switches T1, T2, T3, T4 of the arrangement 10 are embodied here, by way of example, as an IGBT. The collector terminal of the respective IGBT forms the load input, the emitter terminal the load output, and the gate terminal the control input. The respective power semiconductor switches can alternatively also each be embodied as a MOS-FET, preferably as a MOS-FET with a wide band gap, i.e., as a SiC-MOS-FET, or as a HEMT or as a GaN-HEMT. Furthermore, a parallel connection of a plurality of MOS-FETs is possible. In this case, the drain terminal forms the load input, the source terminal the load output, and the gate terminal the control terminal.

[0019] During general operation of a TMLI circuit arrangement, current commutations occur between the power semiconductor switches and power diodes when the power semiconductor switches are switched on and off with a high power factor (high efficiency).

[0020] By means of the arrangement 10 according to the invention and thus a division of a TMLI circuit arrangement into a first power semiconductor module 12 with a first subcircuit, cf. Fig. 2 or Fig. 3, consisting of the first and second power semiconductor switches T1,T2 of the second, third and fourth power diodes D2,D3,D4 and the second power semiconductor module 14, cf. Fig. 4 or Fig. 5, with a second subcircuit consisting of the third and fourth power semiconductor switch T3,T4 of the first, second and third power diodes D1,D2,D3, both power semiconductor modules 12,14 can be switched with low inductance and thus switching losses can be effectively reduced.

[0021] Since, with positive current flow into the AC voltage connection AC, regardless of the voltage direction, the current flows only through the first power semiconductor module 12, and with negative current, the current flows only through the second power semiconductor module 12, current commutations typically do not occur across both power semiconductor modules 12,14.

[0022] Fig. Figure 2 shows the above-described first embodiment of a TMLI circuit arrangement of the arrangement 10 according to the invention, wherein the first subcircuit of the first power semiconductor module 12 is shown as a hatched area. The first subcircuit of the first power semiconductor module 12 comprises the first and second power semiconductor switches T1, T2 as well as the second, third, and fourth power diodes D2, D3, D4.

[0023] Fig. 3 shows a second embodiment of a TMLI circuit arrangement of the arrangement 10 according to the invention, wherein here also the first subcircuit of the first power semiconductor module 12 is shown as a hatched area. Fig. 3 differs from Fig. 2 in that the power inputs of the second and third power semiconductor switches T2,T3 are electrically connected to each other.

[0024] The Fig. 4 and Fig. 5 also show the arrangement 10 of a TMLI circuit arrangement according to the invention. The hatched area in both figures shows the second power semiconductor module 14. The second subcircuit of the second power semiconductor module 14 here comprises the third and fourth power semiconductor switches T3, T4 as well as the first, second, and third power diodes D1, D2, D3. Fig. 4 differs from Fig. 5 in that the power outputs of the second and third power semiconductor switches T2,T3 are electrically connected to each other, whereas in Fig. 5 the power inputs of the two power semiconductor switches T2,T3 are electrically connected to each other.

[0025] The Fig. 6 to 8 show different embodiments of an arrangement 10 according to the invention comprising a first and second power semiconductor module 12, 14 according to the invention in plan view. The two power semiconductor modules 12, 14 are shown in the Fig. 6 to 8 are arranged in series by way of example. The respective power semiconductor module 12, 14 has a base plate with fastening devices 18 for a force-fitting connection to a cooling device. Furthermore, the first power semiconductor module 12 has a first housing 16 and the second power semiconductor module 14 has a second housing 17 with a rectangular basic shape. The upper and lower outer sides are relatively shorter than the right and left outer sides of the first and second housings 16, 17. The fastening devices 18 are arranged in the corner regions of the respective housing 16, 17. Each of the power semiconductor modules 12, 14 has load connection elements with four different polarities, which are also arranged in the corresponding housing 16, 17.The first and second power semiconductor modules 12, 14 are arranged relative to one another in such a way that the load connection elements of the same polarity contained in both power modules have a short connection path. The respective load connection elements are arranged in such a way that the distance required to maintain clearance and creepage distances is maintained.

[0026] Furthermore, both power semiconductor modules 12, 14 have auxiliary connection elements (not shown), which are also arranged in the respective housing 16, 17.

[0027] In Fig. 6, the arrangement 10 has two identically constructed power semiconductor modules 12, 14, which are arranged next to one another. The first and second power semiconductor modules 12, 14 here have, purely as an example, three AC voltage connection elements 24, which are arranged next to one another centrally between the fastening devices 18 in the lower region of the power semiconductor module 12, 14, starting from the left outer side to the right outer side. A first and a second DC voltage connection element 20, 22 are arranged in the upper region of the first and second power semiconductor modules 12, 14, respectively. The first DC voltage connection element 20 of a positive DC voltage source is located in the region of the right outer side of the power semiconductor module 12, 14. At a distance from this, in the region of the left outer side of the power semiconductor module 12, 14, is the second DC voltage connection element 22 of a DC voltage source with negative potential.In both the area of ​​the left and right outer sides of the power semiconductor module 12, 14, a neutral connection element 26 is arranged below the first and second DC voltage connection elements 20, 22 at a distance from them.

[0028] Accordingly, the second DC voltage connection element 22 of the first power semiconductor module 12 and the first DC voltage connection element 20 of the second power semiconductor module 14, the neutral connection element 26 of the first power semiconductor module 12 and the neutral connection element 26 of the second power semiconductor module 14 as well as the AC voltage connection element 24 arranged on the right outer side of the first power semiconductor module 12 and the AC voltage connection element 24 arranged on the left outer side of the second power semiconductor module 14 are opposite one another for connection to one another.

[0029] Fig. 7 differs from Fig. 6 in that in the first power semiconductor module 12 of the arrangement 10, for example, two AC voltage connection elements 24 are arranged centrally on the left outer side of the first housing 16 at a distance from one another. On the right outer side, from top to bottom, the neutral connection element 26, the second DC voltage connection element 22, and the first DC voltage connection element 20 are arranged at a distance from one another. The second power semiconductor module 14 also has two AC voltage connection elements 24, but these are arranged on the right outer side of the housing 17. On the left outer side, in comparison to the first power semiconductor module 12, the neutral connection element 26, the second DC voltage connection element 22, and the first DC voltage connection element 20 are arranged at a distance from one another from top to bottom. Therefore, here too, the same load connection elements are arranged opposite one another for electrical connection to one another.

[0030] Fig. 8 differs from the Fig. 6 and Fig.7, that the first and second power semiconductor modules 12, 14 of the arrangement 10 also have an AC voltage connection element 24, purely by way of example. The two power modules 12, 14 are also constructed identically and have four load connection elements with four different polarities. The respective second DC voltage connection element 22 of the first and second power semiconductor modules 12, 14 is arranged between the fastening devices 18 in the upper corner regions of the first and second housings 16, 17. Towards the lower outer side of the first and second housings 16, 17, the respective neutral connection element 26 and, following thereafter, the first DC voltage connection element 20 are also arranged in series. The respective AC voltage connection element 24 is arranged here in the lower region of the housing 16, 17 between the fastening devices 18 in the corner regions at a distance from the first DC voltage connection element 22. List of reference symbols 10 Arrangement 12 first power semiconductor module 14 second power semiconductor module 16 first housing 17 second housing 18 fastening devices 20 first DC voltage connection element 22 second DC voltage connection element 24 AC connection element 26 Neutral connection element DC+ first DC voltage connection DC- second DC voltage connection AC alternating voltage connection N neutral connection T1 first power semiconductor switch T2 second power semiconductor switch T3 third power semiconductor switch T4 fourth power semiconductor switch D1 first power diode D2 second power diode D3 third power diode D4 fourth power diode QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] DE 10 2013104081 B3

[0002]

Claims

[1] First power semiconductor module (12) for a first subcircuit of a T-MLI circuit arrangement, wherein the T-MLI circuit arrangement comprises a DC branch with an upper first power semiconductor switch (T1) whose power input is connected to a positive potential of a DC voltage source and a first antiparallel connected power diode (D1), with a lower fourth power semiconductor switch (T4) whose power output is connected to a negative potential of a DC voltage source and a fourth antiparallel connected power diode (D4) and with a center tap and a T-branch with a second power semiconductor switch (T2) whose power input is directly or indirectly connected to ground potential and a second anti-parallel connected power diode (D2) and with a third power semiconductor switch (T3) whose power input is directly or indirectly connected to the center tap and with a third anti-parallel connected power diode (D3), and wherein the second and third power semiconductor switches (T2, T3) are connected in series and wherein the first subcircuit comprises the first and second power semiconductor switches (T1,T2), the second, third and fourth power diodes (D2,D3,D4). [2] First power semiconductor module (12) according to claim 1, wherein the first subcircuit is arranged in a first housing (16) with load connection elements, said load connection elements having four different polarities. [3] First power semiconductor module (12) according to one of the preceding claims, wherein the first and second power semiconductor switches (T1, T2) of the first subcircuit are designed as a power semiconductor component or as a group of parallel-connected power semiconductor components, wherein the respective power semiconductor component is designed as an IGBT or a MOS-FET, in particular as a SiC-MOS-FET, or as a HEMT, in particular as a GaN-HEMT. [4] Second power semiconductor module (14) for a second subcircuit of a T-MLI circuit arrangement, wherein the T-MLI circuit arrangement comprises a DC branch with an upper first power semiconductor switch (T1) whose power input is connected to a positive potential of a DC voltage source and a first antiparallel connected power diode (D1), with a lower fourth power semiconductor switch (T4) whose power output is connected to a negative potential of a DC voltage source and a fourth antiparallel connected power diode (D4) and with a center tap and a T-branch with a second power semiconductor switch (T2) whose power input is directly or indirectly connected to ground potential and a second anti-parallel connected power diode (D2) and with a third power semiconductor switch (T3) whose power input is directly or indirectly connected to the center tap and with a third anti-parallel connected power diode (D3), and wherein the power outputs of the second and third power semiconductor switches (T2, T3) are connected in series and wherein the second subcircuit comprises the third and fourth power semiconductor switches (T3,T4), the first, second and third power diodes (D1,D2,D3). [5] Second power semiconductor module (14) according to claim 4, wherein the second subcircuit is arranged in a second housing (17) with load connection elements, said load connection elements having four different polarities. [6] Second power semiconductor module (14) according to one of claims 4 to 5, wherein the third and fourth power semiconductor switches (T3, T4) of the second subcircuit are designed as a power semiconductor component or as a group of parallel-connected power semiconductor components, wherein the respective power semiconductor component is designed as an IGBT or a MOS-FET, in particular as a SiC-MOS-FET, or as a HEMT, in particular as a GaN-HEMT. [7] Arrangement (10) with a first power semiconductor module (12) according to one of claims 1 to 3 and a second power semiconductor module (14) according to one of claims 4 to 6. [8] Arrangement (10) according to claim 7, wherein the first and second power semiconductor modules (12, 14) are arranged such that the load connection elements of the same polarity have a short connection path for connection to one another. [9] Arrangement according to one of claims 7 to 8, wherein the second and third power diodes (D2, D3) are present in the first and second power semiconductor modules (12, 14) respectively.

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