Method for controlling a semiconductor device

Abstract

A method for controlling a semiconductor device, wherein - the semiconductor device comprises: a first switching device (100) and a second switching device (200) which are connected in series between a first potential (VCC) and a second potential (GND) which is lower than the first potential (VCC), - the first and second switching devices (100, 200) each comprise a transistor region (T1) and a diode region (D1) which is electrically connected antiparallel to the transistor region (T1), - the respective transistor region (T1) has a first gate (11) which is controlled by a first gate signal (G I1 ) is controlled, - the respective diode region (D1) has a diode gate (21) which is controlled by a diode gate signal (G D ) is controlled, and - the procedure has: - applying a positive voltage to the diode gate (21) in the diode region (D1) in the second switching device (200) as the diode gate signal (G D ) to turn the diode gate (21) ON at a second time prior to a first time at which a positive voltage is applied to the first gate (11) in the first switching device (100) as the first gate signal (G I1 ) is applied to turn the transistor region (T1) ON, and - Setting the diode gate signal (G D ) to a negative voltage or a zero voltage at the first time or at a time before the first time to turn OFF the diode gate (21) in the diode region (D1) in the second switching device (200).

Description

BACKGROUND OF THE INVENTIONField of the InventionThe present invention relates to methods of controlling a semiconductor device.Description of the Prior ArtConventionally, a method for controlling a reverse conducting insulated gate bipolar transistor (RC-IGBT) including an IGBT and a free wheeling diode on the same semiconductor substrate has been changed according to either one of the conduction states, i.e., a forward mode in which a current flows through the IGBT or a reverse mode in which a current flows through the free wheeling diode, as disclosed in Japanese Patent No. 6,652,173 B2.The document DE 11 2019 001 054 T5 shows a semiconductor device in which a cost-effective protective diode is formed with a low power loss. A semiconductor substrate side of a gate electrode formed on a surface of an anode of a semiconductor substrate including silicon is surrounded by a p-layer, an n-layer and a p-layer via a gate insulating film. The anode is in contact with the p-layer with a low resistance and is also in contact with the n-layer or the p-layer, and a Schottky diode is formed between the anode and the n-layer or the p-layer.WO 2021 / 112 076 A1 discloses a semiconductor device in which the carrier concentration in a drift zone of a semiconductor substrate is controlled by the voltage applied to the gate electrode of a gated diode. In the reverse recovery state, a zero potential or positive bias signal is applied between the gate electrode and the anode, thereby forming an electron layer at the interface of the gate electrode. In the forward delay state, a negative bias signal is applied between the gate electrode and the anode, thereby forming a hole layer at the interface of the gate electrode. After the forward delay state, the negative bias voltage is switched to a voltage signal for applying a zero voltage or a positive bias voltage. The gated diode variably controls the duration of application of the zero voltage or the positive bias voltage depending on the off-time of a series-connected IGBT.Changing the control method in accordance with a conduction state of the RC-IGBT as described above requires detection or estimation of an operation state of the RC-IGBT. Consequently, their implementation was very difficult.SummaryIt is an object of the present invention to provide simplified methods of controlling a semiconductor device.The object on which the invention is based is achieved according to the invention alternatively by a method for controlling a semiconductor device having the features of one of Claims 1, 2 and 3. Advantageous refinements are the subject matter of the respective dependent claims.According to the invention, a semiconductor device based on a first method according to the invention comprises a first switching device and a second switching device connected in series between a first potential and a second potential lower than the first potential, wherein the first and second switching devices each comprise a transistor region and a diode region connected in antiparallel to the transistor region, wherein the transistor region comprises a first gate controlled by a first gate signal, and wherein the diode region comprises a diode gate controlled by a diode gate signal.The first method according to the invention comprises:applying a positive voltage to the diode gate in the diode region in the second switching device as the diode gate signal to turn ON the diode gate at a second timing earlier than a first timing at which a positive voltage is applied to the first gate in the first switching device as the first gate signal to turn ON the transistor region; andsetting the diode gate signal to a negative voltage or a zero voltage at the first time or at a time before the first time to turn OFF the diode gate in the diode region in the second switching device.According to the invention, a semiconductor device based on a second method according to the invention comprises a first switching device and a second switching device connected in series between a first potential and a second potential lower than the first potential, wherein the first and second switching devices each comprise a transistor region and a diode region connected in antiparallel with the transistor region. A respective transistor region has a first gate controlled by a first gate signal and a second gate controlled by a second gate signal. The transistor regions are arranged between a respective first main electrode and a respective second main electrode, which are electrically separated from each other. The respective first gate signal is a signal with respect to the first potential of the respective first main electrode. The respective second gate signal is a signal with respect to the second potential of the respective second main electrode.The second method according to the invention comprises:applying a positive voltage to the second gate as the second gate signal to turn ON the second gate at a second time point that is earlier than a first time point at which a negative voltage or a zero voltage is applied to the first gate as the first gate signal to turn OFF the transistor region; andsetting the second gate signal to the negative voltage or the zero voltage to turn OFF the second gate between the first time and a third time when a positive voltage is applied to the first gate in the first switching device as the first gate signal to turn ON the transistor region.According to the invention, a semiconductor device according to a third method of the invention comprises a first switching device and a second switching device connected in series between a first potential and a second potential lower than the first potential, the first and second switching devices each comprising a transistor region and a diode region connected in antiparallel with the transistor region. A respective transistor region has a first gate controlled by a first gate signal and a second gate controlled by a second gate signal. The respective diode region has a diode gate which is controlled by a diode gate signal. The transistor regions are each arranged between a respective first main electrode and a respective second main electrode, which are electrically separated from each other. The respective first gate signal is a signal with respect to the first potential of the respective first main electrode. The respective second gate signal is a signal with respect to the second potential of the respective second main electrode.The third method according to the invention comprises:applying a positive voltage to the second gate in the first switching device as the second gate signal to turn ON the second gate at a second timing earlier than a first timing at which a negative voltage or a zero voltage is applied to the first gate as the first gate signal to turn OFF the transistor region;setting the second gate signal to the negative voltage or the zero voltage to turn OFF the second gate between the first time and a third time when a positive voltage is applied to the first gate in the first switching device as the first gate signal to turn ON the transistor region;applying a positive voltage to the diode gate in the diode region in the second switching device as the diode gate signal to turn ON the diode gate at a fourth timing earlier than the third timing at which the transistor region is turned ON; andsetting the diode gate signal to the negative voltage or the zero voltage at the third time or at a time before the third time to turn OFF the diode gate in the diode region in the second switching device.Since the semiconductor device underlying the present invention has diode gates in the diode region controlled by a gate signal, control for turning ON the diode gates in preparing the reverse recovery of the diode region reduces an amount of injected holes in the diode region and reduces the reverse recovery loss in the subsequent reverse recovery of the diode region. Therefore, in the semiconductor device embodying the present invention, which includes, in the diode region, the diode gates controlled by the gate signal, the need for detecting or estimating an operation state is eliminated in changing a method for controlling the semiconductor device in accordance with its conduction state. This facilitates control.These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.Brief Description of the FiguresFIG. 1 is a circuit diagram illustrating a structure of an inverter circuit according to Embodiment 1; FIG. 2 is a plan view of an RC-IGBT in the inverter circuit according to Embodiment 1 when viewed from the upper surface; FIG. 3 is a plan view of the RC-IGBT in the inverter circuit according to Embodiment 1 when viewed from the bottom surface; FIG. 4 is a cross-sectional view illustrating a structure of the RC-IGBT of the inverter circuit according to Embodiment 1; FIG. 5 is a cross-sectional view illustrating a structure of the RC-IGBT of the inverter circuit according to Embodiment 1; FIG. 6 is a plan view of an RC-IGBT according to a modification of Embodiment 1 when viewed from the upper surface; FIG. 7 is a cross-sectional view of the RC-IGBT in an inverter circuit according to the modification of Embodiment 1; FIG. 8 is a cross-sectional view of the RC-IGBT in the inverter circuit according to the modification of Embodiment 1; FIG. 9 illustrates timing diagrams to be used for controlling the inverter circuit according to Embodiment 1; FIG. 10 illustrates control in the inverter circuit according to Embodiment 1; FIG. 11 illustrates control in the inverter circuit according to Embodiment 1; FIG. 12 illustrates control in the inverter circuit according to Embodiment 1; FIG. 13 illustrates control in the inverter circuit according to Embodiment 1; FIG. 14 illustrates control in the inverter circuit according to Embodiment 1; FIG. 15 illustrates control in the inverter circuit according to Embodiment 1; FIG. 16 illustrates control in the inverter circuit according to Embodiment 1; FIG. 17 illustrates control in the inverter circuit according to Embodiment 1; FIG. 18 is a circuit diagram illustrating a structure of an inverter circuit according to Embodiment 2; FIG. 19 is a plan view of an RC-IGBT in the inverter circuit according to Embodiment 2 when viewed from the upper surface; FIG. 20 is a plan view of the RC-IGBT in the inverter circuit according to Embodiment 2 when viewed from the bottom surface; FIG. 21 is a cross-sectional view illustrating a structure of the RC-IGBT of the inverter circuit according to Embodiment 2; FIG. 22 is a cross-sectional view illustrating a structure of the RC-IGBT of the inverter circuit according to Embodiment 2; FIG. 23 is a circuit diagram illustrating a structure of an inverter circuit according to Embodiment 3; FIG. 24 is a plan view of an RC-IGBT in the inverter circuit according to Embodiment 3 when viewed from the upper surface; FIG. 25 is a plan view of the RC-IGBT in the inverter circuit according to Embodiment 3 when viewed from the bottom surface; FIG. 26 is a cross-sectional view illustrating a structure of the RC-IGBT of the inverter circuit according to Embodiment 3; FIG. 27 is a cross-sectional view illustrating a structure of the RC-IGBT of the inverter circuit according to Embodiment 3; FIG. 28 is a plan view of an RC IGBT in an inverter circuit according to a modification of Embodiment 3 when viewed from the bottom surface; FIG. 29 is a cross-sectional view of a structure of the RC-IGBT in the inverter circuit according to the modification of Embodiment 3; FIG. 30 is a cross-sectional view of the structure of the RC-IGBT in the inverter circuit according to the modification of Embodiment 3; FIG. 31 illustrates timing diagrams to be used for controlling the inverter circuit according to Embodiment 3; FIG. 32 illustrates control in the inverter circuit according to Embodiment 3; FIG. 33 illustrates control in the inverter circuit according to Embodiment 3; FIG. 34 illustrates control in the inverter circuit according to Embodiment 3; FIG. 35 illustrates control in the inverter circuit according to Embodiment 3; FIG. 36 illustrates control in the inverter circuit according to Embodiment 3; FIG. 37 illustrates control in the inverter circuit according to Embodiment 3; FIG. 38 illustrates control in the inverter circuit according to Embodiment 3; FIG. 39 illustrates control in the inverter circuit according to Embodiment 3; FIG. 40 illustrates specific timing diagrams for controlling the RC-IGBTs in Embodiments 1 to 3; and FIG. 41 illustrates a summary of gate control of the RC-IGBT according to Embodiment 3.Description of Embodiments 1 to 3 Controllable by the Invention[Introduction]In the following description of the present invention, an n-type and a p-type indicate semiconductor conductivity types, the first conductivity type is the n-type, and the second conductivity type is the p-type. Conversely, the first conductivity type may be the p-type and the second conductivity type may be the n-type. Further, an n-type represents an impurity concentration lower than that of the n-type, and an n + type represents an impurity concentration higher than that of the n-type. Similarly, a p-type represents an impurity concentration lower than that of the p-type, and a p + type represents an impurity concentration higher than that of the p-type.Since the figures are schematically illustrated, the respective relationships in size and position between images in the different figures are not necessarily accurate, but may be appropriately changed. In the following description, identical reference numerals are assigned to the same constituent elements, and their names and functions are identical. Accordingly, the detailed description thereof may be omitted.Although in the following description, words representing concrete positions and directions including "top", "bottom", "side", "front", and "rear" are sometimes used in the description, these are used for convenience to facilitate understanding of the details of embodiments, and do not refer to the directions for actual use.[Embodiment 1][Device Structure]FIG. 1 is a circuit diagram illustrating a structure of an inverter circuit IV 1 of one phase according to Embodiment 1, which can be controlled according to the present invention.In the inverter circuit IV 1 of FIG. 1, an RC IGBT 100 (a first switching device) functioning as a high-side arm and an RC IGBT 200 (a second switching device) functioning as a low-side arm are connected in series between a power supply potential VCC (a first potential) and a reference potential GND (a second potential). A connection node between the RC IGBT 100 and the RC IGBT 200 is connected to an inductive load L 1.The RC-IGBT 100 has a structure in which an IGBT region T 1 controlled by a gate signal G I1_H (a first gate signal) is connected in antiparallel with a diode region D 1 controlled by a gate signal G D_H (a diode gate signal).Moreover, the RC-IGBT 200 has a structure in which an IGBT region T 2 controlled by a gate signal G I1_1 (a first gate signal) is connected in antiparallel with a diode region D 2 controlled by a gate signal G D_L (a diode gate signal).Here, the gate signal G I_H is provided to the first trench gates formed in the IGBT region T 1, whereas the gate signal G I1_L is provided to the first trench gates formed in the IGBT region T 2. Further, the gate signal G D_H is provided to the diode trenches formed in the diode region D 1, whereas the gate signal G D_L is provided to the diode trenches formed in the diode region D 2.Consequently, applying the control signals such as the gate signals G D_H and G D_L simplifies the control more significantly than conventional semiconductor devices using two gate signals.FIG. 2 is a plan view of the RC IGBT 100 in the inverter circuit IV 1 according to Embodiment 1 when viewed from the upper surface. FIG. 3 is a plan view of the RC IGBT 100 when viewed from the lower surface. The IGBT region T 1 is referred to as an IGBT region 10 (a transistor region) for convenience in the following description, and the diode region D 1 is referred to as a diode region 20 (a diode region). The illustration of, for example, electrodes and insulating layers formed in the semiconductor substrate is omitted in the plan views for simplicity.As illustrated in FIG. 2, the RC-IGBT 100 is composed of IGBT regions 10 and diode regions 20 arranged in stripes, and may be categorized as having a stripe region. The RC-IGBT 100 may be composed of a plurality of diode regions 20 arranged in both vertical and horizontal directions and IGBT regions 10 surrounding the diode regions 20. This can be categorized as having an island geometry. Although the RC-IGBT 100 having the stripe geometry will be described below as an example, the RC-IGBT 100 having the island geometry has the same advantages.In FIG. 2, the IGBT regions 10 and the diode regions 20 extend from one end to another end of the RC IGBT 100, and are alternately arranged in stripes in a direction orthogonal to the extension direction of the IGBT regions 10 and the diode regions 20. Further, the IGBT regions 10 and the diode regions 20 in FIG. 2 may be interchanged with each other, and all of the IGBT regions 10 may be inserted between the diode regions 20. Further, the IGBT regions 10 and the diode regions 20 may be positioned adjacent to each other.[Structure of IGBT Region 10]As illustrated in FIG. 2, the IGBT region 10 includes trench active gates 11 (first gates) arranged in stripes. The trench active gates 11 extend in the longitudinal direction of the IGBT region 10, which coincides with the longitudinal direction of the trench active gates 11.Each of the trench active gates 11 is formed by embedding a gate trench electrode 11a through a gate trench insulating layer 11b in a trench formed in a semiconductor substrate. The gate trench electrodes 11 aof the trench active gates 11 are electrically connected to a gate pad, which is not illustrated.N + type source layers 13 are formed over both sides of the trench active gates 11 in a width direction so as to be in contact with the trench gate insulating layers 11b. Each of the n + type source layers 13 is a semiconductor layer including, for example, arsenic or phosphorus as n-type impurities. A concentration of the n-type impurity is in the range of 1.0×10 17 / cm 3 to 1.0×10 20 / cm 3. The n + type source layers 13 and p + type contact layers 14 are alternately formed in the extension direction of the trench active gates 11.Each of the p + contact layers 14 is a semiconductor layer including, for example, boron or aluminum as p-type impurities. A concentration of the p-type impurity is in the range of 1.0×10 15 / cm 3 to 1.0×10 20 / cm 3.FIG. 4 illustrates a cross-sectional view taken along a dashed line A-A of the RC IGBT 100 in FIG. 2. The RC-IGBT 100 in FIG. 4 includes a semiconductor substrate including an n - type drift layer 1. The n - type drift layer 1 is a semiconductor layer including, for example, arsenic or phosphorus as n-type impurities. A concentration of the n-type impurity is in the range of 1.0×10 12 / cm 3 to 1.0×10 15 / cm 3. The semiconductor substrate extends from the n + type source layers 13 and the p + type contact layers 14 to a p-type collector layer 16. the upper end of the n + type source layers 13 and the p + type contact layers 14 in the plane of paper is referred to as a first main surface (an upper surface) of the semiconductor substrate, and the lower end of the p-type collector layer 16 in the plane of paper is referred to as a second main surface (a lower surface) of the semiconductor substrate. The first main surface of the semiconductor substrate is a main surface on the front side of the RC IGBT 100, and the second main surface of the semiconductor substrate is a main surface on the back side of the RC IGBT 100. The RC-IGBT 100 includes, in the IGBT region 10 which is a cell region, the n-type drift layer 1 between the first main surface and the second main surface facing the first main surface.In the IGBT region 10, an n-type carrier storage layer 2 having a higher impurity than the n - type drift layer 1 is disposed on the n - type drift layer 1 on the first main surface side. The n-type carrier storage layer 2 is a semiconductor layer including, for example, arsenic or phosphorus as n-type impurities. A concentration of the n-type impurity is in the range of 1.0×10 13 / cm 3 to 1.0×10 17 / cm 3. The RC-IGBT 100 may have a structure in which the n - type drift layer 1 occupies a region of the n-type charge storage layer 2 without the n-type charge storage layer 2. the n-type charge storage layer 2 may reduce conduction loss when a current flows through the IGBT region 10. The n-type charge storage layer 2 and the n - type drift layer 1 may be collectively referred to as a drift layer.A p-type base layer 15 is disposed on the n-type carrier storage layer 2 on the first main surface side. The p-type base layer 15 is a semiconductor layer including, for example, boron or aluminum as p-type impurities. A concentration of the p-type impurity is in the range of 1.0×10 12 / cm 3 to 1.0×10 19 / cm 3. The p-type base layer 15 is in contact with the gate trench insulating layers 11 bof the trench active gates 11, the n + type source layers 13 are disposed on the p-type base layer 15 on the first main surface side so as to be in contact with the gate trench insulating layers 11 bof the trench active gates 11, and the p + contact layers 14 are disposed on the remaining regions on the p-type base layer 15. The n + type source layers 13 and the p + type contact layers 14 form the first main surface of the semiconductor substrate. The p + type contact layers 14 are regions having a higher p-type impurity than the p-type base layer 15. Alternatively, the p + type contact layers 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.Further, the RC-IGBT 100 includes, on the n - type drift layer 1 on the second main surface side, an n-type buffer layer 3 having a higher impurity than the n - type drift layer 1. The n-type buffer layer 3 suppresses punch-through of a depletion layer extending from the p-type base layer 15 toward the second main surface side when the RC-IGBT 100 is in an OFF state. The n-type buffer layer 3 may be formed by injecting phosphorus (P) and / or protons (H +). for example. The n-type buffer layer 3 has an n-type impurity concentration in a range of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3.The RC-IGBT 100 may have a structure in which the n - drift layer 1 occupies a region of the n-type buffer layer 3 in FIG. 4 without the n-type buffer layer 3.The RC-IGBT 100 has the p-type collector layer 16 on the n-type buffer layer 3 on the second main surface side. In other words, the p-type collector layer 16 is disposed between the n - drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as p-type impurities. A concentration of the p-type impurity is in the range of 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3. The p-type collector layer 16 forms the second main surface of the semiconductor substrate. A portion of the p-type collector layer 16 may extend from the IGBT region 10 and enter the diode region 20.The RC-IGBT 100 has trenches that penetrate the p-type base layer 15 from the first main surface of the semiconductor substrate and reach the n - type drift layer 1. Each of the trenches includes the trench active gate 11 formed by embedding the trench gate electrode 11 athrough the trench gate insulating film 11 b.The gate trench electrodes 11a face the n - type drift layer 1 through the gate trench insulating layers 11b. The gate trench isolation layers 11 bof the trench active gates 11 are in contact with the p-type base layer 15 and the n + type source layers 13, and when a gate driving voltage is applied to the gate trench electrodes 11 a, a channel is formed in the p-type base layer 15 which is in contact with the gate trench isolation layers 11 bof the trench active gates 11.An interlayer insulating film 4 is disposed on the gate trench electrodes 11 aof the trench active gates 11. The interlayer insulating film 4 on the gate trench electrodes 11 aof the trench active gates 11 isolates the gate trench electrodes 11 afrom an emitter electrode 6 so that the gate trench electrodes 11 areceptor the gate signal G I1.A barrier metal 5 is formed on a region without the interlayer insulating film 4 on the first main surface of the semiconductor substrate and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor including titanium (Ti), for example, a conductor formed of TiSi obtained by alloying silicon (Si) with titanium nitride or titanium. The barrier metal 5 is in ohmic contact with and electrically connected to the n + type source layer 13 and an n + type contact layer 17. the emitter electrode 6 is disposed on the barrier metal 5. The emitter electrode 6 may be formed of, for example, an aluminum alloy such as an aluminum silicon alloy (an Al-Si based alloy). The emitter electrode 6 may also be an electrode obtained by forming, on an electrode formed of an aluminum alloy, a metal layer having a plurality of layers on each of which a plated layer is formed by electroless plating or electroplating. The plated layers formed by electroless plating or electroplating may be, for example, nickel (Ni) plated layers. When the RC-IGBT 100 has a thin region between the emitter electrode 6 and the adjacent interlayer insulating film 4 and the thin region is not sufficiently embedded by the emitter electrode 6, tungsten having embedding characteristics better than those of the emitter electrode 6 can be disposed on the thin region, and then the emitter electrode 6 can be disposed on the tungsten. The emitter electrode 6 may be disposed on the n + type source layer 13 and the n + type contact layer 17 without the barrier metal 5. Moreover, the barrier metal 5 may be disposed only on the n-type semiconductor layers such as the n + type source layers 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode.A collector electrode 7 is disposed on the p-type collector layer 16 on the second main surface side. The collector electrode 7 may be formed of an aluminum alloy or an aluminum alloy and plated layers, similar to the emitter electrode 6. The collector electrode 7 is in ohmic contact with and electrically connected to the p-type collector layer 16.A cross-sectional view of the RC-IGBT 100 in FIG. 5 taken along a dotted line B-B differs from the cross-sectional view taken along the dotted line A-A by excluding the n + type source layers 13 which are in contact with the trench active gates 11 and formed on the first main surface of the semiconductor substrate. In other words, the n + type source layers 13 are selectively disposed on a p-type base layer on the first main surface side. The p-type base layer here denotes a p-type base layer, which is a general name for the p-type base layer 15 and the p + type contact layers 14.[Structure of Diode Region 20]As illustrated in FIG. 2, diode trench gates 21 (diode gates) extend from one end to the other end of the diode region 20, which is a cell region, along the first main surface of the RC IGBT 100. Each of the diode trench gates 21 is formed by embedding a diode trench electrode 21a through a diode trench insulating layer 21b in a trench of the diode region 20 formed in the semiconductor substrate.As illustrated in FIG. 5, the diode trench electrodes 21a face the n-type drift layer 1 through the diode trench insulating layers 21b. The n + type contact layers 17 and p + type contact layers 24 are disposed between the two adjacent diode trench gates 21. Each of the n + type contact layers 17 is a semiconductor layer including, for example, arsenic or phosphorus as n-type impurities. A concentration of the n-type impurity is in the range of 1.0×10 17 / cm 3 to 1.0×10 20 / cm 3. Each of the p + type contact layers 24 is a semiconductor layer including, for example, boron or aluminum as p-type impurities. A concentration of the p-type impurity is in the range of 1.0×10 15 / cm 3 to 1.0×10 20 / cm 3. The n + type contact layers 17 and the p + type contact layers 24 are alternately formed in the longitudinal direction of the diode trench gates 21.As illustrated in the cross-sectional view of FIG. 4 taken along the dashed line A-A of the RC IGBT 100, the diode region 20 has the semiconductor substrate including the n - type drift layer 1 also in the IGBT region 10. The n - type drift layer 1 in the diode region 20 and the IGBT region 10 is continuously and integrally formed, and is included in the same semiconductor substrate. The upper end of the n + type contact layers 17 in the plane of the paper is referred to as the first main surface of the semiconductor substrate, and the lower end of an n + type cathode layer 26 in the plane of the paper is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 20 is flush with the first main surface of the IGBT region 10, and the second main surface of the diode region 20 is flush with the second main surface of the IGBT region 10.The diode region 20 includes the n-type charge storage layer 2 disposed on the n - type drift layer 1 on the first main surface side and the n-type buffer layer 3 on the n - type drift layer 1 on the second main surface side, similarly to the IGBT region 10. Even when the IGBT region 10 includes the n-type charge storage layer 2, the diode region 20 can exclude the n-type charge storage layer 2. Further, the n-type drift layer 1, the n-type charge storage layer 2, and the n-type buffer layer 3 may be collectively referred to as a drift layer, similar to that in the IGBT region 10. The n + type contact layers 17 are disposed between the n - drift layer 1 and the first main surface.The n + type contact layers 17 are disposed on a p-type anode layer 25 on the first main surface side. A concentration of n-type impurities of the n + type contact layers 17 may be identical to or different from that of the n + type source layers 13 in the IGBT region 10. The n + type contact layers 17 form the first main surface of the semiconductor substrate. The n + type contact layers 17 are regions having a higher concentration than that of the p-type anode layer 25.The diode region 20 includes the n + type cathode layer 26 on the n-type buffer layer 3 on the second main surface side. The n + type cathode layer 26 is disposed between the n - drift layer 1 and the second main surface. The n + type cathode layer 26 is a semiconductor layer including, for example, arsenic or phosphorus as n-type impurities. A concentration of the n-type impurity is in the range of 1.0×10 16 / cm 3 to 1.0×10 21 / cm 3. The n + type cathode layer 26 is formed in a part or over the entire diode region 20. The n + type cathode layer 26 forms the second main surface of the semiconductor substrate. Although not illustrated, selectively doping a region of the n + type cathode layer 26 with p-type impurities may additionally form a p-type cathode layer including a part of a region of the n + type cathode layer 26 as a p-type semiconductor.The diode region 20 of the RC IGBT 100 has trenches that penetrate the p-type anode layer 25 from the first main surface of the semiconductor substrate and reach the n - type drift layer 1. The diode trench gate 21 is formed by embedding the diode trench electrode 21 athrough the diode trench isolation layer 21 binto the trench of the diode region 20.The barrier metal 5 is formed on the diode trench electrodes 21 aand a p + type contact layer 24. The barrier metal 5 is in ohmic contact with and electrically connected to the p + type contact layer 24. the barrier metal 5 may have the same structure as that of the barrier metal 5 in the IGBT region 10. The emitter electrode 6 in the diode region 20 and the IGBT region 10 are continuously formed. The emitter electrode 6 in the diode region 20 may be in ohmic contact with the p + type contact layer 24 without the barrier metal 5 as in the IGBT region 10. The interlayer insulating film 4 is formed on the diode trench electrodes 21 aof the diode trench gates 21, and isolates the diode trench electrodes 21 afrom the emitter electrode 6 so that the diode trench electrodes 21 areceptor the gate signal G D.The collector electrode 7 is disposed on the n + type cathode layer 26 on the second main surface side. The collector electrode 7 in the diode region 20 and the IGBT region 10 is continuously formed, similar to the emitter electrode 6.As illustrated in FIG. 5, the cross-sectional view of the RC-IGBT 100 taken along the broken line B-B differs from the cross-sectional view taken along the broken line A-A in FIG. 4 in that the p + type contact layer 24 is included between the p-type anode layer 25 and the barrier metal 5. The barrier metal 5 is in ohmic contact with and electrically connected to the p + type contact layer 24. the barrier metal 5 may have the same structure as that of the barrier metal 5 in the IGBT region 10. The emitter electrode 6 in the diode region 20 and the IGBT region 10 are continuously formed. The emitter electrode 6 in the diode region 20 may be in ohmic contact with the p + type contact layer 24 without the barrier metal 5 as in the IGBT region 10.FIG. 3, which is a plan view of the RC IGBT 100, omits the collector electrode 7 from being viewed from the lower surface, that is, from the collector electrode 7 for convenience, and illustrates an exposed state of the p-type collector layer 16 and the n + type cathode layer 26; FIGS. 4 and 5 also illustrate the cross-sectional view taken along the dashed line A-A and the cross-sectional view taken along the dashed line B-B, respectively, in FIG. 3.[Modification]Next, an RC-IGBT 101 according to a modification of Embodiment 1 will be described with reference to FIGS. 6 to 8. FIG. 6 is a plan view of the RC IGBT 101 when viewed from the upper surface. FIG. 7 is a cross-sectional view taken along a dotted line A-A in FIG. 6. FIG. 8 is a cross-sectional view taken along a dotted line B-B in FIG. 6.[Structure of IGBT Region 10]As illustrated in FIG. 6, the IGBT region 10 of the RC IGBT 101 includes the trench active gates 11 and dummy trench gates 12 arranged in stripes. The trench active gates 11 and the dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, which coincides with the longitudinal direction of the trench active gates 11 and the dummy trench gates 12.As illustrated in FIG. 7, each of the trench active gates 11 is formed by embedding the gate trench electrode 11 athrough the gate trench insulating layer 11 binto the trench formed in the semiconductor substrate. Each of the dummy trench gates 12 is formed by embedding a dummy trench electrode 12 athrough a dummy trench insulating layer 12 binto a trench in the semiconductor substrate. The gate trench electrodes 11 aof the trench active gates 11 are electrically connected to a gate pad, which is not illustrated. The dummy trench electrodes 12 aof the dummy trench gates 12 are electrically connected to the emitter electrode 6 formed on a first main surface of the RC-IGBT 101.The n + type source layers 13 are formed over both sides of the trench active gates 11 in the width direction so as to be in contact with the trench gate insulating layers 11 b. Each of the n + type source layers 13 is a semiconductor layer including, for example, arsenic or phosphorus as n-type impurities. A concentration of the n-type impurity is in the range of 1.0×10 17 / cm 3 to 1.0×10 20 / cm 3. The n + type source layers 13 and the p + type contact layers 14 are alternately formed in the extension direction of the trench active gates 11. The p + type contact layer 14 is also disposed between the two adjacent dummy trench gates 12. Each of the p + type contact layers 14 is a semiconductor layer including, for example, boron or aluminum as p-type impurities. A concentration of the p-type impurity is in the range of 1.0×10 15 / cm 3 to 1.0×10 20 / cm 3.The number of dummy trench gates 12 included in each of the IGBT regions 10 may be one or more, or zero. In other words, all the trenches included in each of the IGBT regions 10 may be the trench active gates 11. In such a case, the RC-IGBT 100 is formed in FIG. 2.The gate trench electrodes 11a face the n - type drift layer 1 through the gate trench insulating layers 11b. The dummy trench electrodes 12 afacing the n - type drift layer 1 through the dummy trench insulating layers 12 b. In FIGS. 7 and 8 illustrating the cross-sectional views taken along the broken line A-A and the broken line B-B, respectively, the interlayer insulating film 4 isolates the n + type source layers 13 and the p + type contact layers 14 in a region including the dummy trench gates 12 from the emitter electrode 6.The dummy trench gates 12 may increase the carrier storage effect and may provide an advantage of reducing conduction loss by reducing resistance.[Operations]Next, the gate control in the RC-IGBT 100 will be described with reference to FIGS. 9 to 17. FIG. 9 illustrates timing diagrams of the gate control in the RC IGBT 100 functioning as the high-side arm in the inverter circuit IV 1 in FIG. 1 in a left diagram, and timing diagrams of the gate control in the RC IGBT 200 functioning as the low-side arm in the same circuit in a right diagram.In the left diagram in FIG. 9, an upper level illustrates a timing chart of the gate signal G I1, which is provided to the trench active gates 11 in the IGBT regions, a middle level illustrates a timing chart of the gate signal G D, which is provided to the trench diode gates 21 in the diode regions, and a lower level illustrates a timing chart of the output of the inverter circuit IV 1.In the right diagram in FIG. 9, an upper level illustrates a timing chart of the gate signal G I1, which is provided to the trench active gates 11 in the IGBT regions, a middle level illustrates a timing chart of the gate signal G D, which is provided to the trench diode gates 21 in the diode regions, and a lower level illustrates a timing chart of the output of the inverter circuit IV 1.As illustrated in FIG. 9, the RC IGBT 100 and the RC IGBT 200 are controlled by pulse width modulation (PWM). The trench active gates 11 in the IGBT regions receive pulse signals inverted between the high-side arm and the low-side arm according to the PWM signals. The diode trench gates 21 in the diode regions receive a pulse signal generated with respect to the gate signal G I1 provided to the active trench gates 11.Since the RC-IGBT 100 and the RC-IGBT 200 have the same structure, the following describes the RC-IGBT 100 as an example. Each of FIGS. 10 to 17 illustrates a timing chart of the RC-IGBT 100 in a left diagram, and a cross-sectional view of the RC-IGBT 100 corresponding to that in FIG. 4 in a right diagram. Figs. 10 to 17 schematically illustrate a quantity of injected holes using the size of an arrow.FIG. 10 illustrates a charge carrier state in which the RC-IGBT 100 in the right diagram at a time t 1 in the time chart of the left diagram. At time t 1, the IGBT region 10 is placed in a forward conduction, and only the trench active gates 11 that are closer to the emitter electrode 6 in the IGBT region 10 are ON. When the collector electrode 7 injects holes, the IGBT region 10 is placed in the forward conduction by channel layers CH formed on the side surfaces of the trench active gates 11.FIG. 11 illustrates a charge carrier state in the RC-IGBT 100 in the right diagram, at a time t 2 ain the timing diagram of the left diagram. At time t 2 a, the turn-off of the IGBT region 10 is prepared. The diode trench gates 21 in the diode region 20 are ON, so that channel layers CH are formed on the side surfaces of the diode trench gates 21. However, since holes are not injected into the diode region 20 from the bottom surface, but into the IGBT region 10, the diode region 20 does not undergo a large change.FIG. 12 illustrates a charge carrier state in the RC-IGBT 100 in the right diagram, at a time t 2 bin the timing diagram of the left diagram. At time t 2 b, the IGBT region 10 is turned off, and the trench active gates 11 and the diode trench gates 21 are also OFF. However, since the collector electrode 7 continues to inject holes until the diode region 20, which is an opposite arm of the IGBT region 10, conducts, the IGBT region 10 is continuously brought into the forward conduction.FIG. 13 illustrates a charge carrier state in which the RC-IGBT 100 in the right diagram at a time t 3 in the time chart of the left diagram. At time t 3, the IGBT region 10 does not conduct. Since all the gates are OFF, the injection of holes ends and the IGBT region 10 does not conduct. These describe the IGBT mode, and are the same operations as those of the conventional RC-IGBTs.FIG. 14 illustrates a charge carrier state in which the RC-IGBT 100 in the right diagram at a time t 4 in the time chart of the left diagram. At time t 4, the diode region 20 is placed in a reverse conduction. The trench active gates 11 in the IGBT region 10 are ON but away from the diode region 20.FIG. 15 illustrates a charge carrier state in the RC-IGBT 100 in the right diagram, at a time t 5 ain the timing diagram of the left diagram. At time t 5 a, the reverse recovery of the diode region 20 is prepared. Since the diode trench gates 21 are ON, the amount of injected holes in the diode region 20 decreases.FIG. 16 illustrates a charge carrier state in the RC-IGBT 100 in the right diagram, at a time t 5 bin the timing diagram of the left diagram. The time point t 5 bis a reverse recovery time point of the diode region 20. the IGBT region 10, which is an opposite arm of the diode region 20, turns ON causes reverse recovery of the diode region 20. Therefore, the backward recovery loss decreases.FIG. 17 illustrates a charge carrier state in which the RC-IGBT 100 in the right diagram at a time t 6 in the time chart of the left diagram. At time t 6, the diode region 20 does not conduct. Since a voltage is applied in a current blocking direction for a diode, the diode region 20 does not conduct.In the aforementioned diode mode, the reverse recovery loss decreases significantly more than that of the conventional RC-IGBTs.[Embodiment 2][Device Structure]FIG. 18 is a circuit diagram illustrating a structure of an inverter circuit IV 2 of one phase according to Embodiment 2, which can be controlled according to the present invention.In the inverter circuit IV 2 of FIG. 18, an RC-IGBT 100A (a first switching device) functioning as a high-side arm and an RC-IGBT 200A (a second switching device) functioning as a low-side arm are connected in series between the power supply potential VCC and the reference potential GND. A connection node between the RC IGBT 100A and the RC IGBT 200A is connected to the inductive load L 1. The RC IGBT 100A has a structure in which an IGBT region T 10 controlled by a gate signal G I1_H( a first gate signal) and a gate signal G I2-H( a second gate signal) is connected in antiparallel with a diode region D 10.Further, the RC IGBT 200A has a structure in which an IGBT region T 20 controlled by a gate signal G I1_L( a first gate signal) and a gate signal G I2_L( a second gate signal) is connected in antiparallel with a diode region D 20.Here, the gate signal G I2_H is provided to the second gate trenches formed in the IGBT regions T 10, whereas the gate signal G I2_L is provided to the second gate trenches formed in the IGBT regions T 20.Applying control signals such as the gate signal G I2_H and the gate signal G I2_L simplifies control and can reduce power loss more significantly than the structure in which each arm is controlled by a gate signal.FIG. 19 is a plan view of the RC IGBT 100A in the inverter circuit IV 2 according to Embodiment 2 when viewed from the upper surface. FIG. 20 is a plan view of the RC IGBT 100A when viewed from the lower surface. The IGBT region T 10 is referred to as an IGBT region 10 for convenience in the following description, and the diode region D 10 is referred to as a diode region 20.As illustrated in FIG. 19, the RC-IGBT 100A is composed of IGBT regions 10 and diode regions 20 arranged in stripes. The IGBT regions 10 are identical to those of the RC-IGBT 100 in FIG. 2, however, in the diode regions 20, only the p + type contact layer 24 is disposed between the two adjacent diode trench gates 21.In FIG. 20, trench active gates 18 (second gates) are arranged in stripes on the lower surface of the IGBT regions 10. The trench active gates 18 extend in the longitudinal direction of the IGBT region 10, which coincides with the longitudinal direction of the trench active gates 18.Each of the trench active gates 18 is formed by embedding a gate trench electrode 18a through a gate trench insulating layer 18b in a trench formed in a semiconductor substrate. The gate trench electrodes 18 aof the trench active gates 18 are electrically connected to a gate pad (a second gate pad), which is not illustrated.The p-type collector layer 16 is formed over both sides of the trench active gates 18 in the width direction to be in contact with the trench gate insulating layers 18 b. The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as p-type impurities. A concentration of the p-type impurity is in the range of 1.0×10 12 / cm 3 to 1.0×10 19 / cm 3. The p-type collector layers 16 and n + type collector layers 19 are alternately formed in the extension direction of the trench active gates 18.Each of the n + type collector layers 19 is a semiconductor layer including, for example, arsenic or phosphorus as n-type impurities. A concentration of the p-type impurity is in the range of 1.0×10 17 / cm 3 to 1.0×10 20 / cm 3.In FIG. 20, diode trench gates 22 are arranged in stripes on the lower surface of the diode region 20. The diode trench gates 22 extend in the longitudinal direction of the diode region 20, which coincides with the longitudinal direction of the diode trench gates 22.Each of the diode trench gates 22 is formed by embedding a diode trench electrode 22a through a diode trench insulating layer 22b in a trench formed in the semiconductor substrate. The n + type cathode layer 26 is disposed between the two adjacent diode trench gates 22.FIGS. 21 and 22 illustrate cross-sectional views taken along a broken line C-C and a broken line D-D, respectively, in the RC-IGBT 100A in FIGS. 19 and 20, identical reference numerals are applied to the constituent elements identical to those of the RC-IGBT 100 in FIGS. 4 and 5, and the overlapping description is omitted.In FIG. 21, the n + type collector layer 19, the p type collector layer 16, and the n type buffer layer 3 are formed in this order from the second main surface of the semiconductor substrate in the lower surface of the IGBT region 10. These impurity layers are in contact with the gate trench isolation layers 18 bon both sides of the trench active gates 18 in the width direction. Further, the bottom of the trench active gates 18 reaches the n - type drift layer 1.The interlayer insulating film 4 is disposed on the gate trench electrodes 18 aof the trench active gates 18. The interlayer insulating film 4 on the gate trench electrodes 18 aof the trench active gates 18 isolates the gate trench electrodes 18 afrom the collector electrode 7 so that the gate trench electrodes 18 areceptor the gate signal G I2.The barrier metal 5 is formed in a region without the interlayer insulating film 4 on the second main surface of the semiconductor substrate and on the interlayer insulating film 4.In FIG. 21, the p + type contact layer 24, the p type anode layer 25, and the n type carrier storage layer 2 are formed in this order from the first main surface of the semiconductor substrate in the upper surface of the diode region 20. These impurity layers are in contact with the diode trench isolation layers 21 bon both sides of the diode trench gates 21 in the width direction. Further, the bottom of the diode trench gates 21 reaches the n-type drift layer 1.The interlayer insulating film 4 is disposed on the gate trench electrodes 21 aof the diode trench gates 21. Although the interlayer insulating film 4 is formed on the diode trench electrodes 21 aof the diode trench gates 21, the diode trench electrodes 21 aare electrically connected to the emitter electrode 6.The barrier metal 5 is formed on a region without the interlayer insulating film 4 on the first main surface of the semiconductor substrate and on the interlayer insulating film 4.In FIG. 21, the n + type cathode layer 26 and the n type buffer layer 3 are formed in this order from the second main surface of the semiconductor substrate in the lower surface of the diode region 20. These impurity layers are in contact with the diode trench isolation layers 22 bon both sides of the diode trench gates 22 in the width direction. Further, the bottom of the diode trench gates 22 reaches the n-type drift layer 1.The interlayer insulating film 4 is disposed on the diode trench electrodes 22 aof the diode trench gates 22. Although the interlayer insulating film 4 is formed on the diode trench electrodes 22 aof the diode trench gates 22, the diode trench electrodes 22 aare electrically connected to the collector electrode 7.In FIG. 22, the p + type contact layer 14, the p type base layer 15, and the n type charge storage layer 2 are formed in this order from the first main surface of the semiconductor substrate in the upper surface of the IGBT region 10. These impurity layers are in contact with the gate trench isolation layers 11 bon both sides of the trench active gates 11 in the width direction. Further, the bottom of the trench active gates 11 reaches the n - type drift layer 1.In FIG. 22, the p-type collector layer 16 and the n-type buffer layer 3 are formed in this order from the second main surface of the semiconductor substrate in the lower surface of the IGBT region 10. These impurity layers are in contact with the gate trench isolation layers 18 bon both sides of the trench active gates 18 in the width direction. Further, the bottom of the trench active gates 18 reaches the n-type drift layer 1.The turn-off loss can be significantly reduced in the IGBT regions in the aforementioned inverter circuit IV 2 according to Embodiment 2, in a relatively easy-to-control method for exclusively controlling the trench active gates 11 and 18.The diode trench gates 21 are formed in the upper surface of the diode region 20, the diode trench gates 22 are formed in the lower surface of the diode region 20, and the diode trench electrodes 21 aand the diode trench electrodes 22 aare respectively set to potentials of the emitter electrode 6 and the collector electrode 7. Consequently, the diode trench gates 21 and 22 that do not operate actively can make the arrangement of the trenches uniform, reduce occurrence of a partially high electric field due to a non-uniform structure, and easily increase the withstand voltage. The trench active gates 11 in the upper surface of the IGBT region 10 need not face the trench active gates 18 in the lower surface of the IGBT region 10. The number of the trench active gates 11 need not be identical to that of the trench active gates 18. Similarly, the diode trench gates 21 in the upper surface of the diode region 20 need not face the diode trench gates 22 in the lower surface of the diode region 20. The number of diode trench gates 21 need not be identical to that of the diode trench gates 22.[Embodiment 3][Device Structure]FIG. 23 is a circuit diagram illustrating a structure of an inverter circuit IV 3 of one phase according to Embodiment 3, which can be controlled according to the present invention.In the inverter circuit IV 3 of FIG. 23, an RC IGBT 100B (a first switching device) functioning as a high-side arm and an RC IGBT 200B (a second switching device) functioning as a low-side arm are connected in series between the power supply potential VCC and the reference potential GND. A connection node between the RC IGBT 100B and the RC IGBT 200B is connected to the inductive load L 1. The RC IGBT 100B has a structure in which the IGBT region T 10 controlled by the gate signal G I1_H( first gate signal) and the gate signal G I2_H( second gate signal) is connected in antiparallel to the diode region D 1 controlled by the gate signal G D_H( diode gate signal).Further, the RC IGBT 200B has a structure in which the IGBT region T 20 controlled by the gate signal G I1_L( first gate signal) and the gate signal G I2_L( second gate signal) is connected in antiparallel to the diode region D 2 controlled by the gate signal G D_L( diode gate signal).Here, the gate signal G I2_H is provided to the second gate trenches formed in the IGBT region T 10, whereas the gate signal G I2_L is provided to the second gate trenches formed in the IGBT region T 20. Further, the gate signal G D_H is provided to the diode trenches formed in the diode region D 1, whereas the gate signal G D_L is provided to the diode trenches formed in the diode region D 2.Consequently, application of the control signals such as the gate signal G I2_H, the gate signal G I2_L, the gate signal G D_H, and the gate signal G D_L simplifies control and can reduce power loss more significantly than the structure in which each arm is controlled by a gate signal.FIG. 24 is a plan view of the RC IGBT 100B in the inverter circuit IV 3 according to Embodiment 3 when viewed from the upper surface. FIG. 25 is a plan view of the RC IGBT 100B when viewed from the lower surface. The IGBT region T 10 is referred to as an IGBT region 10 for convenience in the following description, and the diode region D 1 is referred to as a diode region 20.As illustrated in FIG. 24, the structure of the upper surface of the RC-IGBT 100B is identical to that of the RC-IGBT 100 according to Embodiment 1 in FIG. 2, and the structure of the lower surface of the RC-IGBT 100B is identical to that of the RC-IGBT 100A according to Embodiment 2 in FIG. 20.FIGS. 26 and 27 illustrate cross-sectional views taken along a broken line C-C and a broken line D-D, respectively, in the RC-IGBT 100B in FIGS. 24 and 25. Although the cross-sectional structure in FIG. 26 is basically identical to that of the RC-IGBT 100A according to Embodiment 2 in FIG. 21, the n + type contact layers 17, the p-type anode layer 25, and the n-type carrier storage layer 2 are formed in this order from the first main surface of the semiconductor substrate in the upper surface of the diode region 20 in FIG. 26. These impurity layers are in contact with the diode trench isolation layers 21 bon both sides of the diode trench gates 21 in the width direction. Further, the bottom of the diode trench gates 21 reaches the n-type drift layer 1. the diode trench electrodes 21a have a structure for receiving the gate signal G D. The trench active gates 11 in the upper surface of the IGBT region 10 need not face the trench active gates 18 in the lower surface of the IGBT region 10. The number of the trench active gates 11 need not be identical to that of the trench active gates 18. Similarly, the diode trench gates 21 in the upper surface of the diode region 20 need not face the diode trench gates 22 in the lower surface of the diode region 20. The number of diode trench gates 21 need not be identical to that of the diode trench gates 22.Although the cross-sectional structure in FIG. 27 is basically identical to that of the RC-IGBT 100A according to Embodiment 2 in FIG. 22, the diode trench electrodes 21 ahave a structure for receiving the gate signal G D.In the inverter circuit IV 3 according to Embodiment 3, the trench active gates 11 are formed in the upper surface of the IGBT region 10, the trench active gates 18 are formed in the lower surface of the IGBT region 10, the diode trench gates 21 are formed in the upper surface of the diode region 20, the diode trench gates 22 are formed in the lower surface of the diode region 20, and the gate signal G D is provided to the diode trench gates 21 to control the RC IGBT 100B. The turn-off loss in the IGBT regions and the reverse recovery loss in the diode regions can be significantly reduced in a relatively simple control method under this structure. This mechanism will be described later.[Modification]Next, an RC-IGBT 100B 1 according to a modification of Embodiment 3 will be described with reference to FIGS. 28 to 30. FIG. 28 is a plan view of the RC IGBT 100B 1 as viewed from the lower surface. FIGS. 29 and 30 illustrate cross-sectional views taken along a broken line C-C and a broken line D-D in FIG. 28, respectively. The upper surface structure of the RC-IGBT 100B 1 is identical to that of FIG. 24.On the lower surface of the IGBT region 10 in FIG. 28, a plurality of p-type collector layers 16 are arranged in stripes, and a plurality of n + type collector layers 19 are arranged such that the p-type collector layers 16 surround the respective n + collector layers 19. The n-type buffer layer 3 is a region surrounded by the p-type collector layers 16.In FIG. 28, the n + type cathode layer 26 is formed throughout the lower surface of the diode region 20.Although the cross-sectional structure of the upper surface of the IGBT region 10 in FIG. 29 is identical to that of FIG. 26, a planar gate 181 is formed in the lower surface of the IGBT region 10 instead of the trench active gates 18. The planar gate 181 includes gate insulating films 181 bbetween ends of the adjacent n + type collector films 19, respectively, and gate electrodes 181 adisposed on the gate insulating films 181 b. The gate electrodes 181 aare covered by the interlayer insulating film 4 to isolate the gate electrodes 181 afrom the collector electrode 7, so that the gate electrodes 181 areceptor the gate signal G I2. The trench active gates 11 in the upper surface of the IGBT region 10 may be replaced with a planar gate.Further, the n + type cathode layer 26 is formed in the lower surface of the diode region 20. The barrier metal 5 is formed on the n + type cathode layer 26, the interlayer insulating layer 4, and a region without the interlayer insulating layer 4, and the collector electrode 7 is formed on the barrier metal 5.Although the cross-sectional structure in FIG. 30 is basically identical to that in FIG. 29, the structure excludes the n + type collector layers 19 in the p-type collector layers 16.The above-mentioned RC-IGBT 100B 1 includes the planar gate 181 instead of the trench active gates 18. Such a structure can significantly reduce the turn-off loss in the IGBT regions and the reverse recovery loss in the diode regions.[Operations]Next, the gate control in the RC-IGBT 100B will be described with reference to FIGS. 31 to 39. FIG. 31 illustrates timing diagrams of the gate control in the RC IGBT 100B functioning as the high-side arm in the inverter circuit IV 3 in FIG. 23 in a left diagram, and timing diagrams of the gate control in the RC IGBT 200B functioning as the lower arm in the same circuit in a right diagram. Figs. 32 to 39 schematically illustrate a quantity of injected holes using the size of an arrow.In the left diagram of FIG. 31, an upper level illustrates a timing diagram of a gate signal provided to an RC IGBT functioning as a high-side arm in a conventional inverter circuit, and the second level illustrates, from above, a timing diagram of the gate signal G I1, provided to the trench active gates 11 in the IGBT regions. The third level from the top illustrates a timing diagram of the gate signal G I2, which is provided to the trench active gates 18 in the IGBT regions, the fourth level from the top illustrates a timing diagram of the gate signal G D, which is provided to the diode trench gates 21 in the diode regions, and the lower level illustrates a timing diagram of the output of the inverter circuit IV 3.In the right diagram of FIG. 31, the upper level illustrates a timing diagram of a gate signal provided to an RC-IGBT functioning as a low-side arm in the conventional inverter circuit, and the second level illustrates, from above, a timing diagram of the gate signal G I1, provided to the trench active gates 11 in the IGBT regions. The third level from the top illustrates a timing diagram of the gate signal G I2, which is provided to the trench active gates 18 in the IGBT regions, the fourth level from the top illustrates a timing diagram of the gate signal G D, which is provided to the diode trench gates 21 in the diode regions, and the lower level illustrates a timing diagram of the output of the inverter circuit IV 3.As illustrated in FIG. 31, the RC IGBT 100B and the RC IGBT 200B are PWM controlled. Each of the trench active gates 11 and 18 in the IGBT regions receives pulse signals inverted between the high-side arm and the low-side arm in accordance with PWM signals. The diode trench gates 21 in the diode regions receive a pulse signal generated with respect to the gate signal G I1 provided to the active trench gates 11.Since the RC-IGBT 100B and the RC-IGBT 200B have the same structure, the RC-IGBT 100B will be described below as an example. Each of FIGS. 32 to 39 illustrates a timing chart of the RC-IGBT 100B in a left diagram, and a cross-sectional view of the RC-IGBT 100B corresponding to that in FIG. 26 in a right diagram.FIG. 32 illustrates a charge carrier state in the RC-IGBT 100B in the right diagram at a time t 1 in the time chart in the left diagram. At time t 1, the IGBT region 10 is placed in a forward conduction, and only the trench active gates 11 that are closer to the emitter electrode 6 in the IGBT region 10 are ON. When the collector electrode 7 injects holes, the IGBT region 10 is placed in the forward conduction by channel layers CH formed on the side surfaces of the trench active gates 11.FIG. 33 illustrates a charge carrier state in the RC-IGBT 100B in the right diagram at a time t 2 ain the time chart in the left diagram. At time t 2 a, turn-off of the IGBT region 10 is prepared, and the diode trench gates 21 in the diode region 20 and also the active trench gates 18 are ON. Consequently, the injection of holes from the lower surface decreases.FIG. 34 illustrates a charge carrier state in the RC-IGBT 100B in the right diagram, at time t 2 bin the timing diagram in the left diagram. At time t 2 b, the IGBT region 10 is turned off, and the trench active gates 11 and the diode trench gates 21 are also OFF. However, since the collector electrode 7 continues to inject holes until the diode region 20, which is an opposite arm of the IGBT region 10, conducts, the IGBT region 10 is continuously brought into the forward conduction. Since the trench active gates 18 are ON, the injection of holes decreases. This consequently reduces turn-off loss.FIG. 35 illustrates a charge carrier state in the RC-IGBT 100B in the right diagram at a time t 3 in the time chart in the left diagram. At time t 3, the IGBT region 10 does not conduct. Since gates other than the trench active gates 18 are OFF, the injection of holes ends and the IGBT region 10 does not conduct. The turn-off loss in the aforementioned IGBT mode decreases more significantly than that of the conventional RC-IGBTs. This mechanism for significantly reducing turn-off loss applies to the structure of the inverter circuit IV 2 according to Embodiment 2.FIG. 36 illustrates a charge carrier state in the RC-IGBT 100B in the right diagram, at a time t 4 in the time diagram in the left diagram. At time t 4, the diode region 20 is placed in a reverse conduction. The trench active gates 11 in the IGBT region 10 are ON but away from the diode region 20.FIG. 37 illustrates a charge carrier state in the RC-IGBT 100B in the right diagram, at a time t 5 ain the time diagram in the left diagram. At time t 5 a, the reverse recovery of the diode region 20 is prepared. Since the diode trench gates 21 are ON, the amount of injected holes in the diode region 20 decreases.FIG. 38 illustrates a charge carrier state in the RC-IGBT 100B in the right diagram, at time t 5 bin the timing diagram in the left diagram. The time point t 5 bis a reverse recovery time point of the diode region 20. the IGBT region 10, which is an opposite arm of the diode region 20, turns ON causes reverse recovery of the diode region 20. Therefore, the backward recovery loss decreases.FIG. 39 illustrates a charge carrier state in the RC-IGBT 100B in the right diagram, at a time t 6 in the time diagram in the left diagram. At time t 6, the diode region 20 does not conduct. Since a voltage is applied in a current blocking direction for a diode, the diode region 20 does not conduct.In the aforementioned diode mode, the reverse recovery loss decreases more significantly than those of the conventional RC-IGBTs.As such, the RC-IGBT 100B is controlled in both the IGBT mode and the diode mode in the inverter circuit IV 3 according to Embodiment 3. Therefore, the turn-off loss and the reverse recovery loss decrease remarkably.[Concrete Example of Timing Charts]Hereinafter, FIG. 40 illustrates a concrete example of timing diagrams for controlling the RC-IGBTs in Embodiments 1 to 3. Since the RC-IGBT 100 in Embodiment 1 does not include the trench active gates 18, a timing diagram except for the gate signals G I2_H and G I2_L is applied to the RC-IGBT 100. A timing chart except for the gate signals G D_H and G D_L is applied to the RC-IGBT 100A in Embodiment 2.FIG. 40 illustrates the timing diagrams of the gate signals G I1_H, G I2_H, G D_H, G I1_L, G I2_L, and G D_L sequentially from above. In FIG. 40, other gate signals are generated with respect to the gate signal G I1_H. For example, the trench active gates 18 are turned OFF in a period Δtb during an off period (Wn_off) of the trench active gates 11 which are main gates. The gate signal G I2_H is generated in a period Δta so that the trench active gates 18 are turned ON before the trench active gates 11 are OFF.Here, the definition of the periods in Fig. 40 will be described. The period Δta is a period from a time when the trench active gates 18 are ON with respect to a potential of the collector electrode 7 which is the second main electrode in the IGBT regions to a time when the trench active gates 11 are OFF with respect to a potential of the emitter electrode 6 which is the first main electrode in the IGBT regions.The period Δtb is a period from a time when the trench active gates 18 are OFF with respect to the potential of the collector electrode 7 in the IGBT regions to a time when the trench active gates 11 are ON with respect to the potential of the emitter electrode 6 in the IGBT regions.The period Δtc is a period from a time when the diode trench gates 21 are ON with respect to the potential of the emitter electrode 6 functioning as an anode electrode in the diode regions to a time when the diode trench gates 11 are OFF with respect to the potential of the emitter electrode 6 in the IGBT regions in the opposite arm, and the diode trench gates 21 are OFF with respect to the potential of the emitter electrode 6 in the diode regions. When the dead time in the period Δtc is short, synchronizing the diode trench gates 21 with the time when an IGBT in the same arm is OFF is expected to produce an advantage in terms of sufficient loss reduction.If the periods Δta and Δtc are too long, the conduction loss increases. Thus, the time periods Δta and Δtc preferably correspond to 20 microseconds (μs) or less, or 20 μs maximum, such that the conduction losses in the IGBT regions and the diode regions are kept within acceptable limits.Based thereon, the size ratio between the periods Δta, Δtb, Δtc, and Wn_off is represented by 20 μs≥Δta≥0, Wn_off≥Δtb≥0, and 20 μs≥Δtc≥0.During a period in which the trench active gates 11 which are the main gates are OFF, a leakage current is less. However, when a period in which the trench active gates 18, that is, sub-gates, are ON overlaps with a period in which the trench active gates 11 are ON, the turn-on loss increases. Therefore, the turn-on loss is adjusted by the period Δtb.[Summary of Gate Control]FIG. 41 illustrates, as a list, the gate control with respect to the RC IGBT 100B according to Embodiment 3. FIG. 41 illustrates modes at the respective timings in FIGS. 32 to 38 and voltages of the gate signals in the modes. In FIG. 41, "V" denotes an arbitrary voltage, "Vc" denotes a collector voltage, and "Ve" denotes an emitter voltage.The present invention enables low loss operations of an RC-IGBT using a plurality of gates under the same control regardless of directions of currents as illustrated in FIG. 41.As described above in detail, the advantages described in the description can be produced regardless of whether the IGBT regions 10 or the diode regions 20 are arranged to have an island geometry or a stripe geometry, whether the gates are trenches or planar gates, or whether dummy gates are present or not.[Other Applications]The semiconductor device leads, in connection with the methods for control according to the present invention, to a reduction of losses in an RC-IGBT, regardless of the dimensions of an insulated region between the IGBT region 10 and the diode region 20, or even in the absence of the insulated region. The trench active gates 18 reach the n - type drift layer 1 through the n type buffer layer 3 in Embodiments 1 to 4. The trench active gates 18 whose ends are located in the n-type buffer layer 3 also produce the advantage of reducing losses in the RC-IGBT.Embodiments 1 to 4 describe, as a semiconductor device according to the present disclosure, an example RC IGBT in which IGBT regions and diode regions are formed on the same semiconductor substrate. The RC-IGBT exhibits high heat dissipation and an increase in productivity of modules, as well as a reduction in losses as described above.The present invention is applicable to a structure in which the IGBT regions 10 and the diode regions 20 are respectively formed on separate semiconductor substrates as an IGBT chip and a diode chip, and the diode chip is connected in antiparallel to the IGBT chip. This structure produces the same advantages as those of the RC-IGBTs. Moreover, the application of the individual chips simplifies the control without interaction between the IGBT chip and the diode chip with respect to reducing losses. The IGBT chip may be replaced by a MOSFET chip.

Claims

A method for controlling a semiconductor device, wherein - the semiconductor device comprises: a first switching device (100) and a second switching device (200) connected in series between a first potential (VCC) and a second potential (GND) lower than the first potential (VCC), - the first and second switching devices (100, 200) each comprise a transistor region (T1) and a diode region (D1) electrically connected in antiparallel to the transistor region (T1), - the respective transistor region (T1) comprises a first gate (11) controlled by a first gate signal (G I1) - the respective diode region (D1) comprises a diode gate (21), which is controlled by a diode gate signal (G D) and the method comprises: applying a positive voltage to the diode gate (21) in the diode region (D1) in the second switching device (200) as the diode gate signal (G D), to turn ON the diode gate (21) at a second timing earlier than a first timing at which a positive voltage is applied to the first gate (11) in the first switching device (100) as the first gate signal (G I1) to turn ON the transistor region (T1), setting the diode gate signal (G D) to a negative voltage or a zero voltage at the first time or at a time before the first time to turn OFF the diode gate (21) in the diode region (D1) in the second switching device (200).A method for controlling a semiconductor device, wherein: - the semiconductor device comprises: a first switching device (100A) and a second switching device (200A) connected in series between a first potential (VCC) and a second potential (GND) lower than the first potential (VCC), - each of the first and second switching devices (100A, 200A) comprises a transistor region (T10) and a diode region (D10) electrically connected in antiparallel to the transistor region (T10), - the respective transistor region (T10) comprises a first gate (11) controlled by a first gate signal (G I1) and a second gate (18), which is controlled by a second gate signal (G I2) - the transistor regions (T10) are arranged between a respective first main electrode (6) and a respective second main electrode (7) which are electrically separated from one another, - the respective first gate signal (G I1) is a signal with respect to the first potential (VCC) of the respective first main electrode (6), - the respective second gate signal (G I2) is a signal with respect to the second potential (GND) of the respective second main electrode (7), and - wherein the method comprises: - applying a positive voltage to the second gate (18) as the second gate signal (G I2), turning ON the second gate (18) at a second time point which is earlier than a first time point at which a negative voltage or a zero voltage is applied to the first gate (11) as the first gate signal (G I1) to turn OFF the transistor region (T10); setting the second gate signal (G I2) to the negative voltage or the zero voltage to turn OFF the second gate (18) between the first time and a third time at which a positive voltage is applied to the first gate (11) in the first switching device (100A) as the first gate signal (G I1) to turn ON the transistor region (T10).A method for controlling a semiconductor device, wherein: - the semiconductor device comprises: a first switching device (100B) and a second switching device (200B) connected in series between a first potential (VCC) and a second potential (GND) lower than the first potential (VCC), - each of the first and second switching devices (100B, 200B) comprises a transistor region (T10) and a diode region (D1) electrically connected in antiparallel to the transistor region (T10), - the respective transistor region (T10) comprises a first gate (11) controlled by a first gate signal (G I1) and a second gate (18), which is controlled by a second gate signal (G I2) - the respective diode region (D1) has a diode gate (21) which is controlled by a diode gate signal (GD), - the transistor regions (T10) are each arranged between a respective first main electrode (6) and a respective second main electrode (7) which are electrically separated from one another, - the respective first gate signal (G I1) is a signal with respect to the first potential (VCC) of the respective first main electrode (6), - the respective second gate signal (G I2) is a signal with respect to the second potential (GND) of the respective second main electrode (7), and the method comprises: applying a positive voltage to the second gate (18) in the first switching device as the second gate signal (G I2), to turn ON the second gate (18), at a second timing earlier than a first timing at which a negative voltage or a zero voltage is applied to the first gate (11) as the first gate signal (G I1) to turn OFF the transistor region (T10); setting the second gate signal (G I2) to the negative voltage or the zero voltage to turn OFF the second gate (18) between the first time and a third time when a positive voltage is applied to the first gate (11) in the first switching device (100B) as the first gate signal (G I1) to turn ON the transistor region (T10); applying a positive voltage to the diode gate (21) in the diode region (D1) in the second switching device (200B) as the diode gate signal (G D), to turn ON the diode gate (21) at a fourth time point that is earlier than the third time point at which the transistor region (T10) is turned ON; and setting the diode gate signal (G D) to the negative voltage or the zero voltage at the third time point or at a time point before the third time point to turn OFF the diode gate (21) in the diode region (D1) in the second switching device (200B).The method according to any one of claims 1 to 3, wherein a respective transistor region (T1, T10) and a respective diode region (D1, D10) are formed in the same semiconductor substrate.The method of any of claims 1 to 3, wherein a respective transistor region (T1, T10) and a respective diode region (D1, D10) are formed in separate semiconductor substrates.The method of any one of claims 1 to 3, wherein the second time is at most 20 microseconds before the first time.The method of claim 3, wherein the fourth time is at most 20 microseconds before the third time.

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