Semiconductor package arrangements

Abstract

Semiconductor package assembly (500B) with: a first semiconductor die (132B) and a second semiconductor die (102B) stacked on top of each other, the first semiconductor die (132B) has the following features: a first interface (132DTD) that overlaps and is electrically connected to a second interface (102DTD) located on the second semiconductor die (102B); and a third interface (132DDR) located on a first edge (132E1) of the first semiconductor die (132B); and a memory package (400) next to the first semiconductor die (132B), wherein the memory package (400) is electrically connected to the first semiconductor die via the third interface (132DDR); wherein the second semiconductor die (102B) and the memory package (400) are arranged side by side along a first direction (100), and wherein the second semiconductor die (102B) and the memory package are stacked on the first semiconductor die (132B) along a second direction (120) which is different from the first direction (100); the first semiconductor die (132B) has the following features: third via interconnects (132TV3) arranged in the third interface (132DDR) and electrically connected to the memory package (400); and fourth via interconnects (132TV1) arranged in the first interface (132DTD) and electrically connected to the second interface (102DTD) of the second semiconductor die (102B); and wherein the third through-hole interconnects (132TV3) are arranged in a first column (C2) and a second column (C1) adjacent to the first column and have the following: Ground through-hole interconnects (132TVG) that are arranged only in the first column (C2); and Signal via interconnects (132TVS) arranged in the first column (C2) and the second column (C1), wherein the signal via interconnects in the first column are nested with the ground via interconnects (132TVG), and the signal via interconnects in the second column are adjacent to the ground via interconnects.

Description

BACKGROUND OF THE INVENTION Area of ​​the invention

[0001] The present invention relates to a semiconductor package arrangement and in particular an interface layout plan for a package-on-package semiconductor package (PoP semiconductor package). Description of the state of the art

[0002] With the increasing demand for smaller devices with more functionality, package-on-package (PoP) technology has become increasingly widespread. PoP technology stacks two or more packages vertically, minimizing the trace lengths between different components, such as a controller and a memory device. This improves electrical performance because shorter trace lengths result in faster signal propagation and reduced noise and crosstalk.

[0003] Although existing semiconductor package designs generally meet the requirements placed upon them, they are not entirely satisfactory. For example, fulfilling the channel requirements for integrating various components into a single package can be challenging. Therefore, further improvements to semiconductor package designs are needed to provide flexibility in channel design.

[0004] EP 3 605 603 A1 describes a semiconductor package with an interposer, wherein the semiconductor package comprises: a package-base substrate; a lower redistribution line structure (RDL structure) arranged on the package-base substrate and comprising a plurality of lower redistribution lines; at least one interposer comprising a plurality of first interconnection columns spaced apart on the lower RDL structure and each connected to sections of the plurality of lower redistribution lines, as well as a plurality of interconnection wires; an upper RDL structure comprising a plurality of upper redistribution lines, each connected to the plurality of first interconnection columns and the plurality of interconnection wires on the plurality of first interconnection columns and the at least one interposer;and at least two semiconductor chips attached to the upper RDL structure while spaced apart from each other.

[0005] US Patent 2020 / 0098692A1 describes a microelectronic assembly comprising a bridge structure, a first chip, and a second chip. The first chip is connected to a surface of the bridge structure by first connections, with the first chip at least partially overlapping the bridge structure.

[0006] The second chip is connected to the surface of the bridge structure via secondary connections, with the second chip at least partially overlapping the bridge structure. The bridge structure can be an active interposer and may include active or passive circuits (e.g., transistors, diodes, resistors, inductors, and capacitors, among others). BRIEF DESCRIPTION OF THE INVENTION

[0007] The invention is defined by the main claim and the dependent claims. The subclaims describe further embodiments of the invention. One embodiment provides a semiconductor package arrangement. The semiconductor package arrangement comprises a first semiconductor die, a second semiconductor die, and a memory package. The first semiconductor die and the second semiconductor die are stacked on top of each other. The first semiconductor die has a first interface and a third interface. The first interface overlaps a second interface located on the second semiconductor die and is electrically connected to it. The third interface is located on a first edge of the first semiconductor die. The memory package is arranged adjacent to the first semiconductor die, and the memory package is electrically connected to the first semiconductor die via the third interface.

[0008] One embodiment provides a semiconductor package arrangement. The semiconductor package arrangement includes a fan-out package. The fan-out package includes a memory package, a first semiconductor die, and a second semiconductor die. The first semiconductor die is arranged adjacent to the memory package along a first direction. The second semiconductor die is arranged adjacent to the memory package along a second direction. The first semiconductor die has a first interface and a third interface. The first interface overlaps a second interface located on the second semiconductor die and is electrically connected to it. The third interface is located near the memory package and is electrically connected to it.

[0009] Furthermore, one embodiment provides a semiconductor package assembly. The semiconductor package assembly includes a fan-out package. The fan-out package comprises a first redistribution layer (RDL) structure, a second redistribution layer (RDL) structure, an upper semiconductor die, a memory package, and a lower semiconductor die. The first and second RDL structures are stacked on top of each other. The upper semiconductor die and the memory package are arranged on the first RDL structure. The upper semiconductor die has a first interface. The lower semiconductor die is positioned between the first and second RDL structures. The lower semiconductor die has a second interface and first through-hole interconnects (TV interconnects). The second interface overlaps the first interface.The first through-hole interconnects (TV interconnects) are located in the second interface and are electrically connected to the first interface via the first RDL structure. The memory package is electrically connected to the upper and lower semiconductor dies via the first RDL structure instead of the second RDL structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention is best understood by reading the following detailed description and examples with reference to the accompanying drawings, wherein: Fig. 1A is a sectional view of a semiconductor package arrangement according to some embodiments of the disclosure; the Fig. 1B and Fig. 1C Perspective bottom views of a fan-out package of the semiconductor package array of Fig. 1A according to some embodiments of the disclosure, which show the arrangement of interfaces of upper and lower semiconductor dies and through-hole interconnects (TV interconnects) of the lower semiconductor die; Fig. 2A is a sectional view of a semiconductor package arrangement according to some embodiments of the disclosure; the Fig. 2B, Fig. 2C and Fig. 2D perspective bottom views of a fan-out package of the semiconductor package array from Fig. 2A according to some embodiments of the disclosure, which show the arrangement of interfaces of upper and lower semiconductor dies and through-hole interconnects (TV interconnects) of the lower semiconductor die; Fig. 2E an enlarged plan view of the lower semiconductor die of the fan-out package of the semiconductor package assembly of Fig. 2A according to some embodiments of the disclosure, which shows the arrangement of through-hole interconnects (TV interconnects) of the lower semiconductor die; Fig. 3A is a sectional view of a semiconductor package arrangement according to some embodiments of the disclosure; Fig. 3B a perspective bottom view of a fan-out package of the semiconductor package array of Fig. 3A according to some embodiments of the disclosure, which shows the arrangement of interfaces of upper and lower semiconductor dies, through-hole interconnects (TV interconnects) of the lower semiconductor die and conductive structures of the semiconductor package arrangement; Fig. 4 is a sectional view of a semiconductor package arrangement according to some embodiments of the disclosure; Fig. 5 is a sectional view of a semiconductor package arrangement according to some embodiments of the disclosure; and Fig. Figure 6 shows an enlarged sectional view of a semiconductor package arrangement according to some embodiments of the disclosure, showing a trench capacitor inserted into a lower semiconductor die of a fan-out package of the semiconductor package arrangement. Fig. 4 and Fig. 5 is embedded. DETAILED DESCRIPTION OF THE INVENTION

[0011] The following description serves to illustrate the general principles of the invention. The scope of protection of the invention is determined by the attached claims.

[0012] Fig. Figure 1A is a sectional view of a semiconductor package assembly 500A according to some embodiments of the disclosure. Fig. 1B and Fig. 1C are perspective bottom views (floor plans) of a fan-out package 300A of the semiconductor package assembly 500A. Fig. 1A according to some embodiments of the disclosure, which show the arrangement of interfaces of semiconductor dies 102A and 132A and through-hole interconnects (TV interconnects) 132TV1 and 132TV2 of semiconductor die 132A. In some embodiments, the semiconductor package arrangement 500A is a three-dimensional (3D) chiplet package arrangement. The semiconductor package arrangement 500A can comprise a wafer-plane semiconductor package, such as the fan-out package 300A with at least two vertically stacked semiconductor dies 102A and 132A and a memory package 400 mounted on a base 200.

[0013] As in Fig. As shown in Figure 1A, the base 200, for example a printed circuit board (PCB), can be made of polypropylene (PP), pre-impregnated composite fiber material (prepreg material), FR-4, and / or another epoxy laminate material. It should also be noted that the base 200 can be a single-layer or a multi-layer structure. A plurality of pads 202 and / or conductive traces (not shown) are arranged on the base 200. In one embodiment, the conductive traces can have signal trace segments or ground trace segments used for the input / output (I / O) connections of the fan-out package 300A. Furthermore, the fan-out package 300A is mounted directly onto the conductive traces. In some other embodiments, the pads 202 are arranged on the base 200 and connected to various terminals of the conductive traces.The Pads 202 are used for the Fan-out-Package 300A, which is mounted directly onto them.

[0014] As in Fig. As shown in Figure 1A, the fan-out package 300A is mounted onto the base 200 by a bonding process. The fan-out package 300A is mounted onto the base 200 using conductive structures 322. The fan-out package 300A is a three-dimensional (3D) semiconductor package comprising the semiconductor dies 102A and 132A, the redistribution layer structures (RDL structures) 316 and 366, the molding compounds 312 and 362, the via interconnects (TV interconnects) 314, and the conductive structures 322. The conductive structures 322 are in contact with the RDL structure 316 and electrically connected to it. Furthermore, the conductive structures 322 are electrically connected to the base 200.In some embodiments, the conductive structures 322 have a conductive spherical structure, such as a copper sphere, a conductive contact hill structure, such as a copper contact hill or a solder contact hill structure, or a conductive column structure, such as a copper column structure.

[0015] In some embodiments of the Fan-out Package 300A, a chiplet architecture is used to divide a large, single semiconductor die into several smaller, functional semiconductor dies (called chiplets) that are fabricated at different technology nodes. Each chiplet can exhibit improved device performance and fabrication yield. Furthermore, the Fan-out Package 300A can benefit from lower fabrication costs. As described in Fig. As shown in Figure 1A, the fan-out package 300A has at least two semiconductor dies, such as semiconductor dies 102A and 132A (also called chiplets 102A and 132A), stacked along direction 120 (e.g., a vertical direction). Semiconductor die 102A is located on the RDL structure 366 and side by side with the memory package 400 along a direction 100 (e.g., a lateral direction) that differs from direction 120. Semiconductor die 132A is located between RDL structures 316 and 366 and partially overlaps semiconductor die 102 and memory package 400 along direction 120. Because semiconductor die 102A and semiconductor die 132A are located near a top 300TS and a bottom 300BS of fan-out package 300A, respectively, semiconductor die 102A and semiconductor die 132A are also referred to as an upper semiconductor die 102A and a lower semiconductor die 132A.

[0016] Semiconductor die 102A has an active surface 102as and a back surface 102bs facing the active surface 102as. Semiconductor die 132A has an active surface 132as and a back surface 132bs facing the active surface 132as. In some embodiments, semiconductor die 102A and semiconductor die 132A are fabricated using flip-chip technology. Semiconductor die 102A can be flipped and positioned on RDL structure 366 opposite semiconductor die 132A. Furthermore, semiconductor die 132A can be flipped and positioned on RDL structure 316 opposite the conductive structures 322. In some embodiments, the semiconductor dies 102A and 132A each independently feature a system-on-chip die (SoC die), a logic device, a memory device, a radio frequency device (RF device), the like, or a combination thereof.The semiconductor die 102A and the semiconductor die 132A can, for example, each independently contain an MCU die (MCU: microcontrol unit), an MPU die (MPU: microprocessor unit), a PMIC die (PMIC: power management integrated circuit), a GPS device (GPS: global positioning system), a CPU die (CPU: central processing unit), a GPU die (GPU: graphics processing unit), an EA die (EA: input / output), a DRAM IP core (DRAM: dynamic random access memory), an SRAM (SRAM: static random access memory), an HBM (HBM: high bandwidth memory), the like, or a combination thereof. In some embodiments, the semiconductor dies 102A and 132A have different functions.

[0017] In some embodiments, the semiconductor die 132A further includes through-hole interconnects (TV interconnects) 132TV1 and 132TV2, which are fabricated to extend through the semiconductor die 132A. Therefore, the semiconductor die 132A can also be referred to as a TV die 132A. The TV interconnects 132TV1 and 132TV2 may be free of the back surface 132bs of the semiconductor die 132A. Furthermore, the TV interconnects 132TV1 and 132TV2 have substantially vertical sidewalls and extend from the top of the active surface 132as and the back surface 132bs of the semiconductor die 132A, but the present disclosure is not limited thereto. The TV interconnects 132TV1 and 132TV2 in the semiconductor die 132A may have other configurations and numbers. In some embodiments, the TV interconnects 132TV1 and 132TV2 may be made of conductive material, such as a metal.The TV interconnects 132TV1 and 132TV2, for example, can be made of copper.

[0018] The semiconductor dies 102A and 132A can be manufactured at different technology nodes. In some embodiments, the semiconductor die 102A has a first critical dimension (CD), and the semiconductor die 132A has a second critical dimension that differs from the first critical dimension to provide different functionalities at a reduced cost. For example, the first critical dimension is narrower than the second critical dimension. Therefore, the semiconductor dies 102A and 132A can each have different interfaces to meet the internal and external signal transmission requirements of the Fan-out Package 300A.

[0019] The RDL structure 316 is arranged on the active surface 132as of the semiconductor die 132A. In other words, the semiconductor die 132A is arranged on the RDL structure 316. Furthermore, the RDL structure 316 is arranged between the semiconductor die 132A and the base 200 along direction 120. Pads 134 on the active surface 132as of the semiconductor die 132A are electrically connected to the RDL structure 316 using conductive structures 142. In some embodiments, the conductive structures 142 comprise conductive materials, such as metal. The conductive structures 142 can comprise microbumps, C4 contact bumps (C4: controlled collapse chip connection), BGA balls (BGA: ball grid array), the like, or a combination thereof. As shown in Fig. As shown in Figure 1A, the RDL structure 316 can have one or more conductive lines 320 and one or more vias 318 arranged in one or more dielectric layers 317. In some embodiments, the conductive lines 320 and the vias 318 comprise a conductive material, such as metals including copper, gold, silver, or other suitable metals. The dielectric layers 317 can comprise extreme-low-k dielectrics (ELK dielectrics) and / or an ultra-low-k dielectric (ULK dielectric). Furthermore, the dielectric layers 317 can comprise epoxy. The semiconductor die 132A is electrically connected to the base 200 using the vias 318 and the conductive lines 320 of the RDL structure 316 and the corresponding conductive structures 322.It should be noted that the number of vias is 318, the number of conductive traces is 320, and the number of dielectric layers is 317, which are in . Fig. Figure 1A is shown only as an example and does not represent a limitation of the present invention.

[0020] The through-hole interconnects (TV interconnects) 314 are located on the RDL structure 316 and next to the semiconductor die 132A. As shown in Fig. As shown in Figure 1A, the TV interconnects 314 are electrically connected to the vias 318 and the conductive lines 320 of the RDL structure 316. In some embodiments, the TV interconnects 314 are electrically connected to the semiconductor die 132A using the vias 318 and the conductive lines 320 in the RDL structure 316.

[0021] As in Fig. As shown in Figure 1A, the molding compound 312 is arranged on and in contact with the RDL structure 316. The molding compound 312 surrounds the semiconductor die 132A and the TV interconnects 314 and is in contact with them. Furthermore, the TV interconnects 314 pass through the molding compound 312. The rear surface 132bs of the second semiconductor die 132A may be free of the molding compound 312. In some embodiments, the molding compound 312 may be made of a non-conductive material, such as an epoxy, a resin, a malleable polymer, or the like. The molding compound 312 may be applied while essentially liquid and then cured by a chemical reaction, for example, to form an epoxy or resin.In some other embodiments, the molding compound 312 can be a UV-cured (UV: ultraviolet) or thermally cured polymer that is applied as a gel or a moldable solid, which can be arranged around the semiconductor die 132A and then cured using a thermal or UV curing process. The molding compound 312 can be cured using a mold.

[0022] The RDL structure 366 is arranged on the active surface 102as of the semiconductor die 102A. Furthermore, the RDL structure 366 is located between the active surface 102as of the semiconductor die 102A and the back surface 132bs of the second semiconductor die 132A along direction 120 and is electrically connected to the TV interconnects 314. As shown in Fig. As shown in Figure 1A, the semiconductor die 132A is separated from the memory package 400 by the RDL structure 366. The molding compound 312 fills a space (not shown) between the RDL structures 316 and 366 and borders the side walls of the semiconductor die 132A and adjacent surfaces of the RDL structures 316 and 366. The RDL structures 316 and 366 are in contact with opposite ends of the TV interconnects 314. In other words, the semiconductor die 132A and the TV interconnects 314 are positioned between the RDL structures 316 and 366. Pads 104 on the active surface 102as of the semiconductor die 102A are electrically connected to the RDL structure 366 using conductive structures 112. In some embodiments, the conductive structures 112 and 142 may have the same or similar materials and structures.In some embodiments, the RDL structure 366 is electrically connected to the semiconductor die 132A via the TV interconnects 132TV1 and 132TV2, the TV interconnects 314, and the RDL structure 316. Since the RDL structure 366 and the RDL structure 316 are located near a top 300TS and a bottom 300BS of the fan-out package 300A, respectively, they can also be referred to as an upper RDL structure 366 and a lower RDL structure 316.

[0023] In some embodiments, the RDL structure 366 has one or more conductive lines 370 and one or more vias 368 arranged in one or more dielectric layers 367. In some embodiments, the material of the conductive lines 370 may be similar to the material of the conductive lines 320. The material of the vias 368 may be similar to the material of the vias 318. Furthermore, the material of the dielectric layers 367 may be similar to the material of the dielectric layers 317. It should be noted that the number of vias 368, the number of conductive lines 370, and the number of dielectric layers 367 in Fig. Figure 1A is shown only as an example and does not represent a limitation of the present disclosure.

[0024] As in Fig. As shown in Figure 1A, the memory package 400 is arranged on the RDL structure 366 by a bonding process. In some embodiments, the memory package 400 comprises a DRAM package (DRAM: dynamic random access memory) or another suitable memory package. In some embodiments, the memory package 400 comprises a substrate 418, at least one semiconductor die, for example, two semiconductor dies 402 and 404 stacked on the substrate 418, and conductive structures 422. In some embodiments, each of the semiconductor dies 402 and 404 comprises a DRAM die (DRAM: dynamic random access memory) (e.g.,a DDR4 DRAM die (DDR: double data rate), an LPDDR4 DRAM die (LP: low-power), an SDRAM die (SDRAM: synchronous dynamic random access memory), or the like, or another suitable memory die. In some other embodiments, the semiconductor dies 402 and 404 may have the same or different devices. In some embodiments, the memory package 400 may also include one or more passive components (not shown), such as resistors, capacitors, inductors, the like, or a combination thereof.

[0025] In this embodiment, as in Fig. Figure 1A shows two semiconductor dies 402 and 404 mounted on substrate 418 with a paste (not shown). Each semiconductor die 402 and 404 has corresponding pads 408 and 410 on it. The pads 408 and 410 of the semiconductor dies 402 and 404 can be electrically connected to the substrate 418 using bond wires 414 and 416, respectively. However, the number of stacked memory dies is not limited to the disclosed embodiment. Alternatively, the semiconductor dies 402 and 404 can be arranged as shown in Fig. As shown in Figure 1A, the semiconductor dies 402 and 404 can be arranged side by side and mounted on the substrate 418 with a paste (not shown). Alternatively, the semiconductor dies 402 and 404 can be manufactured using flip-chip technology and electrically connected to the substrate 418 without the use of bond wires 414 and 416.

[0026] As in Fig. As shown in Figure 1A, the substrate 418 can have circuits 428 and contact pads 420 and 430 arranged in one or more dielectric extremely low k layers (ELK layers) (ELK: extra-low k) and / or dielectric ultra-low k layers (ULK layers) (not shown). The contact pads 420 are located on the top surfaces of the circuits 428 near the top surface (die terminal area) of the substrate 418. Furthermore, the bond wires 414 and 416 are electrically connected to the corresponding contact pads 420. The contact pads 430 are located on the bottom surfaces of the circuits 428 near the bottom surface (contact hump terminal area) of the substrate 418. The contact pads 430 are electrically connected to the corresponding contact pads 420. In some embodiments, the bond wires 414 and 416, the contact pads 420 and 430, and the circuits 428 comprise a conductive material, such as metals including copper, gold, silver, or other suitable metals.

[0027] As in figure Fig. As shown in Figure 1A, the conductive structures 422 are arranged on the underside of the substrate 418 opposite the semiconductor dies 402 and 404. The conductive structures 422 are electrically connected to (or in contact with) the corresponding contact pads 430 of the substrate 418 and the RDL structure 366. In some embodiments, the conductive structures 422 comprise a conductive spherical structure, such as a copper sphere, a conductive contact mound structure, such as a copper contact mound or a solder contact mound structure, or a conductive column structure, such as a copper column structure.

[0028] In some embodiments, such as in Fig. As shown in Figure 1A, the molding material 412 covers the substrate 418 and encapsulates the semiconductor dies 402 and 404 as well as the bond wires 414 and 416. The top surface of the molding material 412 can serve as a top surface 400T of the memory package 400. In some embodiments, the molding materials 312 and 412 can comprise the same or similar materials and manufacturing processes.

[0029] As in Fig. As shown in Figure 1A, the molding compound 362 covers the RDL structure 366, the semiconductor die 102A, and the memory package 400. The molding compound 362 encloses the semiconductor die 102A and the memory package 400. The molding compound 362 borders the back surfaces 102bs and side walls (not shown) of the semiconductor die 102A and the top surface 400TS and side walls (not shown) of the memory package 400. Furthermore, one top surface of the molding compound 362 forms a top surface 300TS of the fan-out package 300A of the semiconductor package assembly 500A. Additionally, the top surface 400TS of the memory package 400 is close to the top surface 300TS of the semiconductor package assembly 500A. In some embodiments, the mold materials 312, 362 and 412 may include the same or similar materials and manufacturing processes.In some embodiments, the edges 312E of the molding compound 312 are aligned with corresponding edges 316E of the RDL structure 316 and corresponding edges 366E of the RDL structure 366. Edges 362E of the molding compound 362 are aligned with corresponding edges 366E of the RDL structure 366. Therefore, the edges 312 of the molding compound 312, the edges 362E of the molding compound 362, the edges 316E of the RDL structure 316, and the edges 366E of the RDL structure 366 can collectively serve as package edges of the fan-out package 300A.

[0030] As in Fig. As shown in Figure 1A, the fan-out package 300A can further include underfills (not shown) that fill a gap (not shown) between the RDL structure 316 and the semiconductor die 132A, a gap (not shown) between the RDL structure 336 and the semiconductor die 102A, and a gap (not shown) between the RDL structure 336 and the memory package 400. In some embodiments, the underfills enclose portions of the conductive structures 112, 142, and 422 and are in contact with portions of the RDL structures 316 and 336 to further reduce the thermal resistance from the semiconductor die 132A to the RDL structure 316 and from the semiconductor die 102A and the memory package 400 to the RDL structure 366.Furthermore, the underfills can be arranged to compensate for different coefficients of thermal expansion (CTEs) between the semiconductor dies 102A and 132A, the RDL structures 316 and 366, and the conductive structures 112, 142, and 422. In some embodiments, the underfill comprises a capillary underfill (CUF), a molded underfill (MUF), or a combination thereof.

[0031] Since the semiconductor die 102A and the memory package 400 are side by side on the upper RDL structure 366 of the fan-out package 300A, a thickness 362T of the molding compound 362 (measured from the top 300TS of the fan-out package 300A to an interface between the molding compound 362 and the upper RDL structure 366) can depend mainly on a thickness 400T of the memory package 400. Therefore, the thickness of the semiconductor die 102A can be increased to 102T to be equal to or similar to the thickness of the memory package 400T to improve thermal performance (for example, the increased thickness of the semiconductor die 102A, which is mainly formed by silicon, can improve heat dissipation and resolve the problem of differing coefficients of thermal expansion (CTE) between the semiconductor die 102A and different materials in the semiconductor package assembly 500A).

[0032] As in Fig. As shown in Figure 1A, the fan-out package 300A further includes an electronic component 330 mounted on the RDL structure 316 opposite the semiconductor die 132A. In some embodiments, the electronic component 330 has pads 332 on it and is electrically connected to the conductive traces 320 of the RDL structure 316. In some embodiments, the electronic component 330 is arranged between the conductive structures 322. The electronic component 330 may be free of any covering by a molding compound. In some embodiments, the electronic component 330 includes an integrated passive device (IPD), such as a capacitor, an inductor, a resistor, or a combination thereof. In some embodiments, the electronic component 330 includes DRAM dies.

[0033] As in the Fig. As shown in Figures 1A-1C, the semiconductor die 102A and the semiconductor die 132A of the fan-out package 300A of the semiconductor package assembly 500A can have interfaces located on the edges of the semiconductor dies 102A and 132A. In some embodiments, the interfaces of the fan-out package 300A used in the present disclosure can have circuits and input / output connections (e.g., the pads 104 and 134) located on the active surface 102as of the semiconductor die 102A and the active surface 132as of the semiconductor die 132A. In some embodiments, the interfaces of semiconductor dies 102A and 132A are used for the signal (data), power, and ground lines between the different semiconductor dies 102A and 132A, between semiconductor die 102A and memory package 400, or between semiconductor die 132A and memory package 400. It should be noted that the Fig. 1B and Fig. Figure 1C shows only the semiconductor dies 102A and 132A, the mold material 312 / 362, and the conductive structures 422 of the memory package 400 for illustrative purposes; the other features can be seen in the schematic sectional views of Fig. 1A. It is understood that although some features are shown in some embodiments but not in others, these features may (or may not) be present in other embodiments whenever possible. For example, although each of the illustrated exemplary embodiments shows specific arrangements of the interfaces of the semiconductor dies 102A and 132A and the conductive structures 422 of the memory package 400, other combinations of the arrangements of the interfaces of the semiconductor dies 102A and 132A and the conductive structures 422 of the memory package 400 may also be used, if necessary.

[0034] As in Fig. As shown in Figure 1B, semiconductor dies 102A and 132A can have a rectangular plan shape. Semiconductor die 102A can have opposite edges 102E1 and 102E3 extending substantially along direction 110, and opposite edges 102E2 and 102E4 extending substantially along direction 100. Semiconductor die 132A can have opposite edges 132E1 and 132E3 extending substantially along direction 110, and opposite edges 132E2 and 132E4 extending substantially along direction 100. Edge 102E1 of semiconductor die 102A is close to edge 132E3 of semiconductor die 132A. Edge 102E2 of semiconductor die 102A, which is connected between (or adjacent to) edges 102E1 and 102E3, is close to edge 132E2 of semiconductor die 132A, which is connected between edges 132E1 and 132E3.Edge 102E4 of semiconductor die 102A, which is connected between (or adjacent to) edges 102E1 and 102E3, is close to edge 132E4 of semiconductor die 132A, which is connected between edges 132E1 and 132E3. Edge 102E3 of semiconductor die 102A, which is connected between edges 102E2 and 102E4, is far from edge 132E1 of semiconductor die 132A, which is connected between edges 132E2 and 132E4.

[0035] In some embodiments, the upper semiconductor die can be used to control the memory package and can have various interfaces for electrical connections with the lower semiconductor dies and the memory package in the fan-out package. The lower semiconductor die, which is fabricated with TV interconnects, can have only one interface for electrical connections with the upper semiconductor die of the fan-out package. For example, semiconductor die (the upper semiconductor die) 102A can have interfaces 102DDR (with interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4) and 102DTD, which extend along direction 110 and are arranged side by side along direction 100. The 102DDR interfaces are located on edge 102E1 near memory package 400.Interface 102DTD is located adjacent to interfaces 102DDR opposite edge 102E1, such that interfaces 102DDR are located between interface 102DTD and memory package 400 along direction 100. Furthermore, semiconductor die 132A, which has TV interconnects 132TV1 and 132TV2, can have a single interface 132DTD located on edge 132E3, overlapping interface 102DTD along direction 120. If the semiconductor die 102A is a SOC die, the memory package 400 is a DDR4 DRAM package (DDR4: double data rate 4), and the interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4 can be DDR4 interfaces used to control the memory package 400 (e.g., to transfer data to / from the memory controller in the semiconductor die 102A).In some embodiments, the interfaces 102DDR-1, 102DDR-2, 102DDR-3, and 102DDR-4 are electrically connected to the memory package 400 via the RDL structure 366 instead of the RDL structure 316. Furthermore, the interface 102DTD of semiconductor die 102A and the interface 132DTD of semiconductor die 132A can be die-to-die interfaces (DTD interfaces), providing any suitable direct conductive electrical connection between two different semiconductor dies 102A and 132A for data transmission. In some embodiments, the TV interconnects 132TV1 are arranged in the interface 132DTD, which is located on the semiconductor die 132A, and are electrically connected to the interface 102DTD, which is located on the semiconductor die 102A, by the RDL structure 366 instead of by the interfaces 102DDR-1, 102DDR-2, 102DDR-3 and 102DDR-4.In some embodiments, the TV interconnects 132TV2 can be arranged in other interfaces (not shown) of the semiconductor die 132A, overlapping the interfaces 102DDR of the semiconductor die 102A. The TV interconnects 132TV2 are electrically connected to the interfaces 102DDR of the semiconductor die 102A by the RDL structure 366 to provide additional power transmission and ground lines from the interfaces 102DDR to the base 200.

[0036] In some embodiments, the conductive structures 422 of the memory package 400 (e.g., the DDR4 DRAM package) are arranged according to the given configuration. For example, the conductive structures 422 of the memory package 400 are arranged in two groups 422G1 and 422G2 (with a single column or multiple columns of conductive structures 422) along the direction 100, as shown in Fig. Figure 1B shows that each group 422G1 and 422G2 of the conductive structures 422 can provide two data channels for the conductive structures 422. To reduce the length of the routing path between the upper package 400 and the lower package 300, the interfaces 102DDR-1, 102DDR-2, 102DDR-3, 102DDR-4 of the semiconductor die 102A can be arranged according to the arrangement of the conductive structures 422 of the memory package 400. Since the semiconductor die 102A, which has the interfaces 102DDR, and the memory package 400 are arranged side-by-side without an RDL structure in between, the interfaces 102DDR-1 and 102DDR-2 of the semiconductor die 102A can be located near the group 422G1 of the conductive structures 422. The interfaces 102DDR-3 and 102DDR-4 of the semiconductor die 102A can be located near the group 422G2 of the conductive structures 422, as shown in Fig. 1B is shown.

[0037] According to the arrangement of interfaces 102DDR and 102DTD of semiconductor die 102A and interface 132DTD and TV interconnects 132TV1 and 132TV2 of semiconductor die 132A, the memory package 400 is electrically connected to semiconductor die 102A for signal transmission via conductive structures 422, interfaces 102DDR, and RDL structure 366, instead of via TV interconnects 314 and RDL structure 316. Furthermore, interfaces 102DTD and 132DTD are electrically connected to base 200 for power transmission and grounding via conductive structures 422, interfaces 102DDR, RDL structures 316 and 366, and TV interconnects 132TV2. The RDL structure 366 is electrically connected to the interfaces 102DDR, 102DTD and 132DTD and the TV interconnects 132TV1 and 132TV2.Therefore, the memory package 400 can be electrically connected to the semiconductor die 132A via the conductive structures 422, the interfaces 102DDR, 102DTD and 132DTD, the RDL structure 366 and the TV interconnects 132TV1 instead of via the TV interconnects 314 and the RDL structure 316.

[0038] In some embodiments, the interfaces 102DDR can be arranged on three adjacent edges of the semiconductor die 102A. As shown in Fig. As shown in Figure 1C, an interface 102DDR-1' of the semiconductor die 102A can be located on edge 102E4, connected to edges 102E1 and 102E3, and opposite edge 102E2. Furthermore, an interface 102DDR-4' of the semiconductor die 102A can be located on edge 102E2, connected to edges 102E1 and 102E3, and opposite edge 102E4. The memory package 400 is electrically connected to the semiconductor die 102A via interfaces 102DDR-1', 102DDR-2, 102DDR-3, and 102DDR-4'. According to the arrangements of the interfaces 102DDR-1' and 102DDR-4', the flexibility of the site plan design (including interface and / or routing design) of the semiconductor die 102A for the channel arrangements of the memory package 400 can be increased.

[0039] In some embodiments, the lower semiconductor die, fabricated with the TV interconnects, can have different interfaces for electrical connections with the upper semiconductor die and the memory package in the fan-out package. The upper semiconductor die may only have the interface for electrical connections with the upper semiconductor die of the fan-out package. Therefore, the upper semiconductor die can control the memory package through the lower semiconductor die. Fig. Figure 2A is a sectional view of a semiconductor package assembly 500B according to some embodiments of the disclosure. Fig. 2B, Fig. 2C and Fig. 2D are perspective bottom views (floor plans) of a fan-out package 300B of the semiconductor package array 500B. Fig. 2A according to some embodiments of the disclosure, which show the arrangement of the interfaces of semiconductor dies 102B and 132B and the through-hole interconnects (TV interconnects) 132TV1 and 132TV3 of semiconductor die 132B. Elements of the embodiments below, which are described above with reference to the Fig. Items described in sections 1A-1C, which are the same or similar, are not repeated for the sake of brevity.

[0040] As in the Fig. 2A and Fig. As shown in Figure 2B, the fan-out package 300B can contain one or more semiconductor dies 102B. For example, the fan-out package 300B can contain semiconductor dies 102B-1 and 102B-2, each having only one type of interface, such as the 102DTD interface. Semiconductor die 102B-1 (or semiconductor die 102B-2) and memory package 400 are arranged side by side along direction 100. Semiconductor dies 102B-1 and 102B-2 and memory package 400 are stacked on semiconductor die 132B, which has various interfaces 132DDR (with the ones shown in Figure 2B). Fig. The semiconductor die 132B has interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4, as well as 132DTD and TV interconnects 132TV1 and 132TV3, along direction 120, which differs from direction 100. In other words, the semiconductor die 132B is arranged alongside the semiconductor dies 132B-1 and 132B-2 and the memory package 400 along direction 120. In some embodiments, the interfaces 132DDR are located on the edge 132E1 of the semiconductor die 132B, and the memory package 400 is arranged overlapping along direction 120. The memory package 400 is electrically connected to the semiconductor die 132B via the interfaces 132DDR and the RDL structure 366. The 132DTD interfaces are located on edge 132E3 opposite edge 132E1 of semiconductor die 132B. Furthermore, the 132DTD interfaces are arranged to overlap the corresponding 102DTD interfaces of semiconductor dies 102B-1 and 102B-2 along direction 120.

[0041] As in the Fig. 2A and Fig. As shown in Figure 2B, the TV interconnects 132TV1 of semiconductor die 132B are arranged in the interfaces 132DTD and electrically connected to the interfaces 102DTD of semiconductor dies 102B-1 and 102B-2. Furthermore, semiconductor die 132B may also have TV interconnects 132TV3, which are arranged in the interfaces 132DDR and electrically connected to the memory package 400. In some embodiments, the TV interconnects 132TV1, 132TV2 ( Fig. 1A) and Fig. 132TV3 exhibit the same or similar materials and structures.

[0042] Since the semiconductor die 132B, which has the interfaces 132DDR, and the memory package 400 are arranged in an overlapping configuration with the RDL structure 366 located between them, the interfaces 132DDR-1 and 132DDR-2 of the semiconductor die 132B can be arranged to overlap the group 422G1 of the conductive structures 422. Furthermore, the interfaces 132DDR-3 and 132DDR-4 of the semiconductor die 132B can be arranged to overlap the group 422G2 of the conductive structures 422, as shown in Fig. 2B is shown.

[0043] According to the arrangement of the interfaces 132DDR and the TV interconnects 132TV3 of the semiconductor die 132B, the memory package 400 is electrically connected to the semiconductor die 132B via a shortened trace path for data transmission. Furthermore, the TV interconnects 132TV3 in the interfaces 132DDR can be electrically connected to the conductive structures 322 for power transmission and ground connection via the conductive structures 142, without passing through other interfaces on the semiconductor die 132B.

[0044] In some embodiments, the interfaces 132DDR can be arranged on three adjacent edges of the semiconductor die 132B. As shown in Fig. As shown in Figure 2C, an interface 132DDR-1' of the semiconductor die 132B can be located on edge 132E4, connected to edges 132E1 and 132E3, and opposite edge 132E2. Furthermore, an interface 132DDR-4' of the semiconductor die 132B can be located on edge 132E2, connected to edges 132E1 and 132E3, and opposite edge 132E4. The memory package 400 is electrically connected to the semiconductor die 132B via interfaces 132DDR-1', 132DDR-2, 132DDR-3, and 132DDR-4. According to the arrangements of the interfaces 132DDR-1' and 132DDR-4', the flexibility of the site plan design (including interface and / or routing design) of the semiconductor die 132B for the channel arrangements of the memory package 400 can be increased.

[0045] In some embodiments, the orientation and shape of the distribution area and the pin order of the TV interconnects 132TV3 in the interfaces 132DDR of the semiconductor die 132B can be the same as or similar to those of the conductive structures 422 of the memory package 400 that overlap the interfaces 132DDR in order to shorten the trace path (between the interfaces 132DDR and the conductive structures 422) for data transmission. In a plan view, as in Fig. As shown in 2D, the TV interconnects 132TV3, arranged in interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4, can have distribution areas 132DDR-1A, 132DDR-2A, 132DDR-3A, and 132DDR-4A. The conductive structures 422, arranged in the two data channels of group 422G1, can have distribution areas 422C1A and 422C2A. Furthermore, the conductive structures 422, arranged in the two data channels of group 422G2, can have distribution areas 422C3A and 422C4A. In some embodiments, the distribution areas 132DDR-1A, 132DDR-2A, 132DDR-3A and 132DDR-4A of the TV interconnects 132TV3 coincide with and at least partially overlap the distribution areas 422C1A, 422C2A, 422C3A and 422C4A of the conductive structures 422.

[0046] In some embodiments, the ground TV interconnects and the signal TV interconnects in the DDR interfaces can be nested. Each ground TV interconnect is positioned between two adjacent signal TV interconnects to reduce crosstalk interference from neighboring signal TV interconnects. Fig. 2E is an enlarged plan view of semiconductor die 132B of fan-out package 500B of semiconductor package assembly 500B. Fig. 2A according to some embodiments of the disclosure, which shows the arrangement of the TV interconnects in the interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-4 of the semiconductor die (the lower semiconductor die) 132B. Elements of the embodiments below, which are further detailed above with reference to the Fig. Items 1A-1C and 2A-2D, which are the same or similar as those described, are not repeated for the sake of brevity. It should be noted that Fig. Figure 2E shows only mass TV interconnects 132TVG and signal TV interconnects 132TVS in interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-4 for illustrative purposes; the power TV interconnects are hidden in the figure. As shown in Fig. As shown in 2E, the TV interconnects (such as those in the Fig. The TV interconnects (TV3) shown in Figures 2A-2B have signal TV interconnects (TVS) and ground TV interconnects (TVG) in interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4, arranged in multiple columns, for example, in two columns C1 and C2. In some embodiments, the ground TV interconnects (TVG) are arranged only in column C1, while the signal TV interconnects (TVS) are arranged in columns C1 and C2. In some embodiments, the signal TV interconnects (TVS) in column C1 are nested with the ground TV interconnects (TVG). Furthermore, the signal TV interconnects in column C2 are designed to be adjacent to the mass TV interconnects 132TVG in column C1.

[0047] In some embodiments, the lower semiconductor die may also have an additional interface (also called a digital input / output (I / O) interface) to send digital input / output (I / O) signals and thus control other external integrated circuits (ICs) connected to the base. The digital I / O interface may be located adjacent to the DDR4 interfaces and near the edge of the lower semiconductor die to facilitate the use of the conductive structures between the DDR4 interfaces and the corresponding package edge of the fan-out package. Fig. Figure 3A is a sectional view of a semiconductor package assembly 500C according to some embodiments of the disclosure. Fig. 3B is a perspective plan (the bottom view) of a fan-out package 300C of the semiconductor package assembly 500C from Fig. 3A according to some embodiments of the disclosure, which shows the arrangement of an interface 132IO of a semiconductor die 132C and the conductive structures 322, with the exception of interfaces 132DDR-1, 132DDR-2, 132DDR-3, 132DDR-4, and 132DTD. It should be noted that the Fig. Figure 3B shows only the TV interconnects 132TV1 in interfaces 132DTD and 132DTD, and 132TV3 in interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4 for illustrative purposes, but 102B, 400, and 422 are hidden in the figure. Elements of the embodiments described below, which are illustrated above with reference to the Fig. Sections 1A-1C and 2A-2E, which are the same or similar, are not repeated for the sake of brevity.

[0048] As in the Fig. 3A and Fig. As shown in Figure 3B, the difference between the 500B semiconductor package assembly and the 500C semiconductor package assembly is that the 132C semiconductor die of the 500C fan-out package assembly can still have the 132 IO interface to send digital input / output (I / O) signals and thus control other external ICs (not shown) connected to base 200. The 132 IO interface can be located adjacent to the 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4 interfaces and closer to the 132E1 edge than the 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4 interfaces. In other words, interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-4 are located near edge 132E1 and between interfaces 132DTD and interface 132IO along direction 100.In some embodiments, the interface 132IO is electrically connected to the conductive structures 322 in a region 380 outside the edge 132E1 along direction 100 by the RDL structure 316 instead of the RDL structure 366, as shown in . Fig. Figure 3B is shown. Furthermore, the region 380 is positioned between edge 132E1 and the corresponding edge 316E of the RDL structure 316 (also called the package edge 316E of the semiconductor package arrangement 500C). Therefore, the use of the conductive structures 322 outside the interfaces 132DDR-1, 132DDR-2, 132DDR-3 and 132DDR-4 is improved.

[0049] In some embodiments, the lower semiconductor die may still incorporate an embedded trench capacitor (such as a deep trench capacitor (DTC)) to provide a higher capacitance than the conventional on-die capacitor for the Memory Package 400. Fig. Figure 4 is a sectional view of a semiconductor package assembly 500D according to some embodiments of the disclosure. Fig. Figure 5 is a sectional view of a semiconductor package arrangement 500E according to some embodiments of the disclosure. Fig. Figure 6 is an enlarged sectional view of the semiconductor package assembly 500D or 500E according to some embodiments of the disclosure, showing a trench capacitor 132DTC inserted into a semiconductor die 132D or 132E of a fan-out package 300D or 300E of the semiconductor package assembly 500D or 500E. Fig. 4 and Fig. 5 is embedded. Elements of the embodiments described below, which are described above with reference to the Fig. Items 1A-1C, 2A-2E and 3A-3B, which are the same or similar as those described, are not repeated for the sake of brevity.

[0050] As in Fig. As shown in Figure 4, the difference between the semiconductor die 132A of the semiconductor package assembly 500A and a semiconductor die 132D of the semiconductor package assembly 500D is that the semiconductor die 132D has a trench capacitor 132DTC embedded within it. In some embodiments, the trench capacitor 132DTC is located in a region of the semiconductor die 132D that overlaps the interfaces 102DDR of the semiconductor die 102A. Furthermore, the trench capacitor 132DTC may be located adjacent to the TV interconnects 132TV2. In some embodiments, the trench capacitor 132DTC can be electrically connected to the memory package 400 through the RDL structure (the upper RDL structure) 366 and the interfaces 102DDR-1, 102DDR-2, 102DDR-3 and 102DDR-4 of the semiconductor die (the upper semiconductor die) 102A.

[0051] As in Fig. As shown in Figure 5, the difference between the semiconductor die 132B of the semiconductor package assembly 500B and a semiconductor die 132E of the semiconductor package assembly 500E is that the semiconductor die 132E has the trench capacitor 132DTC embedded within it. In some embodiments, the trench capacitor 132DTC is located in at least one of the interfaces 132DDR-1, 132DDR-2, 132DDR-3, and 132DDR-4 and is electrically connected to the memory package 400 via the RDL structure 366. Furthermore, the trench capacitor 132DTC can be located adjacent to the TV interconnects 132TV3.

[0052] As in Fig. As shown in Figure 6, the trench capacitor 132DTC can be fabricated from a silicon substrate 132S of the semiconductor die 132D (or the semiconductor die 132E) using semiconductor processes. The trench capacitor 132DTC can be fabricated in a trench (not shown) in a doped region 132DR of the silicon substrate 132S and separated from the silicon substrate 132S by a dielectric layer DTC-1D for insulation. Furthermore, the conductivity of the doped region 132DR can differ from that of the doped region 132D. In some embodiments, the trench capacitor 132DTC can have a first electrode DTC-1E, a dielectric layer DTC-2D, a second electrode DTC-2E, a first electrode contact DTC-1C, and a second electrode contact DTC-2C. The first electrode DTC-1E and the second electrode DTC-2E, formed from doped silicon, polysilicon or conductive materials, have been manufactured conformally in the trench.Furthermore, the dielectric layer DTC-2D is arranged between the first electrode DTC-1E and the second electrode DTC-2E. The first electrode contact DTC-1C is located on the first electrode DTC-1E and is electrically connected to it. The second electrode contact DTC-2C is located on the second electrode DTC-2E and is electrically connected to it. In some embodiments, the second electrode contact DTC-2C may also be electrically connected to the doped area 132DR to increase the capacitance. In some embodiments, the first electrode contact DTC-1C and the second electrode contact DTC-2C may form part of the RDL structure 366 and include the conductive lines 370 and the vias 368 (as shown in the figures). Fig. 4 and Fig. 5 is shown).

[0053] Embodiments provide a semiconductor package assembly. The semiconductor package assembly comprises a fan-out package with an upper semiconductor die (e.g., a SoC die), a lower semiconductor die, and a memory package, stacked on top of each other and mounted on a base. The upper semiconductor die and the memory package are arranged side-by-side along a lateral direction (e.g., direction 100) and both stacked on the lower semiconductor die, with the through-hole interconnects (TV interconnects) oriented along a vertical direction (e.g., direction 120). Therefore, the upper semiconductor die can be manufactured with a greater thickness (e.g., the thickness of the upper semiconductor die can be similar to the thickness of the memory package) to improve thermal performance. The third interface, used to control the memory package, is located on the lower semiconductor die.Therefore, the third interface of the lower semiconductor die can overlap the memory package along the vertical direction. Furthermore, the third interface of the lower semiconductor die can accommodate the TV interconnects for data and power transmission, as well as the ground connection. This allows for further reductions in the trace lengths between the third interface of the lower semiconductor die and the memory package, and consequently, in the size of the semiconductor package assembly. The ground and signal TV interconnects in the third interface are nested. Each ground TV interconnect can act as a shield between two adjacent signal TV interconnects, thereby improving signal integrity issues such as crosstalk and latency uncertainty.In some embodiments, the orientation and shape of the distribution area and the pin order of the TV interconnects in the third interface of the lower semiconductor die can be the same as or similar to those of the overlapping conductive structures of the memory package, in order to shorten the trace path (between the third interface and the conductive structures of the memory package) for data transmission. In some embodiments, the lower semiconductor die can further include an additional digital input / output (I / O) interface adjacent to the third interface to send digital input / output (I / O) signals and thus control other external ICs through the base. Therefore, the utilization of the conductive structures of the fan-out package in the area outside the third interface can be further improved.In some embodiments, the lower semiconductor die may still have trench capacitors to provide a higher capacitance than the conventional capacitor located on the die for the memory package.

[0054] The invention is defined by the main claim and the dependent claims. The subclaims describe further embodiments of the invention.

Claims

[1] Semiconductor package arrangement (500B) with: a first semiconductor die (132B) and a second semiconductor die (102B) stacked on top of each other, the first semiconductor die (132B) has the following features: a first interface (132DTD) that overlaps and is electrically connected to a second interface (102DTD) located on the second semiconductor die (102B); and a third interface (132DDR) located on a first edge (132E1) of the first semiconductor die (132B); and a memory package (400) next to the first semiconductor die (132B), wherein the memory package (400) is electrically connected to the first semiconductor die via the third interface (132DDR); wherein the second semiconductor die (102B) and the memory package (400) are arranged side by side along a first direction (100), and wherein the second semiconductor die (102B) and the memory package are stacked on the first semiconductor die (132B) along a second direction (120) which is different from the first direction (100); the first semiconductor die (132B) has the following features: third via interconnects (132TV3) arranged in the third interface (132DDR) and electrically connected to the memory package (400); and fourth via interconnects (132TV1) arranged in the first interface (132DTD) and electrically connected to the second interface (102DTD) of the second semiconductor die (102B); and wherein the third through-hole interconnects (132TV3) are arranged in a first column (C2) and a second column (C1) adjacent to the first column and have the following: Ground through-hole interconnects (132TVG) that are arranged only in the first column (C2); and Signal via interconnects (132TVS) arranged in the first column (C2) and the second column (C1), wherein the signal via interconnects in the first column are nested with the ground via interconnects (132TVG), and the signal via interconnects in the second column are adjacent to the ground via interconnects. [2] Semiconductor package arrangement (500B) according to claim 1, wherein the first semiconductor die (132B) has a first critical dimension and the second semiconductor die (102B) has a second critical dimension, wherein the first critical dimension is narrower than the second critical dimension. [3] Semiconductor package arrangement (500B) according to claim 1 or 2, wherein the first semiconductor die (132B) has a fourth interface (132DDR-1', 132DDR-4') arranged on a second edge (132E4, 132E2) of the first semiconductor die and connected to the first edge (132E1), wherein the memory package (400) is electrically connected to the first semiconductor die and the second semiconductor die (102B) through the fourth interface. [4] Semiconductor package arrangement (500B) according to one of the preceding claims, wherein the third interface (132DDR) is arranged overlapping the memory package (400) along the second direction (120). [5] Semiconductor package arrangement (500B) according to one of the preceding claims, wherein the first interface (132DTD) is arranged on a third edge (132E3) of the first semiconductor die (132B) and opposite the first edge (132E1). [6] Semiconductor package arrangement (500B) according to one of the preceding claims, wherein the memory package (400) comprises first conductive structures (422) arranged in a group (422G1, 422G2) and having a first distribution area, the third via interconnects (132TV3) having a second distribution area which coincides with and at least partially overlaps the first distribution area. [7] Semiconductor package arrangement (500E) according to one of the preceding claims, wherein the first semiconductor die (132E) has a trench capacitor (132DTC) embedded in the third interface (132DDR) and electrically connected to the storage package (400). [8] Semiconductor package arrangement (500B) according to any one of the preceding claims, further comprising: a fan-out package (300B) comprising the first semiconductor die (132B), the second semiconductor die (102B) and the memory package (400), the fan-out package further comprising: a first redistribution layer structure (366) arranged between the first semiconductor die (132B) and the second semiconductor die (102B), wherein the first redistribution layer structure (366) is electrically connected to the first interface (132DTD), the second interface (102DTD), the third interface (132DDR) and the memory package (400); a second redistribution layer structure (316) which is electrically connected to the first redistribution layer structure (366) and is separated from the storage package (400) by the first redistribution layer structure; a first molding compound (362) covering the first redistribution layer structure (366) and the storage package (400); a second molding compound (312) that fills a space between the first redistribution layer structure (366) and the second redistribution layer structure (316); a fifth via interconnect (314) that passes through the second molding compound (312) and is electrically connected to the first redistribution layer structure (366) and the second redistribution layer structure (316); and second conductive structures (322) that are in contact with and electrically connected to the second redistribution layer structure (316). [9] Semiconductor package arrangement (500C) according to claim 8, wherein the first semiconductor die (132C) has a fifth interface (132IO) which is adjacent to the third interface (132DDR) and closer to the first edge (132E1) than the third interface (132DDR). [10] Semiconductor package arrangement (500C) according to claim 9, wherein the fifth interface (132IO) is electrically connected to the second conductive structures (322) outside the first edge (132E1) by the second redistribution layer structure (316) instead of by the first redistribution layer structure (366). [11] Semiconductor package arrangement (500B) with: a fan-out package (300 lbs) which includes the following: a storage package (400); a first semiconductor die (132B) arranged next to the memory package (400) along a first direction (120); and a second semiconductor die (102B) which is arranged next to the memory package (400) along a second direction (100), the first semiconductor die (132B) has the following features: a first interface (132DTD) that overlaps and is electrically connected to a second interface (102DTD) located on the second semiconductor die (102B); and a third interface (132DDR) which is located near the memory package (400) and electrically connected to it; the semiconductor package arrangement (500B) further comprises the following: a first redistribution layer structure (366) arranged between the first semiconductor die (132B) and the second semiconductor die (102B), wherein the first redistribution layer structure is electrically connected to the first interface (132DTD), the second interface (102DTD), the third interface (132DDR) and the memory package (400); and a second redistribution layer structure (316) which is electrically connected to the first redistribution layer structure (366) and is separated from the storage package (400) by the first redistribution layer structure; wherein the first semiconductor die (132B) is arranged between the first redistribution layer structure (366) and the second redistribution layer structure (316) and has via interconnects (132TV) arranged in the first interface (132DTD) and the third interface (132DDR); and wherein the via interconnects (132TV3) arranged in the third interface (132DDR) are arranged in a first column (C2) and a second column (C1) adjacent to the first column and have the following: Ground through-hole interconnects (132TVG) that are arranged only in the first column (C2); and Signal via interconnects (132TVS) arranged in the first column (C2) and the second column (C1), wherein the signal via interconnects in the first column are nested with the ground via interconnects (132TVG), and the signal via interconnects in the second column are adjacent to the ground via interconnects. [12] Semiconductor package arrangement (500B) according to claim 11, wherein the first semiconductor die (132B) has a fourth interface (132DDR-4'), wherein the third interface (132DDR-3') and the fourth interface are arranged on adjacent edges (132E2, 132E1) of the first semiconductor die, wherein the memory package (400) is electrically connected to the first semiconductor die (132B) through the fourth interface. [13] Semiconductor package arrangement (500B) according to claim 11 or 12, wherein the memory package (400) comprises first conductive structures (422) arranged in a group (422G1, 422G2) and having a first distribution area, and the via interconnects (132TV3) arranged in the third interface (132DDR) having a second distribution area which is identical to and at least partially overlaps the first distribution area. [14] Semiconductor package arrangement (500C) according to any one of claims 11 to 13, wherein the first semiconductor die (132C) has a fifth interface (132IO) which is adjacent to the third interface (132DDR) and is arranged on a first edge (132E1) of the first semiconductor die (132C), such that the third interface is arranged between the first interface (132DTD) and the fifth interface (132IO) along the second direction (100). [15] Semiconductor package arrangement (500C) according to claim 14, wherein the fifth interface (132IO) is electrically connected to second conductive structures (322) by the second redistribution layer structure (316) instead of by the first redistribution layer structure (366), which are in contact with the second redistribution layer structure (316) and are electrically connected to the second redistribution layer structure outside the first edge (132E1). [16] Semiconductor package arrangement according to any one of claims 11 to 15, wherein the first semiconductor die (132E) has a trench capacitor (132DTC) embedded in the third interface (132DDR) and electrically connected to the storage package (400) through the first redistribution layer structure (366). [17] Semiconductor package arrangement (500B) with: a fan-out package (300 lbs) which includes the following: a first redistribution layer structure (366) and a second redistribution layer structure (316) stacked on top of each other; an upper semiconductor die (102B) and a memory package (400) arranged on the first redistribution layer structure, wherein the upper semiconductor die (102B) has a first interface (102DTD); and a lower semiconductor die (132B) arranged between the first redistribution layer structure (366) and the second redistribution layer structure (316), wherein the lower semiconductor die has the following: a second interface (132DTD) that overlaps the first interface (102DTD); and first through-hole interconnects (132TV1) located in the second interface (132DTD) and electrically connected to the first interface (102DTD) via the first redistribution layer structure (366), and wherein the memory package (400) is electrically connected to the upper semiconductor die (102B) and the lower semiconductor die (132B) via the first redistribution layer structure (366) instead of the second redistribution layer structure (316); wherein the lower semiconductor die (132B) has a fourth interface (132DDR) that overlaps the memory package (400), the memory package being electrically connected to the lower semiconductor die via the fourth interface; and wherein the lower semiconductor die (132B) has third via interconnects (132TV3) arranged in the fourth interface (132DDR) and electrically connected to the memory package (400); wherein the third through-hole interconnects (132TV3) are arranged in a first column (C2) and a second column (C1) adjacent to the first column and have the following: Ground through-hole interconnects (132TVG) that are arranged only in the first column (C2); and Signal via interconnects (132TVS) arranged in the first column (C2) and the second column (C1), wherein the signal via interconnects in the first column are nested with the ground via interconnects (132TVG), and the signal via interconnects in the second column are adjacent to the ground via interconnects. [18] Semiconductor package arrangement (500C) according to claim 17, wherein the lower semiconductor die (132C) has a fifth interface (132IO) which is adjacent to the fourth interface (132DDR) and is arranged on a first edge (132E1) of the lower semiconductor die, such that the fourth interface is arranged between the second interface (132DTD) and the fifth interface (132IO). [19] Semiconductor package arrangement (500E) according to claim 17 or 18, wherein the lower semiconductor die (132E) has a trench capacitor (132DTC) embedded in the lower semiconductor die and electrically connected to the memory package (400).

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