POWER SEMICONDUCTOR DEVICE WITH SIC SEMICONDUCTOR BODY

Abstract

A power semiconductor device (100) is proposed. The power semiconductor device (100) comprises a silicon carbide (SiC) semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite the first surface (1031). The SiC semiconductor body (102) contains a transistor cell region (104) with transistor cells (1041). Each of the transistor cells (1041) contains a gate structure (106) comprising a gate dielectric structure (108) and a gate electrode structure (110) on the gate dielectric structure (108). The gate dielectric structure (108) comprises a first gate dielectric layer (1081) adjacent to the SiC semiconductor body (102). The gate dielectric structure (108) further comprises a second gate dielectric layer (1082).The gate dielectric structure (108) also includes a charge storage layer (1085) arranged between the first gate dielectric layer (1081) and the second gate dielectric layer (1082).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a power semiconductor device, in particular to a power semiconductor device including a SiC semiconductor body. BACKGROUND

[0002] The technological development of newer generations of SiC power semiconductor devices, e.g., insulated-gate field-effect transistors (IGFETs) such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs), aims to improve electrical device properties such as short-circuit current capability. For example, reference is made to the disclosure content of the documents DE 10 2014 111 981 B4, US 2023 / 0 088 637 A1, DE 10 2020 200 060 A1, and US 2005 / 0 263 853 A1. A multitude of compromises and challenges must be met or overcome when improving the short-circuit current capability of a SiC semiconductor device. For example, improving the short-circuit current capability, e.g.,by reducing the saturation current through lower overdrive voltages and / or through higher threshold voltages Vth and / or through lower gate voltages and / or through longer MOS channels, may have a negative impact on the overall performance of the device or increase the complexity of the circuit.

[0003] There is a need to improve the short-circuit current capability of SiC power semiconductor devices. SUMMARY

[0004] The invention is defined in the independent claims. Further developments are the subject of the dependent claims. One example of the present disclosure relates to a power semiconductor device. The power semiconductor device comprises a silicon carbide, SiC, semiconductor body having a first surface and a second surface opposite the first surface. The SiC semiconductor body has a transistor cell region containing transistor cells. Each of the transistor cells includes a gate structure comprising a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure includes a first gate dielectric layer adjacent to the SiC semiconductor body, a second gate dielectric layer, and a charge storage layer arranged between the first gate dielectric layer and the second gate dielectric layer.

[0005] Another example of the present disclosure relates to a method for manufacturing a power semiconductor device. The method includes providing a silicon carbide, SiC, semiconductor body having a first surface and a second surface opposite the first surface. The method further includes forming a transistor cell region with transistor cells in the SiC semiconductor body. Each of the transistor cells includes a gate structure including a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure includes a first gate dielectric layer adjacent to the SiC semiconductor body, a second gate dielectric layer, and a charge storage layer disposed between the first gate dielectric layer and the second gate dielectric layer.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of SiC semiconductor devices and, together with the description, serve to explain the principles of the embodiments. Additional embodiments are described in the following detailed description and claims. Fig. 1A schematically and exemplarily shows a partial cross-sectional view of a configuration example of a SiC power semiconductor device including a planar gate structure. Fig. 1B schematically and exemplarily shows a partial cross-sectional view of a configuration example of a SiC power semiconductor device including a trench gate structure. Fig. 2 schematically and exemplarily shows a partial cross-sectional view of a configuration example of a SiC power MOSFET including a trench gate structure. Fig. 3A to 3C are schematic views to describe operation modes of a configuration example of a power MOSFET. Fig. 4A to 7 are band diagrams to illustrate operating modes of configuration examples of a power MOSFET. DETAILED DESCRIPTION

[0008] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples in which semiconductor substrates may be processed. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used on or in connection with other examples to arrive at yet another example. It is intended that the present disclosure cover such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference numerals in the various drawings unless otherwise noted.

[0009] The terms "have," "contain," "comprise," "have," and the like are open-ended terms. These terms indicate the presence of certain structures, elements, or features, but do not preclude the presence of additional elements or features. The indefinite and definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0010] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor material. The term "electrically coupled" may include one or more intermediate elements suitable for signal and / or power transmission being connected between the electrically coupled elements, for example, elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0011] If two elements A and B are combined with "or," this can be understood to disclose all possible combinations, i.e., only A, only B, and A and B, unless explicitly or implicitly defined otherwise. An alternative formulation for the same combinations is "at least one of A and B" or "A and / or B." The same applies mutatis mutandis to combinations of more than two elements.

[0012] Ranges specified for physical dimensions include the boundary values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. The same applies to ranges with a boundary value such as "at most" and "at least."

[0013] The main components of a layer or structure made of a chemical compound or alloy can be those elements whose atoms form the chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0014] The term "on" should not be construed to mean only "directly on." Rather, if an element is positioned "on" another element (e.g., a layer is positioned "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).

[0015] An example of a power semiconductor device includes a silicon carbide, SiC, semiconductor body having a first surface and a second surface opposite the first surface. The SiC semiconductor body may include a transistor cell region having transistor cells. Each of the transistor cells may include a gate structure comprising a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure may include a first gate dielectric layer adjacent to the SiC semiconductor body. The gate dielectric structure may further include a second gate dielectric structure. The gate dielectric structure may further include a charge storage layer disposed between the first gate dielectric layer and the second gate dielectric layer.

[0016] The power semiconductor device may, for example, be part of an integrated circuit or be a discrete semiconductor device or a semiconductor module. The power semiconductor device may, for example, be or include an insulated gate field-effect transistor (IGFET) such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The power semiconductor device may be a vertical power semiconductor device with a load current flow between the first surface and the second surface opposite the first surface. The vertical power semiconductor device may be configured to conduct currents of more than 1 A, or more than 10 A, or more than 30 A, or more than 50 A, or more than 75 A, or even more than 100 A, and may further be configured to conduct voltages between load electrodes, e.g.between the collector and emitter of an IGBT or between the drain and source of a MOSFET, in the range of a few hundred to a few thousand volts, e.g., 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the power semiconductor device.

[0017] The power semiconductor device may be based on a semiconductor body made of crystalline SiC semiconductor material with a larger band gap than the band gap of silicon, i.e., greater than 1.12 eV. For example, the semiconductor material may be 2H-SiC (2H-polytype SiC), 6H-SiC, or 15R-SiC. According to one example, the semiconductor material is 4H-polytype silicon carbide (4H-SiC). The semiconductor body may include or consist of a semiconductor substrate having no, one, or more than one semiconductor layer thereon, e.g., epitaxially grown layers.

[0018] For example, the first surface may be a front surface or a top surface of the semiconductor body, and the second surface may be a rear surface or a back surface of the semiconductor body. The semiconductor body may be attached to a lead frame, for example, via the second surface. Bond pads may be arranged over the first surface of the semiconductor body, for example, and bond wires may be bonded to the bond pads.

[0019] To achieve a desired current carrying capacity, the SiC power semiconductor device can be designed using a plurality of transistor cells connected in parallel. The transistor cells connected in parallel can, for example, be transistor cells formed in the form of a strip or a strip segment. Of course, the transistor cells can also have any other shape, e.g., circular, elliptical, polygonal such as hexagonal or octahedral. The transistor cells are arranged in the transistor cell region of the SiC semiconductor body. The transistor cell region can be an active region in which an emitter region of an IGBT (or a source region of a MOSFET) and a collector region of an IGBT (or a drain region of a MOSFET) are arranged opposite one another along the vertical direction. In the active region, a load current can, for example,enter or exit the semiconductor body of the power semiconductor device via contact plugs on the first surface of the SiC semiconductor body. The power semiconductor device may further include an edge termination region comprising a termination structure. In a blocking mode or in a reverse-biased mode of the power semiconductor device, the blocking voltage between the transistor cell region and a field-free area drops laterally across the termination structure. The termination structure may have a higher or slightly lower voltage blocking capacity than the transistor cell region. The termination structure may, for example, include a junction termination extension (JTE) with or without variation of lateral doping (VLD), one or more laterally separated guard rings, or any combination thereof.

[0020] For example, the gate structure may be a planar gate structure or it may be a trench gate structure. The gate structure may be strip-shaped. The gate electrode structure may also have a different layout or geometry in plan view, e.g., hexagonal, square, circular, elliptical. The gate electrode structure of the gate structure may, for example, be electrically connected to a gate pad via a gate interconnect structure. The gate interconnect structure or a part thereof may be arranged outside the transistor cell region and may be arranged laterally between the transistor cell region and the edge termination region. The interconnect electrode may comprise one or more conductive materials, e.g., a metal, metal alloys, e.g., Cu, Au, AlCu, Ag, or alloys thereof, metal compounds, e.g.,TiN, a highly doped semiconductor material such as highly doped polysilicon. The one or more conductive materials can, for example, form a layer stack. At least a portion of the interconnect electrode can be a so-called gate channel or gate runner that transitions into the gate pad. The gate pad and, for example, a first load electrode pad, e.g., a source pad of a MOSFET or an emitter pad of an IGBT, can be part of a wiring region above the body of a wide bandgap semiconductor. The wiring region can contain one or more than one, e.g., two, three, four, or even more, wiring levels. Each wiring level can be formed by a single or a stack of conductive layers, e.g., metal layer(s). The wiring levels can, for example, be patterned lithographically. An interlayer dielectric structure can be arranged between stacked wiring levels.Contact plugs (contact plugs) and / or a contact line (contact lines) may be formed in openings of the interlayer dielectric structure in order to electrically connect parts, e.g., metal lines or contact areas, of different wiring levels.

[0021] By providing the charge storage layer in the gate dielectric structure, an intermediate insulating layer can be integrated into the gate dielectric structure, e.g., between the first gate dielectric layer and the second gate dielectric layer. The charge storage layer, e.g., an interlayer, can be configured to trap charges depending on the operating state of the power semiconductor device. For example, in a normal operating state or mode of the power semiconductor device, the interlayer can be uncharged. In the event of a short-circuit current event, charges, e.g., electrons, can be injected from the channel region of the power semiconductor device into this interlayer and form a charge QOX in this interlayer. This charging process can be induced, for example, by a temperature increase within the power semiconductor device.The temperature rise may, for example, be due to a short-circuit current event. In the case of an n-channel power semiconductor device, this may increase the negative electron charge in the interlayer and thus the threshold voltage of the power semiconductor device. Consequently, this may lead to a reduction in the so-called overdrive voltage. The saturation current and thus the thermal stress in the short-circuit case may also decrease. If the power semiconductor device is suitably designed, a complete shutdown of the power semiconductor device can be achieved. Technical effects and advantages associated with the configuration examples of power semiconductor devices disclosed herein include, among others, one or more of the following: - A self-triggering shutdown or short-circuit shutdown can avoid significant thermal stress on the power semiconductor device without affecting device parameters. This can also enable the use of gate materials sensitive to elevated temperatures (e.g., materials with a high dielectric constant); - optimization of the short-circuit withstand capability or short-circuit current capability of the power semiconductor device can be performed independently of the optimization of other important electrical properties (e.g. channel density, JFET, dual-gate); - Additional circuitry is not necessarily required for monitoring, detecting, and isolating the short circuit. This can reduce the complexity of the entire system and, most importantly, transfer the added value of these functions to the power semiconductor device; - after the power semiconductor device has switched itself off by means of self-triggering and the cause of the short circuit in the overall system has been eliminated, the threshold voltage can be restored to or close to its original value, e.g., by selectively applying a negative gate voltage.

[0022] For example, a power band offset at the first interface between the SiC semiconductor body and the first dielectric layer may have a value in a range from 1.0 eV to 2.0 eV or from 1.5 eV to 2.0 eV. This may be achieved by using a suitable material for the first dielectric layer. The conduction band offset range of 1.0 eV to 2.0 eV or from 1.5 eV to 2.0 eV may enable the accumulation of a charge in the charge storage layer based on thermionic emission described by Richardson's law, which allows the power semiconductor device to be turned off in a suitable time period based on the shift in the threshold voltage caused by the charging process.

[0023] Furthermore, for example, the gate dielectric structure may include a third gate dielectric layer arranged between the second gate dielectric layer and the gate electrode. The third gate dielectric layer may be adjacent to the gate electrode. Providing the third gate dielectric layer may enable optimization of the second gate dielectric layer with respect to trapping the charge in the charge storage layer, on the one hand, e.g., by appropriately defining a band offset between the charge storage layer and the second gate dielectric layer, and on the other hand, by optimizing the third gate dielectric layer with respect to contact with the termination of the gate dielectric structure to the gate electrode structure.

[0024] For example, the third gate dielectric layer may be a high-dielectric-constant layer. For example, a high-dielectric-constant material in the third gate dielectric layer or any other high-dielectric-constant layer of the gate dielectric structure may include at least one of Al2O3, ZrO2, HfO2, AlN, aluminosilicate AlSiOx, silicon-doped HfO2, lanthanum-doped HfO2, TiO2, Y2O3, or Si3N4, ONO (oxide-nitride-oxide), or any stacked combination thereof.

[0025] The second gate dielectric layer may, for example, be adjacent to the gate electrode. This may make it possible to provide a gate dielectric structure containing a charge storage layer for self-triggering shutdown, which can be easily fabricated by including a minimum number of dielectric sublayers.

[0026] The charge storage layer may, for example, have a potential well for electrons. A conduction band offset at a second interface between the charge storage layer and the first gate dielectric layer may be smaller than a conduction band offset at a third interface between the charge storage layer and the second gate dielectric layer. This may prevent the trapped charges, e.g., electrons, from being transferred from the charge storage layer to the gate electrode structure.

[0027] For example, a difference between the conduction band offset at the third interface and the conduction band offset at the second interface may have a value in a range of 0.5 eV to 3 eV.

[0028] The conduction band offset at the second interface can, for example, have a value in a range of 0.5 eV to 1.5 eV.

[0029] The charge storage layer can be, for example, a Hf2O3 layer. The first gate dielectric layer can be an Al2O3 layer. The second gate dielectric layer can be a SiO2 layer. This can create a potential well for electrons that has a larger band offset toward the gate electrode structure than toward the SiC semiconductor body. This can prevent the trapped charges, e.g., electrons, from transferring from the charge storage layer to the gate electrode structure.

[0030] For example, the charge storage layer may be an interface layer having interface trap states at an interface between the first gate dielectric layer and the second gate dielectric layer. A surface treatment process of the first gate dielectric layer prior to formation, e.g., deposition, of the second gate dielectric layer on the treated surface may, for example, enable the establishment of an interface trap density. A surface treatment process of the first gate dielectric layer prior to formation, e.g., deposition, of the second gate dielectric layer on the treated surface may enable a reduction in the trap density at the interface between the first gate dielectric layer and the SiC semiconductor body. After the first gate dielectric layer has been annealed, the second dielectric layer is deposited.Materials for the first and second gate dielectric layers may, for example, correspond to each other.

[0031] The charge storage layer may, for example, be a transition gate dielectric layer having a material composition that changes along a thickness direction of the gate dielectric structure from the material composition of the first gate dielectric layer to the material composition of the second gate dielectric layer. According to one configuration example, the transition gate dielectric layer may transition from a material composition of Al2O3 (first gate dielectric layer) to a material composition of SiO2 (second gate dielectric layer). According to another configuration example, the transition gate dielectric layer may transition from a material composition of Al x SiO y(first gate dielectric layer) into a material composition SiO2 (second gate dielectric layer). According to another configuration example, the gate dielectric layer can transition from a material composition AlN (first gate dielectric layer) into a material composition Al2O3 (second gate dielectric layer). According to yet another configuration example, the gate dielectric layer can transition from a material composition HfO2 (first gate dielectric layer) into a material composition SiO2 (second gate dielectric layer).

[0032] For example, a thickness of the gate dielectric layer with junction may have a value in a range of 0.1 nm to 3 nm.

[0033] For example, the gate dielectric layer with junction may have an impurity concentration with a value in a range of 10 11 cm -3 up to 10 13 cm-3 The defects can, for example, be configured as acceptor-like states within the dielectric band gap.

[0034] For example, the thickness of the first gate dielectric has a value in a range of 3 nm to 20 nm. If the thickness of the first gate dielectric is reduced below the lower limit, unwanted direct tunneling of electrons from the channel into the charge storage layer becomes more likely. If the thickness of the first gate dielectric is increased above the upper limit, the effect on the shift of the threshold voltage Vth may be too small.

[0035] The power semiconductor device may, for example, be a vertical n-channel power MOSFET (or IGBT) having a gate trench containing the gate structure.

[0036] For example, the vertical power MOSFET may include a p-doped diode region adjacent to a sidewall of opposite first and second sidewalls of the gate trench. The p-doped diode region may also be adjacent to a bottom side of the gate trench. The p-doped diode region may, for example, be configured to shield the gate dielectric structure at a bottom side of the gate trench from high electric field strengths. One sidewall adjacent to the p-doped diode region may define a non-channel region of the vertical power MOSFET. The other sidewall of the gate trench may define a channel region formed by a portion of a p-doped body region adjacent to the gate structure at the other sidewall of the gate trench. For example, a conductivity of the channel region may be influenced by a potential applied to the gate electrode structure, e.g. B. by means of a field effect.For example, a positive voltage applied to the gate electrode structure in an n-channel MOSFET may induce an n-inversion channel in a part of the p-doped body region, for example, adjacent to the first gate dielectric layer. The body region may be electrically connected via the first surface, e.g., by a contact plug on a top surface of the body region and / or a recess contact that may extend into the SiC semiconductor body and is electrically connected to the body region via a sidewall of the recess contact. The channel region part of the body region may, for example, include partial compensation by dopants of the second conductivity type, e.g., n-type dopants in the case of a p-doped body region, in order to adjust the threshold voltage. The partial compensation may, for example, be achieved by an oblique orTilted ion implantation can be achieved through a trench sidewall. For example, gate trench sidewalls may not be tapered or may be only slightly tapered. In the case of slightly tapered gate trench sidewalls, a channel length may be slightly larger than the vertical extent of a channel region. The cone angle of the trench-gate structure can be determined by the process technology, e.g., the aspect ratio of trench etch processes, and can also be used to maximize charge carrier mobility in the channel region, which depends on the direction along which a channel current flows. Another example of a tapered trench-gate structure is a V-shaped gate trench.

[0037] An example of a method for operating the power semiconductor device of any of the configuration examples described herein includes at least partially resetting the charge storage layer of the power semiconductor device by applying a negative gate-source voltage pulse.

[0038] Details regarding the structure or function or technical utility of features described above with respect to a power semiconductor device, such as an FET or IGBT, apply equally to the exemplary methods described herein. The processing of the SiC semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0039] The description and drawings merely illustrate the principles of the disclosure. Furthermore, any examples relied upon herein are expressly intended for illustrative purposes only to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to advance the art. All statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to include their equivalents.

[0040] It should be understood that the disclosure of multiple acts, processes, operations, steps, or functions disclosed in the description or claims should not be construed as occurring or occurring in the specific order unless, for example, expressly or implicitly indicated otherwise for technical reasons, e.g., by terms such as "thereafter." Therefore, the disclosure of multiple acts or functions does not limit them to a particular order unless those acts or functions are not interchangeable for technical reasons. Moreover, in some examples, a single act, function, process, operation, or step may be included or divided into multiple subacts, subfunctions, subprocesses, suboperations, or substeps.Such partial acts may be included in the disclosure of that single act and form part of it, unless expressly excluded.

[0041] A method for manufacturing a power semiconductor device comprises providing a silicon carbide, SiC, semiconductor body having a first surface and a second surface opposite the first surface. The method further comprises forming a transistor cell region with transistor cells in the SiC semiconductor body. Each of the transistor cells includes a gate structure having a gate dielectric structure and a gate electrode structure on the gate dielectric structure. The gate dielectric structure may include a first gate dielectric layer adjacent to the SiC semiconductor body. The gate dielectric structure may further include a second gate dielectric layer. The gate dielectric structure may further include a charge storage layer disposed between the first gate dielectric layer and the second gate dielectric layer.

[0042] The examples and features described above and below can be combined.

[0043] Some of the above and following examples are described in connection with a silicon carbide substrate. Alternatively, a wide-bandgap semiconductor substrate, such as a wide-bandgap wafer, may be processed, for example, comprising a wide-bandgap semiconductor material other than silicon carbide. The wide-bandgap semiconductor wafer may have a larger bandgap than the silicon bandgap (1.12 eV). For example, the wide-bandgap semiconductor wafer may be a silicon carbide (SiC) wafer, a gallium arsenide (GaAs) wafer, or a gallium nitride (GaN) wafer.

[0044] More details and aspects are mentioned in connection with the examples described above or below. A processing of a SiC semiconductor wafer may include one or more optional additional features according to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0045] The description and drawings merely illustrate the principles of the disclosure. Furthermore, any examples provided herein are expressly intended to be for illustrative purposes only, to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to advance the prior art. All statements herein that recite principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to include their equivalents.

[0046] Further examples of field-effect transistors (FETs) are explained below in conjunction with the accompanying drawings. Functional and structural details described with respect to the above examples are equally applicable to the exemplary embodiments illustrated in the figures and described below. N-channel FETs are illustrated in the illustrated examples. However, the examples described herein may also be applied to p-channel devices, e.g., p-channel MOSFETs or p-channel IGBTs.

[0047] Details relating to the structure or function or technical benefits of features described above apply equally to the examples below and vice versa.

[0048] Fig. 1A schematically illustrates, by way of example, a partial cross-sectional view of a power semiconductor device 100 configured as a planar gate SiC power MOSFET.

[0049] The partial cross-sectional view of Fig. 1A illustrates a portion of a transistor cell 1041 in a SiC semiconductor body 102 having a first surface 1031 and a second surface 1032 opposite the first surface 1031. The SiC power MOSFET includes a gate structure 106 configured as a planar gate structure. The gate structure 106 includes a gate dielectric structure 108. A gate electrode structure 110 of the gate structure 106 is disposed on the gate dielectric structure 108. A first gate dielectric layer 1081 of the gate dielectric structure 108 is adjacent to the SiC semiconductor body 102 at a first surface 1221. A charge storage layer 1085 is disposed on and adjacent to the first gate dielectric layer 1081. A second gate dielectric layer 1082 is disposed on and adjacent to the charge storage layer 1085.

[0050] Fig. 1B schematically and exemplarily shows a partial cross-sectional view of a power semiconductor device 100 configured as a SiC power MOSFET with a trench gate.

[0051] The partial cross-sectional view of Fig. 1B illustrates a portion of a transistor cell 1041 in the SiC semiconductor body 102. The SiC power MOSFET has the gate structure 106 configured as a trench gate structure in a gate trench 124. The gate structure 106 is as described above with reference to Fig. Configured as described in 1A.

[0052] Fig. 2 schematically and exemplarily shows a partial cross-sectional view of a configuration example of a power semiconductor device 100 configured as a trench-gate SiC power MOSFET. The SiC power MOSFET is a vertical power semiconductor device that further includes an edge termination region that at least partially surrounds the transistor cell region 104 (in Fig. 2 not illustrated).

[0053] The gate structure 106 is as above with reference to Fig. 1B. The first gate dielectric layer 1081 borders a channel region 112. The channel region 112 is defined by a portion of a p-doped body region 114, which borders the first gate dielectric layer 1081 at a first sidewall 1241 of the gate structure 106. For example, a conductivity of the channel region 112 may be controlled by a potential applied to the gate electrode structure 110, e.g., by means of a field effect. A positive voltage applied to the gate electrode structure 110 may, for example, induce an n-type inversion channel in the channel region 112, which borders, for example, the first gate dielectric layer 1081. The p-doped body region 114 may be exposed via the first surface 1031, e.g.,by a contact plug on a top surface of the body region 114 and / or a recess contact that may extend into the SiC semiconductor body 102 and may be electrically connected to the body region 114 through a sidewall of the recess contact (in . Fig. 2), may be electrically connected to a first load electrode L1. The channel region 112 as part of the body region 114 may, for example, include partial compensation by n-type dopants for adjusting the threshold voltage. The partial compensation may, for example, be achieved by means of a tilted ion implantation through a sidewall of a trench. The first gate dielectric layer 1081 of the gate dielectric structure 108 also borders on an n +doped source region 116, which is arranged between the p-doped body region 114 and the first surface 1031. The first gate dielectric layer 1081 of the gate dielectric structure 108 further borders an n-doped current spreading region 118, which is arranged between the p-doped body region 114 and an n-doped drift region 120. The n-doped drift region 120 has a lower doping concentration than the current spreading region 118. The n-doped drift region 120 is electrically coupled to a second load electrode L2 via the second surface 1032 of the SiC semiconductor body 102.

[0054] At a second sidewall 1242 of the gate structure 106, the first dielectric layer 1081 borders a p-doped diode region 123. The p-doped diode region 123 comprises a first subregion 1231 and a second subregion 1232. Doping concentration profiles of the first and second subregions 1231, 1232 overlap each other along a vertical direction y. The number of subregions may also differ from the illustrated example with two subregions, e.g., one, three, four, or five, or even more. An interlayer dielectric 126 electrically insulates the gate electrode structure 110 from the first load electrode L1.

[0055] The schematic views of the Fig. 3A to 3C serve to illustrate the operating principle of power semiconductor devices configured as n-channel power MOSFETs as described in the examples herein.

[0056] Referring to Fig. 3A, the power MOSFET contains the charge storage layer 1085 integrated in the gate structure 106. In a Fig. In the normal operating mode illustrated in Figure 3B, an electron channel current flow is indicated by circles. The electrons do not reach the charge storage layer 1085. In a short-circuit mode of the power MOSFET, which is shown in Fig. As illustrated in Figure 3C, some of the electrons flowing through the channel region reach the charge storage layer 1085 and contribute to a self-triggering shutdown of the short circuit.

[0057] Fig. 4A and Fig. 4B are exemplary conduction band diagrams to illustrate gate dielectric structures 108. The charge storage layer 1085 defines a potential well for electrons and is arranged between the gate dielectric layer 1081 and the second gate dielectric layer 1082. The gate dielectric structure 108 further comprises a third gate dielectric layer 1083 arranged between the second gate dielectric layer 1082 and the gate electrode structure 110. At a first interface 1221 between the SiC semiconductor body 102 and the first gate dielectric layer 1081, a conduction band offset Φ B,1 The schematic conduction band diagrams of the Fig. 4A and Fig. 4B differ from each other in that the conduction band offset at the second interface 1222 between the charge storage layer 1085 and the first gate dielectric layer 1081 in Fig. 4A smaller than in Fig. 4B. This results in a larger asymmetry of the conduction band offsets of the potential well. Furthermore, an asymmetry in the thickness of the barriers defined by the first gate dielectric layer 1081 and the second gate dielectric layer 1082 is present in Fig. 4A smaller than in Fig. 4B. In the Fig. 4A, Fig. In the normal operating mode illustrated in Figure 4B, electrons in the conduction band Ec of the SiC semiconductor body 102 do not reach the charge storage layer 1085 at low temperatures and positive gate-source voltage.

[0058] Fig. 5A and Fig. 5B are exemplary conduction band diagrams based on the band diagrams of Fig. 4A and 4B respectively, but refer to higher temperatures (e.g., initiated by a short-circuit event). At the higher temperatures, some of the electrons flowing through the channel region reach the Fig. 5B) or by thermionic emission (see Fig. 5A) the charge storage layer 1085 and contribute to a self-triggering shutdown of the short circuit.

[0059] Fig. 6A and Fig. 6B are exemplary conduction band diagrams based on the band diagrams of Fig. 4A and 4B, respectively, and illustrate a negative gate-source voltage pulse that resets the charge storage layer 1085 of the power MOSFET by removing the electrons from the charge storage layer 1085 using a Fowler-Nordheim tunneling process ( Fig. 6A) and a direct tunneling process ( Fig. 6B) back into the SiC semiconductor body 102.

[0060] Fig.7 is an exemplary conduction band diagram to illustrate a gate dielectric structure with a charge storage layer 1085 having a varying material composition. The varying material composition is a transition gate dielectric layer having a material composition that changes along a thickness direction x1 of the gate dielectric structure 108 over an extension d from the material composition of the first gate dielectric layer 1081 to the material composition of the second gate dielectric layer 1082. The transition gate dielectric layer contains impurities configured as acceptor-like states within the band gap of the dielectric. The acceptor-like states are exemplified by reference symbols Ea1, Ea2 and have a higher energy than the conduction band edge E Cof the SiC semiconductor body. When the extension d shrinks to zero, the acceptor-like states become interface trap states at an interface between the first gate dielectric layer 1081 and the second gate dielectric layer 1082.

[0061] The aspects and features mentioned and described together with one or more of the previously described examples and figures may also be combined with one or more of the other examples to replace a similar feature of the other example or to additionally introduce the feature into the other example.

Claims

[1] A power semiconductor device (100), comprising: a silicon carbide, SiC, semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite the first surface (1031), wherein the SiC semiconductor body (102) contains a transistor cell region (104) with transistor cells (1041), wherein each of the transistor cells (1041) a gate structure (106) comprising a gate dielectric structure (108) and a gate electrode structure (110) on the gate dielectric structure (108), wherein the gate dielectric structure (108) comprises a first gate dielectric layer (1081) adjoining the SiC semiconductor body (102), a second gate dielectric layer (1082) and a dielectric charge storage layer (1085) arranged between the first gate dielectric layer (1081) and the second gate dielectric layer (1082), wherein the charge storage layer (1085) contains a potential well for electrons and a conduction band offset at a second interface (1222) between the charge storage layer (1085) and the first gate dielectric layer (1081) is smaller than a conduction band offset at a third Interface (1223) between the charge storage layer (1085) and the second gate dielectric layer (1082). [2] Power semiconductor device (100) according to the preceding claim, wherein a conduction band offset (Φ B,1 ) at a first interface (1221) between the SiC semiconductor body (102) and the first dielectric layer (1081) has a value in a range of 1.0 eV to 2 eV. [3] The power semiconductor device (100) of any preceding claim, wherein the gate dielectric structure (108) further includes a third gate dielectric layer (1083) disposed between the second gate dielectric layer (1082) and the gate electrode structure (110), the third gate dielectric layer (1083) being adjacent to the gate electrode structure (110). [4] The power semiconductor device (100) according to the preceding claim, wherein the third gate dielectric layer (1083) is a high dielectric constant layer. [5] The power semiconductor device (100) of claim 1 or 2, wherein the second gate dielectric layer (1082) is adjacent to the gate electrode structure (110). [6] The power semiconductor device (100) according to claim 1, wherein a difference between the conduction band offset at the third interface (1223) and the conduction band offset at the second interface (1222) has a value in a range of 0.5 eV to 3 eV. [7] The power semiconductor device (100) according to the preceding claim, wherein the conduction band offset at the second interface (1222) has a value in a range of 0.5 eV to 1.5 eV. [8] The power semiconductor device (100) according to any one of the preceding claims, wherein the charge storage layer (1085) is a Hf2O3 layer, the first gate dielectric layer (1081) is an Al2O3 layer, and the second gate dielectric layer (1082) is a SiO2 layer. [9] A power semiconductor device (100), comprising: a silicon carbide, SiC, semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite the first surface (1031), wherein the SiC semiconductor body (102) contains a transistor cell region (104) with transistor cells (1041), wherein each of the transistor cells (1041) a gate structure (106) comprising a gate dielectric structure (108) and a gate electrode structure (110) on the gate dielectric structure (108), wherein the gate dielectric structure (108) comprises a first gate dielectric layer (1081) adjacent to the SiC semiconductor body (102), a second gate dielectric layer (1082), and a dielectric charge storage layer (1085) arranged between the first gate dielectric layer (1081) and the second gate dielectric layer (1082), wherein the charge storage layer (1085) is an interface layer having interface trap states at an interface between the first gate dielectric layer (1081) and the second gate dielectric layer (1082). [10] Power semiconductor device (100), comprising: a silicon carbide, SiC, semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite the first surface (1031), wherein the SiC semiconductor body (102) contains a transistor cell region (104) with transistor cells (1041), wherein each of the transistor cells (1041) a gate structure (106) comprising a gate dielectric structure (108) and a gate electrode structure (110) on the gate dielectric structure (108), wherein the gate dielectric structure (108) comprises a first gate dielectric layer (1081) adjoining the SiC semiconductor body (102), a second gate dielectric layer (1082), and a dielectric charge storage layer (1085) arranged between the first gate dielectric layer (1081) and the second gate dielectric layer (1082), wherein the charge storage layer (1085) is a transition gate dielectric layer having a material composition that transitions along a thickness direction of the gate dielectric structure from the material composition of the first gate dielectric layer (1081) into the material composition of the second gate dielectric layer (1082) changes. [11] The power semiconductor device (100) according to the preceding claim, wherein a thickness of the gate junction dielectric layer has a value in a range of 0.1 nm to 3 nm. [12] The power semiconductor device (100) according to any one of the two preceding claims, wherein the junction gate dielectric layer has an impurity concentration having a value in a range of 10 11 cm -3 up to 10 13 cm -3 contains. [13] The power semiconductor device (100) according to any one of the preceding claims, wherein a thickness of the first gate dielectric (1081) has a value in a range of 3 nm to 20 nm. [14] The power semiconductor device (100) of any preceding claim, wherein the power semiconductor device (100) is a vertical n-channel power MOSFET having a gate trench (124) containing the gate structure (106). [15] The power semiconductor device (100) of the preceding claim, wherein the vertical power MOSFET includes a p-doped diode region adjacent to a sidewall of opposite first and second sidewalls of the gate trench (124), and wherein the p-doped diode region is adjacent to a bottom of the gate trench (124). [16] A method for operating the power semiconductor device (100) according to any one of the preceding claims, comprising: at least partially resetting the charge storage layer (1085) of the power semiconductor device (100) by applying a negative gate-source voltage pulse. [17] A method of manufacturing a power semiconductor device (100), the method comprising: Providing a silicon carbide, SiC, semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite the first surface (1031); Forming a transistor cell region (104) with transistor cells (1041) in the SiC semiconductor body (102), wherein each of the transistor cells (1041) contains a gate structure (106) comprising a gate dielectric structure (108) and a gate electrode structure (110) on the gate dielectric structure (108), wherein the gate dielectric structure (108) comprises a first gate dielectric layer (1081) adjoining the SiC semiconductor body (102), a second gate dielectric layer (1082), and a dielectric charge storage layer (1085) arranged between the first gate dielectric layer (1081) and the second gate dielectric layer (1082),wherein the charge storage layer (1085) contains a potential well for electrons and a conduction band offset at a second interface (1222) between the charge storage layer (1085) and the first gate dielectric layer (1081) is smaller than a conduction band offset at a third interface (1223) between the charge storage layer (1085) and the second gate dielectric layer (1082).

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