TRANSISTOR ELEMENT WITH AN EDGE TERMINATION STRUCTURE AND METHOD

Abstract

A transistor device with an edge termination structure and a method are disclosed.

Description

[0001] This disclosure generally relates to a transistor device, in particular to a vertical transistor device with an edge termination structure.

[0002] A vertical transistor device is a transistor device in which source regions of transistor cells are spaced apart from a drain region of the transistor device in a vertical direction of a semiconductor body. The source regions can be arranged near a first surface of the semiconductor body, and the drain region can be arranged near a second surface opposite the first surface. Side surfaces (sidewalls) of the semiconductor body are surfaces that terminate the semiconductor body in lateral directions perpendicular to the first and second surfaces.

[0003] The transistor cells can be arranged in an inner region of the semiconductor body, wherein the inner region is surrounded in lateral directions by an edge region. Typically, vertical transistor components are designed such that the edge region is connected to the drain region in sections near the sidewalls. In this case, an edge termination structure arranged in the edge region absorbs a voltage that may arise between the drain region and the source regions when the transistor component is in an off-state. The reverse voltage withstand capability is the maximum voltage that the transistor component can withstand in the off-state. The edge termination structure can be configured to absorb a voltage that is at least equal to or higher than the reverse voltage withstand capability.

[0004] The transistor cells each comprise a gate electrode that is dielectrically insulated from the semiconductor body by a gate dielectric and configured to control an operating state of the transistor components. Typically, a gate-controlled transistor component can be operated in a reverse operating state (diode state). This is an operating state in which body diodes formed between the body regions of the transistor cells and a drift region are conductive. Operating the transistor component in a diode state is associated with a charge carrier plasma formed in the drift region and comprising charge carriers of a first type (e.g., electrons) and a second type (e.g., holes).When the transistor device changes from the diode state to the off state, the charge carriers that form the charge carrier plasma must be removed from the drift region both in the interior and in the edge region of the semiconductor body.

[0005] An example of an edge termination structure is disclosed in US 2020 / 0105918 A1.

[0006] There is a need for an edge termination structure that can withstand stresses that may arise between the inner region and the edge region of the transistor device and that can efficiently remove charge carriers from the edge region after the transistor device has been operated in the diode state.

[0007] One example relates to a transistor component. The transistor component comprises a semiconductor body having an inner region and an edge region; a drain region of a first doping type arranged in the inner region and the edge region; a plurality of transistor cells at least partially integrated in the inner region of the transistor component; and an edge termination structure. The edge termination structure comprises an edge trench extending from a first surface of the semiconductor body into the edge region and having a trench bottom and an inner trench sidewall facing the inner region.The edge termination structure further comprises a first insulating layer covering the trench bottom and the inner trench sidewall, a first edge region of a second doping type complementary to the first doping type, arranged adjacent to the inner sidewall and connected to a source node of the transistor device, a first field electrode arranged above the first insulating layer, connected to a gate node of the transistor device and at least partially overlapping the inner trench sidewall in a first lateral direction of the semiconductor body.

[0008] Another example relates to a transistor component. The transistor component comprises a semiconductor body having an inner region and an edge region; a drain region of a first doping type arranged in the inner region and the edge region; a plurality of transistor cells at least partially integrated in the inner region of the transistor component; and an edge termination structure.The edge termination structure comprises an edge trench extending from a first surface of the semiconductor body into the edge region and comprising a trench bottom and an inner trench sidewall facing the inner region, a first insulating layer covering the trench bottom and the inner trench sidewall, a first edge region of a second doping type complementary to the first doping type, which is connected to a source node of the transistor device and extends adjacent to the inner trench sidewall from the trench bottom to the first surface of the semiconductor body, and a first field electrode arranged above the first insulating layer and connected to a gate node of the transistor device.

[0009] Yet another example relates to a method. The method comprises forming an edge termination structure of a transistor device. Forming the edge termination structure comprises forming an edge trench in an edge region of a semiconductor body such that the edge trench comprises a trench bottom and an inner trench sidewall facing an interior region of the semiconductor body, and forming a first edge region of a second doping type adjacent to the inner trench sidewall. Forming the first edge region comprises implanting dopant atoms of the second doping type at least into the inner trench sidewall.

[0010] Examples are explained below with reference to the drawings. The drawings are intended to illustrate certain principles, so only aspects necessary for an understanding of those principles are shown. The drawings are not to scale. Throughout the drawings, like reference numerals indicate like features. Fig. 1 schematically illustrates a vertical cross-sectional view of a portion of a transistor device comprising a semiconductor body having an inner region and an edge region, transistor cells in the inner region, and an edge termination structure; Fig. 3-5 illustrate various modifications of the Fig. 1 shown edge termination structure; Fig. 6 illustrates transistor cells each comprising a gate electrode according to an example; Fig. Figure 7 illustrates an example of the gate electrodes in more detail; Fig. Figure 8 illustrates a more detailed vertical cross-sectional view of a portion of a transistor device of the Fig. 1 type shown; Fig. 9 illustrates a modification of the Fig. 8 shown edge termination structure; Fig. 10A-10B each illustrate a top view of the transistor device according to an example; Fig. Figure 11 illustrates a vertical cross-sectional view of a transistor device of the Fig. 8 in a vertical section plane different from that shown in Fig. 8 shown vertical section plane; Fig. 12 illustrates an edge termination structure based on the edge termination structure according to one of the Fig. 3-5 and includes additional features; Fig. 13-15 and 16A-16D illustrate various examples of methods for forming doped regions of the edge termination structure; and Fig. 17 illustrates a modification of the Fig. 16A-16C.

[0011] In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and, for the purpose of illustration, show examples of how the invention may be used and implemented. It is to be understood that the features of the various embodiments described herein may be combined with one another, unless expressly stated otherwise.

[0012] Fig. 1 schematically illustrates a transistor device according to an example. In particular, Fig. 1 schematically shows a vertical cross-sectional view of a portion of the transistor device. The transistor device comprises a semiconductor body 100 having a first surface 101 and a second surface 102 opposite the first surface. Fig. 1 illustrates the transistor device in a vertical section plane that is substantially perpendicular to the first and second surfaces 101, 102.

[0013] According to one example, the semiconductor body 100 comprises a monocrystalline semiconductor material. The semiconductor material is, for example, silicon (Si) or silicon carbide (SiC).

[0014] Referring to Fig. 1, the semiconductor body 100 comprises an inner region 130 and an edge region 140. The edge region 140 surrounds the inner region 130 in lateral directions, which are directions that are substantially parallel to the first and second surfaces 101, 102. Hereinafter, "inner region of the transistor device" refers to those regions of the transistor device that comprise the inner region 130 of the semiconductor body 100 and portions of the transistor device that are arranged adjacent to the first surface 101 in a vertical direction z and adjacent to the second surface 102 in the vertical direction z. Furthermore, "edge region of the transistor device" refers to those regions of the transistor device that comprise the edge region 140 of the semiconductor body 100 and portions of the transistor device that are arranged adjacent to the first surface 101 and the second surface 102 in the vertical direction z.The vertical direction z is a direction perpendicular to the first and second surfaces 101, 102.

[0015] Referring to Fig. 1, the transistor component comprises a drain region 13 of a first doping type. The drain region 13 is arranged in the inner region 130 and the edge region 140 of the semiconductor body 100 and can adjoin the second surface 102.

[0016] In addition, the transistor component comprises a plurality of transistor cells 10 that are at least partially integrated in the interior region 130 of the semiconductor body 100. “At least partially integrated” includes that at least portions of the transistor cells are integrated in the semiconductor body and other portions may be arranged on the first surface 101. The transistor cells 10 are in Fig. 1 is not shown in detail. Instead, the transistor cells 10 are represented by a circuit symbol of a transistor.

[0017] For illustrative purposes only, the Fig. 1 represents an N-type transistor device, specifically an N-type enhancement-mode MOSFET (normally off-mode MOSFET). However, this is only an example. The transistor device is not limited to being an N-type transistor device, but may also be a P-type transistor device. Furthermore, the transistor device is not limited to being a normally-off device, but may also be a normally-on device.

[0018] Referring to Fig. 1, the transistor component further comprises an edge termination structure 20. The edge termination structure 20 comprises an edge trench 6, which extends from the first surface 101 of the semiconductor body 100 into the edge region 140. The edge trench comprises a trench bottom 61 and an inner trench sidewall 62, which is a sidewall of the edge trench facing the inner region 130. The edge trench further comprises an outer trench sidewall opposite the inner trench sidewall 62. The outer trench sidewall is in Fig. 1 is not shown and is explained further below.

[0019] The edge termination structure 20 further includes a first insulating layer 51 covering the trench bottom 61 and the inner trench sidewall 62. According to one example, the first insulating layer 51 completely fills the edge trench 6.

[0020] The edge termination structure 20 further comprises a first edge region 71 of a second doping type complementary to the first doping type. The first edge region 71 is arranged adjacent to the inner trench sidewall 62 and connected to a source node S of the transistor component. According to one example, the first edge region 71 extends along the entire inner trench sidewall 62 from the trench bottom 61 to the first surface 101 of the semiconductor body 100.

[0021] In addition, the edge termination structure 20 comprises a first field electrode 31. The first field electrode 31 is arranged above the first insulating layer 51 and connected to a gate node G of the transistor device. The first field electrode 31 at least partially overlaps the inner trench sidewall 62 of the edge trench 6. That is, a projection of the first field electrode 31 onto the edge trench 6 in the vertical direction z overlaps the inner trench sidewall 62. In Fig. 1, ovl denotes the overlap between the first field electrode 31 and the inner trench sidewall 62.

[0022] The first field electrode 31 contains, for example, doped polysilicon.

[0023] At least portions of the inner surface 62 are inclined relative to the vertical direction z, such that the inner trench sidewall 62 has a specific width w62 in a first lateral direction x that differs from zero. The first lateral direction x is substantially parallel to the first and second surfaces 101, 102. According to one example, the edge trench 6 is elongated in a second lateral direction y perpendicular to the first lateral direction x. The width w62 of the inner trench sidewall 62 in the first lateral direction x is, for example, between 0.5 micrometers and 2 micrometers, in particular between 0.8 micrometers and 1.2 micrometers.

[0024] The source node S is a circuit node of the transistor device to which the source regions of the transistor cells 10 are connected. The gate node G of the transistor device is a circuit node to which the gate electrodes of the transistor cells 10 are connected. Examples of the transistor cells comprising source regions and gate electrodes are explained further below. In addition to the source node S and the gate node G, the transistor device also includes a drain node D. The drain node D is a circuit node connected to or formed by the drain region 13.

[0025] The first field electrode 31 is, for example, a planar electrode. According to one example, the first field electrode 31 is arranged in a horizontal plane that is spaced apart from the first surface 101 of the semiconductor body 100 in the vertical direction z. For this purpose, the first field electrode 31 can be arranged on a second insulating layer 52, wherein portions of the second insulating layer 52 are arranged on the first insulating layer 51 and other portions can be formed on the first surface 101.

[0026] The second insulating layer 52 is in Fig. 1 is only shown schematically. The first insulating layer 51, which fills the edge trench 6, and the second insulating layer 52 can be manufactured by the same process, so that the first and second insulating layers 51, 52 can be part of a contiguous insulating layer manufactured by the same manufacturing process.

[0027] As stated above, at least portions of the inner trench sidewall 62 are inclined relative to the vertical direction z, so that the edge trench widens towards the first surface 101. For illustrative purposes only, the Fig. 1 is curved, so that at different positions of the inner trench sidewall 62 there are different angles of inclination relative to the vertical direction z. However, this is only an example. According to another embodiment shown in Fig. In the example illustrated in Figure 2, the inner trench sidewall 62 is substantially straight. In each of the examples explained above, an edge trench 8 with a curved inner trench sidewall 62 or a substantially straight inner trench sidewall 62 may be used.

[0028] The formation of the edge trench 6 may include an isotropic etching process using an etch mask formed on the first surface 101. In this process, portions of the semiconductor body 100 are removed in directions perpendicular to the first surface 101 and in lateral directions below the etch mask, thereby obtaining inclined inner and outer trench sidewalls. This type of method is generally known, so no further explanation is required.

[0029] The Fig. 3-5 illustrate various modifications of the Fig. 1 and Fig. 2. For illustrative purposes only, the inner trench side walls 62 are shown in the Fig. 3-5 examples shown are curved.

[0030] Referring to Fig. 3, the edge termination structure 20 may further comprise a second edge region 81 of the first doping type. The second edge region 81 is arranged adjacent to the trench bottom 61 in the vertical direction z and is arranged adjacent to the first edge region 71 in the first lateral direction x. Furthermore, the edge termination structure 20 may comprise a third edge region 72 of the second doping type. The third edge region 72 is adjacent to the first edge region 71 and the second edge region 82 in the vertical direction z.

[0031] Referring to Fig. 4, the first field electrode 31 may completely overlap the inner trench sidewall 62. In this example, the overlap ovl is equal to the width w62 of the inner trench sidewall in the first lateral direction x. In the first lateral direction x, the first field electrode 31 may extend beyond the inner trench sidewall 62 in the direction of the inner region 120. In this example, as shown in Fig. 4, the first field electrode 31 forms portions of the first edge region 71 that adjoin the inner trench sidewall 62. According to one example (not shown), the first field electrode 31 extends beyond the first edge region 71 in the first lateral direction x in the direction of the inner region 130.

[0032] Referring to Fig. 5, the first edge region 71 may comprise three sections: a first section 711 extending along the inner trench sidewall 62, a second section 712 extending in the first lateral direction x in the direction of the inner region 130 and along the first surface 101 away from the inner trench sidewall 62, and a third section 713 extending in the lateral direction x along a section of the trench bottom 61 away from the inner region 130. A dimension d1 of the second section 712 in the first lateral direction x is, for example, between 1 micrometer and 15 micrometers, in particular between 3 micrometers and 10 micrometers. A dimension d2 of the third section 713 in the first lateral direction x is, for example, between 1 micrometer and 15 micrometers, in particular between 2 micrometers and 5 micrometers.

[0033] As explained above, the transistor component comprises a plurality of transistor cells 10 which are at least partially integrated in the inner region 130 of the semiconductor body 100. Fig. 6 schematically illustrates transistor cells 10 according to an example. In particular, Fig. 6 a vertical cross-sectional view of a portion of the semiconductor body 100 in which the transistor cells 10 are formed.

[0034] Referring to Fig. 6, each transistor cell 10 comprises a source region 11 of a first doping type, a body region 12 of a second doping type complementary to the first doping type, and a gate electrode 21. The gate electrode 21 is adjacent to the body region 12, is dielectrically insulated from the body region 12 by a gate dielectric 22, and is arranged in a gate trench 120 that extends from the first surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0035] Referring to Fig. 6, source and body regions 11, 12 of two adjacent transistor cells 10 may be arranged in a mesa region between adjacent gate trenches 120. In this example, the body regions 12 of the two adjacent transistor cells 10 may be formed by a contiguous doped region of the second doping type. Furthermore, two (other) adjacent transistor cells may share the gate electrode 21. That is, the gate electrodes 21 of two adjacent transistor cells may be formed by a contiguous electrode arranged in a gate trench 120.

[0036] The gate electrodes 21 comprise an electrically conductive material. Examples of the electrically conductive material include doped polysilicon or a metal such as tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), or the like. The gate dielectric 22 comprises, for example, an oxide. According to one example, the oxide is silicon oxide (SiO2).

[0037] As stated above, the source regions 11 of the transistor cells 10 are connected to the source node S of the transistor device. Referring to Fig. 6, the transistor device may comprise a source electrode 41, wherein the source electrode 41 either forms the source node S or is connected to the source node S. The source electrode 41 comprises an electrically conductive material such as aluminum (Al), copper (Cu), or an aluminum-copper alloy (AlCu).

[0038] The source electrode 41 is electrically connected to the source and body regions 11, 12 of the transistor cells 10. Connections between the source electrode 41 and the source and body regions 11, 12 are in Fig. 6 is only shown schematically. Such connections can be realized using electrically conductive vias extending from the source electrode 41 through an insulating layer 53 to the source and body regions 11, 12. This is generally known, so no further explanation is required.

[0039] The insulating layer 53 is formed on the first surface 101 and the gate electrodes 21 and separates the source electrode 41 from the semiconductor body 100 and the gate electrodes 21. The insulating layer 53 may include portions of the second insulating layer 52 previously discussed herein.

[0040] Referring to Fig. 6, the transistor component further comprises a drift region 14 of the first doping type. The drift region 14 borders the body regions 12 of the transistor cells 10, so that PN junctions are formed between the body regions 12 and the drift region 14. Furthermore, the drift region 14 is arranged vertically between the body regions 12 and the drain region 13.

[0041] Optionally, a buffer region 16 of the first doping type, which has a doping concentration higher than the doping concentration of the drift region 14 and lower than the doping concentration of the drain region 13, is arranged between the drift region 14 and the drain region 13.

[0042] Referring to Fig. 6, the gate trenches with the gate electrodes 21 are spaced apart from one another in a third lateral direction x1. The third lateral direction x1 is perpendicular to the vertical direction z of the semiconductor body 100 and may correspond to the first lateral direction x explained above. According to one example, the gate electrodes 21 are formed as strip electrodes (elongated electrodes). In this example, the gate electrodes 21 are elongated in a fourth lateral direction y1 perpendicular to the third lateral direction x1, wherein the fourth lateral direction y1 may correspond to the second lateral direction y explained above.

[0043] An example of elongated gate electrodes 21 is shown in Fig. 7 shown. Fig. 7 illustrates a portion of the semiconductor body 100 in a Fig. 6, which intersects the gate trenches 120 with the gate electrodes 21 and the gate dielectrics 22. The horizontal cutting plane BB is substantially parallel to the first and second surfaces 101, 102.

[0044] According to one example, the transistor component is formed as a superjunction transistor component. In this example, the transistor component comprises a plurality of compensation regions 15 (illustrated in dashed lines) spaced apart from one another in a lateral direction of the semiconductor body 100. The compensation regions 15 are each adjacent to a respective portion of the drift region 14.

[0045] For illustrative purposes only, the Fig. In the example shown in Figure 6, the compensation regions 15 are spaced apart from one another in the third lateral direction x1. According to a further example (not shown), the compensation regions 15 are spaced apart from one another in the fourth lateral direction y1.

[0046] The transistor component can be operated in an on-state or an off-state. In the on-state, conductive channels exist in the body regions 12 along the gate dielectrics between the source regions 11 and the drift region 14. For this purpose, the drift region 14 borders the gate dielectric 22 and the body region 12 of at least one of the transistor cells 10.

[0047] In addition, the optional compensation regions 15 are each adjacent to at least one of the sections of the drift region 14 and are connected to the source electrode 41. In the Fig. In the example shown in Figure 6, the compensation regions 15 each border on the body region 12 of at least one transistor cell and are connected to the source electrode 41 via the respective body region 12.

[0048] The transistor device can be operated in a conventional manner by applying a drive voltage (gate-source voltage) between the gate electrodes 21 and the source electrode 41. The transistor device is in the on-state (conductive state) when the drive voltage is such that conductive channels are created in the body regions 12 along the gate dielectrics 22 between the source regions 11 and the drift region 14. The transistor device is in the off-state (blocking state) when the electrically conductive channels are interrupted.

[0049] The transistor component can be embodied as an N-type transistor component or as a P-type transistor component. For example, an N-type transistor component is in the on state when the drive voltage is higher than a predefined positive threshold voltage and in the off state when the drive voltage is below the threshold voltage.

[0050] In an N-type transistor device, the doped regions of the first doping type are N-type regions, and the doped regions of the second doping type are P-type regions. In a P-type transistor device, the doped regions of the first doping type are P-type regions, and the doped regions of the second doping type are N-type regions.

[0051] The source regions 11, the body regions 12, the drift and compensation regions 14, 15, the buffer region 16, and the drain region 13 can also be referred to as active device regions. For an N-type transistor component, doping concentrations of the active device regions are selected, for example, from the following ranges: Source area 11: 5E19 cm -3 - 5E20 cm -3 Body area 12: 3E19 cm -3 - 3E20 cm -3 Drainage area 13: 5E18 cm -3 - 5E20 cm -3 Drift area 14: 7E15 cm -3 - 7E16 cm -3 Compensation area 15: 7E15 cm -3 - 7E16 cm -3 Buffer area 16: 5E15 cm -3 - 5E16 cm -3 Body contact area 17: 1E20 cm -3 - 1E21 cm -3

[0052] Fig. Figure 8 illustrates in more detail an example of a transistor device of the Fig. 1. In particular, Fig. 8 is a vertical cross-sectional view of a portion of the semiconductor body 100, wherein the portion of the Fig. 8 comprises sections of the inner region 130 and the edge region 140.

[0053] The Fig. The transistor component shown in Figure 8 comprises transistor cells of the Fig. 6. In addition, the Fig. 8, the transistor component has an edge termination structure 20 of the Fig. 5. However, this is only an example. Any other type of edge termination structure previously explained here may also be used in the transistor device according to Fig. 8 be trained.

[0054] The Fig. 8 are superjunction transistor cells which, in addition to the drift region 14, comprise compensation regions 15. According to an example shown in Fig. As shown in Figure 8, drift and compensation regions are arranged not only in the inner region 130, but also in the edge region 140. Hereinafter, the drift regions arranged in the edge region 140 are referred to as edge drift regions 14', and compensation regions arranged in the edge region 140 are referred to as edge compensation regions 15'. In the vertical direction z, the edge drift and compensation regions 14', 15' can be spaced further from the first surface 101 than the drift and compensation regions 14, 15 in the inner region 130.

[0055] As stated above, the source and body regions 11, 12 of the transistor cells are connected to the source electrode 41. According to an example shown in Fig. As shown in Figure 8, the source and body regions 11, 12 are connected to the source electrode 41 by electrically conductive vias 42 that extend from the source electrode 41 through the insulating layer 53 into the semiconductor body 100 to the source and body regions 11, 12. Optionally, the transistor cells each comprise a body contact region 17 of the second doping type, which provides an ohmic contact between a body region 12 and the respective electrically conductive via 42. The body contact regions 17 have a higher doping concentration than the body regions 12.

[0056] As explained above, the first edge region 71 is connected to the source node S of the transistor component. For this purpose, in the Fig. In the example shown in Figure 8, the first edge region 71 is connected to the source electrode 41 via at least one electrically conductive via 43. Optionally, a contact region 18 of the second doping type adjoins the via and provides an ohmic contact between the via 43 and the first edge region 71. The contact region 18 has a higher doping concentration than the first edge region 71.

[0057] Referring to Fig. 8, the transistor component further comprises a gate runner 44, which is spaced apart from the first field electrode 31 in the vertical direction z and is electrically connected to the first field electrode 31. The gate runner 44 is arranged on an insulating layer 5. Portions of the insulating layer 5 separate the gate runner 44 from the first field electrode 31. The insulating layer 5 is arranged between the first surface 101 on one side and the gate runner 44 and the source electrode 41 on the other side. The third insulating layer 53 and the second insulating layer 52, which were previously explained herein, are portions of this insulating layer 5.

[0058] As explained above, the first field electrode 31 is connected to the gate node G. As will be explained further below, the gate runner 44 is connected to the gate node G. Thus, in the example according to Fig. 8 for connecting the first field electrode 31 to the gate node G, the first field electrode 31 is connected to the gate runner 44 via an electrically conductive via 45 which extends from the gate runner 44 downwards to the first field electrode 31 in the insulating layer 5.

[0059] The fabrication of the semiconductor body 100 of the transistor device may comprise epitaxially growing a plurality of epitaxial layers one above the other and implanting dopant atoms into each of the epitaxial layers before forming the next epitaxial layer. In particular, the drift regions 14, 14', the compensation regions 15, 15', and the third edge region 72 may be formed in this way. The source and body regions 11, 12 may be formed by implanting dopant atoms into the semiconductor body 100 via the first surface 101 after each of the epitaxial layers has been formed. The drain region 13 may be formed by a semiconductor substrate on which the epitaxial layers are grown.

[0060] The epitaxial layers have a (low) basic doping, for example, as low as intrinsic. After the individual component regions explained above have been formed, regions may remain in the semiconductor body 100 that comprise the basic doping of the epitaxial layers. Examples of such regions having the basic doping are shown in Fig. 8 and is designated by the reference symbol BD.

[0061] Referring to Fig. 8, the plurality of transistor cells comprise an edge transistor cell, which is the one of the transistor cells closest to the edge region 140. The edge transistor cell may comprise a source region 11 (in Fig. 8 shown in dashed lines). Alternatively, the source region 11 in the edge transistor cell is omitted.

[0062] According to one example, the body region 12 of the edge transistor cell extends in a lateral direction to the first edge region 71. In the Fig. In the example illustrated in Figure 8, the third lateral direction x3, in which the gate electrodes 21 of the transistor cells 10 are spaced apart from one another, corresponds to the first lateral direction x of the edge termination structure 20. In this example, the body region 12 extends in the first and third lateral directions x, x1 to the first edge region 71.

[0063] In the Fig. 8, the first field electrode 31 completely overlaps the inner trench sidewall 62 and overlaps portions of the first edge region 71. However, the first field electrode 31 does not completely overlap the first edge region 71, so that the first edge region 71 can be directly connected to the source electrode 41 via the electrically conductive via 43.

[0064] Fig. 9 shows a modification of the transistor device according to Fig. 8. In the Fig. In the example shown in Figure 9, the first field electrode 31 completely overlaps the first edge region 71. In this example, the electrically conductive via 43 connects the source electrode 41 to the body region 12 of the edge transistor cell and thus connects the first edge region 71, which borders the body region 12, to the source electrode 41.

[0065] The Fig. 10A and Fig. 10B each illustrate a top view of a transistor device according to an example. In particular, the Fig. 10A and Fig. 10B each shows a plan view of the semiconductor body 100, wherein the source electrode 41 and the gate runner 44 are formed on the insulating layer 5. Referring to the Fig. 10A and Fig. 10B, the gate runner 44 surrounds the source electrode 41 in lateral directions of the semiconductor body 100.

[0066] The transistor device further includes a gate pad 45 connected to the gate runner 44. The gate pad 45 forms the gate node G or is connected to the gate node G of the transistor device. The gate pad 45 may be adjacent to the gate runner 44, as shown in the Fig. 10A and Fig. 10B. Alternatively, the gate pad 45 is spaced from the gate runner 44, and a resistor (gate resistor) is connected between the gate pad 45 and the gate runner 44.

[0067] In the Fig. 10A, the gate pad 45 is arranged at a position that is substantially midway between two opposite side walls 103, 106 of the semiconductor body 100. In the example according to Fig. 12B, the gate pad 45 is arranged at a position close to a corner formed by two adjacent sidewalls 105, 106 of the semiconductor body 100.

[0068] The transistor cells are in the Fig. 10A and Fig. 10B outside the illustration. For the purpose of illustration, Fig. 10A and Fig. 10B, the position of three gate electrodes 21 relative to the source electrode 41 and the gate runner 44 is shown by bold lines. Fig. 10A and Fig. In the example shown in Figure 10B, the gate electrodes 21 are elongated electrodes, wherein a longitudinal direction of these gate electrodes 21 corresponds to the second and fourth lateral directions y, y1, which were previously explained. The vertical cross-sectional view of the gate electrodes 21 shown in Fig. 6 is a cross-sectional view in section planes AA, which for example in the Fig. 10A and Fig. 10B. The vertical cross-sectional view of the edge transistor cell and an adjacent portion of the Fig. 8 and Fig. 9 is a cross-sectional view in section planes CC, which, for example, in the Fig. 10A and Fig. 10B are shown.

[0069] The edge termination structure 20 surrounds the inner region 130 of the semiconductor body 100 in lateral directions. Fig. 8 and Fig. 9, sections of the edge termination structure 20 are shown, which are arranged adjacent to the inner region 130 in the first lateral direction x, which is equal to the third lateral direction x3 in which the gate electrodes 21 of the individual transistor cells are spaced from one another, and which is perpendicular to a longitudinal direction of the gate electrodes 21. The Fig. 8 and Fig. The edge termination structure 20 shown in Figure 9 is arranged between the inner region 130 and a first side wall 103 of the Fig. 10A and Fig. 10B. On the opposite side, that is, between the inner region 130 and the opposite side wall 105, the edge termination structure is the same as in the Fig. 8 and Fig. 9 shown.

[0070] According to one example, the edge termination structure 20 surrounding the inner region 130 includes at least the edge trench 6 with the first insulating layer 51, the first edge region 71, and the first field electrode 31 surrounding the inner region 130 in lateral directions. That is, the edge trench 6, the first insulating layer 51, the first edge region 71, and the first field electrode 31 each form a closed loop around the inner region 130. According to one example, the second and third edge regions 81, 71 also form a respective closed loop around the inner region 130.

[0071] Fig. 11 shows a vertical cross-sectional view of the edge termination structure 20, which is arranged between longitudinal ends of the gate trenches 21 and a sidewall of the semiconductor body 100. In addition to the edge termination structure 20, the gate electrode 21 of a transistor cell in Fig. 11. The Fig. The vertical cross-sectional view shown in Figure 11 is a sectional view in section plane DD, which, for example, in the Fig. 10A-10B. In this example, the Fig. 11 is arranged between the inner region and a second side wall 104 perpendicular to the first side wall 103. On the opposite side, that is, between the inner region 130 and the opposite side wall 106, the edge termination structure is the same as in Fig. 11 shown.

[0072] According to one example, the gate electrodes 21 are each connected to the gate runner 44 at least at one longitudinal end. An example for connecting the Fig. 11 shown gate electrodes 21 to the gate runner 44 is shown in Fig. 11. In this example, the gate electrode 21 is connected to the first field electrode 31 via a contact finger 32 extending from the first field electrode 31 to the gate electrodes 21. The first field electrode 31 and the contact finger can be manufactured using the same process, so that the first field electrode 31 and the contact finger 32 are formed by a continuous electrode layer. The electrode layer is an electrically conductive layer, such as a doped polysilicon layer.

[0073] As explained above, the first edge region 71 is connected to the source electrode 41. In the Fig. 11, the source electrode 41 is connected to the first edge region 71 at positions spaced from the contact finger 32, so that in Fig. 11 no connection between the source electrode 41 and the first edge region 71 is shown.

[0074] The figures explained previously illustrate a portion of the edge termination structure 20 in a portion of the edge region 140 adjacent to the inner region 130. The remainder of the edge termination structure is not shown in these drawings. A vertical cross-sectional view of the entire edge termination structure 20 according to an example is shown in Fig. 12. The Fig. The edge termination structure shown in Figure 12 is based on the edge termination structure according to one of the Fig. 4 and Fig. 5. The Fig. The cross-sectional view shown in Figure 12 is a cross-sectional view in section planes CC and DD, which, for example, in the Fig. 10A and Fig. 10B. Thus, Fig. 12 shows a portion of the edge termination structure 20 arranged between the inner region 130 and the first surface 103 or between the inner region 130 and the second surface 104. Between the inner region 130 and the third and fourth surfaces 105, 106, the edge termination structure 20 can be arranged in the same way as in Fig. 12 shown.

[0075] Referring to Fig. 12, the edge trench 6 comprises an outer trench sidewall 63, which is a trench sidewall facing the respective sidewall 103, 104 of the semiconductor body 100. According to one example, the edge termination structure 20 further comprises a second field electrode 32 arranged above the first insulating layer 51. According to one example, the second field electrode 32 at least partially overlaps the outer trench sidewall 63. The other trench sidewall 63 may have the same shape as the inner trench sidewall 62. According to one example, the second field electrode 32 is connected to a drain runner 46. The drain runner 46 is arranged on the insulating layer 5 and is spaced apart in lateral directions from both the source electrode 41 and the gate runner 44.The drain runner 46 comprises an electrically conductive material such as tungsten (W), titanium (Ti), aluminum (Al), copper (Cu) or an alloy of one or more of these materials.

[0076] According to one example, the drain runner 46 is connected to the second field electrode 32 via an electrically conductive via 47 that extends from the drain runner 46 through portions of the insulating layer 5 to the second field electrode 32.

[0077] The drain runner 46 is arranged between the gate runner 44 and the sidewalls 103, 104, 105, 106 of the semiconductor body 100. According to one example, the drain runner 46 forms a closed loop around the source electrode 41, the gate runner 44, and the gate pad 45. Fig. 10A and Fig. However, the drain runner 46 is not shown in Figure 10B.

[0078] Referring to Fig. 12, the edge termination structure 20 may further comprise a field stop 73 of the first doping type. The field stop 73 extends along the sidewalls 103, 104 between the first surface 101 and the buffer region 16 (as shown) or the drain regions 13. The field stop region 73 surrounds the inner region 120. That is, the field stop region 73 forms a closed loop around the inner region 130. According to one example, the drain runner 46 is electrically connected to the field stop region 73.

[0079] The drain runner 46 may be connected to the field stop region 73 at one or more positions. The drain runner 46 may be connected to the field stop region 73 by an electrically conductive via 46 extending from the drain runner 46 through portions of the insulating layer 5 to the field stop region 73. According to one example, the drain runner 46 is connected to the field stop region 73 only in areas of the four corners of the semiconductor body 100.

[0080] Referring to Fig. 12, the edge termination structure 20 may further comprise a third field plate 33 arranged in a trench extending from the first surface 101 into the field stop region 73. The third field electrode 33 is dielectrically insulated from the semiconductor body 100 by a field electrode dielectric 53. The third field electrode 33 comprises an electrically conductive material, such as doped polysilicon. The field electrode dielectric 53 comprises, for example, an oxide. The third field electrode 33 is electrically connected to the drain runner 46, for example, by an electrically conductive via 49.

[0081] Referring to Fig. 12, the second and third edge regions 81, 72 may extend in the first lateral direction x in the direction pointing away from the inner region 130 beyond the edge trench 6 and the third field electrode 33. This is shown in Fig. 12 is shown in dashed lines. According to another example (shown in solid lines), the second and third edge regions 81, 72 end below the edge trench 6 in the first lateral direction x.

[0082] The transistor component explained above can be operated in a diode state. This is an operating state in which a voltage is applied between the drain and source nodes D, S, forward-biasing the PN junctions between the drift region 14 and the body regions 12 of the transistor cells 10. For example, an N-type transistor component is in a diode state when a positive voltage is applied between the drain node D and the source node S and when the transistor cells are driven such that the conductive channels in the body regions 12 along the gate dielectrics 22 are interrupted.

[0083] In this operating state, a charge carrier plasma comprising charge carriers of the first type (e.g., electrons) and the second type (e.g., holes) is generated in the drift region 14. When the transistor device transitions from the diode state to the off-state, which is an operating state in which the PN junctions are reverse-biased and the conducting channels in the transistor cells 10 are interrupted, the charge carrier plasma must be removed from the drift regions 14, 14'. The majority charge carriers, which are electrons in an N-type device, are collected by the drain region 13 and the optional buffer region 16 when the transistor device transitions from the diode state to the off-state. The minority charge carriers, which are holes in an N-type transistor device, are collected by the body regions 12 of the transistor cells 10 in the interior region 130 of the transistor device.In the edge region of the transistor device, the first edge region 71 and the optional third edge region 72 efficiently collect the minority charge carriers and therefore ensure increased robustness of the transistor device during the transition between the diode state and the off state.

[0084] Furthermore, the edge termination structure 20 with the first insulating layer 51 and the optional second and third edge regions 81, 72 efficiently absorbs the drain-source voltage in the edge region of the transistor device. The drain-source voltage is the voltage applied between the drain node D and the source node S. Due to the field stop region 73 connected to the drain regions 13, the voltage applied between the drain and source nodes D, S also occurs between the edge surfaces 103-106 and the interior region 130 of the transistor device. The first electrode 31, which is connected to the gate node G and overlaps the inner trench sidewall 62, shapes the electric field in the edge region in a favorable manner, so that the edge termination structure 20 can withstand voltages that occur between the sidewalls and the interior region.

[0085] The maximum voltage that can occur between the sidewalls and the interior region 130 depends on the blocking voltage capability of the transistor component. For example, the blocking voltage capability of the transistor component is 600 V or higher.

[0086] The first, second and third edge regions 71, 81, 72 can be manufactured in different ways. Examples of manufacturing these edge regions 71, 81, 72 are described below with reference to Fig. 13, 14, 15, and 16A-16B. These figures each show a portion of the semiconductor body 100 during the respective manufacturing process.

[0087] According to a Fig. 13, the formation of the first edge region 71 comprises implanting dopant atoms of the second type at least into the inner trench sidewall 62 of the edge trench 6. The implantation of the dopant atoms of the second type into the first trench sidewall 62 forms the first section 711 (see Fig. 5) of the first edge region 71. According to one example, dopant atoms of the second type are also implanted into portions of the first surface 101 adjacent to the trench sidewall 62 and into portions of the trench bottom 61 adjacent to the trench sidewall to form second and third portions 712, 713 (see Fig. 5) of the first peripheral area 71.

[0088] The implantation process uses an implantation mask having an opening defining the regions of the semiconductor body 100 into which the dopant atoms are to be implanted. The implantation mask 301 is either a mask formed on the semiconductor body 100 (as illustrated) or is a metal mask held spaced apart from the first surface 101 of the semiconductor body.

[0089] According to a Fig. In the example illustrated in Figure 13, a direction in which the second-type dopant atoms are implanted is substantially equal to the vertical direction z. In this case, an implantation angle relative to the vertical direction z is 0.

[0090] According to another in Fig. In the example illustrated in Figure 14, the implantation process is an inclined implantation process. The implantation angle relative to the vertical direction z is selected, for example, between 2° and 10°. Furthermore, the implantation angle is such that the implantation direction is inclined toward the inner trench sidewall 62, thereby reducing the implantation dose into the trench sidewall 62 compared to the Fig. 13 illustrated example.

[0091] As explained above, the edge trench 6 surrounds the inner region 130 in lateral directions of the semiconductor body 100. In this example, the edge trench 6 comprises four different inner trench sidewalls, so that the inclined implantation process may comprise four inclined implantation processes, each for implanting dopant atoms of the second type into one of the four different inner trench sidewalls.

[0092] The implantation dose is selected, for example, between 1E13 cm -2 and 5E13 cm -2 According to one example, the implantation dose is the dose of implanted dopant atoms in a region perpendicular to the implantation direction. The implantation energy is selected between 120 keV and 180 keV. The doped atoms are, for example, boron atoms.

[0093] The implantation of the dopant atoms of the second type results in a first implanted region 71' in the semiconductor body 100. In addition to the implantation of the dopant atoms of the second type, the formation of the first edge region 71 may include an annealing process in which the implanted dopant atoms of the second type are activated (and may diffuse in the semiconductor body 100).

[0094] The optional third edge region 72 may be formed before forming the first edge region 71. According to one example, dopant atoms for forming the third edge region 72 are formed before forming the first edge region 71. Fig. 13 and Fig. 14. In this example, the same annealing process or different annealing processes may be used to activate the implanted atoms forming the first and third edge regions 71, 72.

[0095] According to a Fig. In the example illustrated in FIG. 15, forming the second edge region 81 may include implanting dopant atoms of the first type into the trench bottom 61 using a further implantation process 302. In addition to implanting the dopant atoms of the first type, forming the second edge region 81 may include an annealing process that activates the implanted dopant atoms of the first type. The dopant atoms of the first type for forming the second edge region 81 may be implanted into the semiconductor body before or after implanting the dopant atoms of the second type for forming the first edge region 71. The same annealing process or different annealing processes may be used to activate the dopant atoms of the second type implanted for forming the first edge region 71 and the dopant atoms of the first type implanted for forming the second edge region 81.

[0096] As explained above, the semiconductor body 100 may comprise several epitaxial layers formed one above the other. A topmost of these epitaxial layers forms the first surface 101, in which the edge trench 6 is formed and into which dopant atoms can be implanted to form the source and body regions 11, 12 of the transistor cells 10.

[0097] Fig. 16A schematically illustrates a portion of an epitaxial layer 100 n-1 , on which the top epitaxial layer is grown. This epitaxial layer 100 n-1 is referred to below as the penultimate epitaxial layer. According to one example, the formation of the third edge region 72 comprises implanting dopant atoms of the second type into the penultimate epitaxial layer 100. n-1 using an implantation mask 303 which covers the sections of the epitaxial layer 100 n-1defines the region into which the dopant atoms are to be implanted. The implantation of the dopant atoms of the second type results in an implanted region 72' comprising dopant atoms of the second type. In addition to implanting the dopant atoms of the second type, the formation of the third edge region 72 includes an annealing process that activates the implanted dopant atoms.

[0098] As stated above, the formation of the second edge region 81 may comprise implanting dopant atoms into the trench bottom 61. Alternatively, as in Fig. 16B, forming the second edge region 81 comprises implanting dopant atoms of the first type into the penultimate epitaxial layer using a further implantation mask 304. Implanting the dopant atoms of the first type results in an implanted region 81', wherein forming the second edge region 81 comprises an annealing process that activates (and diffuses) the implanted dopant atoms of the first type.

[0099] Referring to the Fig. 16C and Fig. 16D, the method further comprises forming the top epitaxial layer 100 n on the penultimate epitaxial layer 100 n-1 and forming the edge trench 6 in the semiconductor body 100. According to one example, the edge trench 6 is formed only in the uppermost epitaxial layer 100 nAccording to another example (not shown), the edge trench 6 extends through the uppermost epitaxial layer 100 n into sections of the penultimate epitaxial layer 100 n-1 .

[0100] The annealing process for activating the implanted dopant atoms in the Fig. 16A and Fig. 16B may be performed after implanting the dopant atoms to form the first edge region 71.

[0101] In the Fig. 16A-16D, the doping concentration of the third edge region 72 is essentially determined by the implantation dose at the Fig. 16A illustrated implantation process.

[0102] According to one example, the third edge region 72 is formed such that the doping concentration in the third edge region 72 decreases in the first lateral direction x in a direction pointing away from the inner region 130. A third edge region 72 of this type can be formed by implanting dopant atoms of the second type into the penultimate epitaxial layer 100 n-1 in a further implantation process before or after the Fig. 16A. This is shown in Fig. 17 illustrates.

[0103] Fig. 17 illustrates a vertical cross-sectional view of the penultimate epitaxial layer 100 n-1 during the further implantation process. The implanted areas 72', which are formed by the Fig. 6A illustrated implantation process before the further implantation process are prepared in Fig. 17 shown in dashed lines.

[0104] In the Fig. 17, dopant atoms of the second type are implanted into the penultimate epitaxial layer 100 n-1 implanted using an implantation mask 305 comprising a plurality of openings 306 spaced apart from one another in the lateral direction x. In the further implantation process, dopant atoms of the second type are introduced through the openings 306 into the penultimate epitaxial layer 100. n-1 implanted to form further implanted areas 72" which cover the areas formed by the Fig. 16A illustrated implantation process provided locally increase the implantation dose.

[0105] A width and a mutual distance of the openings 306 in the first lateral direction x define a doping concentration gradient in the finished third edge region 72. According to one example, the width and / or the mutual distance increase from opening to opening 306 in the direction pointing away from the interior region 130. According to one example, the further implantation mask 305 is such that, during the further implantation process, dopant atoms of the second type are implanted only into those regions located below the first edge region 71 in the finished device in order to provide a doping concentration gradient in the third region 72 in regions below the first edge region 71. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 2020 / 0105918 A1

[0005]

Claims

[1] Transistor device comprising: a semiconductor body (100) having an inner region (130) and an edge region (140); a drain region (13) of a first doping type arranged in the inner region (130) and the edge region (140); a plurality of transistor cells (10) which are at least partially integrated in the interior region (130) of the transistor component; and an edge termination structure (20), wherein the edge termination structure (20) comprises: an edge trench (6) extending from a first surface (101) of the semiconductor body (100) into the edge region (140) and having a trench bottom (61) and an inner trench sidewall (62) facing the inner region (130), a first insulating layer (51) covering the trench bottom (61) and the inner trench sidewall (62), a first edge region (71) of a second doping type, which is complementary to the first doping type, is arranged adjacent to the inner sidewall (62) and is connected to a source node (S) of the transistor component, a first field electrode (31) arranged above the first insulating layer (51), connected to a gate node (G) of the transistor component, and at least partially overlapping the inner trench sidewall (62) in a first lateral direction (x) of the semiconductor body (100). [2] Transistor component according to claim 1, wherein the first edge region (71) in the semiconductor body (100) extends along the inner trench sidewall (62) from the trench bottom (61) to the first surface (101). [3] Transistor device comprising: a semiconductor body (100) having an inner region (130) and an edge region (140); a drain region (13) of a first doping type arranged in the inner region (130) and the edge region (140); a plurality of transistor cells (10) which are at least partially integrated in the interior region (130) of the transistor component; and an edge termination structure (20), wherein the edge termination structure (20) comprises: an edge trench (6) extending from a first surface (101) of the semiconductor body (100) into the edge region (140) and having a trench bottom (61) and an inner trench sidewall (62) facing the inner region (130), a first insulating layer (51) covering the trench bottom (61) and the inner trench sidewall (62), a first edge region (71) of a second doping type, which is complementary to the first doping type, is connected to a source node (S) of the transistor component and extends adjacent to the inner trench sidewall (62) from the trench bottom (61) to the first surface (101) of the semiconductor body (100); and a first field electrode (31) disposed over the first insulating layer (51) and connected to a gate node (G) of the transistor device. [4] Transistor component according to claim 3, wherein the first field electrode (31) at least partially overlaps the inner trench sidewall (62) in a first lateral direction (x) of the semiconductor body (100). [5] Transistor component according to one of claims 2 to 4, wherein the first edge region (71) extends in the first lateral direction (x) over a first distance (d1) along the first surface (101). [6] Transistor component according to claim 5, where the first distance (d1) is between 1 micrometer and 15 micrometers. [7] Transistor component according to one of the preceding claims, wherein the first field electrode (31) completely overlaps the inner trench sidewall (62) in the first lateral direction (x). [8] Transistor component according to claim 7, wherein the first field electrode (31) extends beyond the inner trench sidewall (62) in the first lateral direction (x). [9] Transistor component according to one of the preceding claims, wherein the first edge region (71) extends in the first lateral direction (x) over a second distance (d2) along the trench floor (61). [10] Transistor component according to claim 9, where the second distance (d2) is between 1 micrometer and 15 micrometers. [11] Transistor component according to one of the preceding claims, wherein the edge termination structure (20) further comprises a second edge region (81) of the first doping type, wherein the second edge region (81) is arranged adjacent to the trench bottom (61) in a vertical direction (z) of the semiconductor body (100) and is arranged adjacent to the first edge region (71) in the first lateral direction (x). [12] Transistor component according to one of the preceding claims, wherein the edge termination structure (20) further comprises a third edge region (72) of the second doping type, wherein the third edge region (72) is adjacent to the first edge region (71) in the vertical direction (z). [13] A transistor device according to any one of the preceding claims, further comprising: a gate runner (44) connected to the first field electrode and spaced from the first surface (101) in the vertical direction (z). [14] Transistor component according to one of the preceding claims, wherein the edge termination structure (20) further comprises: a field stop region (73) of the first doping type, which adjoins side walls of the semiconductor body (100), a second field electrode (32) disposed over the first insulating layer (51) and connected to the field stop region (73). [15] A transistor device according to claim 14, further comprising: a drain runner (46) connected to the second field electrode (32) and the field stop region (73) and spaced from the first surface (101) in the vertical direction (z). [16] A transistor device according to claim 15, wherein the edge termination structure (20) further comprises: a third field electrode (33), wherein the third field electrode (33) is arranged in a field electrode trench which extends from the first surface (101) into the semiconductor body (100), is dielectrically insulated from the semiconductor body (100) by a field electrode dielectric (53) and is connected to the drain runner (46). [17] Transistor component according to one of claims 13 to 16, wherein the transistor cells (10) each have a gate electrode (21) which is connected to the gate runner (44). [18] Transistor component according to claim 17, wherein the transistor device further comprises a source electrode (41), and wherein the transistor cells (10) each have a source region connected to the source electrode (41). [19] Transistor component according to one of claims 13 to 18, wherein the gate runner (44) and the source electrode (41) are arranged above the first surface (101) of the semiconductor body (100). [20] Transistor component according to one of the preceding claims, wherein the drain region (13) is arranged adjacent to a second surface (102) opposite the first surface (101) of the semiconductor body (100). [21] A transistor device according to any one of the preceding claims, further comprising: a plurality of drift regions (14, 14') of the first doping type in the inner region (130) and the edge region (140), and a plurality of compensation regions (15, 15') of the second doping type in the inner region (130) and the edge region (140). [22] Transistor component according to one of the preceding claims, wherein the semiconductor body (100) further comprises side walls, and wherein the edge region (140) is arranged between the inner region (130) and the side walls. [23] Transistor component according to one of the preceding claims, wherein at least portions of the inner trench sidewall (62) are inclined relative to the vertical direction (z). [24] Method comprising: Producing an edge termination structure (20) of a transistor component, wherein the production of the edge termination structure (20) comprises: Producing an edge trench (6) in an edge region (140) of a semiconductor body (100) such that the edge trench (6) has a trench bottom (61) and an inner trench sidewall (62) facing an inner region (130) of the semiconductor body (100); and Producing a first edge region (71) of a second doping type adjacent to the inner trench sidewall (62), wherein forming the first edge region (71) comprises implanting dopant atoms of the second doping type at least into the inner trench sidewall (62). [25] The method of claim 24, further comprising: Producing a first insulating layer (51) covering the inner trench sidewall (62) and the trench bottom (61), and Producing a first field electrode (31) which is arranged above the first insulating layer (51) and at least partially overlaps the inner trench sidewall (62) in a first lateral direction (x) of the semiconductor body (100). [26] Method according to claim 24 or 25, wherein the implantation of the dopant atoms of the second doping type comprises a tilted implantation process. [27] Method according to claim 26, wherein an inclination angle in the implantation process relative to a vertical direction (z) of the semiconductor body (100) is between 1° and 10°. [28] The method of claim 27, wherein an implantation dose in the implantation process is selected between 1E13 cm -2 and 5E13 cm -2 . [29] Method according to claim 27 or 28, wherein an implantation energy in the implantation process is selected between 100 keV and 200 keV, in particular between 120 keV and 180 keV. [30] A method according to any one of claims 24 to 29, further comprising: Producing a second edge region (81) of a first doping type which is complementary to the second doping type, such that the second edge region (81) is arranged adjacent to the trench bottom (61) in a vertical direction (z) of the semiconductor body (100) and is arranged adjacent to the first edge region (71) in a first lateral direction (x). [31] Method according to claim 30, wherein the formation of the second edge region (81) comprises implanting dopant atoms of the first doping type into the trench bottom (61). [32] Method according to claim 30, wherein the formation of the second edge region (81) comprises implanting dopant atoms into a first semiconductor layer (100 n-1 ), wherein a second semiconductor layer (100 n ) on the first semiconductor layer (100 n-1 ) is produced, and wherein the edge trench (6) in the further semiconductor layer (100 n ) is produced. [33] The method of claim 32, further comprising: Producing a third edge region (72) of the second doping type such that the third edge region (72) is adjacent to the first edge region (71) in the vertical direction (z) of the semiconductor body (100), wherein the formation of the third edge region (72) comprises implanting dopant atoms of the second doping type into the first semiconductor layer (100 n-1 ).

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