INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR INSULATION

Abstract

Integrated circuit structures with deep via-rail insulation are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends across a plurality of source or drain structures, with individual trench contacts alternating with individual gate lines. A backside metal routing layer extends beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one or more of the plurality of trench contacts. The conductive structure includes a cut between the first and second conductive structural parts.A cut in the first of the multitude of gate lines next to the cut in the conductive structure is smaller than a cut in the second of the multitude of gate lines next to the first or second conductive structural part.

Description

TECHNICAL AREA

[0001] Embodiments of the disclosure are in the field of advanced manufacturing of an integrated circuit structure and, in particular, integrated circuit structures with deep via-bar isolation. STATE OF THE ART

[0002] Over the past few decades, the scaling of features in integrated circuits has been a driving force behind the steadily growing semiconductor industry. Scaling down to ever smaller features enables increased densities of functional units on the limited usable area of ​​semiconductor chips. For example, shrinking the transistor size allows for the inclusion of a greater number of memory or logic devices on a single chip, which is advantageous for manufacturing products with increased capacity. However, the drive for ever greater capacities also presents challenges. The need to optimize the performance of each device is becoming increasingly important.

[0003] Variability in conventional and currently known manufacturing processes may limit the possibility of extending them further into the 10-nanometer or sub-10-nanometer node range. Consequently, manufacturing the functional components required for future technology nodes may necessitate the introduction of new methodologies or the integration of new technologies into, or replacement of, current manufacturing processes.

[0004] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more common due to the ongoing downscaling of device dimensions. Tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred because of their lower cost and compatibility with the existing high-yield bulk silicon substrate infrastructure.

[0005] However, the scaling of multi-gate transistors has not been without consequences. With the reduction in the dimensions of these fundamental building blocks of a microelectronic circuit arrangement and the increase in the sheer number of basic components manufactured in a given area, the limitations of the semiconductor processes used to fabricate these components have become overwhelming. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates cross-sectional views of a front-side power supply intermediate stack and a rear-side power supply intermediate stack according to an embodiment of the present disclosure. Fig. Figure 2 illustrates an angled cross-sectional view of an integrated circuit structure with a deep via-bar (DVB) architecture according to an embodiment of the present disclosure. Fig. Figure 3 shows a front-view plan view of an integrated circuit structure with a deep via bar cut at a point where a gate cut is present. Fig. Figure 4 shows a front-view plan of an integrated circuit structure with a gate cut at an existing location of a deep via-bar cut, which may be referred to as a gate cut according to the deep via-bar cut approach, according to an embodiment of the present disclosure. Fig. Figure 5 illustrates an angled cross-sectional view of an integrated circuit structure with a recessed deep via-bar (DVB) architecture according to an embodiment of the present disclosure. Fig. Figures 6 to 8 illustrate angled cross-sectional views depicting various operations in a method for fabricating an integrated circuit structure with a recessed deep via-bar (DVB) architecture, according to an embodiment of the present disclosure. Fig. Figure 9 illustrates an angled cross-sectional view and a planar cross-sectional view of an integrated circuit structure with a recessed deep via-bar (DVB) architecture according to an embodiment of the present disclosure. Fig. Figure 10A illustrates a top view of a semiconductor device with a gate contact positioned over a non-active part of a gate electrode. Fig. Figure 10B illustrates a cross-sectional view of a non-planar semiconductor device with a gate contact positioned over a non-active part of a gate electrode. Fig. Figure 11A illustrates a top view of a semiconductor device with a gate contact via arranged over an active part of a gate electrode, according to an embodiment of the present disclosure. Fig. Figure 11B illustrates a cross-sectional view of a non-planar semiconductor device with a gate contact via arranged over an active part of a gate electrode, according to an embodiment of the present disclosure. Fig. Figures 12A-12J illustrate cross-sectional views of various processes in a method for fabricating a gate all-around structure of an integrated circuit according to an embodiment of the present disclosure. Fig. 13 illustrates a computing device according to an implementation of the disclosure. Fig. Figure 14 illustrates an interposer that includes one or more embodiments of the disclosure. Fig. Figure 15 is an isometric view of a mobile computing platform that uses an IC manufactured according to one or more processes described herein or that incorporates one or more features described herein, according to an embodiment of the present disclosure. Fig. Figure 16 illustrates a cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure. DESCRIPTION OF THE EMBODIMENTS

[0006] Integrated circuit structures with deep via-bar isolation are described. Numerous specific details, such as particular integration and material regimes, are presented in the following description to provide a comprehensive understanding of embodiments of the present disclosure. It is understood by a person skilled in the art that embodiments of the present disclosure can be implemented in practice without these specific details. In other cases, known features, such as the design layouts of integrated circuits, are not described in detail in order to avoid unnecessarily obscuring embodiments of the present disclosure. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0007] The following detailed description is for illustrative purposes only and is not intended to limit embodiments of the invention or the application and uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be considered preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any theory, expressed or implied, presented in the preceding technical field, background, summary, or detailed description.

[0008] This description includes references to "exactly one embodiment" or "one embodiment." The appearance of the phrases "in exactly one embodiment" or "in one embodiment" does not necessarily refer to the same embodiment. Certain features, structures, or properties may be combined in any suitable manner consistent with this disclosure.

[0009] Terminology. The following paragraphs provide definitions or context for terms that appear in this disclosure (including the attached claims):

[0010] "Comprehensive." This term is to be understood as open-ended. As used in the attached claims, this term does not exclude additional structure or additional processes.

[0011] "Designed to." Various units or components may be described or claimed to be "designed to" perform a task or tasks. In such contexts, "designed to" is used to imply a structure by indicating that the units or components incorporate a structure that performs that task or tasks during operation. Therefore, it can be said that the unit or component is designed to perform the task even if the specified unit or component is not currently operational (e.g., not powered on or active). The statement that a unit, circuit, or component is "designed to" perform one or more tasks is expressly not intended to invoke 35 USC § 112, sixth paragraph, for that unit or component.

[0012] As “first”, “second”, etc. are used herein, these expressions are used as labels for nouns that they precede, but do not imply any kind of order (e.g. spatial, temporal, logical, etc.).

[0013] "Coupled" - The following description refers to elements or nodes or features that are "coupled" to one another. As used herein, unless expressly stated otherwise, "coupled" means that an element or node or feature is directly or indirectly connected to (or communicates with) another element or node or feature, and this connection is not necessarily mechanical.

[0014] Furthermore, certain terminology in the following description may be used merely for reference purposes and is therefore not intended to be restrictive. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the referenced drawings. Terms such as "front," "back," "rear," "side," "outside," and "inside" describe the orientation or position, or both, of parts of the component within a consistent but arbitrary frame of reference, which is clarified by referring to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0015] "Inhibit" - As used herein, inhibit is used to describe a reduction or minimization effect. When a component or feature is described as inhibiting an action, movement, or condition, it can completely prevent the outcome, result, or future state. Furthermore, "inhibit" can also refer to a reduction or decrease of the result, performance, or effect that might otherwise occur. Accordingly, when a component, element, or feature is described as inhibiting an outcome or state, it need not completely prevent or eliminate the outcome or state.

[0016] The embodiments described herein can be directed toward front-end-of-line (FEOL) semiconductor processing and structuring. FEOL is the first part of integrated circuit (IC) fabrication, in which the individual devices (e.g., transistors, capacitors, resistors, etc.) are structured within the semiconductor substrate or semiconductor layer. FEOL generally covers everything up to (but not including) the deposition of metal interlayers. Following the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0017] The embodiments described here can relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, in which the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected via wiring on the wafer, such as the metallization layer(s). BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-package connections. During the BEOL part of the manufacturing process, contacts (contact pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in the BEOL.

[0018] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both. Although an exemplary processing scheme may be illustrated using an FEOL processing scenario, such approaches can also be applied to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches can also be applied to FEOL processing.

[0019] One or more embodiments are directed toward deep via-bar (DVB) isolation using poly-cut (PCT) processing. One or more embodiments are directed toward approaches that involve the use of PCT to eliminate DVG and DVP for some layouts. One or more embodiments described herein are directed toward integrated gate all-around circuit structures fabricated to incorporate deep via-bar isolation. It is understood that, unless otherwise specified, references to nanowires herein may refer to nanowires, nanoribbons, nanoplates, or fork plates. One or more embodiments described herein relate to fin-based integrated circuit structures fabricated to incorporate deep via-bar isolation.

[0020] Embodiments can be implemented to reduce process complexity by eliminating two immersion layers and a significant number of process operations. Embodiments can be implemented to eliminate the need for a power plug-in operation while maintaining targeted connectivity.

[0021] To provide context, in a standard cell design, the diffusion placement and metal routing layers are designed around a power supply scheme. This can be achieved through a front-side contact mound to M0 and the diffusion contact, or, in newer architectures, through metals on the wafer backside with a tap via a via that would contact the diffusion contact on the front side. When implemented, there is a dedicated space allocation for the power supply either on the front-side metals or the diffusion layer.

[0022] Power is typically supplied from a front-end interconnect. At the standard cell level, power can be supplied directly above transistors or from an upper and lower cell boundary. Power supplied from an upper and lower cell boundary allows for a relatively shorter standard cell height with a slightly higher power network resistance. However, a front-end power network shares the interconnect stack with the signal routing, reducing the number of signal routing traces. Additionally, for high-power designs, the upper and lower cell boundary power metal wires must be wide enough to reduce power network resistance and improve efficiency. This usually results in an increase in cell height.According to one or more embodiments of the present disclosure, power delivery from a wafer or substrate backside can be implemented to solve area and power handling problems. At the cell level, a wider metal 0 power supply at the top and bottom cell boundaries may no longer be required, and therefore the cell height can be reduced. Furthermore, the power network resistance can be significantly reduced, resulting in improved power handling. At the block and chip level, front-side signal routing paths are increased due to the elimination of power routing, and the power network resistance is significantly reduced due to very wide wires, large vias, and reduced interconnection layers.

[0023] In earlier technologies, a power supply network from the contact mound to the transistor required significant block resources. Such resource utilization on the metal stack was reflected in some process nodes as standard cell architectures with layout versioning or restrictions on cell placement at the block level. In one embodiment, eliminating the power supply network from the front-facing metal stack allows for free-floating cell placement within the block without power supply complications or placement-related delay variation.

[0024] For comparison, illustrated Fig. 1 Cross-sectional views of an intermediate stack with a front-side power supply and an intermediate stack with a rear-side power supply according to an embodiment of the present disclosure.

[0025] With reference to Fig. 1 includes an intermediate interconnect stack 100 with front-side power delivery, a transistor 102, and a signal and power supply metallization 104. The transistor 102 includes a bulk substrate 106, semiconductor fins 108, a terminal 110, and a device contact 112. The signal and power supply metallization 104 includes conductive vias 114, conductive traces 116, and a metal contact mound 118.

[0026] With further reference to Fig. Assembly 1 comprises a rear-side power supply interconnect stack 150, a transistor 152, a front-side signal metallization 154A, and a power supply metallization 154B. The transistor 152 includes semiconductor nanowires or nanotapes 158, a terminal 160, a device contact 162, and a deep via bar 163. The front-side signal metallization 154A includes conductive vias 164A and conductive traces 166A. The power supply metallization 154B includes conductive vias 164B, conductive traces 166B, and a metal contact mound 168.

[0027] To provide further context, one of the ultimate goals in standard cell design is to minimize the area-based impact of the power supply on signal routing while maintaining a robust power scheme that would exhibit minimal voltage drop from the supply. With front-side power, commercially available standard cell architectures had to allocate routing paths for power and ground from the top of the front stack to the first metal routing layer, M0. This approach would utilize metal routing paths. This means that tighter metal grid dimensions are required to deliver power while simultaneously routing signals. Tighter metal grid dimensions result in higher capacitance and resistance, leading to increased power consumption.Furthermore, due to the resistance, a larger voltage drop occurs from the top of the stack to the source of the transistor.

[0028] Deep Via Bar (DVB) power delivery allows power to be supplied from the rear without requiring the allocation of traces in the metal routing traces on the front. However, this technology requires space between the NMOS and PMOS devices across the cell boundary to deliver power to the front-facing diffusion contact for standard cells. In DVB technology, power is supplied from the rear through the space between n-diffusions and p-diffusions.

[0029] As an exemplary structure illustrated Fig. 2 an angled cross-sectional view of an integrated circuit structure with a deep via-bar (DVB) architecture according to an embodiment of the present disclosure.

[0030] With reference to Fig. Figure 2 comprises an integrated circuit structure 200 gate lines 202, N-source or N-drain structures 204A, P-source or N-drain structures 204B, deep via bars (DVBs) 206, front-side local interconnects 208, and back-side metal routing layers 210 (BM0 layers). A PP difference spacing and an NN difference spacing are shown to accommodate intervening deep via bars (DVBs) 206. The gate lines 202 are located above channel structures, such as nanowire-based, nanoribbon-based, nanosheet-based, or fin-based channel structures. Locations where gate lines 202 are cut also accommodate the deep via bars (DVBs) 206.

[0031] Although depicted as continuous deep via bars 206, in one embodiment one or more cuts can be made in one of the deep via bars 206 at locations where connectivity is to be removed. Using a prior art deep via bar technology, the deep via bar 206 is cut at locations where gate lines 202 have been cut. A deep via bar cut dielectric plug is formed at the cut points. As an example, this is illustrated Fig. 3 A front-up top view of an integrated circuit structure incorporating a deep via-bar cut at a point of an existing gate-cut, which may be referred to as a gate-cut prior to a deep via-bar cut approach.

[0032] With reference to Fig. Figure 3 includes an integrated circuit structure 300 and a plurality of gate lines 302, all of which have the same section spacing 304. The deep via-bar sections 306A and 306B are separated by a deep via-bar section 310. Optionally, the deep via-bar 306A is shown with column sections 308, as contained in a recessed deep via-bar, which is shown below in conjunction with Fig. As described in Figure 5, the gate lines 302 and the deep via-bar sections 306A and 306B are shown relative to the backside metallization 312A and 312B as BM0 lines. A dielectric plug is ultimately formed in the deep via-bar interface 310. However, the dielectric plug can be difficult to fabricate because all the gate lines 302 were cut at a relatively large spacing 304, e.g., about 30 nm, before the cut between the deep via-bar sections 306A and 306B was made.

[0033] As opposed to Fig. 3 shows Fig. 4. A front-view plan of an integrated circuit structure with a gate cut at an existing location of a deep via-bar cut, which may be referred to as a gate cut following the deep via-bar cut approach, according to an embodiment of the present disclosure. It is understood that, according to an embodiment of the present disclosure, such a gate cut following the deep via-bar approach is made during the fabrication of the integrated circuit structure 200 from Fig. 2 can be used.

[0034] With reference to Fig. Figure 4 includes an integrated circuit structure 400 and a plurality of gate lines 402, the first of which, 402A, have a larger cut spacing than the second, 402B. The deep via-bar sections 406A and 406B are separated by a deep via-bar section 410. Optionally, the deep via-bar 406A is shown with column sections 408, as contained in a recessed deep via-bar, which is shown below in conjunction with Fig. 5 is described. In this case, unlike... Fig. 3 The deep via-bar cut 410 is formed before the formation of cuts 404 in the gate lines 402B. The gate lines 402 and the deep via-bar portions 406A and 406B are shown relative to the backside metallization 412A and 412B, as BM0 lines. A dielectric plug is ultimately formed in the deep via-bar interface 410. However, a gate-cut plug can be fabricated to plug both the deep via-bar cut 410 and the cut spacing 404, e.g., about 14 nm, for the second of the gate lines 402B, which can reduce processing costs.

[0035] In another aspect, the implementation of a metal gate-cutting process according to an embodiment of the present disclosure enables a self-aligning fabrication scheme for the DVB, wherein the DVB and gate-end distance is defined by a conformal lining instead of a resist-defined rim, resulting in a significantly reduced DVB-gate-end distance without compromising reliability. Regarding the reset, even if the DVB can be fabricated closer to the gate end using a self-aligning scheme, further incrementing the drive below a certain distance does not overcome the performance-related capacity deficit caused by the coupling between the gate and the DVB.In one embodiment, resetting the DVB in the areas aligned with the gate ends reduces the capacitance, which in turn allows for a reduction in the lining thickness, resulting in cell scaling by either increasing the active transistor area or decreasing the cell height.

[0036] To provide further context, the current deep via bar (DVB) process boundary opposite the gate end is undefined. It is a wall of a via that extends upwards from the back-side metal layer BM0. Currently, the distance between the DVB and the gate ends is resist-defined. Consequently, with an edge placement error, the DVB may end up being closer to the gate ends than nominally intended. Therefore, the distance between the DVB and the gate ends must be set to a distance that takes into account the clearance required to avoid insulator breakdown and edge placement errors, which would result in a larger than desired cell height, or in other words, a loss of area.Since the DVB is a continuous wall of a via, it is coupled to multiple ends and drain diffusion regions of transistors, resulting in a higher than desired capacitance and limiting scaling in terms of performance at the cell level.

[0037] According to one or more embodiments of the present disclosure, a process flow is used which enables self-alignment of a DVB edge to poly edges and a reset of the bulk via that is not connected to the source.

[0038] Advantages of implementing one or more of the embodiments described herein may include one or more of (1) self-alignment with the gate edges and a reset of the DVB activation area and performance scaling of the technology, (2) enabling on the order of a 40% reduction of the DVB gate end distance, which can be used either for cell height reduction and / or performance improvement, 3) self-alignment of the DVB can be captured by a distinct material change around the deep via bar at a uniform thickness.

[0039] A recessed DVB cable can have full thickness in some locations and be recessed in others. This illustrates an exemplary architecture. Fig. 5 An angled cross-sectional view of an integrated circuit structure 500 with a recessed deep via-bar (DVB) architecture according to an embodiment of the present disclosure. It is understood that according to an embodiment of the present disclosure, a gate cut following a deep via-bar cut approach, as described above in conjunction with Fig. 4 described, which can be used in the manufacturing of the integrated circuit structure 500.

[0040] With reference to Fig. 5 includes an integrated circuit structure 500, gate lines 502, N-source or -drain structures 504A, P-source or -drain structures 504B, the recessed deep via bar (DVB) structure 506 / 506A, local front-side interconnects 508, and back-side metal guide layers 510 (BM0 layers). In one embodiment, the recessed deep via bars (DVBs) are formed using a self-aligning process scheme. The gate lines 502 are located above channel structures, such as nanowire-based, nanoribbon-based, or nanosheet-based channel structures, or fin-based channel structures. Locations where gate lines 502 are cut also accommodate the recessed deep via bar (DVB) structure 506 / 506A.

[0041] Again with reference to Fig. 5 includes an integrated circuit structure 500 according to one or more embodiments of the present disclosure, comprising a plurality of gate lines 502. In one embodiment, the plurality of gate lines 502 extends over a plurality of semiconductor nanowire stack channel structures (which may also refer to nanoribbon structures or nanoplatform structures). In another embodiment, the plurality of gate lines 502 extends over a plurality of semiconductor fin structures.

[0042] The integrated circuit structure 500 also includes a plurality of trench contacts 508 extending over a plurality of source or drain structures 504A / 504B, with individual of the plurality of trench contacts 508 alternating with individual of the plurality of gate lines 502. A rear metal routing layer 510 extends below one or more of the plurality of gate lines 502 and below one or more of the plurality of trench contacts 508. A conductive structure 506 / 506A couples the rear metal routing layer 510 to one of the one or more of the plurality of trench contacts 508. The conductive structure 506 / 506A includes a column part 506A in contact with one of the one or more of the plurality of trench contacts 508, the column part 506A on a line part 506, the line part 506 being in contact with and extending along the rear metal routing layer 510.

[0043] In one embodiment, the rear metal routing layer 510 is a rear power supply line. In another embodiment, the conductive structure 506A / 506 is a recessed deep via-bar structure.

[0044] In one embodiment, the column portion 506A of the conductive structure 506 / 506A extends between a pair of N-source or -drain structures 504A of a plurality of source or drain structures 504A / 504B, as shown for the conductive structure 506 / 506A on the right. In another embodiment, the column portion 506A of the conductive structure 506 / 506A extends between a pair of P-source or -drain structures 504B of a plurality of source or drain structures 504A / 504B.

[0045] To illustrate as an exemplary processing scheme Fig. 6 to 8 angled cross-sectional views showing different operations in a method for fabricating an integrated circuit structure with a recessed deep via-bar (DVB) architecture, according to an embodiment of the present disclosure. Fig. Figure 9 illustrates an angled cross-sectional view and a planar cross-sectional view of an integrated circuit structure 900 with a recessed deep via-bar (DVB) architecture according to an embodiment of the present disclosure. It is understood that, according to an embodiment of the present disclosure, a gate cut is made following a deep via-bar cut approach, as described above in conjunction with Fig. 4 described, which can be used in the manufacturing of the Integrated Circuit Structure 900.

[0046] With reference to Fig. Figure 6 includes a starter structure 600 and a plurality of fins or subfins 604 on a substrate 602. The fins may be for FinFET devices or may be subfins beneath a stack of nanowires. Several gate lines 606 (each containing, for example, a metal gate and a high-k-gate dielectric) are located above the multiple fins or subfins 604. An insulating cap 608 is located on the multiple gate lines 606. Epitaxial source or drain structures 610 alternate with the multiple gate lines 606. Dielectric gate-cut plugs 612 may cut some of the plurality of gate lines 606. A trench 614 is etched at a location where a recessed deep via bar is to be formed.

[0047] With reference to Fig. 7 a protective helmet layer 618 on the structure 600 of Fig. 6. A conductive fill material 616 is formed in trench 614. Structure 600 can effectively be considered an unrecessed deep via-bar.

[0048] With reference to Fig. 8 The conductive filler material 616 is recessed at selected locations to provide a recessed deep via-bar structure 616A with intersecting dielectric plug parts 620.

[0049] With reference to Fig. A structure 900 resulting from the above process may include multiple fins or subfins 904 on a substrate 902. The fins may be for FinFET devices or subfins beneath a stack of nanowires. Multiple gate lines 906 (each including, for example, a metal gate and a high-k-gate dielectric) are located above the multiple fins or subfins 904. An insulating cap 908 is located on the multiple gate lines 906. Epitaxial source or drain structures 910 alternate with the multiple gate lines 906. The structure includes a recessed deep via-bar structure 916A with intersecting dielectric plug portions 920. Trench contact structures 930 and trench contact plugs 932 may also be included. From the perspective on the right, the lower conduit section 916B of the recessed deep via-bar structure 916A is visible.In one embodiment, the deep via-bar structure 916A or busbar is self-aligned at the gate / S / D, which is intersected by a dielectric lining. In one embodiment, the metal within the busbar is recessed everywhere except for a connection with the above metal layer / contact.

[0050] Another aspect describes COAG (Contact over Active Gate) structures and processes, e.g., structures that can further enable the compaction of a cell architecture incorporating deep via-bar isolation. One or more embodiments of the present disclosure relate to semiconductor structures or devices with one or more gate contact structures (e.g., as gate-contact vias) arranged over active parts of gate electrodes of the semiconductor structures or devices. One or more embodiments of the present disclosure relate to methods for fabricating semiconductor structures or devices with one or more gate contact structures formed over active parts of gate electrodes of the semiconductor structures or devices.The approaches described here can be used to reduce the standard cell area by enabling gate contact formation over active gate regions. According to one or more embodiments, tapered gate and trench contacts are implemented to enable COAG fabrication. Embodiments can be implemented to allow structuring with tight grid dimensions.

[0051] To provide further context for the importance of a COAG processing scheme, in technologies where space and layout constraints are somewhat less stringent compared to current generations, contact with a gate structure can be established by making contact with a portion of the gate electrode positioned above an isolation region. As an example, this is illustrated... Fig. Figure 10A shows a top view of a semiconductor device with a gate contact positioned over a non-active part of a gate electrode.

[0052] With reference to Fig. 10A comprises a semiconductor structure or device 1000A, a diffusion or active region 1004, which is located in a substrate 1002 and within an isolation region 1006. One or more gate lines (also known as poly lines), such as gate lines 1008A, 1008B, and 1008C, are located over the diffusion or active region 1004 and over a portion of the isolation region 1006. Source or drain contacts (also known as trench contacts), such as contacts 1010A and 1010B, are located over source and drain regions of the semiconductor structure or device 1000A. Trench contact vias 1012A and 1012B provide contact to trench contacts 1010A and 1010B, respectively. A separate gate contact 1014, and an overlying gate contact via 1016, provides a contact to the gate line 1008B.Unlike the source or drain contacts 1010A or 1010B, the gate contact 1014 is located above the isolation region 1006 in a top-down perspective, but not above the diffusion or active region 1004. Furthermore, neither the gate contact 1014 nor the gate contact via 1016 is located between the source or drain trench contacts 1010A and 1010B.

[0053] Fig. Figure 10B illustrates a cross-sectional view of a non-planar semiconductor device with a gate contact positioned over a non-active portion of a gate electrode. With reference to Fig. 10B includes a semiconductor structure or device 1000B, e.g. a non-planar version of the device 1000A made of Fig. 10A, a non-planar diffusion or active region 1004B (e.g., a fin structure) formed by the substrate 1002 and within the isolation region 1006. The gate line 1008B is arranged over the non-planar diffusion or active region 1004B and over part of the isolation region 1006. As shown, the gate line 1008B includes a gate electrode 1050 and a gate dielectric layer 1052 together with a dielectric cap layer 1054. The gate contact 1014 and the overlying gate contact via 1016 are also seen from this perspective, along with an overlying metal intermediate 1060, all arranged in interlayer dielectric stacks or layers 1070. This is also shown from the perspective of Fig. 10B is the gate contact 1014 located above the isolation area 1006, but not above the non-planar diffusion or active area 1004B.

[0054] Again with reference to Fig. 10A and Fig. In semiconductor structure or device 1000A or 1000B, the gate contact is placed over the isolation regions. Such an arrangement wastes layout space. However, placing the gate contact over active regions would either require an extremely tight coverage accuracy budget or would necessitate an increase in gate dimensions to provide sufficient space for the gate contact. Furthermore, historically, contacting a gate over diffusion regions has been avoided due to the risk of drilling through other gate material (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described here address the above problems by providing feasible approaches and the resulting structures for fabricating contact structures that contact portions of a gate electrode formed over a diffusion or active region.

[0055] As an example, it illustrates Fig. 11A A top view of a semiconductor device with a gate contact via arranged over an active part of a gate electrode, according to an embodiment of the present disclosure. With reference to Fig. 11A comprises a semiconductor structure or device 1100A, a diffusion or active region 1104, which is located in a substrate 1102 and within an isolation region 1106. One or more gate lines, such as gate lines 1108A, 1108B, and 1108C, are located over the diffusion or active region 1104 and over a portion of the isolation region 1106. Source or drain contacts, such as contacts 1110A and 1110B, are located over source and drain regions of the semiconductor structure or device 1100A. Trench contact vias 1112A and 1112B provide contact to trench contacts 1110A and 1110B, respectively. A gate contact via 1116 without an intervening separate gate contact layer provides contact to gate line 1108B. In contrast to Fig. 10A is the gate contact 1116 located above the diffusion or active area 1104 and between the source or drain contacts 1110A and 1110B from a top-down perspective.

[0056] Fig. Figure 11B illustrates a cross-sectional view of a non-planar semiconductor device with a gate contact via arranged over an active part of a gate electrode, according to an embodiment of the present disclosure. With reference to Fig. 11B includes a semiconductor structure or device 1100B, e.g. a non-planar version of the device 1100A made of Fig. 11A, a non-planar diffusion or active region 1104B (e.g., a fin structure) formed by the substrate 1102 and within the isolation region 1106. The gate line 1108B is arranged over the non-planar diffusion or active region 1104B and over part of the isolation region 1106. As shown, the gate line 1108B includes a gate electrode 1150 and a gate dielectric layer 1152 together with a dielectric cap layer 1154. The gate contact via 1116 is also seen from this perspective together with an overlying metal interlayer 1160, both arranged in interlayer dielectric stacks or layers 1170. Also when viewed from the perspective of Fig. 11B is located on Gate Via 1116 above the non-planar diffusion or active area 1104B.

[0057] Accordingly, with reference to Fig. 11A and Fig. In one embodiment, the trench contact vias 1112A, 1112B and the gate contact viae 1116 are formed in the same layer and are essentially coplanar. In comparison to Fig. 10A and Fig. 10B would otherwise include the contact to the gate line and an additional gate contact layer, which could, for example, run perpendicular to the corresponding gate line. In the case of the (the) in association with Fig. 11A and Fig. However, the structure(s) described in 11B enable the fabrication of structures 1100A and 1100B, respectively, to arrange a contact directly from a metal interleaved layer onto an active gate portion without short-circuiting to adjacent source-drain regions. In one embodiment, such an arrangement provides a significant area reduction in a circuit layout by eliminating the need for transistor gates to extend onto insulation to form a reliable contact. As used throughout, in one embodiment, a reference to an active portion of a gate refers to that part of a gate trace or structure that is located (from a top-down perspective) over an active or diffusion region of an underlying substrate.In one embodiment, a reference to an inactive part of a gate refers to that part of a gate line or structure which (from a top-down perspective) is arranged above an isolation area of ​​an underlying substrate.

[0058] In one embodiment, the semiconductor structure or device 1100 is a non-planar device, such as, among others, a FinFET or Tri-Gate device. In such an embodiment, a corresponding semiconducting channel region consists of or is formed within a three-dimensional body. In such an embodiment, the gate electrode stacks of the gate lines 1108A and 1108B surround at least one upper surface and a pair of side walls of the three-dimensional body. In another embodiment, at least the channel region is manufactured such that it is a discrete three-dimensional body, as in a gate all-around device. In such an embodiment, the gate electrode stacks of the gate lines 1108A and 1108B each completely surround the channel region.

[0059] In general, one or more embodiments relate to approaches for, and structures formed from, placing a gate-contact via directly on an active transistor gate. Such approaches can eliminate the need to extend a gate line on insulation for contact purposes. Such approaches can also eliminate the need for a separate gate contact (GCN) layer to conduct signals from a gate line or structure. In one embodiment, the elimination of the above features is achieved by recessing contact metals in a trench contact (TCN) and introducing an additional dielectric material in the process flow (e.g., a trench insulation layer (TILA)).The additional dielectric material is included as a trench contact dielectric cap layer with different etching characteristics than the gate dielectric material cap layer used for trench contact alignment in a GAP processing scheme (GAP: Gate Aligned Contact Process - Gate-aligned contact process) (e.g. using a gate insulating layer (GILA)).

[0060] As an exemplary fabrication scheme, a starter structure comprises one or more gate stack structures arranged above a substrate. The gate stack structures may include a gate dielectric layer and a gate electrode. Trench contacts, e.g., contacts to diffusion regions of the substrate or to an epitaxial region formed within the substrate, are spaced apart from the gate stack structures by dielectric spacers. An insulating cap layer may be placed on the gate stack structures (e.g., GILA). In one embodiment, contact-blocking regions or "contact plugs," which may be made of an interlayer dielectric material, are included in areas where contact formation is to be blocked.

[0061] In one embodiment, the contact structuring is essentially perfectly aligned with an existing gate structuring, while eliminating the need for a lithographic process with an extremely tight coverage accuracy budget. In such an embodiment, this approach allows the use of an intrinsically highly selective wet etching (or anisotropic dry etching processes, some of which are non-plasma, gas-phase isotropic etchings (e.g., as opposed to classical dry or plasma etching) to create contact openings. In another embodiment, a contact structure is formed by utilizing an existing gate structure in combination with a contact-plug lithography process. In such an embodiment, the approach eliminates the need for an otherwise critical lithography process to generate a contact structuring, as used in other approaches.This also enables perfect or near-perfect self-alignment with a larger margin of error for edge placement. In one embodiment, a trench contact grid is not structured separately, but instead formed between poly(gate) lines. For example, in such an embodiment, a trench contact grid is formed after the gate grid structuring, but before gate grid cuts.

[0062] Furthermore, the gate stack structures can be fabricated using a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride column material, can be removed and replaced with a permanent gate electrode material. In this embodiment, a permanent gate dielectric layer is also formed in this process, rather than being carried over from a previous processing step. In one embodiment, dummy gates are removed by a dry or wet etching process. In one embodiment, dummy gates consist of polycrystalline silicon or amorphous silicon and are removed by a dry etching process including SF6. In another embodiment, dummy gates consist of polycrystalline silicon or amorphous silicon and are removed by a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide.In one embodiment, dummy gates consist of silicon nitride and are removed by wet etching including aqueous phosphoric acid.

[0063] In one embodiment, one or more of the approaches described here essentially provide a dummy or substitute gate process in combination with a dummy and substitute contact process. In such an embodiment, the substitute contact process is carried out after the substitute gate process to enable high-temperature annealing of at least a portion of the permanent gate stack. For example, in a particular embodiment, annealing of at least a portion of the permanent gate structures is carried out at a temperature higher than approximately 600 degrees Celsius, e.g., after a gate dielectric layer has been formed. The annealing is performed before the formation of the permanent contacts.

[0064] Next, the trench contacts can be reset to provide recessed trench contacts that have a height below the upper surface of adjacent spacers. An insulating cap layer is then formed on the recessed trench contacts (e.g., TILA). According to one embodiment of the present disclosure, the insulating cap layer on the recessed trench contacts consists of a material with a different etching characteristic than the insulating cap layer on the gate stack structures.

[0065] The trench contacts can be selectively reset relative to the spacer and gate insulation cap materials by a process. For example, in one embodiment, the trench contacts are reset by an etching process, such as a wet or dry etching process. The trench contact insulation cap layer can be formed by a process suitable for providing a conformal and sealing layer above the exposed portions of the trench contacts. For example, in one embodiment, the trench contact insulation cap layer is formed as a conformal layer above the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, for example, by chemical-mechanical polishing (CMP), to provide the trench contact insulation cap layer material only above the reset trench contacts.

[0066] Regarding suitable material combinations for gate-to-trench contact insulating cap layers, in one embodiment, one of the pair of gate-to-trench contact insulating cap materials consists of silicon oxide, while the other consists of silicon nitride. In another embodiment, one of the pair of gate-to-trench contact insulating cap materials consists of silicon oxide, while the other consists of carbon-doped silicon nitride. In another embodiment, one of the pair of gate-to-trench contact insulating cap materials consists of silicon oxide, while the other consists of silicon carbide. In yet another embodiment, one of the pair of gate-to-trench contact insulating cap materials consists of silicon nitride, while the other consists of carbon-doped silicon nitride.In another embodiment, one of the pair of gate-versus-trench contact insulating cap materials consists of silicon nitride, while the other consists of silicon carbide. In another embodiment, one of the pair of gate-versus-trench contact insulating cap materials consists of carbon-doped silicon nitride, while the other consists of silicon carbide.

[0067] Another aspect describes nanowire or nanoribbon structures. Nanowire or nanoribbon exposure processing can be performed via a substitute gate trench. Examples of such exposure processes are described below. Furthermore, another aspect concerns backend (BE) interconnect scaling, which can lead to lower performance and higher fabrication costs due to structuring complexity. The embodiments described herein can be implemented to enable front- and back-end interconnect integration for nanowire transistors. These embodiments can provide an approach to achieving a relatively wider interconnect grid size. The result can be improved product performance and lower structuring costs.Implementation models can be developed to enable robust functionality of scaled low-power, high-performance nanowire or nanoband transistors.

[0068] One or more embodiments described herein relate to dual epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In one embodiment, an integrated circuit structure is fabricated by forming source-drain openings of nanowire / nanoribbon transistors that are partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trenching on either the source or drain side allows direct contact with a backside intermediate connection plane.

[0069] To illustrate an exemplary process flow for manufacturing another gate all-around device Fig. 12A to 12J Cross-sectional views of various processes in a method for manufacturing a gate all-around structure of an integrated circuit according to an embodiment of the present disclosure.

[0070] With reference to Fig. Document 12A includes a method for fabricating an integrated circuit structure by forming a starter stack comprising alternating sacrificial layers 1204 and nanowires 1206 above a fin 1202, such as a silicon fin. The nanowires 1206 can be described as a vertical array of nanowires. A protective cap 1208 can be formed above the alternating sacrificial layers 1204 and nanowires 1206, as shown. A relaxed buffer layer 1252 and a defect modification layer 1250 can be formed below the alternating sacrificial layers 1204 and nanowires 1206, as also shown.

[0071] With reference to Fig. In 12B, a gate stack 1210 is formed above the vertical array of horizontal nanowires 1206. Portions of the vertical array of horizontal nanowires 1206 are then released by removing portions of the sacrificial layers 1204 to provide recessed sacrificial layers 1204' and cavities 1212, as shown in Fig. 12C is shown.

[0072] It goes without saying that the structure consists of Fig. 12C can be completely manufactured without first performing the deep etching and asymmetric contact processing described below. In both cases (e.g., with or without asymmetric contact processing), a manufacturing process in one embodiment involves the use of a process scheme that provides a gate-all-around structure of an integrated circuit with epitaxial studs, which can be vertically discrete source or drain structures.

[0073] With reference to Fig. In step 12D, upper gate spacers 1214 are formed on the side walls of the gate structure 1210. Cavity spacers 1216 are formed in the cavities 1212 below the upper gate spacers 1214. Deep trench contact etching is then optionally performed to form trenches 1218 and recessed nanowires 1206'. A structured relaxed buffer layer 1252' and a structured defect modification layer 1250' may also be present, as shown.

[0074] A sacrificial material from 1220 was then formed in the ditches in 1218, as in Fig. Figure 12E is shown. In other process schemes, an isolated trench bottom or silicon trench bottom may be used.

[0075] With reference to Fig. In 12F, a first epitaxial source or drain structure (e.g., left features 1222) is formed at a first end of the vertical array of horizontal nanowires 1206'. A second epitaxial source or drain structure (e.g., right features 1222) is formed at a second end of the vertical array of horizontal nanowires 1206'. In one embodiment, the epitaxial source or drain structures 1222, as shown, are vertically discrete source or drain structures and can be referred to as epitaxial studs.

[0076] An interlayer dielectric (ILD) material 1224 is then formed on the sides of the gate electrode 1210 and adjacent to the source or drain structures 1222, as shown in Fig. 12G is shown. With reference to Fig. In 12H, a replacement gate process is used to form a permanent gate dielectric 1228 and a permanent gate electrode 1226. The ILD material 1224 is then removed, as shown in Fig. 12I is shown. The sacrificial material 1220 is then removed from one of the source-drain points (e.g., on the right) to form trench 1232, but is not removed from the other of the source-drain points to form trench 1230.

[0077] With reference to Fig. In 12J, a first conductive contact structure 1234 is formed, which is coupled to the first epitaxial source or drain structure (e.g., the features 1222 on the left side). A second conductive contact structure 1236 is formed, which is coupled to the second epitaxial source or drain structure (e.g., features 1222 on the right side). The second conductive contact structure 1236 is formed deeper along the fin 1202 than the first conductive contact structure 1234. In one embodiment, the method, although this is in Fig. 12J is not shown, furthermore forming an exposed surface of the second conductive contact structure 1236 on a bottom side of the fin 1202. Conductive contacts can include a contact resistance reduction layer and a primary contact electrode layer, with examples including Ti, Ni, Co (for the former and W, Ru, Co for the latter).

[0078] In one embodiment, the second conductive contact structure 1236 is located deeper along the fin 1202 than the first conductive contact structure 1234, as shown. In another embodiment, the first conductive contact structure 1234 is not located along the fin 1202, as shown. In yet another embodiment, not shown, the first conductive contact structure 1234 is located partially along the fin 1202.

[0079] In one embodiment, the second conductive contact structure 1236 is located along an entirety of the fin 1202. In another embodiment, the second conductive contact structure 1236, although not shown, has an exposed surface on the underside of the fin 1202 when the underside is exposed by a backside substrate removal process.

[0080] Another aspect is that the integrated circuit structures described herein can be fabricated using a backside exposure approach for frontside fabrication, providing access to both conductive contact structures of a pair of asymmetric source and drain contact structures. In some embodiments, backside exposure of a transistor or other device structure involves backside processing at the wafer level. Unlike conventional TSV-type technology, backside exposure of a transistor as described here can be performed at the device cell density and even within subregions of a device.Furthermore, such backside exposure of a transistor can be performed to essentially remove the entire donor substrate on which a device layer was placed during frontside device processing. Therefore, micrometer-deep TSV becomes unnecessary, with the thickness of a semiconductor in the device cells following backside exposure of a transistor potentially being only a few tens or hundreds of nanometers.

[0081] The disclosure techniques described herein can enable a paradigm shift from bottom-up fixture fabrication to center-out fabrication, where "center" is any layer used in front-side fabrication, exposed from the back, and reused in back-side fabrication. Processing both a front and an exposed back of a fixture structure can address many of the challenges associated with 3D IC fabrication when relying primarily on front-side processing.

[0082] Exposing the back side of a transistor deposition can be used, for example, to remove at least a portion of a support layer and intermediate layer of a donor-host substrate assembly. The process flow begins with the input of a donor-host substrate assembly. A thickness of the support layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the support layer can be employed. For example, if the support layer is a group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor can be used. Likewise, any wet etching or plasma etching process known to be suitable for thinning the group IV semiconductor can be employed.

[0083] In some embodiments, the foregoing is preceded by splitting the support layer along a fracture plane substantially parallel to the intervening layer. The splitting or fracture process can be used to remove a substantial portion of the support layer as a bulk mass, thereby reducing the polishing or etching time required to remove the support layer. For example, if a support layer has a thickness of 400–900 µm, 100–700 µm can be cleaved off by applying any area-wide implantation known to promote at-wafer-level fracture. In some embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the support layer where the fracture plane is desired.Following such a cleavage process, the remaining thickness of the carrier layer in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, if the carrier layer is not cleaved, the grinding, polishing, and / or etching process can be used to remove a greater thickness of the carrier layer.

[0084] Next, the exposure of an intermediate layer is detected. Detection is used to identify a point where the back surface of the donor substrate has almost reached the device layer. It is known that any endpoint detection technique suitable for detecting a transition between the materials used for the support layer and the intermediate layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting a change in the optical absorption coefficient or the emission of the back surface of the donor substrate during polishing or etching. In some other embodiments, the endpoint criteria are associated with a change in the optical absorption coefficient or the emission of byproducts during polishing or etching of the donor substrate back surface.For example, the absorption coefficient or emission wavelengths associated with the byproducts of substrate etching can change as a function of the different compositions of the substrate and the interlayer. In other embodiments, the endpoint criteria are associated with a change in the mass of species in byproducts of polishing or etching the back surface of the donor substrate. For example, the processing byproducts can be sampled by a quadrupole mass analyzer, and a change in species mass can be correlated with the different compositions of the substrate and the interlayer. In another embodiment, the endpoint criteria are associated with a change in friction between a back surface of the donor substrate and a polishing surface in contact with the back surface of the donor substrate.

[0085] Detection of the interlayer can be improved if the removal process is selective with respect to the substrate relative to the interlayer, as any non-uniformity of the substrate removal process can be mitigated by an etch rate delta between the substrate and the interlayer. Detection can even be skipped if the grinding, polishing, and / or etching process removes the interlayer at a rate sufficiently lower than the rate at which the substrate is removed. If no endpoint criterion is used, a grinding, polishing, and / or etching process of a predetermined fixed duration can stop on the interlayer material if the thickness of the interlayer is sufficient for etch selectivity. In some examples, the ratio of substrate etch rate to interlayer etch rate is 3:1 to 10:1 or greater.

[0086] When exposing the interlayer, at least a portion of the interlayer can be removed. For example, one or more component layers of the interlayer can be removed. A thickness of the interlayer can be removed uniformly by polishing. Alternatively, a thickness of the interlayer can be removed using a masked or full-surface etching process. The process can employ the same polishing or etching process as that used to thin the substrate, or it can be a distinct process with distinct process parameters. For example, if the interlayer provides an etch stop for the carrier removal process, the latter can employ a different polishing or etching process that promotes removal of the interlayer by removing the fixture layer.When less than a few hundred nanometers of an intermediate layer thickness needs to be removed, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than the process used to remove the support layer. For example, a CMP process might employ a slurry that offers very high selectivity (e.g., 100:1–300:1 or more) between the semiconductor (e.g., silicon) and a dielectric material (e.g., SiO₂) surrounding the device layer and embedded within the intermediate layer, for example, as electrical insulation between adjacent device areas.

[0087] For embodiments in which the fixture layer is exposed by complete removal of the intervening layer, backside processing can begin on an exposed backside of the fixture layer or on specific fixture regions there. In some embodiments, backside fixture layer processing involves further polishing or wet / dry etching through a thickness of the fixture layer located between the intervening layer and a fixture region previously fabricated in the fixture layer, such as a source or drain region.

[0088] In some embodiments where the substrate, interlayer, or device backside is reset by wet and / or plasma etching, such etching may be a structured etch or a materially selective etch, providing significant non-planarity or topography to the device backside surface. As described below, the structuring may be within a device cell (i.e., “intracell structuring”) or may extend across device cells (i.e., “intercell structuring”). In some embodiments with structured etching, at least a partial thickness of the interlayer is used as a hard mask for backside device backside structuring. Therefore, a masked etching process may precede a correspondingly masked device backside etching.

[0089] The processing scheme described above can result in a donor-host substrate assembly containing IC devices that have a backside of an intermediate layer, a backside of the device layer, and / or a backside of one or more semiconductor regions within the device layer, and / or exposed frontside metallization. Additional backside processing of any of these exposed regions can then be performed during downstream processing.

[0090] As described throughout the present application, a substrate may consist of a semiconductor material that can withstand a fabrication process and in which charge can migrate. In one embodiment, a substrate described herein is a bulk substrate consisting of a crystalline silicon, silicon / germanium, or germanium layer doped with a charge carrier, such as unrestricted phosphorus, arsenic, boron, or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, a bulk substrate consists of an epitaxial layer grown on a distinct crystalline substrate, e.g., an epitaxial silicon layer grown on a boron-doped monocrystalline bulk silicon substrate.Alternatively, a bulk substrate can consist of a group III-V material. In one embodiment, a bulk substrate consists of a group III-V material such as, among others, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In another embodiment, a bulk substrate consists of a group III-V material, and the charge carrier dopant atoms are such as, among others, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0091] As described throughout the present application, isolation regions, such as shallow trench isolation regions or subfin isolation regions, can consist of a material suitable for ultimately electrically isolating or contributing to the isolation of parts of a permanent gate structure from an underlying bulk substrate, or for isolating active regions formed in an underlying bulk substrate, such as the isolation of active fin regions. For example, in one embodiment, an isolation region consists of one or more layers of a dielectric material, such as, among others, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or a combination thereof.

[0092] As described throughout the present application, gate lines or gate structures can consist of a gate-electrode stack comprising a gate dielectric layer and a gate electrode layer. In one embodiment, the gate electrode of the gate-electrode stack is a metal gate, and the gate dielectric layer is a high-k material. For example, in one embodiment, the gate dielectric layer is a material such as, without limitation, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc cniobate, or a combination thereof. Furthermore, a portion of the gate dielectric layer can include a layer of native oxide formed from the upper few layers of a semiconductor substrate.In one embodiment, the gate dielectric consists of an upper high-k portion and a lower portion composed of an oxide of a semiconductor material. In another embodiment, the gate dielectric layer consists of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In some implementations, part of the gate dielectric is a U-shaped structure comprising a lower portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the substrate's upper surface.

[0093] In one embodiment, the gate electrode consists of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a particular embodiment, the gate electrode consists of a non-work function filler material formed above a work function metal layer. The gate electrode layer can consist of a p-type or an n-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer can consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive filler layer.For a PMOS transistor, metals that can be used for the gate electrode include ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. A p-type metal layer will allow the formation of a PMOS gate electrode with a work function between approximately 4.9 eV and approximately 5.2 eV. For an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will allow the formation of an NMOS gate electrode with a work function between approximately 3.9 eV and approximately 4.2 eV.In some implementations, the gate electrode can consist of a "U"-shaped structure comprising a lower part essentially parallel to the substrate surface and two sidewall parts essentially perpendicular to the substrate's upper surface. In another implementation, at least one of the metal layers forming the gate electrode can simply be a planar layer essentially parallel to the substrate's upper surface and lacking any sidewall parts essentially perpendicular to the substrate's upper surface. In further implementations of the disclosure, the gate electrode can consist of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode can consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0094] As described throughout the present application, spacers associated with gate leads or electrode stacks can consist of a material suitable for ultimately electrically isolating or contributing to the isolation of a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers consist of a dielectric material, such as, among others, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0095] In one embodiment, the interlayer dielectric (ILD) material, as used throughout this description, consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known from the prior art, and combinations thereof. The interlayer dielectric material can be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0096] In one embodiment, as used throughout this description, metal conductors or an interconnecting conductor material (and via material) consist of one or more metal structures or other conductive structures. A common example is the use of copper conductors and structures, which may or may not include barrier layers between the copper and the surrounding ILD material. As used herein, the term "metal" includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnecting conductors may include barrier layers (e.g., layers including Ta and / or TaN and / or Ti and / or TiN), stacks of different metals or alloys, etc. Accordingly, the interconnecting conductors may be a single layer of material or may be formed from several layers, including conductive lining layers and filler layers.Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form interconnects. In one embodiment, the interconnects consist of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. These interconnects are sometimes referred to in technical terms as conductors, wires, conductors, metal, or simply interconnects.

[0097] In one embodiment, the hard mask materials, as used throughout this description, consist of dielectric materials different from the interlayer dielectric material. In another embodiment, different hard mask materials can be used in different regions to provide varying growth or etch selectivity with respect to each other and to underlying dielectric and metal layers. In some embodiments, a hard mask layer comprises a layer of silicon nitride (e.g., silicon nitride), a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hard mask material may include a metal species.For example, a hard mask or overlying material may contain a layer of titanium nitride or another metal (e.g., titanium nitride). Potentially, smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, depending on the specific implementation, other hard mask layers known in the art may be used. The hard mask layers may be formed by CVD, PVD, or other deposition processes.

[0098] In one embodiment, as used throughout this description, lithographic processes are performed using 193 nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, electron beam direct write (EBDW) lithography, or the like. A positive or negative photoresist may be used. In one embodiment, a lithographic mask is a three-layer mask consisting of a topographic masking layer, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular embodiment, the topographic masking layer is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0099] In one embodiment, the approaches described herein may involve the formation of a contact structure that is highly aligned with an existing gate structure, while eliminating the need for a lithographic process with an extremely tight coverage accuracy budget. In such an embodiment, this approach enables the use of an intrinsically highly selective wet etching (e.g., compared to dry or plasma etching) to create contact openings. In another embodiment, a contact structure is formed by utilizing an existing gate structure in combination with a contact-plug lithography process. In such an embodiment, the approach eliminates the need for an otherwise critical lithography process to create a contact structure, as used in other approaches.In one embodiment, a trench contact grid is not structured separately, but is instead formed between poly(gate) lines. For example, in such an embodiment, a trench contact grid is formed after the gate grid structuring, but before gate grid cuts.

[0100] Furthermore, a gate stack structure can be fabricated using a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride column material, can be removed and replaced with a permanent gate electrode material. In this embodiment, a permanent gate dielectric layer is also formed in this process, rather than being carried over from a previous processing step. In one embodiment, dummy gates are removed by a dry or wet etching process. In one embodiment, dummy gates consist of polycrystalline silicon or amorphous silicon and are removed by a dry etching process, including the use of SF6. In another embodiment, dummy gates consist of polycrystalline silicon or amorphous silicon and are removed by a wet etching process, including the use of aqueous NH4OH or tetramethylammonium hydroxide.In one embodiment, dummy gates consist of silicon nitride and are removed by wet etching including aqueous phosphoric acid.

[0101] In one embodiment, one or more of the approaches described herein essentially provide a dummy or substitute gate process in combination with a dummy and substitute contact process to reach the structure. In such an embodiment, the substitute contact process is performed after the substitute gate process to enable high-temperature annealing of at least a portion of the permanent gate stack. For example, in a particular embodiment, annealing of at least a portion of the permanent gate structures is performed at a temperature higher than approximately 600 degrees Celsius, e.g., after a gate dielectric layer has been formed. The annealing is performed before the formation of the permanent contacts.

[0102] In some embodiments, the arrangement of a semiconductor structure or device places a gate contact over portions of a gate line or a gate stack over isolation regions. However, such an arrangement can be considered an inefficient use of layout space. In another embodiment, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region. In general, one or more embodiments of the present disclosure involve first using a gate-aligned trench contact process prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in the same layer as a trench contact via. Such a process can be implemented to form trench contact structures for semiconductor fabrication, e.g., for integrated circuit fabrication.In one embodiment, a trench contact structure is formed in alignment with an existing gate structure. In contrast, other approaches typically involve an additional lithography process with strict overlap accuracy of a lithographic contact structure with an existing gate structure in combination with selective non-contact etching. For example, another process may involve structuring a poly(gate) grid with separate structuring of contact features.

[0103] It is understood that grid spacing processing and structuring scenarios can be implemented to enable, or be included as part of, the embodiments described herein. Grid spacing structuring typically refers to grid spacing halving, grid spacing quartering, etc. Grid spacing schemes can be applicable to FEOL processing, BEOL processing, or both FEOL (fixture) and BEOL (metallization) processing. According to one or more of the embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., either strictly unidirectional or mostly unidirectional) at a predefined grid spacing. Grid spacing processing is then implemented as a technique to increase line density.

[0104] In one embodiment, the term "lattice structure" is used herein for fins, gate leads, metal leads, ILD leads, or hard mask leads to refer to a lattice structure with a narrow grid spacing. In such an embodiment, the narrow grid spacing is not directly achievable by a selected lithography. For example, a structure based on a selected lithography may first be formed, but the grid spacing can be halved by using spacer mask structuring, as is known in the art. Furthermore, the original grid spacing can be quartered by a second pass of spacer mask structuring. Accordingly, the lattice-like structures described herein can feature metal leads, ILD leads, or hard mask leads with a substantially uniform grid spacing and width.For example, in some embodiments the grid dimension variation would be within ten percent and the width variation would be within ten percent, and in other embodiments the grid dimension variation would be within five percent and the width variation would be within five percent. The structure can be manufactured using a grid dimension halving, grid dimension quartering, or another grid dimension division approach. In one embodiment, the grid does not necessarily have a single grid dimension.

[0105] In one embodiment, a cover film is patterned using lithography and etching, which may include, for example, spacer-based double patterning (SBDP) or screen division halving, or spacer-based quadruple patterning (SBQP) or screen division quartering. It is understood that other screen division approaches may also be implemented. In any case, in one embodiment, a grid-like layout may be produced by a selected lithography approach, such as 193 nm immersion lithography (193i). Screen division may be implemented to increase the density of lines in the grid-like layout by a factor of n. A grid-like layout created using 193i lithography plus screen division by a factor of 'n' may be referred to as 193i + P / n screen division.In such an embodiment, the 193 nm immersion scaling can be extended for many generations with cost-effective grid spacing.

[0106] It is also understood that not all aspects of the processes described herein need to be implemented to fall within the idea and scope of protection of embodiments of this disclosure. For example, in one embodiment, dummy gates need never be formed prior to the fabrication of gate contacts over active parts of the gate stack. The gate stacks described above can actually be permanent gate stacks, as initially formed. Furthermore, the processes described herein can be used to form one or more semiconductor devices. The semiconductor devices can be transistors or similar devices. For example, in one embodiment, the semiconductor devices are metal-oxide-semiconductor (MOS) transistors for logic or memory, or they are bipolar transistors.Furthermore, in one embodiment, the semiconductor devices have a three-dimensional architecture, such as a tri-gate device, a dual-gate device with independent access, a FIN-FET, a nanowire, or a nanoribbon. One or more embodiments can be particularly useful for fabricating semiconductor devices with a 10-nanometer (10 nm) technology node or a sub-10-nanometer (10 nm) technology node.

[0107] Additional or intermediate operations for FEOL layer or structure fabrication may include standard microelectronic manufacturing processes such as lithography, etching, thin-film deposition, planarization (such as chemical-mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, or any other associated action with microelectronic component fabrication. It is also understood that the process operations described for the preceding process flow may be implemented in alternative sequences, not every operation needs to be performed, additional process operations may be performed, or both.

[0108] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processing units (GPUs), digital signal processors (DSPs), microcontrollers, and the like. In other embodiments, semiconductor memory can be manufactured. Furthermore, the integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), mobile phones, personal electronic devices, etc. The integrated circuits can be coupled to a bus and other components in the systems. For example, a processor can be connected to a memory, a chipset, etc., via one or more buses.be coupled. Each of the processor, memory, and chipset can potentially be manufactured using the approaches revealed here.

[0109] Fig. Figure 13 illustrates a computing device 1300 according to one implementation of the disclosure. The computing device 1300 houses a circuit board 1302. The circuit board 1302 may contain, but is not limited to, a number of components, such as a processor 1304 and at least one communication chip 1306. The processor 1304 is physically and electrically coupled to the circuit board 1302. In some implementations, the at least one communication chip 1306 is also physically and electrically coupled to the circuit board 1302. In other implementations, the communication chip 1306 is part of the processor 1304.

[0110] Depending on its applications, the computing device 1300 may include other components that may not be physically and electrically coupled to the circuit board 1302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen control unit, a battery, an audio codec, a video codec, a power amplifier, a global positioning system device (GPS device), a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (such as a hard disk drive, a CD (Compact Disk), a DVD (Digital Versatile Disk), and so on).

[0111] The 1306 communication chip enables wireless communication for the transmission of data to and from the 1300 computing device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices contain no wires whatsoever, although in some embodiments they may not. The 1306 communication chip can implement any number of wireless standards or protocols, including, but not limited to, WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.11, and IEEE 802.11.The computing device 1300 can include multiple communication chips 1306. For example, a first communication chip 1306 can be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 1306 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0112] The processor 1304 of the computing device 1300 includes an integrated circuit die packaged within the processor 1304. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor comprises one or more structures, such as integrated circuit structures constructed according to implementations of the invention. The term "processor" can refer to any device or any part of a device that processes electronic data from registers or a memory to convert such electronic data, or both, into other electronic data that can be stored in registers or a memory.

[0113] The communication chip 1306 also includes an integrated circuit die encapsulated within the communication chip 1306. According to another implementation of the disclosure, the integrated circuit die of the communication chip is constructed according to implementations of the disclosure.

[0114] In further implementations, another component housed within the computing device 1300 may contain a die with an integrated circuit constructed according to implementations of embodiments of the disclosure.

[0115] In various embodiments, the Computing Device 1300 can be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultramobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, the Computing Device 1300 can be any other electronic device that processes data.

[0116] Fig. Figure 14 illustrates an interposer 1400 incorporating one or more embodiments of the disclosure. The interposer 1400 is an intermediate substrate used as a bridge from a first substrate 1402 to a second substrate 1404. The first substrate 1402 can be, for example, an integrated circuit die. The second substrate 1404 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. In general, the purpose of an interposer 1400 is to spread a connection to a wider grid dimension or to redirect a connection to another connection. For example, an interposer 1400 can couple an integrated circuit die to a ball grid array (BGA) 1406, which can then be coupled to the second substrate 1404. In some embodiments, the first and second substrates 1402 / 1404 are attached to opposite sides of the interposer 1400.In other embodiments, the first and second substrates 1402 / 1404 are attached to the same side of the interposer 1400. In further embodiments, three or more substrates are connected to each other by means of the interposer 1400.

[0117] The Interposer 1400 can be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the Interposer 1400 can be formed from alternating rigid or flexible materials, which may include the same materials previously described for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.

[0118] The Interposer 1400 can incorporate metal interconnects 1408 and vias 1410, including, among others, silicon through-silicon vias (TSVs) 1412. The Interposer 1400 can also incorporate embedded devices 1414, including both passive and active devices. Such devices include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and ESD (electrostatic discharge) devices. More complex devices, such as high-frequency or RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, can also be formed on the Interposer 1400. According to embodiments of the disclosure, facilities or processes disclosed herein may be used in the manufacture of the Interposer 1400 or in the manufacture of components contained in the Interposer 1400.

[0119] Fig. Figure 15 is an isometric view of a mobile computing platform 1500 which uses an integrated circuit (IC) manufactured according to one or more processes described herein or which incorporates one or more features described herein, according to an embodiment of the present disclosure.

[0120] The mobile computing device 1500 can be a portable device designed for electronic data display, electronic data processing, and wireless transmission of electronic data. For example, the mobile computing platform 1500 can be any tablet, smartphone, laptop computer, etc., and includes a display screen 1505, which in the exemplary embodiment is a touchscreen (capacitive, inductive, resistive, etc.), an integrated system 1510 at the chip level (SoC) or package level, and a battery 1513. As illustrated, the portion of the mobile computing platform 1500 occupied by the battery 1513 or non-volatile memory, such as a solid-state drive, or the number of transistor gates for improved platform functionality, is greater the higher the level of integration in the system 1510, which is enabled by a higher transistor packing density.Similarly, the greater the charge carrier mobility of each transistor in the System 1510, the greater the functionality. Therefore, the techniques described here can enable performance and form factor improvements in the Mobile Computing Platform 1500.

[0121] The integrated system 1510 is further illustrated in the extended view 1520. In the exemplary embodiment, the encapsulated device 1577 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or graphics processor) manufactured according to one or more of the processes described herein or incorporating one or more of the features described herein. The encapsulated device 1577 is further combined with an integrated power management integrated circuit (PMIC) 1515 and / or an integrated RF (wireless) circuit (RFIC) 1525, including a wideband RF (wireless) transmitter and / or receiver (e.g., a multi-core microprocessor and / or a multi-core microprocessor).including a digital baseband and an analog front-end module, which further includes a power amplifier on a transmit path and a low-noise amplifier on a receive path) and a control thereof 1511 coupled to the board 1560. Functionally, the PMIC 1515 performs battery power regulation, DC-DC conversion, etc., and thus has an input coupled to the battery 1513, and an output providing power to all other functional modules. As further illustrated, in the exemplary embodiment, the RFIC 1525 has an output coupled to an antenna to provide any number of wireless standards or protocols for implementation, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.11, and IEEE 802.11.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules can be integrated on separate ICs coupled to the package substrate of the 1577 packaged device, or within a single IC (SoC) coupled to the package substrate of the 1577 packaged device.

[0122] Another aspect is that semiconductor packages are used to protect an integrated circuit (IC) chip or die and to provide the die with an electrical interface to an external circuit arrangement. With the increasing demand for smaller electronic devices, semiconductor packages are being designed to be even more compact and to support higher circuit densities. Furthermore, the demand for higher-performance devices is creating a need for improved semiconductor packages that offer a thin encapsulation profile and low overall curvature compatible with subsequent assembly processing.

[0123] In one embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount a die to a ceramic or organic package substrate. In particular, C4 solder ball connections can be implemented to provide flip-chip interconnects between semiconductor devices and substrates. A flip-chip or controlled-collapse chip connection (C4 controlled-collapse chip connection) is a type of assembly used for semiconductor devices, such as integrated circuit (IC) chips, MEMS, or components that use solder bumps instead of wire bonding. The solder bumps are deposited on the C4 pads located on the top side of the substrate package. To mount the semiconductor device to the substrate, it is flipped over with the active side facing down toward the mounting surface.The solder contact mounds are used to connect the semiconductor device directly to the substrate.

[0124] Fig. Figure 16 illustrates a cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure.

[0125] With reference to Fig.Figure 16 includes a device 1600 comprising a die 1602, such as an integrated circuit (IC), which is manufactured according to one or more processes described herein or incorporates one or more features described herein, according to an embodiment of the present disclosure. The die 1602 includes metallized pads 1604 on it. A housing substrate 1606, such as a ceramic or organic substrate, includes connections 1608 on it. The die 1602 and the housing substrate 1606 are electrically connected by solder balls 1610, which are coupled to the metallized pads 1604 and the connections 1608. An underfill material 1612 surrounds the solder balls 1610.

[0126] Processing a flip chip can be similar to conventional IC fabrication, with a few additional steps. Near the end of the manufacturing process, the mounting pads are metallized to make them more receptive to solder. This typically involves several treatments. A small spot of solder is then deposited on each metallized pad. The chips are then cut from the wafer as usual. To mount the flip chip in a circuit, the chip is flipped over to transfer the solder spots onto connectors on the underlying electronic component or printed circuit board. The solder is then remelted to create an electrical connection, typically using ultrasonic soldering or, alternatively, a remelt soldering process. This also leaves a small gap between the chip's circuitry and the underlying mounting.In most cases, an electrically insulating adhesive is then "underfilled" to provide a stronger mechanical connection, to provide a thermal bridge, and to ensure that the solder joints are not stressed due to differential heating of the chip and the rest of the system.

[0127] In other embodiments, according to one embodiment of the present disclosure, novel encapsulation and die-to-die interposer approaches, such as silicon vias (TSV) and silicon interposers, are implemented to fabricate a high-performance multi-chip module (MCM) and a system-in-package (SiP) that incorporate an integrated circuit (IC) manufactured according to one or more of the processes described herein, or that include one or more of the features described herein.

[0128] Thus, embodiments of the present disclosure include integrated circuit structures with deep via-bar isolation.

[0129] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of protection of the present disclosure, even if only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative and not limiting, unless otherwise stated. The above description is intended to cover such alternatives, modifications, and equivalents as are obvious to a person skilled in the art using the present disclosure.

[0130] The scope of protection of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof, regardless of whether it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during an examination of the present application (or an application claiming priority thereof) for any such combination of features. In particular, with reference to the attached claims, features from dependent claims may be combined with those of the independent claims, and features from respective independent claims may be combined in any appropriate manner, not only in the specific combinations listed in the attached claims.

[0131] The following examples relate to further embodiments. The various features of the different embodiments can be combined in various ways, including some features and excluding others, in order to be suitable for a variety of different applications.

[0132] Exemplary embodiment 1: An integrated circuit structure comprises a plurality of gate lines extending across a plurality of semiconductor nanowire stacked channel structures. A plurality of trench contacts extends across a plurality of source or drain structures, with individual trench contacts alternating with individual gate lines. A backside metal routing layer extends beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one or more of the plurality of trench contacts. The conductive structure includes a section between the first and second conductive structural parts.A cut in the first of the multitude of gate lines next to the cut in the conductive structure is smaller than a cut in the second of the multitude of gate lines next to the first or second conductive structural part.

[0133] Example 2: The integrated circuit structure from Example 1, wherein the rear metal routing layer is a rear power supply line.

[0134] Example 3: The integrated circuit structure according to example 1 or 2, wherein the conductive structure is a deep via-bar structure.

[0135] Exemplary embodiment 4: The integrated circuit structure according to Exemplary embodiment 1 or 2, wherein the conductive structure is a recessed deep via-bar structure.

[0136] Exemplary embodiment 5: The integrated circuit structure according to exemplary embodiment 1, 2, 3 or 4, which further includes a dielectric plug in the section of the first of the plurality of gate lines and in the section in the conductive structure.

[0137] Exemplary embodiment 6: An integrated circuit structure includes a plurality of gate lines extending across a plurality of semiconductor fin structures. A plurality of trench contacts extends across a plurality of source or drain structures, with individual trench contacts alternating with individual gate lines. A backside metal routing layer extends beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one or more of the plurality of trench contacts. The conductive structure includes a section between the first and second conductive structural parts.A cut in the first of the multitude of gate lines next to the cut in the conductive structure is smaller than a cut in the second of the multitude of gate lines next to the first or second conductive structural part.

[0138] Exemplary embodiment 7: The integrated circuit structure from exemplary embodiment 6, wherein the rear metal routing layer is a rear power supply line.

[0139] Exemplary embodiment 8: The integrated circuit structure according to exemplary embodiment 6 or 7, wherein the conductive structure is a deep via-bar structure.

[0140] Exemplary embodiment 9: The integrated circuit structure according to exemplary embodiment 6 or 7, wherein the conductive structure is a recessed deep via-bar structure.

[0141] Exemplary embodiment 10: The integrated circuit structure according to exemplary embodiment 6, 7, 8 or 9, which further includes a dielectric plug in the section of the first of the plurality of gate lines and in the section in the conductive structure.

[0142] Exemplary embodiment 11: A computing device comprises a circuit board and a component coupled to the circuit board. The component comprises an integrated circuit structure containing a plurality of gate lines extending across a plurality of semiconductor nanowire stacked channel structures or semiconductor fin structures. A plurality of trench contacts extends across a plurality of source or drain structures, with individual trench contacts alternating with individual gate lines. A backside metal routing layer extends beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a section between the first and second conductive structural parts.A cut in a first of the multiple gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second of the multiple gate lines adjacent to the first or second conductive part of the structure.

[0143] Exemplary embodiment 12: The computing device from exemplary embodiment 11, which includes the semiconductor nanowire stacked channel structures.

[0144] Exemplary embodiment 13: The computing device from exemplary embodiment 11, which includes the semiconductor fin structures.

[0145] Exemplary embodiment 14: The computing device according to exemplary embodiment 11, 12 or 13, which further includes a memory that is coupled to the circuit board.

[0146] Exemplary embodiment 15: The computing device according to exemplary embodiment 11, 12, 13 or 14, which further includes a communication chip that is coupled to the circuit board.

[0147] Exemplary embodiment 16: The calculating device from exemplary embodiment 11, 12, 13, 14 or 15, which further includes a battery that is coupled to the circuit board.

[0148] Exemplary embodiment 17: The computing device from exemplary embodiments 11, 12, 13, 14, 15 or 16, which further includes a camera coupled to the circuit board.

[0149] Exemplary embodiment 18: The calculating device from exemplary embodiment 11, 12, 13, 14, 15, 16 or 17, which further includes a display that is coupled to the circuit board.

[0150] Exemplary embodiment 19: The computing device from Exemplary embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is an encapsulated integrated circuit die.

[0151] Exemplary embodiment 20: The computing device from exemplary embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

[1] Integrated circuit structure comprising: a plurality of gate lines extending across a plurality of semiconductor nanowire stacked channel structures; a plurality of trench contacts extending across a plurality of source or drain structures, wherein individual ones of the plurality of trench contacts alternate with individual ones of the plurality of gate lines; a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure having a cut between the first and second conductive structure portions, wherein a cut in a first of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second of the plurality of gate lines adjacent to the first or second conductive structure portion. [2] The integrated circuit structure of claim 1, wherein the backside metal routing layer is a backside power supply line. [3] The integrated circuit structure of claim 1 or 2, wherein the conductive structure is a deep via bar structure. [4] The integrated circuit structure of claim 1 or 2, wherein the conductive structure is a recessed deep via bar structure. [5] The integrated circuit structure of claim 1, 2, 3 or 4, further comprising a dielectric plug in the cut of the first of the plurality of gate lines and in the cut in the conductive structure. [6] Integrated circuit structure comprising: a plurality of gate lines extending across a plurality of semiconductor fin structures; a plurality of trench contacts extending across a plurality of source or drain structures, wherein individual ones of the plurality of trench contacts alternate with individual ones of the plurality of gate lines; a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure having a cut between the first and second conductive structure portions, wherein a cut in a first of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second of the plurality of gate lines adjacent to the first or second conductive structure portion. [7] The integrated circuit structure of claim 6, wherein the backside metal routing layer is a backside power supply line. [8] The integrated circuit structure of claim 6 or 7, wherein the conductive structure is a deep via bar structure. [9] The integrated circuit structure of claim 6 or 7, wherein the conductive structure is a recessed deep via bar structure. [10] The integrated circuit structure of claim 6, 7, 8 or 9, further comprising a dielectric plug in the cut of the first of the plurality of gate lines and in the cut in the conductive structure. [11] Computing device comprising: a circuit board; and a component coupled to the board, the component including an integrated circuit structure comprising: a plurality of gate lines extending across a plurality of semiconductor nanowire stacked channel structures or semiconductor fin structures; a plurality of trench contacts extending across a plurality of source or drain structures, wherein individual ones of the plurality of trench contacts alternate with individual ones of the plurality of gate lines; a backside metal routing layer extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts; and a conductive structure coupling the backside metal routing layer to one of the one or more of the plurality of trench contacts, the conductive structure having a cut between the first and second conductive structure portions, wherein a cut in a first of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second of the plurality of gate lines adjacent to the first or second conductive structure portion. [12] The computing device of claim 11, comprising the semiconductor nanowire stacked channel structures. [13] The computing device of claim 11, comprising the semiconductor fin structures. [14] A computing device according to claim 11, 12 or 13, further comprising: a memory that is coupled to the circuit board. [15] A computing device according to claim 11, 12, 13 or 14, further comprising: a communication chip that is coupled to the circuit board. [16] A computing device according to claim 11, 12, 13, 14 or 15, further comprising: a battery coupled to the circuit board. [17] A computing device according to claim 11, 12, 13, 14, 15 or 16, further comprising: a camera that is coupled to the board. [18] A computing device according to claim 11, 12, 13, 14, 15, 16 or 17, further comprising: a display coupled to the circuit board. [19] The computing device of claim 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is an encapsulated integrated circuit die. [20] The computing device of claim 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communications chip and a digital signal processor.

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