Power stage package with half-bridge connected transistor chips and driver chip with through-connection

Abstract

A package (100) configured as a power stage and comprising a first transistor chip (102) and a second transistor chip (104) connected together to form a half-bridge, a driver chip (106) configured to drive the first transistor chip (102) and the second transistor chip (104), and an encapsulation (108) at least partially encapsulating the first transistor chip (102), the second transistor chip (104), and the driver chip (106), wherein the driver chip (106) has electrically conductive driver pads (110, 112), at least one of which is arranged on each of two opposite major surfaces of the driver chip (106), and at least one electrically conductive driver via (114) extending through the driver chip (106) between the opposite major surfaces.

Description

background

[0001] The present invention relates to a package and a method for producing a package.

[0002] A package may contain an electronic component, such as a semiconductor chip. Packages may be embodied as an encapsulated electronic component with electrical connections extending from the encapsulation and coupled to an electronic peripheral. A molding compound or laminate may be used as the encapsulation.

[0003] However, service packages can suffer from high losses. Summary

[0004] There may be a need to provide a performance package with low losses.

[0005] According to an exemplary embodiment, a package is provided which is configured as a power stage and comprises a first transistor chip and a second transistor chip connected to each other to form a half-bridge, a driver chip configured to drive the first transistor chip and the second transistor chip, and an encapsulation which at least partially encapsulates the first transistor chip, the second transistor chip and the driver chip, wherein the driver chip has electrically conductive driver pads, at least one of which is arranged on each of two opposite main surfaces of the driver chip (i.e.at least one of the driver pads may be arranged on one main surface of the driver chip, and at least one other of the driver pads may be arranged on the opposite other main surface of the driver chip), and having at least one electrically conductive driver via extending through the driver chip between the opposite main surfaces.

[0006] According to another exemplary embodiment, a method of manufacturing a package configured as a power stage is provided, the method comprising connecting a first transistor chip and a second transistor chip to form a half-bridge, configuring a driver chip to drive the first transistor chip and the second transistor chip, at least partially encapsulating the first transistor chip, the second transistor chip, and the driver chip by an encapsulation, and providing the driver chip with electrically conductive driver pads, at least one of which is arranged on each of two opposite main surfaces of the driver chip, and with at least one electrically conductive driver via extending through the driver chip between the opposite main surfaces.

[0007] An exemplary embodiment provides a power package that can act as a power stage during operation. Two transistor chips, which can be driven by a driver chip having one or more respective driver pads as electrically conductive terminals on each of two opposite main surfaces thereof, can be connected together to provide half-bridge functionality when used. An encapsulation, for example, a laminate-type encapsulation, can partially or fully encapsulate the chips. Advantageously, the driver chip can be provided with one or more electrically conductive driver via connections that can extend along a vertical, stepped, or inclined path through the entire thickness of the driver chip, preferably through semiconductor material thereof.In short, providing one or more driver pads on each of the opposing main surfaces of the driver chip, in combination with at least one driver via extending across the entire driver chip thickness, can shorten the electrically conductive paths of the power stage package. This can result in less signal distortion, less signal loss, less heat dissipation, better signal quality, and improved power density. Furthermore, these measures can reduce the effort required to construct redistribution structures in the encapsulation to redistribute signals propagating through the package. For example, the number of package vias extending through the encapsulation can be significantly reduced. This can also contribute to a compact and low-loss package. Description of further exemplary embodiments

[0008] Further exemplary embodiments of the package and the method are explained below.

[0009] In the context of the present application, the term "package" may, in particular, refer to a device that may comprise packaged chips. The chips of the package may be at least partially encapsulated by an encapsulation.

[0010] Furthermore, an electrically conductive connection structure can form part of the package.

[0011] In the context of the present application, the term "power stage" may specifically refer to a chip circuit that provides a power conversion function. For example, a power stage may perform basic power conversion from an input voltage to an output voltage and may include chip-like switches. A power stage may be a power management package formed from interconnected power semiconductor chips.

[0012] In the context of the present application, the term "chip" may in particular refer to a semiconductor chip (in particular a power semiconductor chip). The chip may be an active electronic device. In particular, the chip may be a semiconductor chip having at least one integrated circuit element (such as a transistor) in a surface portion thereof. The chip may be a bare chip or may already be packaged or encapsulated. Semiconductor chips implemented according to exemplary embodiments may, for example, be formed using silicon technology, gallium nitride technology, silicon carbide technology, etc.

[0013] In the context of the present application, the term "transistor chip" can refer in particular to a chip, such as a semiconductor chip, in which at least one transistor can be integrated, in particular monolithically integrated. Optionally, the chip can have at least one further integrated circuit element, such as a diode or another transistor.

[0014] In the context of the present application, the term "half-bridge" may in particular refer to a circuit composed of an upper transistor switch or chip ("high-side") and a lower transistor switch or chip ("low-side"). For example, the transistors may be MOSFETs, i.e., metal-oxide-semiconductor field-effect transistors. The transistors may be connected in a cascode arrangement. The two transistor switches may be switched on and off complementarily to each other (in particular, with a non-overlapping dead time) by applying corresponding voltage waveforms to control terminals of the chips. A desired result may be an idealized DC-DC conversion scenario in which a rectangular average voltage level switches between a first electrical potential (such as a DC (direct current) bus voltage) and a second electrical potential (such as ground).However, other output signal shapes that do not have a rectangular characteristic may be possible. The two transistors can be connected by mutually connecting their connection terminals, so that a two-transistor-based switch with implemented diode characteristics can be obtained. The mentioned half-bridge configuration can be used as such or alone, or can be combined with one or more other half-bridges (or other electrical circuits) to realize a more complex electrical function. For example, two such half-bridges can form a full bridge.

[0015] In the context of the present application, the term "driver chip" may, in particular, refer to a chip configured to drive the first and second transistor chips. Driving may include controlling, regulating, managing, signal generation, signal processing, signal transmission, and / or powering the transistor chips. For example, the driver chip may be a logic chip.

[0016] In the context of the present application, the term "encapsulation" may in particular refer to a material, structure, or element surrounding at least a portion of the transistor chips and the driver chip and optionally providing electrical insulation and / or contributing to heat dissipation during operation. In particular, the encapsulation may be predominantly or even entirely electrically insulating. For example, the encapsulation may be a laminate-like encapsulation comprising interconnected stacked layers (e.g., comprising layers comprising resin and optionally glass fibers). Electrically conductive structures (such as layers and / or arrays of vias) may be arranged on and / or within the encapsulation. Alternatively, the encapsulation may be a molding compound. A molding compound may comprise a matrix of a flowable and curable material and filler particles embedded therein.For example, filler particles can be used to adjust the properties of the mold component, particularly to improve thermal conductivity. As an alternative to a molding compound (e.g., based on epoxy resin), the encapsulation can also be a potting compound (e.g., based on a silicone gel).

[0017] In the context of the present application, the term "pads" may refer in particular to (preferably flat and horizontal) electrically conductive connections on a surface of a chip. Such pads may function as an interface with an electronic chip peripheral for transmitting electrical signals and / or electrical energy between an outer and inner surface of a chip and / or propagating through the chip.

[0018] In the context of the present application, the term "via connection" may, in particular, refer to an electrically conductive structure extending through an entire chip, in particular between a lower main surface and an upper main surface of a chip. For example, such a via connection may extend through semiconductor material of the chip. In one embodiment, at least a portion of the via connection may extend vertically through the chip. For example, the via connection may be a metallic post or column, or a metallic via.

[0019] In one embodiment, the encapsulation is a laminate comprising a plurality of laminated layers. In the context of the present application, the term “laminate” may in particular refer to a flat body (such as a sheet or plate) formed by a plurality of laminate layers bonded together, i.e. layers that can be or are bonded together by lamination. In particular, a laminate may comprise a material suitable for bonding together a plurality of laminate layers, for example of the same material. Thus, a laminate may be a plate-shaped or sheet-shaped body made of one or more laminatable or laminated layers. The laminate layers may be bonded or configured to be bondable to other layers by lamination.Lamination may refer to a joining of laminatable layers using elevated temperature, optionally accompanied by additional mechanical pressure applied to stacked laminate layers. In particular, such a laminate may be a pressed multilayer stack of one or more dielectric organic layers and / or one or more metallic foils. One or more dielectric laminate layers may, for example, be prepreg layers. Prepreg is a material comprising a resin, optionally with glass fibers therein. The laminate may also comprise one or more metallic layers, which may be copper foils. More generally, the laminate may comprise at least one dielectric layer capable of curing, polymerizing, and / or crosslinking during a lamination process, thereby contributing to an adhesion force between multiple layers of a multilayer laminate.For example, a laminate can be a printed circuit board (PCB).

[0020] In particular, a laminate material or material of the laminate may be an epoxy resin or another polymer (such as polyimide) or another insulating material filled with filler particles, in particular glass particles, in particular glass fibers. Such a material may be provided as a prepreg, i.e., a layer in which the epoxy resin is not or not fully cured, so that it can become liquid by applying thermal energy. In a laminate, such a prepreg layer may be combined with one or more copper foils, which can be applied during lamination. Resin-coated copper (RCC) is a combination of a copper foil and an uncured epoxy resin without glass fibers.

[0021] In one embodiment, the encapsulation comprises a molding compound. In particular, the encapsulation may be an epoxy-based molding compound. More generally, different types of molding compounds may be used, such as bismaleimide molding compound, imide molding compound, etc. Molding may refer to a manufacturing process for shaping liquid or pliable raw material using a rigid tool called a mold. Thus, the encapsulation of one or more chips (such as semiconductor chips) of the package may be achieved by molding. Consequently, the encapsulation may comprise an organic curable matrix (e.g., based on epoxy resin) with inorganic filler particles (for fine-tuning encapsulation functions) therein.

[0022] In one embodiment, the first transistor chip, the second transistor chip, and the driver chip are arranged in a core of the laminate. A core may be a rigid, fully cured layer in an interior of a laminate that provides stability. One or more openings may be formed in such a core to accommodate the respective first transistor chip, second transistor chip, and / or driver chip. As a result, the package footprint may be reduced while simultaneously achieving high stability. For example, the chips are embedded in a central core of the laminate. For example, such a core may be a carrier layer in the laminate, made of, for example, FR4 material. For example, such a core may be coated with copper layers. Embedding the chips in the core may provide a highly symmetrical arrangement that may suppress warpage.

[0023] In one embodiment, the first transistor chip, the second transistor chip, and the driver chip are arranged side by side on the same vertical plane in the encapsulation. For example, the first transistor chip, the second transistor chip, and the driver chip may be arranged on the same vertical plane in a core. This may result in a compact design and short electrical connection paths. Alternatively, the chips may be arranged on different vertical planes, for example, they may be vertically stacked or staggered.

[0024] In one embodiment, at least a portion of the electrically conductive driver pads on both opposing main surfaces are electrically coupled to each other by at least one of the at least one electrically conductive driver vias. In particular, each of the two opposing ends of the driver vias can be directly connected to a respective one of the driver pads. As a result, a very short—preferably vertical—electrical coupling path can be obtained. This can promote low loss and high-signal-quality transmission.

[0025] In one embodiment, at least one of the at least one electrically conductive driver vias extends vertically between the opposing main surfaces. A vertical connection realized by the respective driver via results in a specific short connection path. However, it is also possible for the connection path formed by the respective driver connection extending through semiconductor material of the driver chip to be inclined or slanted.

[0026] In one embodiment, at least one of the at least one electrically conductive driver vias extends partially horizontally and partially vertically between the opposing main surfaces. In said embodiment, it may be possible for the connection path formed by the respective driver connection extending through semiconductor material of the driver chip to be stepped.

[0027] In such a configuration, the driver through connection can bridge both vertical and horizontal mutual displacement of the connected driver pads.

[0028] In one embodiment, at least one of the at least one electrically conductive driver via extends through semiconductor material of the driver chip. Thus, a via opening may be formed in a semiconductor substrate of the driver chip and may be filled with electrically conductive material to thereby form a short electrical connection path through the driver chip instead of surrounding it. For example, an electrically insulating barrier layer may be formed between the electrically conductive driver via and the semiconductor material.

[0029] In one embodiment, at least one of the first transistor chip and the second transistor chip has electrically conductive transistor pads on both opposite main surfaces thereof (i.e., at least one of the transistor pads may be arranged on one main surface of the respective transistor chip, and at least one other of the transistor pads may be arranged on the opposite other main surface of the respective transistor chip) and has at least one electrically conductive transistor via extending through the at least one of the first transistor chip and the second transistor chip between the opposite main surfaces (e.g., extending vertically, inclined, or stepped).Advantageously, (e.g., elongated) vias extending through a respective chip thickness can be formed not only to extend through the driver chip, but also to extend through one or both of the transistor chips. This can further contribute to reducing the length of the electrical connection paths between pads of the chips.

[0030] In one embodiment, at least one of the first transistor chip and the second transistor chip is a field-effect transistor chip or is a bipolar transistor chip. In particular, a respective integrated transistor chip may be a field-effect transistor chip having at least a source terminal (or pad), a drain terminal (or pad), and a gate terminal (or pad). Alternatively, a respective integrated transistor chip may be a bipolar transistor chip having at least an emitter terminal (or pad), a collector terminal (or pad), and a base terminal (or pad). Specific examples of the transistor chips are a metal-oxide-semiconductor field-effect transistor (MOSFET) and an insulated-gate bipolar transistor (IGBT).

[0031] In one embodiment, the first transistor chip has a first gate pad and a first source pad on an upper main surface and a first drain pad on a lower main surface. Thus, the first transistor chip may be a device that experiences vertical current flow during operation. This may enable the implementation of very thin transistor chips, further contributing to package compactness.

[0032] In one embodiment, the first transistor chip has a first sensing pad on the top main surface. The first transistor chip may be configured to provide a sensing signal at the first sensing pad, which may be transmitted to the driver chip and may indicate an electrical parameter characterizing the operation of the first transistor chip (e.g., a current value of an electrical current flowing through the first transistor chip).

[0033] In one embodiment, the first transistor chip has a further first gate pad on the lower main surface, wherein the gate pad and the further gate pad of the first transistor chip are electrically coupled to each other by an electrically conductive transistor via extending through the first transistor chip between the opposing main surfaces. Such a configuration may allow for providing a gate pad on each of the two opposing main surfaces of the first transistor chip. This may improve design flexibility and may provide another option for keeping electrical connection paths short within the package.

[0034] In one embodiment, the second transistor chip has a second gate pad and a second source pad at a lower main surface and a second drain pad at an upper main surface. Thus, the second transistor chip may be a device with vertical current flow during operation. This may enable the implementation of very thin transistor chips, further contributing to package compactness. Furthermore, the described configuration indicates that the second transistor chip may be flipped or turned over with respect to the first transistor chip to create a large switching node. This arrangement may also contribute to short electrically conductive connection paths and therefore a low-loss configuration that provides high signal quality.

[0035] In one embodiment, the second transistor chip has a second sensing pad on the bottom main surface. The second transistor chip may be configured to provide a sensing signal at the second sensing pad, which may be transmitted to the driver chip and may indicate an electrical parameter characterizing the operation of the second transistor chip (e.g., a current value of an electrical current flowing through the second transistor chip).

[0036] Providing a sensing signal from both the first transistor chip and the second transistor chip to the driver chip can promote efficient and precise control of the operation of the transistor chips by the driver chip based on or taking into account the transmitted current values.

[0037] In one embodiment, the second transistor chip has a further second gate pad on the upper main surface, wherein the second gate pad and the further second gate pad of the second transistor chip are electrically coupled to each other by an electrically conductive transistor via extending through the second transistor chip between the opposing main surfaces. Such a configuration may allow for providing a gate pad on each of the two opposing main surfaces of the second transistor chip. This may improve design flexibility and may provide another option for keeping electrical connection paths short within the package.

[0038] In one embodiment, the package comprises a bottom redistribution layer (RDL) extending beneath the first transistor chip, the second transistor chip, and the driver chip and interconnecting at least a portion of the first transistor chip, the second transistor chip, and the driver chip. Such a bottom redistribution layer may be embedded within the encapsulation, which may preferably be a laminate-like encapsulation. Thus, the bottom redistribution layer may be formed by electrically conductive layers (such as patterned copper foils) and interconnected electrically conductive vias (such as copper vias) within the encapsulation. This may further contribute to short connection paths.

[0039] In one embodiment, the package comprises an upper redistribution layer (RDL) extending over the first transistor chip, the second transistor chip, and the driver chip and interconnecting at least a portion of the first transistor chip, the second transistor chip, and the driver chip. Such an upper redistribution layer may be embedded in the encapsulation, which may preferably be a laminate-like encapsulation. Thus, the upper redistribution layer may be formed by electrically conductive layers (such as patterned copper foils) and interconnected electrically conductive vias (such as copper vias) within the encapsulation. This may further contribute to short connection paths.

[0040] In one embodiment, the upper redistribution layer and the lower redistribution layer are electrically connected to each other by at least one of the at least one electrically conductive driver via interconnect. By electrically coupling the lower redistribution layer to the upper redistribution layer using the electrically conductive driver via interconnect(s) (and optionally using at least one additional electrically conductive transistor via interconnect extending through the first transistor chip and / or the second transistor chip), a circuit design of an exemplary embodiment may be completed. This may enable short electrical connection paths with low losses, low heat dissipation, and high signal integrity.

[0041] In one embodiment, the first transistor chip is a high-side (HS) switch, and the second transistor chip is a low-side (LS) switch. As previously mentioned, the first transistor chip and the second transistor chip may be connected to form a half-bridge. In such a half-bridge configuration, an upper transistor switch ("high-side") may be implemented in the form of the first transistor chip, and a lower transistor switch ("low-side") may be implemented in the form of the second transistor chip.

[0042] In one embodiment, a thickness of the laminate-like encapsulation is in a range between 100 µm and 2000 µm, for example, in a range between 100 µm and 500 µm. The laminate can be formed as a plate. In one embodiment, a thickness of the respective chip (i.e., the first transistor chip, the second transistor chip, or the driver chip) is in a range between 50 µm and 200 µm.

[0043] In one embodiment, the package may comprise at least one of the group consisting of a controller circuit, a driver circuit, and a power semiconductor circuit. All of these circuits may be integrated into one semiconductor chip or separately into different chips. For example, a corresponding power semiconductor application may be realized by the chip(s), wherein integrated circuit elements of such a power semiconductor chip may comprise at least one transistor (in particular a MOSFET, a metal-oxide-semiconductor field-effect transistor), at least one diode, etc. In particular, circuits may be manufactured that fulfill a half-bridge function, a full-bridge function, etc.

[0044] A semiconductor substrate, i.e., a silicon substrate, can be used as the substrate or wafer for the semiconductor chips. Alternatively, a silicon oxide or other insulating substrate can be provided. It is also possible to implement a germanium substrate or a III-V semiconductor material. For example, exemplary embodiments can be implemented using silicon, GaN, or SiC technology.

[0045] The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings, in which like parts or elements are designated by like reference numerals. Short description of the drawings

[0046] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments of the invention and constitute a part of the specification, illustrate exemplary embodiments of the invention.

[0047] In the drawings: Fig. 1 shows a cross-sectional view of a package according to an exemplary embodiment. Fig. 2 shows a top view of a package without a metallization layer according to an exemplary embodiment. Fig. 3 shows a top view of the package of Fig. 2 with metallization layer. Fig. 4 shows a bottom view of a package without a metallization layer according to an exemplary embodiment. Fig. 5 shows a bottom view of the package of Fig. 4 with metallization layer. Fig. 6 shows a top view of a package according to an exemplary embodiment. Fig. 7 shows a top view of a package according to another exemplary embodiment. Fig. 8 shows a top view of a package according to another exemplary embodiment. Fig. 9 shows a top view of a package according to another exemplary embodiment. Fig. 10 shows a cross-sectional view of a portion of a package with a vertical via extending through a driver chip, according to an exemplary embodiment. Fig. 11 shows a cross-sectional view of a portion of a package with a vertical via extending through a transistor die, according to an exemplary embodiment. Detailed description of exemplary embodiments

[0048] The representation in the drawing is schematic and not to scale.

[0049] Before exemplary embodiments are described in more detail with reference to the figures, some general considerations are summarized based on which exemplary embodiments were developed.

[0050] A power stage package design can combine power chips (such as a high-side chip and a low-side chip) and a driver chip, such as a logic chip. Such power stages can be realized using chip embedding technologies with double-sided via connections or a combination of a via connection and a plated area on a respective chip.

[0051] MOSFETs may be connected on both sides to provide drain and source contacts, and can be switched and controlled by the driver chip, which may be connected to gate and sense pads and external input / output pads. The driver chip may only be connected on one side and may need to be connected to the MOSFETs with laminate vias. One of the MOSFETs may be flipped with respect to the other. This means that one of the vias from the driver chip to one of the MOSFETs must be routed through the package. This can be associated with high losses.

[0052] According to an exemplary embodiment, a power stage-type package is provided comprising two transistor chips (which may be power semiconductor chips). The latter may be driven during operation by a driver chip having driver pads as electrically conductive connections, at least one of which is arranged on the top side and at least one on the bottom side of the driver chip. The transistor chips and the driver chip may be in a configuration capable of providing half-bridge functionality. An (e.g., laminate-like) encapsulation may surround the mentioned chips to thereby encapsulate them. Advantageously, one or more (e.g., elongated) electrically conductive driver vias (e.g., through-silicon vias, TSV) may extend along an at least partially vertical direction through the driver chip.For example, this can be achieved by connecting the driver pads on both opposite main surfaces of the driver chip in a short manner. Illustratively speaking, providing driver pads on the top and bottom of the driver chip combined with one or more preferably vertical driver via connections can result in short signal paths within the package. Consequently, signal loss and signal distortion can be efficiently suppressed. In addition, the described configuration can lead to a simplified (particularly with regard to the number of vias) electrically conductive redistribution structure in the encapsulation above and / or below the chips. As a result, a compact package with high electrical performance can be obtained.

[0053] In particular, a chip-embedded power stage can be provided, which can be equipped with a driver chip having contact pads on both sides. A corresponding power stage can advantageously be provided with a through-silicon via (TSV) in the driver chip. This can enable very high power density. A small package dimension can allow the power stages to be placed close to a central processing unit (CPU). This can be advantageous in terms of parasitic effects, losses, and manufacturing complexity.

[0054] A core idea of ​​an exemplary embodiment is to use double-sided pads for the driver chip, which allows for realizing a power stage with fewer or even no through-hole vias connecting a redistribution structure from the top and bottom of the MOSFETs. From a layout standpoint, the through-hole vias in the package can advantageously be shifted to one or more through-silicon vias in the driver chip. This can allow the chips to be placed even closer together and further increase power density by shrinking the package and increasing the silicon content within the package.

[0055] One embodiment may use pads on both sides of a driver chip to create a power stage. This may allow the power stage to be further shrunk compared to conventional approaches and increase the power density within the package. Thus, higher power densities for power stages can be achieved, for example, for server applications and / or artificial intelligence (AI) applications.

[0056] According to one embodiment, a method for manufacturing chip-embedded power stages with a driver having contact pads on both sides is provided. The chip-embedded power stage may be equipped with a driver chip having a contact pad on both sides. A through-silicon via (TSV) may be formed in an interior of the driver chip instead of conventional through-hole vias (THV) in the package to connect redistribution layers on the top and bottom of MOSFETs. Further, a set of low-side and high-side MOSFETs may be embedded in an encapsulation, with the low-side MOSFET flipped relative to the high-side MOSFET, and the driver chip may be connected to both MOSFET chips. Further, the pads on the driver chip for high-side connection may be located on one side of the driver chip.Accordingly, the pads for the low-side connection to the driver chip can be located on the opposite side of the driver chip. One advantage of this architecture is that it can allow the chips to be placed closer together, shrinking the package, and thus increasing power density.

[0057] In a design of an exemplary embodiment, a package is provided in which gate and sense pads, i.e., the control terminals of the respective transistor chip, are arranged on the source side of the respective transistor chip, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor) chip. The driver chip or control chip may have electrical contacts on both its front and back sides, which may shorten a redistribution path length from one side to the other side of the driver chip. This shortening may be achieved, in particular, by vertical through-connections extending through the silicon material of the driver chip, which eliminates the need for a large number of vias in a laminate-like encapsulation. The described configuration may have advantages with regard to the required chip area and power density.

[0058] Fig. 1 shows a cross-sectional view of a package 100 embodied with a power stage according to an exemplary embodiment.

[0059] The illustrated package 100 includes a laminated encapsulation 108 comprising a laminated layer stack composed of a plurality of laminated layers 116, 118. The laminated encapsulation 108 is embodied as a printed circuit board (PCB). In the illustrated example, the laminated encapsulation 108 includes electrically insulating layers 116, which may be embodied as outer prepreg layers and as a core 120 made of FR4. Furthermore, the laminated encapsulation 108 includes electrically conductive layers 118, which may be embodied as copper layers on and within the core 120, as well as on and within the prepreg layers. The electrically conductive layers 118 include horizontal conductive traces and vertical vias that are interconnected.A layered structure in the form of the electrically conductive layers 118 and the prepreg layers may be formed on both opposing major surfaces of the core 120. A patterned solder resist 169 may be formed on one or both opposing major surfaces of the laminated layer stack.

[0060] Furthermore, semiconductor chips 102, 104, 106 are embedded in the laminate-like encapsulation 108. As shown, semiconductor chips 102, 104, 106 may be embedded in (e.g., a central) core 120. The semiconductor chips 102, 104, 106 may be bare chips or encapsulated chips inserted into a respective through-hole of the core 120. Empty spaces of the through-holes not filled by the semiconductor chips 102, 104, 106 may be filled by an adhesive 167, which may, for example, comprise or consist of resin. In particular, the power semiconductor chip with the reference numeral 102 provides a transistor function (may, for example, be embodied as a field-effect transistor chip) and is thus referred to as the first transistor chip 102.Accordingly, the power semiconductor chip with reference numeral 104 also provides a transistor function (for example, it can be embodied as a field-effect transistor chip) and is thus referred to as the second transistor chip 104. The semiconductor chip with reference numeral 106 can be a logic chip that can provide a driver function (or control function) for the transistor chips 102, 104 and is thus referred to as the driver chip (or control chip) 106.

[0061] More specifically, the package 100 can be configured as a power stage. The package 100 includes the first transistor chip 102 and the second transistor chip 104 connected together to form a half-bridge. In this half-bridge configuration, for example, it is possible for the first transistor chip 102 to be configured as a high-side switch, whereas the second transistor chip 104 can be configured as a low-side switch. The driver chip 106 is electrically coupled to the transistor chips 102, 104 and is configured to drive or control the first transistor chip 102 and the second transistor chip 104 based on control signals transmitted from the driver chip 106 to the transistor chips 102, 104. Furthermore, sensing signals or other electrical signals may be transmitted from the transistor chips 102, 104 to the driver chip 106, for example, for use as a basis for the control or driver function of the latter.

[0062] The laminate-like encapsulation 108 completely encapsulates the first transistor chip 102, the second transistor chip 104, and the driver chip 106. Thus, the encapsulation 108 mechanically protects and electrically couples the chips 102, 104, 106, and also provides an electrical insulation function. As previously mentioned, the encapsulation 108 is a laminate comprising a plurality of laminated layers 116, 118 that may be bonded together by pressure and heat.

[0063] Furthermore, the driver chip 106 has electrically conductive driver pads 110, 112 on both opposite main surfaces thereof. More specifically, the driver pads 110 are formed on a lower main surface of the driver chip 106. Accordingly, the driver pads 112 are formed on an upper main surface of the driver chip 106. Electrically conductive driver vias 114 extend vertically through semiconductor material of the driver chip 106 between the opposite main surfaces, thereby electrically coupling the lower-side driver pads 110 to the upper-side driver pads 112. Thus, the electrically conductive driver pads 110, 112 on both opposite main surfaces are electrically coupled to each other by the electrically conductive driver vias 114 extending vertically between the opposite main surfaces.This electrical coupling is achieved through a very short electrically conductive path thanks to the vertical extension of the driver vias 114, which extend through the entire thickness of the driver chip 106 rather than being formed around it. In the embodiment shown, two driver vias 114 are provided, whereas only one or at least three driver vias 114 are possible. For example, electrically conductive driver vias 114 may be embodied as a metal-filled via or as a metallic post or pillar. The metallic material may be inserted (e.g., by plating or in the form of a preformed insert) into a vertical via extending between both opposing major surfaces of the semiconductor body of the driver chip 106, thereby directly electrically coupling the driver pads 110, 112 to each other.

[0064] As shown, the first transistor chip 102, the second transistor chip 104, and the driver chip 106 are arranged on the same vertical plane in the core 120 of the laminate-like encapsulation 108. This can result in reliable mechanical protection of the chips 102, 104, and 106 in the encapsulation 108, a compact design, short electrical paths and thus low signal losses, and a symmetrical configuration resulting in low warpage. This symmetry and compactness can be further improved because the first transistor chip 102, the second transistor chip 104, and the driver chip 106 are arranged side by side on the same vertical plane in the encapsulation 108.

[0065] With further reference to Fig. 1, the first transistor chip 102 and the second transistor chip 104 have bottom-side electrically conductive transistor pads 122 and top-side electrically conductive transistor pads 124. Providing pads 122, 124 on both opposite main surfaces of the respective transistor chips 102, 104 may enable the use of very thin transistor chips 102, 104 with vertical current flow. This may lead to further improved compactness of the package 100.

[0066] In the embodiment shown, the first transistor chip 102 has a first gate pad 134 and a first source pad 130 at an upper main surface and a first drain pad 132 at a lower main surface. In contrast, the second transistor chip 104 has a second gate pad 144 and a second source pad 140 at a lower main surface and a second drain pad 142 at an upper main surface. To be brief, the first transistor chip 102 and the second transistor chip 104 are configured in a mutually flipped configuration. While the first transistor chip 102 is embedded in the encapsulation 108 with a drain-down configuration, the second transistor chip 104 is embodied in a source-down configuration.

[0067] As in Fig. 1, the package 100 includes a lower redistribution layer 150 that extends beneath the first transistor chip 102, the second transistor chip 104, and the driver chip 106 and interconnects the first transistor chip 102, the second transistor chip 104, and the driver chip 106 at a bottom surface. The lower redistribution layer 150 is formed by the electrically conductive layers 118 in the lower portion of the encapsulation 108. Accordingly, the package 100 includes an upper redistribution layer 152 that extends above the first transistor chip 102, the second transistor chip 104, and the driver chip 106 and interconnects the first transistor chip 102, the second transistor chip 104, and the driver chip 106 at a top surface. The upper redistribution layer 152 is formed by the electrically conductive layers 118 in the upper portion of the encapsulation 108.The lower redistribution layer 150 and the upper redistribution layer 152 may be electrically coupled to each other through the electrically conductive driver vias 114, for example, only through the driver vias 114. This may result in extremely short electrical paths and low losses. Alternatively, the coupling of the lower redistribution layer 150 and the upper redistribution layer 152 may also be achieved through optional metal-filled vias (see reference numeral 189 in FIG. Fig. 2 and Fig. 4, which may be referred to as package or laminate vias) of the electrically conductive layers 118.

[0068] Fig. 2 shows a top view of a package 100 without a metallization layer according to an exemplary embodiment. Fig. 3 shows a top view of the package 100 of Fig. 2 with metallization layer. Thus, Fig. 2 and Fig. 3 is a top view of the routing of a power stage type package 100 with a driver chip 106 having electrically conductive driver vias 114 (in Fig. 2 and Fig. 3 not shown, see Fig. 1) embodied as through-silicon vias (TSVs). The electrically conductive driver vias 114 can transmit signals between the front and back of the driver chip 106. This can be done with an extremely short path, resulting in low signal loss, low heat dissipation, and high signal quality. The electrically conductive driver vias 114 can be vertical to connect driver pads 110, 112 that are vertically aligned. Alternatively, the electrically conductive driver vias 114 can be stepped, having both horizontal and vertical sections for connecting driver pads 110, 112 that are shifted vertically and horizontally with respect to one another. Inclined electrically conductive driver vias 114 are also possible for the latter purpose.

[0069] Fig. 4 shows a bottom view of a package 100 without a metallization layer. Fig. 5 shows a bottom view of package 100 of Fig. 4 with metallization layer. Thus, Fig. 4 and Fig. 5 is a bottom view of the routing of a power stage type package 100 with a driver chip 106 having electrically conductive driver vias 114 (in Fig. 4 and Fig. 5 not shown, see Fig. 1) which are embodied as through-silicon vias (TSVs).

[0070] As in Fig. 2, a first transistor chip 102 is provided, which has a first gate pad 134 and a first source pad 130 on an upper main surface and a first drain pad 132 (see Fig. 4) on a lower main surface. Furthermore, the first transistor chip 102 has a first sensing pad 136 on the upper main surface. The first transistor chip 102 may be configured to provide a sensing signal at the first sensing pad 136, which may be transmitted to the driver chip 106 and may indicate a current value of an electric current flowing through the first transistor chip 102.

[0071] As in Fig. 4, the second transistor chip 104 has a second gate pad 144 and a second source pad 140 on a lower main surface and a second drain pad 142 (see Fig. 2) on an upper main surface. Furthermore, the second transistor chip 104 has a second sensing pad 146 on the lower main surface. The second transistor chip 104 may be configured to provide a sensing signal at the second sensing pad 146, which may be transmitted to the driver chip 106 and may indicate a current value of an electric current flowing through the second transistor chip 104.

[0072] Fig. 2 to Fig. 5 refer to a configuration in which the driver pads 110, 112 are connected to the high-side first transistor chip 102 and the low-side second transistor chip 104 and are located on opposite sides. Furthermore, such embodiments relate to a component embedding technology with TSVs in the driver chip 106. The dies or chips 102, 104, 106 are embedded with the low-side second transistor chip 104 flipped relative to the high-side first transistor chip 102. The driver chip 106 is connected to both the first transistor chip 102 and the second transistor chip 104. The driver pads 112 on the driver chip 106 for a high-side connection are located on one side of the driver chip 106 and the driver pads 110 for the low-side connection to the driver chip 106 are located on the opposite side of the driver chip 106.

[0073] One result of such an architecture is that through-hole vias in the encapsulation 108 of the package 100 for vertically connecting chip pads on opposite chip sides can be obsolete or at least reduced. Consequently, high power density can be realized.

[0074] Fig. 6 shows a top view of a package 100 according to an exemplary embodiment. Fig. 7 shows a top view of a package 100 according to another exemplary embodiment.

[0075] The Fig. 6 and Fig. Figure 7 shows two options for how the driver pads 110, 112 can be arranged and routed in the second redistribution layer 152 on the top side and the first redistribution layer 150 on the bottom side. Circles 187 indicate driver pads and transistor pads on the bottom side. Circles 185 indicate driver pads 112 and transistor pads on the top side.

[0076] In general, component embedding technology according to exemplary embodiments with driver via connections 114 (such as TSVs) in the driver chip 106 can be implemented with different design options. Such a principle can also be implemented with a different embedding technology than that described with reference to the figures described above. Embodiments can also implement multi-phase power stages, inlay power stages, multi-die construction with driver, or a driver alone (for example, routed to both sides as an inlay for further embedding into a board, providing additional routing possibilities within a board design).

[0077] Fig. 8 shows a top view of a package 100 according to another exemplary embodiment. Fig. 9 shows a top view of a package 100 according to another exemplary embodiment.

[0078] A corresponding advantage of reducing or eliminating vias through the package and creating a smaller power stage can be realized with other chip configurations. In one embodiment, through-silicon vias can also be implemented within one or both of the MOSFET-like transistor chips 102, 104 in addition to the driver chip 106.

[0079] Fig. 10 shows a cross-sectional view of a portion of a package 100 having a vertical via connection 114 extending through a driver chip 106, according to an exemplary embodiment.

[0080] Fig. 10 shows how the vertical via 114 (e.g., made of copper) extends vertically through the entire thickness of a semiconductor body 199 (e.g., made of silicon) of a driver chip 106. A dielectric separation layer 197 may be arranged between the vertical via 114 and the semiconductor body 199. The vertical via 114 may be embodied as a metal-filled via, which may be formed by plating. For example, it may include a first plating substructure 195 and a second plating substructure 193, and optionally at least one further plating substructure. The vertical via 114 may be directly coupled to a respective driver pad 110, 112 (e.g., made of aluminum) on a top side and a bottom side, respectively. A termination layer 191 may also be applied on the top side.

[0081] Fig. Figure 10 shows a schematic view of the vertical through-connection 114, embodied here as a through-silicon via, implemented in the driver chip 106. In this case, the upper and lower pads 110, 112 directly face each other at the same horizontal position. This is not mandatory. Driver pads 110, 112 that face each other but are not located at the same horizontal position can also be implemented in another embodiment.

[0082] Fig. 11 shows a cross-sectional view of a portion of a package 100 having a vertical via 126 extending through a transistor die 102 or 104, according to an exemplary embodiment. For brevity, Fig. 11 shows a preferred orientation of a transistor chip configured as the first transistor chip 102 described above. When the design shown is used as the second transistor chip 104 described above, it can be Fig. 11 shown orientation.

[0083] In addition to the previously described embodiments, the first transistor chip 102 / second transistor chip 104 may have a further or second gate pad 138 / 148, wherein the gate pad 134 / 144 and the further gate pad 138 / 148 of the first / second transistor chip 102 / 104 are electrically coupled to each other by an electrically conductive transistor via 126 extending through the first / second transistor chip 102 / 104 between its opposite main surfaces. The respective further or second gate pad 138 / 148 may be formed on the opposite main surface of the respective first / second transistor chip 102 / 104 compared to the first gate pad 134 / 144.

[0084] Thus, the illustrated transistor chip 102, 104 of Fig.11 may be configured in a similar manner as described above, but additionally includes an electrically conductive transistor via connection 126 extending through the transistor chip 102, 104 between its opposing main surfaces. The electrically conductive transistor via connection 126 extends vertically through the semiconductor body 199 of the transistor chip 102, 104 between the opposing main surfaces, thereby electrically coupling a bottom-side transistor pad 122 (such as the gate pad 138 / 148) to a top-side transistor pad 124 (such as the gate pad 134 / 144), or vice versa. Thus, the electrically conductive transistor pads 122, 124 on both opposing main surfaces are electrically coupled to each other by the electrically conductive transistor via connection 126 extending vertically between the opposing main surfaces.This electrical coupling is realized with a very short electrically conductive path thanks to the vertical extension of the transistor via connection 126 through the transistor chip 102, 104 instead of being formed around it. In the embodiment shown, one transistor via connection 126 is provided, whereas at least two transistor via connections 126 are also possible. For example, an electrically conductive transistor via connection 126 may be embodied as a metal-filled via or as a metallic post or pillar. The metallic material may be inserted (for example, by plating or in the form of a preformed insert) into a vertical via opening extending between both opposing main surfaces of the semiconductor body 199 of the transistor chip 102, 104, thereby directly electrically coupling the transistor pads 122, 124 to each other.This can also contribute to a compact design, low signal losses and high signal quality of the Package 100.

[0085] It should be noted that the term "comprising" does not exclude other elements or features, and "a" or "an" does not exclude a plurality. Even elements described in connection with different embodiments may be combined. It should also be noted that reference numerals are not intended to limit the scope of the claims. Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

[1] A package (100) configured as a power stage, comprising: • a first transistor chip (102) and a second transistor chip (104) connected together to form a half-bridge; • a driver chip (106) configured to drive the first transistor chip (102) and the second transistor chip (104); and • an encapsulation (108) that at least partially encapsulates the first transistor chip (102), the second transistor chip (104) and the driver chip (106); • wherein the driver chip (106) has electrically conductive driver pads (110, 112), at least one of which is arranged on each of two opposite main surfaces of the driver chip (106), and at least one electrically conductive driver via (114) extending through the driver chip (106) between the opposite main surfaces. [2] The package (100) according to claim 1, comprising at least one of the following features: wherein the encapsulation (108) comprises a laminate having a plurality of laminated layers (116, 118); wherein the encapsulation (108) comprises a molding compound. [3] The package (100) of claim 2, wherein the first transistor chip (102), the second transistor chip (104) and the driver chip (106) are arranged in a core (120) of the laminate. [4] The package (100) according to any one of claims 1 to 3, wherein the first transistor chip (102), the second transistor chip (104) and the driver chip (106) are arranged on the same vertical plane side by side in the encapsulation (108). [5] The package (100) according to any one of claims 1 to 4, wherein at least a portion of the electrically conductive driver pads (110, 112) on both opposing main surfaces are electrically coupled to each other by at least one of the at least one electrically conductive driver vias (114). [6] The package (100) according to one of claims 1 to 5, comprising at least one of the following features: wherein at least one of the at least one electrically conductive driver vias (114) extends vertically or inclined between the opposing major surfaces; wherein at least one of the at least one electrically conductive driver vias (114) extends partially horizontally and partially vertically between the opposing major surfaces. [7] The package (100) according to any one of claims 1 to 6, wherein at least one of the at least one electrically conductive driver via (114) extends through semiconductor material of the driver chip (106). [8] The package (100) according to any one of claims 1 to 7, wherein at least one of the first transistor chip (102) and the second transistor chip (104) has electrically conductive transistor pads (122, 124) on both opposite main surfaces thereof and at least one electrically conductive transistor via connection (126) extending through the at least one of the first transistor chip (102) and the second transistor chip (104) between the opposite main surfaces. [9] The package (100) according to any one of claims 1 to 8, wherein at least one of the first transistor chip (102) and the second transistor chip (104) is a field effect transistor chip or a bipolar transistor chip. [10] The package (100) according to any one of claims 1 to 9, wherein the first transistor chip (102) has a first gate pad (134) and a first source pad (130) on an upper main surface and a first drain pad (132) on a lower main surface. [11] The package (100) of claim 10, wherein the first transistor chip (102) has a first sense pad (136) on the top major surface. [12] The package (100) of claim 10 or 11, wherein the first transistor chip (102) has a further first gate pad (138) on the lower main surface, and wherein the gate pad (134) and the further gate pad (138) of the first transistor chip (102) are electrically coupled to each other by an electrically conductive transistor via connection (126) extending through the first transistor chip (102) between the opposite main surfaces. [13] The package (100) according to any one of claims 1 to 12, wherein the second transistor chip (104) has a second gate pad (144) and a second source pad (140) on a lower main surface and a second drain pad (142) on an upper main surface. [14] The package (100) of claim 13, wherein the second transistor chip (104) has a second sensing pad (146) on the lower major surface. [15] The package (100) of claim 13 or 14, wherein the second transistor chip (104) has a further second gate pad (148) on the upper main surface, and wherein the second gate pad (144) and the further second gate pad (148) of the second transistor chip (104) are electrically coupled to each other by an electrically conductive transistor via connection (126) extending through the second transistor chip (104) between the opposite main surfaces. [16] The package (100) according to any one of claims 1 to 15, comprising a lower redistribution layer (150) extending under the first transistor chip (102), the second transistor chip (104) and the driver chip (106) and interconnecting at least a portion of the first transistor chip (102), the second transistor chip (104) and the driver chip (106). [17] The package (100) according to claims 1 to 16, comprising an upper redistribution layer (152) extending over the first transistor chip (102), the second transistor chip (104) and the driver chip (106) and interconnecting at least a portion of the first transistor chip (102), the second transistor chip (104) and the driver chip (106). [18] The package (100) according to claims 16 and 17, wherein the upper redistribution layer (152) and the lower redistribution layer (150) are electrically connected to each other by at least one of the at least one electrically conductive driver vias (114). [19] The package (100) according to any one of claims 1 to 18, wherein the first transistor chip (102) is a high-side switch and the second transistor chip (104) is a low-side switch. [20] A method of manufacturing a package (100) configured as a power stage, the method comprising: • Connecting a first transistor chip (102) and a second transistor chip (104) to form a half-bridge; • Configuring a driver chip (106) to drive the first transistor chip (102) and the second transistor chip (104); • at least partially encapsulating the first transistor chip (102), the second transistor chip (104) and the driver chip (106) by an encapsulation (108); and • Providing the driver chip (106) with electrically conductive driver pads (110, 112), at least one of which is arranged on each of two opposite main surfaces of the driver chip (106), and with at least one electrically conductive driver via connection (114) extending through the driver chip (106) between the opposite main surfaces.

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