Circuit for a CAM

Abstract

The invention relates to a circuit with a CMOS inverter and a variable resistor (R). fb ), where the variable resistance (R fb ) the entrance (V in ) of the CMOS inverter with the output (V out ) electrically connects the CMOS inverter. The invention also relates to a camera with such a circuit. This makes it possible to realize a circuit that can function both like an analog camera and like a digital camera.

Description

[0001] The invention relates to a circuit for a CAM, and in particular an analog Content Addressable Memory (aCAM).

[0002] CAM stands for "Content-Addressable Memory." Unlike conventional memory types such as RAM (Random Access Memory), where data is accessed via its memory address, CAM allows access to data based on its content. This means that specific data can be searched for in CAM without knowing its exact memory address. This is often referred to as "associative memory." It is possible to apply an input signal to a CAM. The input signal can be a voltage applied to the CAM, and thus an analog signal. The CAM can then output whether the input signal is stored or not. This can be done, for example, by outputting a "0" or a "1," i.e., by outputting a digital value. A CAM can therefore output the value "0" if the input value is not stored in the associative memory.A CAM can output the value "1" if the entered memory value is stored in the CAM.

[0003] From the publications "Can Li et al. 'Analog content-addressable memories with memristors'. In: Nature Communications 11.1 (Apr. 2020). DOI: 10.1038 / s41467-020-15254-4" and "Jinane Bazzi et al. Efficient Analog CAM Design. 2022. DOI: 10.48550 / ARXIV.2203.02500. URL: https: / / arxiv.org / abs / 2203.02500", an "analog CAM" (aCAM) is known in which input signals and stored data can be continuous analog values, not binary numbers. This aCAM outputs a "1" if an input signal matches stored data; otherwise, it outputs a "0".

[0004] From the publication “Giacomo Pedretti et al. “Differentiable Content Addressable Memory with Memristors”, Advanced Electronic Materials 8.8 (Mar. 2022), p. 2101198. DOI: 10.1002 / aelm”, a “differentiable analog CAM” (dCAM) is known which can also output values ​​between 0 and 1 to find partial matches and enable traceability within an aCAM system.

[0005] A CAM (Central Automation Module) can include a CMOS inverter. CMOS is a term for semiconductor devices that use both p-channel and n-channel MOSFETs on a common substrate. A CMOS inverter is an electronic component that can convert one signal format to another. Some CMOS inverters can convert an input voltage to a different output voltage and amplify it in the process. For example, such a CMOS inverter can convert a low input voltage to a higher output voltage, essentially multiplying it by a factor.

[0006] The present invention aims to provide a circuit for a CAM that improves the flexibility of the CAM. In particular, the circuit should enable the creation of a CAM that can exhibit the properties of both an aCAM and a dCAM. Such a CAM can, for example, selectively output either binary or analog values ​​in response to an applied analog input signal. Analog values ​​can indicate a measure of distance or a degree of agreement. Distance can express how far an applied input signal is from a value stored in the CAM, or how closely an applied input signal matches a stored value. The CAM can then, for example, selectively output the values ​​"0" and "1", but also values ​​between "0" and "1", such as "0.6" or "0.5".

[0007] To solve the problem, a circuit is provided. The circuit can include a CMOS inverter. The circuit can include a resistor. The resistor can be arranged so that the output signal of the circuit no longer changes abruptly depending on an input signal, as with a typical CMOS inverter, and thus can only output a "0" or "1". Instead, the output signal can change gradually as soon as the input signal exceeds a threshold. This can be achieved by electrically connecting the input of the CMOS inverter to the output of the CMOS inverter via the resistor. The circuit can also be configured so that the resistor can be changed. For example, the resistance can be changed by switching it back and forth between an output value and a very high final value.The resistance can be changed, for example, by a switch that can be opened and closed. The high-resistance output value can be such that the CMOS inverter behaves like a typical CMOS inverter. The switch can be configured so that the CMOS inverter behaves like a typical CMOS inverter when the switch is open. The output value can be such that the CMOS inverter behaves as described previously.

[0008] The output value can be, for example, at least 1 MΩ (megaohm), or at least 50 MΩ, or at least 100 MΩ, or at least 200 MΩ. The output value can be, for example, less than 500 MΩ or less than 300 MΩ. The final value can be, for example, at least 1 GΩ (gigaohm), or at least 50 GΩ, or at least 100 GΩ.

[0009] The circuit can therefore include a CMOS inverter with a resistive feedback path to modify the conversion of an input signal to an output signal. For example, the gain can be reduced by the CMOS inverter. This circuit makes it possible to create a CAM with greater flexibility. The circuit can support both high-resolution analog CAMs (aCAM) with sharp selection and differentiable CAMs (dCAM) with flat selection function margins for improved intra-cell distance metrics for gradient descent.

[0010] The gain achieved by the CMOS inverter also depends on the potentials V applied to the CMOS inverter. ss and V dd off. By applying voltage to the CMOS inverter as a difference of potentials V ss and V dd It can be determined how much the circuit can amplify an input signal at maximum strength. The potential V sscan be permanently 0 volts. The potential V dd can be permanently 1 volt.

[0011] For example, if a potential V ss = 0 volts and a potential V ddIf an input signal of 1 volt is applied, then the input signal can only be output in inverted form. If the input signal is 0 volts, then the output signal can be 1 volt. If the input signal is 1 volt, then the output signal can be 0 volts. The gain can be modulated around the value of 0.5 volts. If the input signal is 0.5 volts, then the output signal can be 0.5 volts. It is possible for the input signal to be 0.4 volts to produce an output signal of 0.6 volts. It is possible for the input signal to be 0.3 volts to produce an output signal of 0.7 volts. However, this modulation can be limited to the range around a specific value, such as 0.5 volts. Therefore, an input voltage of 0.2 volts might be too low to produce an output signal of less than 1 volt. Thus, an input voltage of 0.2 volts might result in an output voltage of 1 volt.

[0012] The modulation depends on the resistance value. The larger the resistance, the less abruptly an output signal can change from "0" to "1". If the resistance is very high, the circuit behaves like a typical CMOS inverter, which can convert one input voltage to another output voltage abruptly.

[0013] The input of the CMOS inverter can be electrically connected to a memristor. The memristor can be designed to store information. The circuit can therefore be configured and operated so that a voltage can be applied to the memristor to adjust its conductance. This voltage is also called a write voltage. Programming the memristor is then possible. For example, the memristor can be programmed by a digital signal, which can be converted into an analog voltage by a digital-to-analog converter. The memristor's conductance can then be programmed using this converted analog voltage.

[0014] The circuit can be configured and operated in such a way that a voltage can be applied to the memristor, allowing its conductance to be read. This voltage is also called a read voltage.

[0015] The input of the CMOS inverter can be electrically connected to a transistor. The transistor can act as a voltage divider, for example, to read the conductance value of the memristor. The transistor can also be part of a voltage divider.

[0016] The memristor can be electrically connected in series with the transistor.

[0017] The transistor could be an NMOS transistor.

[0018] The electrical connection provided by the variable resistor can be interrupted by a switch to change the electrical resistance. In a technically simple embodiment, the switch can be a transistor. Such a change creates a circuit that can operate both as an analog CAM and as a digital CAM.

[0019] The variable resistor can be configured to switch between a very high conductance and a comparatively low conductance. This allows for the creation of a circuit that can operate as both an analog and a digital CAM. The high conductance can be greater than 1 GΩ, and the low conductance can be less than 500 MΩ.

[0020] The circuit can be part of a CAM. In other words, a CAM comprises at least one circuit as previously described. A CAM can comprise two circuits as previously described. There can be exactly two such circuits. Three or more such circuits are excluded. Each circuit can have an identical layout to minimize the manufacturing effort.

[0021] The CAM can include two CMOS inverters, two memristors, and four other transistors.

[0022] The camera can comprise two sections, each of which can contain a circuit as described previously. Each section can have its own input for an input voltage. Each section can have its own output for an output voltage.

[0023] The input of one section can be connected to the input of the other section via an inverter.

[0024] The outputs of the two sections can be connected via a shared line. This shared line can be used to indicate a hit. This means that an analog voltage corresponding to a signal "0" or a signal "1" can be output via the shared line. Alternatively, a voltage corresponding to a signal between "0" and "1" can be output.

[0025] A CAM according to the invention can be part of a neural network in order to train the neural network. Using the CAM according to the invention, information can be obtained about how well a neural network is working.

[0026] The properties and behaviors of a neural network should resemble those of a biological neural network. A neural network should be able to recognize patterns using machine learning algorithms. Similar to the human brain, a neural network should not have to start from scratch for every task or problem. It should be able to draw on previously acquired knowledge and experience.

[0027] A neural network with memristors is known from publication CN 208922326 U. A circuit serving as a synapse for a neural network made of semiconductor materials with an electrically charged carrier gas is described in publication EP 0 529 565 B1. An integrated circuit for providing a synapse is known from publication US 2019164597 A1. A neural network can be implemented using conventional CMOS technology with a multitude of transistors. A neural network can also include ferroelectric field-effect transistors (FeFETs). The circuit according to the invention can be part of one of these neural networks.

[0028] The invention is explained in more detail below with the aid of figures. The figures show: Fig. 1: Circuit with a CMOS inverter and a variable resistor; Fig. 2: CMOS Inverter; Fig. 3: Design of the circuit Fig. 1; Fig. 4: Behavior of the output voltage relative to the input voltage of the circuit Fig. 3; Fig. 5: Implementation of a variable resistor; Fig. 6: further implementation of a variable resistor; Fig. 7: Circuit for computer simulation; Fig. 8: Result of the computer simulation; Fig. 9: State-of-the-art analog CAM; Fig. 10: Current-voltage characteristic curve of the CAM from Fig. 9; Fig. 11: analog CAM; Fig. 12: analog and digital CAM; Fig. 13: Current-voltage characteristic curve of the CAM from Fig. 12.

[0029] The Fig. Figure 1 shows a circuit 1 with a CMOS inverter with one input V in and an output V out The CMOS inverter comprises, as indicated by circuit symbols in the Fig. Figure 1 shows a p-channel MOSFET and an n-channel MOSFET. A potential V can be applied to the drain terminal D of the n-channel MOSFET of the CMOS inverter. SS A potential V can be applied to the drain terminal D of the p-channel MOSFET of the CMOS inverter. dd The maximum possible gain by the CMOS inverter is determined by the potential difference between the potentials V. SS and V dd fixed. In addition to the CMOS inverter, there is a variable resistor R. fb , which is entrance V in of the CMOS inverter with output V out of the CMOS inverter. With G are in the Fig. 1. The gate terminals of the two MOSFETs are labeled. S is used in the Fig. 1 the source terminals of the two MOSFETs are marked.

[0030] The resistance R fbIt is changeable because its conductance can be changed. There can be at least a first electrical conductance and a second electrical conductance. The resistance R fb It can then be switched so that it can selectively exhibit either the first or the second electrical conductance. It can be switched back and forth between the two conductances. One of the two conductances can correspond to the case where no electrically conductive connection is present, i.e., it is a typical CMOS inverter, such as the one in the Fig. 2 is shown.

[0031] The Fig. Figure 3 shows a further embodiment of a circuit with which a particularly flexible CAM can be created. In addition to the circuit 1, which is only shown schematically, this circuit includes a transistor 2 and a memristor 3. Transistor 2 can be a MOSFET. A conductance can be set for memristor 3. Transistor 2 and memristor 3 can be, as shown in the Fig. The memristor 3 shown can be connected in series. Fig. As shown in point 3, it should be connected to the drain terminal of transistor 2. If a voltage V is applied, DL When applied to the gate terminal of transistor 2, transistor 2 acts as a voltage divider. The applied voltage V DL can be chosen such that after applying the voltage V DLA read voltage is applied to transistor 2. The read voltage can be less than 0.7 V. Memristor 3 then acts like a fixed resistor. The voltage applied to input V in this way in The voltage applied to circuit 1 depends on the conductance of memristor 3. Circuit 1 then outputs V at its output. out a voltage is generated that depends on the set conductance of the resistor R fb depends. Is the conductance R fb If the resistance is very high and lies, for example, in the GΩ range, then V will be at the output. out Basically, a minimum voltage of, for example, 0 volts or a maximum voltage of, for example, 1 volt is output. This corresponds to a "0" or a "1" as information. Is the conductance R fb If the resistance is not very high and is, for example, a few hundred MΩ, a voltage can be output that lies between the minimum and the maximum of the voltages that are present at output V. outcan be output. A measure can be output as information that lies between "0" and "1" and can therefore be considered analog information. It is therefore possible to create a CAM using this circuit that can function like both an aCAM and a dCAM.

[0032] The Fig. Figure 4 shows the behavior of the voltage at output V. out depending on the input V DL applied voltage. Is the resistance R fb very high impedance, then the voltage at the output V jumps out The output voltage ranges from a minimum voltage value according to curve 4 to a maximum voltage value, thus providing purely digital information as soon as the voltage at input V is reached. DL applied voltage a limit value V DL_bound exceeds the resistance R fbIf the resistance is not very high, then medium voltage values ​​according to curve 5 are possible, and thus an analog information can be output at output V. out of the CMOS inverter.

[0033] The Fig. Figure 5 shows an implementation of variable resistance R fb , which can be changed. The variable resistance R fb The circuit includes an ohmic resistor 6, which can have a conductance of several hundred MΩ. A transistor 7 can be used to enable or interrupt the current flow through the ohmic resistor 6. This allows switching between two different states.

[0034] The Fig. Figure 6 shows another implementation of a variable resistor. It is a circuit for implementing a controllable, high-value MOS impedance. The operation of this high-value CMOS circuit is explained in more detail in the publication "Armin Tajalli, Yusuf Leblebici, and Elizabeth Brauer. 'Implementing Ultra-high-Value Floating Tunable CMOS Resistors', Electronics Letters 44 (Feb. 2008). DOI: 10.1049 / el:20082538". By applying potentials V ss and V dd The resistor is switched. The resistor can be configured to switch between a conductance on the order of, for example, 100 MΩ to 500 MΩ and a conductance of, for example, more than 1 GΩ. These conductances occur between contacts 1 and 2. Contacts 1 and 2 are the terminals "-" and "+" that are connected in the Fig. 2 of the aforementioned publication will be shown.

[0035] The influence of the resistance R was determined using a computer simulation. fb checked. Fig. Figure 7 shows the circuit used for the computer simulation. The resistive resistor R1 simulates the memristor 3. The resistive resistor R2 simulates the variable resistor R. fb . The Fig. Figure 8 shows the result of the computer simulation. Two different values ​​for R1 were simulated for the conductance of memristor 3. The simulation showed that changing the conductance of memristor 3 shifts the family of curves along the Vdl axis from approximately 0.6 V to approximately 0.8 V. Therefore, by adjusting the conductance of memristor 3, the VDL-bound threshold can be set, which determines when a jump from the information "0" to the information "1" is possible.

[0036] For the resistor R fb Four different conductance values ​​were simulated: 5 MΩ, 10 MΩ, 23 MΩ, and 50 MΩ. The higher the conductance value for R, the morefb The more the curve resembled that of a typical CMOS inverter with a sudden increase in voltage at output V out The output is generated as soon as the applied voltage Vdl exceeds a limit value. This is determined by the conductance of the resistor R. fb It is therefore possible to adjust how steep the jump from information "0" to information "1" is.

[0037] The conductance value of the in the Fig. The memristor 3 shown can be modified as follows. First, a high voltage can be applied to terminal V. SL+AE The memristor's voltage is applied, and this voltage is chosen to be high enough to reset the memristor. At terminal V SL+OE Following the reset of memristor 3, a voltage high enough can be applied to transistor 2 to reset the memristor using a connection to terminal V. DL to be able to describe the applied voltage.

[0038] The memristor 3 can be used to store information. The conductance of the memristor 3 can be programmed. A programmed conductance of the memristor 3 encodes a voltage and thereby stores information. Using a circuit according to the invention, it can be checked whether an applied voltage V DL the encoded voltage corresponds to this. The operating principle is explained in more detail in the publication "Can Li et al. 'Analog content-addressable memories with memristors' In: Nature Communications 11.1 (Apr. 2020). DOI: 10.1038 / s41467-020-15254-4". The circuit known from this publication is described in the Fig. This printed document shows that this circuit consists of six transistors and two memristors. The circuit shown in the Fig. The circuit shown in this publication compares an analog input signal with a stored range defined by upper and lower limits. The upper limit is determined by the conductance of one memristor. The lower limit is determined by the conductance of the other memristor. The circuit outputs whether a match with the range has been found or not. Fig. This publication provides an example of a result depending on an applied input voltage V. DL shown. A match, and therefore a "1", is output when the current I MLStarting from a value of 0.34 µA, the current jumps to 0 µA. A disadvantage for determining the range is that the falling edge deviates significantly from a vertical. It can therefore be difficult to clearly distinguish between a match and a mismatch. This negatively impacts the storage density. The lack of symmetry between the rising and falling edges is also unfavorable. To obtain a more favorable current-voltage characteristic, a circuit including additional inverter stages is proposed in the publication "Jinane Bazzi et al. Efficient Analog CAM Design. 2022. DOI: 10.48550 / ARXIV.2203.02500. URL: https: / / arxiv.org / abs / 2203.02500". This circuit comprises ten transistors and two memristors. In this case, both the falling and rising slopes are very steep. This allows for a high storage density.However, an asymmetric relationship between the rising and falling flanks still exists.

[0039] In the Fig. Figure 11 shows a circuit with a further improved current-voltage characteristic. This circuit is an aCam and is an independent invention. The circuit comprises two memristors 8 and 9, two CMOS inverters 10 and 11, and four additional transistors 12, 13, 14, and 15. The circuit thus includes two memristors and eight transistors.

[0040] Section 17 of the circuit comprises the memristor 8, the CMOS inverter 10, and the two transistors 12 and 13. This section 17 is identical to section 18, which comprises the memristor 9, the CMOS inverter 11, and the two transistors 14 and 15. The circuit is further configured such that a voltage V is applied to section 17. DL LB can be applied as an input signal and a voltage V can be applied to section 18 DL HB .

[0041] The circuit can include an inverter 16 which takes an applied input voltage V DL inverted. A voltage V can be applied to the first section 17. DL are applied, which are connected to the voltage V DL LB is identical. An inverted voltage can be applied to the second section 18 by means of the inverter 16. VDL¯ outputs are those with the voltage V DL HB is identical.

[0042] The inversion ensures that the second section 18 refers to the rising flank. The first section 17 refers to the falling flank. In the Fig. 11 this is represented by the designations V DL LB and V DL HBThis is expressed by "LB" denoting a "low bound" and "HB" an "upper bound". The inversion also allows sections 17 and 18 to be identical. This not only simplifies the layout but also ensures that the rising and falling edges are symmetrical.

[0043] Inverter 16 can include a digital inverter. Inverter 16 can include an analog-to-digital converter that outputs a voltage V. DL The digital signal is digitized. The digital signal can be inverted by the digital inverter. Subsequently, the inverted digital signal is converted into an analog voltage by a digital-to-analog converter. Inverter 16 can be an analog inverter, such as an operational amplifier.

[0044] The inclusion of an inverter 16 is not strictly necessary. The only requirement is that a voltage V is applied to the first section 17.DL LB can be applied and a suitably inverted voltage V can be applied to the second section 18. DL HB For example, the circuit can be digitally controlled as follows. A voltage V can be applied. DL LB a digital signal is applied to the first section 17. This digital signal can be used to control an analog-to-digital converter (ADC) so that the ADC outputs the voltage V. DL LB applied to the first section 17. A voltage V can be applied. DL HB a digital signal is applied to the second section 18. This digital signal can be used to control an analog-to-digital converter (ADC) so that the ADC outputs the voltage V. DL HB attached to the second section 18. This allows the voltage V to be increased. DL HB so in comparison to the voltage V DL LBThe inversion is such that the first section 17 refers to the falling flank and the second section 18 to the rising flank.

[0045] The conductance of the first memristor 8 therefore defines a lower limit for a stored range. The conductance of the second memristor 9 defines an upper limit for a stored range.

[0046] The circuit can include a conductor track ML (“match line”) via which results from sections 17 and 18 can be output. Potentials V can be connected to sections 17 and 18 together via corresponding conductor tracks. SL+OE and V SL+AE to be set up for operation.

[0047] This independent invention makes it possible to achieve edges as steep as those of the described aCam with its two memristors and 10 transistors. Advantageously, however, the edges are now symmetrical. This can offer further advantages in applications. For example, it can lead to improved results in machine learning.

[0048] The one in Fig. The circuit shown in Figure 11 is not a CAM that can be operated not only like an aCAM but also like a dCAM. To achieve this, for example, the circuit shown in the Fig. 1 circuit shown in the Fig. The circuit shown in section 11 can be integrated. A circuit created in this way will be used in the Fig. 12 shown.

[0049] The Fig. Figure 13 shows current-voltage characteristic curves that correspond to the one in the Fig. The circuit shown in section 12 can be achieved, depending on the resistance R. fB It can be seen that symmetrical current-voltage characteristics can be obtained. The falling edge is symmetrical to the rising edge. The behavior of a dCAM can be achieved with such current-voltage characteristics. Is the resistance R fB sufficiently large, so the one in the Fig. 12 circuits shown, like the one in the Fig. 11 shown circuit, i.e., like an aCAM.

[0050] The variable resistance R FB can during the Fig. The resistance in the circuit shown in Figure 12, for example, can be 800 Ω so that the CAM can operate like an analog CAM. The variable resistor R FB For example, it can be 10 GΩ or more so that the CAM can operate like a digital CAM. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] CN 208922326 U

[0027] EP 0 529 565 B1

[0027] US 2019164597 A1

[0027] Cited non-patent literature

[0000] Can Li et al. “Analog content-addressable memories with memristors”. In: Nature Communications 11.1 (Apr. 2020). DOI: 10.1038 / s41467-020-15254-4

[0003] Jinane Bazzi et al. Efficient analog CAM design. 2022. DOL: 10.48550 / ARXIV.2203.02500. URL: https: / / arxiv.org / abs / 2203.02500

[0003] Giacomo Pedretti et al. „Differentiable Content Addressable Memory with Memristors“, Advanced Electronic Materials 8.8 (Mar. 2022), p. 2101198. DOI: 10.1002 / aelm

[0004] Armin Tajalli, Yusuf Leblebici, and Elizabeth Brauer. „Implementing Ultra-high-Value Floating Tunable CMOS Resistors“, Electronics Letters 44 (Feb. 2008). DOI: 10.1049 / el:20082538

[0034] Can Li et al. „Analog content-addressable memories with memristors“ In: Nature Communications 11.1 (Apr. 2020). DOI: 10.1038 / s41467-020-15254-4

[0038] Jinane Bazzi et al. Efficient Analog CAM Design. 2022. DOI: 10.48550 / ARXIV.2203.02500. URL: https: / / arxiv.org / abs / 2203.02500

[0038]

Claims

[1] Circuit with a CMOS inverter (10, 11) and a variable resistor (R fb ), where the variable resistance (R fb ) the entrance (V in ) of the CMOS inverter (10, 11) with the output (V out ) of the CMOS inverter (10, 11). [2] Circuit according to the preceding claim, characterized by that the entrance (V in ) of the CMOS inverter (10, 11) is electrically connected to a memristor (3, 8, 9). [3] Circuit according to one of the preceding claims, characterized by that the entrance (V in ) of the CMOS inverter (10, 11) is electrically connected to a transistor (2, 12, 14). [4] Circuit according to the two preceding claims, characterized by that the memristor (3, 8, 9) is electrically connected in series with the transistor (2, 12, 14). [5] Circuit according to one of the three preceding claims, characterized bythat the transistor (2, 12, 14) is an NMOS transistor. [6] Circuit according to one of the preceding claims, characterized by that the resistance (R fb ) provided electrical connection can be interrupted by a switch. [7] Circuit according to the preceding claim, characterized by that the switch is a transistor (7). [8] Circuit according to one of the preceding claims, characterized by that the variable resistance (R fb ) is designed so that it can be switched back and forth between a very high-impedance conductance and a comparatively low-impedance conductance. [9] Circuit according to the preceding claim, characterized by that the high-impedance conductance is more than 1 GΩ or at least 10 GΩ and the low-impedance conductance is less than 1 GΩ or less than 500 MΩ. [10] Circuit according to one of the preceding claims, characterized bythat the circuit is part of a neural network. [11] Circuit according to one of the preceding claims, characterized by that the circuit is part of a CAM. [12] Circuit according to the preceding claim, characterized by that the CAM comprises two CMOS inverters (12, 14), two memristors (8, 9) and four further transistors (12, 13, 14, 15). [13] Circuit according to one of the two preceding claims, characterized by that the cam comprises two identical sections (17, 18), each section comprising a circuit having the features of claim 4 and each section having its own input for an input voltage (V DL LB , V OL HB ) has. [14] Circuit according to the preceding claim, characterized by that the input of one section (17) is connected to the input of the other section (18) via an inverter (16). [15] Circuit according to one of the two preceding claims, characterized by that the outputs of the two sections (17, 18) are connected to a shared line (ML).

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