Method for manufacturing a gallium oxide power transistor and gallium oxide power transistor

Abstract

Method (100) for manufacturing a gallium oxide power transistor comprising the steps: • Generating (101) a drift layer on a highly n-doped gallium oxide substrate by means of epitaxy, • Applying (102) a structured mask to the drift layer, wherein the structured mask comprises material having a low diffusion constant for nitrogen ions, • Generation (104) of gallium nitride complexes with a specific diffusion depth of nitrogen ions from the surface of the drift layer into the drift layer by means of a plasma process, • Removing (105) the structured mask, and • Completion (106) of the gallium oxide power transistor.

Description

State of the art

[0001] The invention relates to a method for producing a gallium oxide power transistor and a gallium oxide power transistor.

[0002] Power transistors based on gallium oxide (Ga2O3) exhibit a high breakdown field strength. A disadvantage is the lack of effective acceptor dopants for p-type doping of this semiconductor using conventional semiconductor processes. However, it is technically possible to create gallium nitride complexes in the gallium oxide substrate that exhibit similar properties to p-type doping, namely the creation of inversion channels in a MOS complex and the blocking of voltages. These gallium nitride complexes are created by implantation. The disadvantage is that the gallium oxide crystal structure is destroyed, and thermal processes are required to restore it, whereby some of the introduced nitrogen ions are expelled.

[0003] The object of the invention is to overcome these disadvantages. Disclosure of the invention

[0004] The inventive method for producing a gallium oxide power transistor comprises generating a drift layer on a highly n-doped gallium oxide substrate by epitaxy and applying a patterned mask to the drift layer, wherein the patterned mask comprises material that has a low diffusion constant for nitrogen ions. The method further comprises generating gallium nitride complexes with a specific diffusion depth of nitrogen ions starting from the surface of the drift layer into the drift layer by means of a plasma process, removing the patterned mask, and completing the gallium oxide power transistor.

[0005] The advantage here is that the gallium oxide crystal structure remains intact.

[0006] In a further development, further gallium nitride complexes are produced in one step by means of ion implantation.

[0007] The advantage here is that deep gallium nitride complexes are also created, which exhibit properties similar to p-type doping, while simultaneously avoiding damage to the gallium oxide crystal structure near the surface. Furthermore, the subsequent plasma process compensates for the proportion of expelled nitrogen ions resulting from the activation of the implanted nitrogen atoms.

[0008] In a further embodiment, the specific diffusion depth of the nitrogen ions is adjusted by means of a temperature to which a holding device is heated on which the highly n-doped gallium oxide substrate is arranged.

[0009] The advantage here is that the depth of the gallium nitride complexes can be controlled.

[0010] In a further development, the specific diffusion depth is set by applying a voltage to the holding device.

[0011] The advantage here is that the temperature required to achieve the specific diffusion depth can be reduced, since a high temperature can otherwise lead to decomposition of the gallium oxide surface.

[0012] In a further embodiment, the plasma process is carried out using a remote plasma process.

[0013] The advantage here is that plasma damage to the surface of the drift layer is avoided.

[0014] In a further development, the material of the structured mask comprises SiN or AlN.

[0015] The advantage here is that both mask materials have very low diffusivity for nitrogen ions.

[0016] A vertical gallium oxide MOSFET according to the invention is manufactured using the method according to the invention.

[0017] A gallium oxide FinMOSFET according to the invention is manufactured using the method according to the invention.

[0018] Further advantages arise from the following description of embodiments and the dependent patent claims. Short description of the drawings

[0019] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. They show: Fig. 1 the inventive method for producing a gallium oxide power transistor, Fig. 2 the result of process step 104, Fig. 3 the vertical gallium oxide MOSFET according to the invention, and Fig. 4 the gallium oxide FinMOSFET according to the invention.

[0020] Fig. 1 shows the inventive method 100 for producing a gallium oxide power transistor. The method 100 starts with step 101, in which a drift layer is created on a highly n-doped gallium oxide substrate by means of epitaxy. In a subsequent step 102, a patterned mask is applied to the drift layer, wherein the patterned mask comprises material that has a low diffusion constant for nitrogen ions. A low diffusion constant is defined as values ​​less than 1e-15 cm. 2 / s. The material of the structured mask comprises, for example, SiN or AlN. In a subsequent step 104, gallium nitride complexes with a specific diffusion depth of nitrogen ions are generated by means of a plasma process, starting from a surface of the drift layer down into the drift layer. The specific diffusion depth can be influenced, for example, by the temperature of the holding device on which the gallium oxide substrate is arranged. Alternatively or additionally, a voltage, a so-called bias voltage, can be applied to the holding device. The ions generated in the plasma are accelerated onto the gallium oxide substrate, i.e. the voltage can control the acceleration and thus the diffusion depth. The plasma process is, for example, a remote plasma process.The plasma comprises nitrogen ions N+ with a nitrogen atmosphere between 1 and 100 mTorr and is, for example, an RF plasma with a frequency of 13.56 MHz and a power in the range between 200 W and 2000 W, with the gallium oxide substrate having a temperature between 300 °C and 800 °C. In a subsequent step 105, the patterned mask is removed. In a subsequent step 106, the gallium oxide power transistor is completed.

[0021] In an optional step 103, which can be performed between steps 102 and 104, additional gallium nitride complexes are created by ion implantation. The near-surface GaN complex is created by the plasma process, and the deeper sections are created by ion implantation.

[0022] The method according to the invention is used, for example, to manufacture vertical gallium oxide MOSFETs or gallium oxide FinMOSFETs, which can be used in the electric drivetrain of electric or hybrid vehicles. They are primarily used as DC / DC converters or inverters, and as chargers.

[0023] The process according to the invention can be used to manufacture power transistors such as trench MOSFETs, superjunction MOSFETs, JFETs, and lateral MOSFETs based on gallium oxide. It can also be used to manufacture MPS or JBS diodes based on gallium oxide.

[0024] Fig. 2 shows the result 200 after performing step 104 of the method according to the invention. Shown is a highly doped drain terminal 201 on which a drift layer 202 is arranged. The structured mask 204 is arranged on the drift layer 202. The structured mask 204 comprises a material with a low diffusion constant for nitrogen ions. The material comprises, for example, SiN or AlN. Gallium nitride complexes 203 extend from a surface of the drift layer 202 into the drift layer 202. Due to the low diffusion constant of the material of the structured mask 204, the gallium nitride complexes 203 are located in some regions below the structured mask 202.

[0025] Fig. 3 shows the vertical gallium oxide MOSFET 300 according to the invention, which is manufactured using the method according to the invention. The gallium oxide MOSFET 300 has a heavily n-doped gallium oxide layer 301, on which a lightly n-doped gallium oxide drift layer 302 is arranged. Gallium nitride complexes 303 are arranged within the drift layer, which, in conjunction with the gallium oxide, would have properties similar to a p-doped gallium oxide. The gallium nitride complexes 303 create inversion channels in the MOS complex of the gallium oxide MOSFET 300 and block voltages. The gallium nitride complexes 303 can therefore also be referred to as inversion layers. Heavily n-doped gallium oxide regions 304 are arranged within the gallium nitride complexes 303 or the inversion layers. Above the gallium nitride complexes 303 and the gallium oxide regions 304, a gate dielectric 305 is arranged in regions on the surface of the drift layer 302.A gate electrode 306 is located on the gate dielectric 305. The gallium nitride complexes 303 and the gallium oxide regions 304 are electrically connected in regions to a source electrode 308. The gate electrode 306 and the source electrode 308 are electrically separated from each other by an insulation layer 307. A drain electrode 309 is arranged below the heavily n-doped gallium oxide layer 301.

[0026] Fig.4 shows the gallium oxide FinMOSFET 400 according to the invention, which is manufactured using the method according to the invention. The gallium oxide FinMOSFET 400 has a heavily n-doped gallium oxide layer 401, on which a lightly n-doped gallium oxide drift layer 402 is arranged. The drift layer 402 has a semiconductor fin with a width of less than 500 nm. The semiconductor fin comprises gallium nitride complexes 403 and a heavily n-doped layer 404. A gate dielectric 405 is arranged laterally adjacent to the semiconductor fin. A gate electrode 406 is arranged on the gate dielectric 405. The gallium nitride complexes 403 and the gallium oxide regions 404 are electrically connected in regions to a source electrode 408. The gate electrode 406 and the source electrode 408 are electrically separated from each other by an insulation layer 407. A drain electrode 409 is arranged below the heavily n-doped gallium oxide layer 401.Further gallium nitride complexes 410 can be arranged below the gate dielectric 405. They serve to shield against high electric fields in the off-state condition.

Claims

[1] A method (100) for manufacturing a gallium oxide power transistor comprising the steps of: • Creating (101) a drift layer on a highly n-doped gallium oxide substrate by epitaxy, • Applying (102) a structured mask to the drift layer, wherein the structured mask comprises material having a low diffusion constant for nitrogen ions, • Generation (104) of gallium nitride complexes with a specific diffusion depth of nitrogen ions starting from the surface of the drift layer into the drift layer by means of a plasma process, • Removing (105) the structured mask, and • Completion (106) of the gallium oxide power transistor. [2] Method according to claim 1, characterized by that in a step (103) the further gallium nitride complexes are produced by ion implantation. [3] Method (100) according to claim 1 or 2, characterized bythat the specific diffusion depth of the nitrogen ions is adjusted by means of a temperature to which a holding device is heated on which the highly n-doped gallium oxide substrate is arranged. [4] Method (100) according to claim 3, characterized by that the specific diffusion depth is adjusted by applying a voltage to the holding device. [5] Method (100) according to one of the preceding claims, characterized by that the plasma process is carried out using a remote plasma process. [6] Method (100) according to one of the preceding claims, characterized by that the material of the structured mask comprises SiN or AlN. [7] A vertical planar gate gallium oxide MOSFET (300) fabricated by a method according to any one of claims 1 to 6. [8] Gallium oxide FinMOSFET (400) manufactured by a method according to any one of claims 1 to 6.

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