Method for manufacturing semiconductor devices from a wafer using a carrier wafer

Abstract

The invention relates to a method for manufacturing semiconductor devices, in particular power semiconductor devices, from a wafer, comprising the steps of: Providing a wafer substrate (101), Processing a structured wafer surface (102), Applying a carrier wafer (103) to the wafer substrate (101), and Reduction of the thickness of the wafer substrate (101) by wafer thinning.

Description

Technical area

[0001] The invention relates to a method for producing semiconductor components from a wafer using a carrier wafer, in particular a carrier wafer applied by means of a dam-and-fill process step. State of the art

[0002] To manufacture a power semiconductor or semiconductor chip, a wafer made of silicon (Si), silicon carbide, or sapphire with a diameter of, for example, 150mm, 200mm, or 300mm is generally processed over several individual steps. In the manufacture of products in the field of MEMS and power semiconductor technologies, it is common practice to bond substrates to the wafer, for example to support very thin grinding of the wafer for performance reasons during the manufacturing process. The provision of a temporary carrier wafer made of a robust material such as quartz or silicon carbide serves, among other things, to mechanically stabilize and simplify handling of the wafer during processing. Furthermore, wafer bending, or what is known as wafer bow, can be minimized.In particular, wafers with deep trench structures or thick passivations and metallizations, which are the cause of the wafer bow, can hardly be processed without a carrier wafer in chip thicknesses of less than 150µm.

[0003] A disadvantage of the known processes is that the extreme thinning of wafers and substrates made of a wide variety of materials or the multiple bonding (wafer stacks) results in enormous stresses, especially in connection with thick layers such as metals, passivations and the deep trenches commonly used in power semiconductor technology, which makes the substrates so fragile that they cannot be further processed or can only be processed with great effort. Disclosure of the invention

[0004] The invention relates to a method for producing semiconductor components, in particular power semiconductor components, from a wafer, comprising the steps: - Providing a wafer substrate, - Processing a structured wafer surface, - Applying a carrier wafer to the wafer substrate, and reducing a thickness of the wafer substrate by wafer thinning, wherein according to the invention the application of the carrier wafer to the wafer surface is carried out by a dam-and-fill process step.

[0005] Advantageous developments of the method according to the invention for producing a plurality of semiconductor components from a wafer are set out in the subclaims.

[0006] By applying the carrier wafer to the wafer surface according to the invention using a dam-and-fill process, a wafer-stabilizing carrier layer can be applied very effectively to the fully processed wafer front side, thereby mechanically stabilizing the wafer in subsequent process steps, particularly during wafer thinning to reduce the substrate thickness. In addition to a simple application process, the provision of the carrier wafer according to the invention compensates for stresses in the system. In contrast to purely additively manufactured carrier layers, a significantly higher filled layer thickness can be applied, which offers significant advantages with regard to shrinkage behavior during curing and with regard to a possible CTE mismatch between the carrier system and the wafer.The printed carrier layer also serves as an insulator, reducing the risk of electrical flashover during electrical testing at breakdown voltages of up to approximately 1600V, thus allowing the use of a multiple test head for higher test speeds. Furthermore, compared to other existing carrier technologies, the carrier can remain on the wafer until the final process step of wafer dicing or dividing the wafer into individual semiconductor components. This significantly simplifies handling of the thin wafers in the final process sequences, increases processability, and reduces defect costs. The method according to the invention thus enables optimized process control and more reliable production of semiconductor components.

[0007] The dam-and-fill process step advantageously comprises applying at least one delimiting frame or edge structure in the form of a dam surrounding a volume with a predefined height using conventional digital printing technology, as well as filling the resulting volume or volume delimited by the frame structure with a filling material, preferably using a conventional dispensing process or dispensing step. The frame structure and the filling can be cured individually or together in a conventional manner, for example, using UV or thermal curing.

[0008] The application of the ink to provide the dam or frame structure can be carried out in a conventional manner using a suitable print head that is arranged to be movable relative to the wafer surface or a work surface supporting the wafer. This step advantageously comprises the application of an organic or inorganic ink and subsequent curing. An organic, for example polymer-based, or inorganic ink is advantageously printed onto the finished structured wafer surface with a preferred layer thickness of 5 to 25 µm. The ink can advantageously contain organic and / or inorganic, e.g., mineral or ceramic, fillers to improve the thermal and mechanical properties.

[0009] Advantageously, a filler material, preferably with low shrinkage and a low coefficient of thermal expansion (CTE), is poured into the volume defined by the frame structure as a carrier layer using a conventional dispensing step. The filler material can then be leveled and / or cured using a leveling process such as vibration or ultrasound.

[0010] The resulting carrier wafer serves as a mechanical support during back-thinning and backside metallization, as well as the handling processes in between. It does not deform, is suitable for high vacuum, and is temperature-stable. The carrier wafer can be removed before or during a wafer singulation process using a wafer saw or a laser. Detachment of the carrier wafer can occur, for example, in a water or solvent bath and / or by adding additives. Alternatively, the carrier wafer can be removed by thermal or optical stimulation.

[0011] The application of the carrier wafer can comprise several dam-and-fill process steps for the application of several superimposed layers, which are applied sequentially and each subsequently cured. Advantageously, the application is carried out in such a way that a carrier wafer with a layer thickness of 5 to 500 µm is provided.

[0012] The dam-and-fill process step can advantageously comprise the application of at least one frame structure surrounding a metallization area of ​​the wafer surface to provide openings in the fill material. Within an outer frame structure, an additional inner frame structure surrounding the respective metallization area can be applied or printed as a dam before a volume located between the frame structures is filled in the dam-and-fill process. As a result, the respective metallization area is not covered by the carrier wafer, so that the wafer can be electrically contacted and tested during the subsequent process. This allows the wafer to continue to be tested both after back-thinning and after sputtering of the backside metallization.

[0013] Further advantageously, the openings provided in the filler material of the carrier wafer can be filled or printed using a separate, removable filler or support material, preferably during the dam-and-fill process step and using digital printing technology. This can improve the contour sharpness of the carrier wafer in the area of ​​the openings, allowing smaller openings to be realized, especially with thicker layers. The support material can be removed again after the carrier wafer has been applied, for example, in a water or solvent bath, or with the aid of thermal stimulation.

[0014] Furthermore, the method can advantageously comprise a selective removal of the filler material, in which a metallization area arranged on the wafer surface is exposed from the filler material of the carrier wafer arranged above it. In this case, the applied filler material can be selectively removed in the region of a metallization area, for example by means of laser irradiation, such that it can be electrically contacted and tested during the further process.

[0015] Advantageously, the method can include a leveling step after the application of the printed carrier wafer, in which a predefined and preferably uniform layer thickness of the carrier wafer is created or achieved on the wafer surface. This can be done, for example, with a doctor blade. In particular, excess ink can be removed or the surface of the applied layer(s) can be smoothed.

[0016] Advantageously, during the dam-and-fill process step, a frame structure and / or a filler material is applied to an outer rounded area of ​​the wafer substrate in such a way that the rounded area is leveled and, in particular, leveled with a surface of the wafer substrate. This allows a rounded edge area to be leveled and a flat carrier wafer to be applied closer to the edge area. In particular, this avoids the risk of chipping during the re-thinning process, since otherwise, no counterpressure can be applied by the carrier wafer in these areas.

[0017] Further advantageously, the method can comprise applying a water-soluble support layer, preferably laterally delimited by a previously applied frame structure, to the wafer surface before applying a filler material to the carrier wafer. This support layer can be detached or removed by the process fluid during a singulation process, thereby also enabling simplified detachment of the singulated carrier wafer layers from the individual semiconductor components.

[0018] Further advantageously, the method can also include applying an abrasive film over the carrier wafer, which in particular covers openings arranged therein. This can prevent premature dissolution of the support layer during the wafer thinning or re-thinning process, which also involves the use of process fluids.

[0019] According to the invention, the step of applying the carrier wafer takes place before wafer thinning or a wafer re-thinning process, in which the wafer is reduced from its original wafer thickness to a component thickness desired or necessary for the subsequent application of the semiconductor components or chips. Depending on the specific requirements of the manufacturing process and the desired wafer thickness, this can be done, for example, by grinding, chemical mechanical polishing (CMP), or etching. In a preferred embodiment, the wafer is re-thinned to a thickness of less than 300 µm, more preferably to less than 200 µm, and even more preferably to less than 150 µm.

[0020] Furthermore, the invention relates to a semiconductor component, in particular a power semiconductor component, which is or can be produced by the method described above.

[0021] Further advantages and details of the invention will become apparent from the following description of preferred embodiments of the invention and from the drawings which are only schematically illustrated. Short description of the drawings Fig. 1a-e show process steps of a first preferred embodiment of the process according to the invention by means of schematic side views of the wafer, Fig. 2a-c show process steps of a further preferred embodiment of the process with application of a separate, soluble support layer, Fig. 3a-c show detailed views of the application of the carrier wafer to an edge region of the wafer. Embodiments of the invention

[0022] Identical elements or elements with the same function are provided with the same reference numbers in the figures.

[0023] As in Fig. As shown in Figure 1a, a wafer substrate 101, for example, consisting of silicon (Si), silicon carbide (SiC), or gallium nitride (GaN), is first provided as the basis for processing the semiconductor components to be formed on the wafer. In a conventional manner, the desired or process-specified layers and structures 102 for producing semiconductor components such as transistors, diodes, or integrated circuits are then formed on a wafer substrate surface.

[0024] As in Fig. 1b and Fig. As shown in Figure 1c, the next step involves applying a carrier wafer 103 to the wafer substrate 101 using a dam-and-fill process step. First, a dam or frame structure 103a, 103b made of an organic or inorganic ink with a typical layer thickness of 5-25 µm and a preferred wall thickness of preferably 50 to several hundred µm is printed onto the fully processed wafer surface, preferably using digital printing technology or inkjet technology. The ink is cured or sintered during printing or after printing a layer (e.g., by UV or thermal means).

[0025] After printing, a leveling step can optionally be performed, for example, using a squeegee, to create layers that are as flat as possible. To achieve larger layer thicknesses, e.g., in the range of 50–500 µm, this process is repeated several times, similar to conventional inkjet-based 3D printing. Optionally, after printing the respective layers, a final curing or sintering step is performed to achieve complete crosslinking and improve the mechanical properties. The ink preferably contains organic and / or inorganic fillers, e.g., mineral or ceramic, to improve the thermal properties.

[0026] Subsequently, a volume 104 defined by the frame structure is filled with highly filled filler material 105 by dispensing. The filler material can be an underfill material or be formed as a globe top and advantageously exhibits low shrinkage and a low coefficient of thermal expansion (CTE). The filler material can then be leveled using a leveling process such as vibration or ultrasound.

[0027] The filler material 105 is preferably introduced in such a way that openings 107 remain free for metallization areas 106 of the wafer. For this purpose, the applied frame structure preferably comprises an inner frame structure 103b, which surrounds one or more metallization areas 106 of the structured wafer surface 102.

[0028] Optionally, a removable filling material or support material 108 can be applied and, in particular, printed in the area of ​​the openings 107 in parallel with the application of the carrier wafer 103. This is shown in Fig. 1b shows the right opening as an example. This allows the contour sharpness of the carrier wafer 103 to be improved in the area of ​​the openings 107, allowing smaller openings to be realized, especially with thicker layers. The support material 108 can be removed again after printing the carrier wafer 103, for example, in a water bath, solvent bath, or by thermal stimulation.

[0029] As in Fig. As shown in Figure 1d, an abrasive film 101 can optionally be applied to the front side of the wafer before a re-thinning step of the wafer substrate 101.

[0030] As in Fig. As shown in Figure 1e, the method comprises the further step of back-thinning or wafer thinning, in which the wafer substrate 101 is reduced to a predefined thickness. The back-thinning can be carried out, for example, by grinding with a suitable abrasive 112. In a preferred embodiment, the wafer is back-thinned to a thickness of less than 300 µm, preferably less than 200 µm, more preferably less than 150 µm. After the back-thinning process, the optionally applied abrasive film 101 can be removed, and a metal contact can be applied to the back of the wafer.

[0031] In a subsequent manufacturing step (not shown), the wafer substrate 101 can be separated or singulated into individual semiconductor components.

[0032] As an alternative to the previously described embodiment, the method may comprise the full-surface covering of the wafer surface 102 with filler material 105 within the printed frame structure 103a, wherein the wafer thinning or a re-thinning step takes place after the application of the carrier wafer 103. Openings 107 may then be produced in the carrier wafer 103 by selective ablation, for example by laser, such that one or more metallization areas 106 arranged on the wafer surface are exposed by the filler material of the carrier wafer 103 arranged thereover for contacting during a wafer test.

[0033] Fig. 2a to 2c show a further preferred embodiment of the method. This differs from the method according to Fig. 1a-e in that after processing a structured wafer surface 102, as in Fig. 1a, a detachable and in particular water-soluble support layer 110 is printed onto the wafer surface, preferably by means of digital printing technology. This can be done during the application of the frame structure 103a by means of printing technology. In this case, the frame structure 103a preferably surrounds the support layer 110 laterally. Subsequently, the application and formation of the carrier wafer 103 takes place by means of a dam-and-fill process step, as in Fig. 2c shown schematically.

[0034] In a later wafer singulation step, the support layer 110 can be detached or removed by the process fluid. This also detached the separated carrier wafer layer. The frame structure 103a provided on the side also protects the support layer 110 during the re-thinning process, in which process fluids are also used, so that the support layer 110 is not prematurely dissolved. Additionally, an optional grinding film 110 (see Fig. 1d) in the area of ​​the openings 107 to protect the support layer 110 from contact with process fluid.

[0035] Fig. 3a-3c show an edge region 109 of the wafer substrate 101. This is rounded in the first 100 to 300 µm, thereby increasing the risk of breakouts during the rethinning process of the wafer substrate. Advantageously, during the method according to the invention, the frame structure 103a is applied or printed during the application of the carrier wafer 103 such that the rounded region is leveled and, in particular, leveled with a surface 113 of the wafer substrate. This can be achieved by means of multi-layer formation or printing of the frame structure 103a, as schematically shown in FIGS. Fig. 3a to 3c. By leveling the rounded region 109 of the wafer 101, the carrier wafer 103 can be placed closer to an outer wafer edge.

Claims

[1] Method for producing semiconductor components, in particular power semiconductor components, from a wafer, comprising the steps: - providing a wafer substrate (101), - processing a structured wafer surface (102), - applying a carrier wafer (103) to the wafer substrate (101), and - reducing a thickness of the wafer substrate (101) by wafer thinning, characterized by that the application of the carrier wafer (103) to the wafer surface (102) is carried out by a dam-and-fill process step. [2] Method according to claim 1, characterized by that the dam-and-fill process step comprises applying at least one frame structure (103a, 103b) to the wafer surface (102) by means of digital printing technology and filling a volume (104) delimited by the frame structure (103a, 103b) with a filling material (105) by means of dispensing. [3] Method according to claim 1 or 2, characterized by that the dam-and-fill process step comprises applying a frame structure (103b) surrounding at least one metallization area (106) of the wafer surface (102) to provide openings (107) in the filling material (105). [4] Method according to claim 3, characterized by that the openings (107) in the filling material (105) of the carrier wafer (103) are filled by means of a separate, removable filling material (108), preferably by means of digital printing technology. [5] Method according to one of the preceding claims, characterized by that the method comprises a selective removal of filler material, preferably by means of a laser, in which at least one metallization surface (106) arranged on the wafer surface (102) is exposed from filler material (105) of the carrier wafer (103) arranged thereabove. [6] Method according to one of the preceding claims, characterized bythat the application of the carrier wafer (103) comprises the application of an organic or inorganic ink and subsequent curing. [7] Method according to one of the preceding claims, characterized by that the application of the carrier wafer (103) comprises several dam-and-fill process steps for applying several superimposed layers, which are applied sequentially and each with subsequent curing. [8] Method according to one of the preceding claims, characterized by in that, in the dam-and-fill process step, a frame structure and / or a filling material is applied in an outer rounded region (109) of the wafer substrate (101) in such a way that the rounded region is leveled and, in particular, leveled with a surface (113) of the wafer substrate (102). [9] Method according to one of the preceding claims, characterized bythat the method, before applying a filling material (105) of the carrier wafer (103), comprises applying a water-soluble support layer (110) which is preferably laterally delimited by a frame structure (103a) to the wafer surface (102), preferably by means of digital printing technology. [10] Method according to claim 9, characterized by that the method comprises applying an abrasive film (111) over the carrier wafer (103), which in particular covers openings (107) arranged therein. [11] Semiconductor component manufactured by a method according to the preceding claims.

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