Method for producing a wafer with a spacer

Abstract

The invention relates to a method for producing a wafer (100) with a spacer (150) for protecting a surface (110) to be protected, comprising a coupled wafer (101) comprising a SOI wafer (140) and a functional wafer (120) connected thereto, wherein the SOI wafer (140) has a handle wafer (146), a functional layer (142) with first structures (143a, 143b) and a silicon dioxide layer (144) arranged between the handle wafer (146) and the functional layer (142), and the functional wafer (120) has second structures (120a, 120b), and generating (340) the spacer (150) by selectively removing the handle wafer (146) and the silicon dioxide layer (144), thereby exposing the surface (110) to be protected.

Description

Technical area

[0001] The present invention relates to the field of wafer processing and concerns a method for producing a wafer with a spacer for protecting a surface to be protected. Furthermore, it relates to a corresponding wafer and a method for processing such a wafer. State of the art

[0002] US 2008 / 0303129 A1 discloses a method for preventing damage to sensitive surfaces in MEMS (microelectromechanical system) manufacturing. For this purpose, the use of a chuck with a structured contact surface is proposed. A cover wafer is described in detail, which is to be connected to an interposer wafer during a manufacturing process. The cover wafer is positioned on the chuck, and the structuring ensures that mechanical damage is avoided. DE 10 2015 206 996 A1 discloses the so-called EPyC process (EPyC: epitaxial polysilicon cycle) for manufacturing microelectromechanical structures with large vertical dimensions. This process uses epitaxial polysilicon as a functional and sacrificial material and builds up a layer structure of epitaxial polysilicon layers (EpiPoly layers) using repeated cycles. Disclosure of the invention

[0003] According to the invention, a method for producing a wafer with a spacer for protecting a surface to be protected as well as a corresponding wafer and a method for processing such a wafer are proposed.

[0004] According to a first aspect of the invention, a method for producing a wafer with a spacer for protecting a surface to be protected is proposed. The method comprises providing a coupled wafer comprising a SOI wafer (SOI: silicon-on-insulator) and a functional wafer bonded thereto, wherein the SOI wafer has a handle wafer, a functional layer (also referred to as a "device layer") with first structures, and a silicon dioxide layer (also referred to as "buried oxide" (BOX)) arranged between the handle wafer and the functional layer, and the functional wafer has second structures. The connection between the functional wafer and the SOI wafer can be produced using common wafer bonding methods, such as silicon direct bonding, thermocompression bonding, or eutectic bonding.It is irrelevant for the invention whether, for example, the provision of the coupled wafer involves bonding an SOI wafer to an already structured functional wafer, or whether the process begins with an SOI wafer and the functional wafer is built and structured on it. The first structures of the SOI wafer can be created before or after bonding to the functional wafer.

[0005] The method further comprises creating the spacer by removing the handle wafer and the silicon dioxide layer in certain areas, thereby exposing the surface to be protected. Both the handle wafer and the silicon dioxide layer are thus removed in a specific area of ​​the SOI wafer in such a way that the underlying surface to be protected is exposed. This surface is typically formed by a surface of the functional layer, which now contacts the external environment of the wafer via a space previously covered by the other layers. The resulting combination, comprising functional wafer, functional layer, and spacer, represents the manufactured wafer.

[0006] The functional wafer typically has one or more semiconductors or consists of one or more semiconductors, for example comprising silicon or consisting of silicon. The functional layer and the handle wafer of the SOI wafer consist of silicon or comprise it. Metals and / or semiconductor oxides can also be contained in the functional wafer and / or the functional layer. For example, the functional wafer and / or the functional layer can comprise sacrificial regions made of a semiconductor such as silicon and / or a semiconductor oxide such as silicon dioxide. The first and / or second structures can be or comprise, for example, structures for one or more electronic circuits, integrated circuits (ICs), MEMS, electrodes and / or vias such as through-silicon vias (TSVs).These structures can also be or include structures for a plurality of semiconductor chips (also referred to as chips for short in the context of this invention). The silicon dioxide layer of the SOI wafer consists of silicon dioxide (SiO2) or comprises silicon dioxide.

[0007] The spacer is created by removing the handle wafer and the silicon dioxide layer of the SOI wafer in sections. The removal of the handle wafer and the removal of the silicon dioxide layer can be performed in separate steps. Thus, the removal of the handle wafer can preferably be performed by etching, for example, by trench etching using a trench mask, such as a resist mask, while the removal of the silicon dioxide layer can be performed in a subsequent step, for example, by means of RF gas-phase etching, plasma etching, and / or wet-chemical etching. The trench mask defines a base area of ​​the spacer. Preferably, subsequent dicing of the wafer is performed by etching processes, for example, with or after exposing MEMS structures. Therefore, typically, no space needs to be reserved for dicing by sawing or similar dicing processes.

[0008] Furthermore, the production of the spacer can also include re-thinning the handle wafer, which can be carried out, for example, before the partial removal of the handle wafer. The re-thinning can be done, for example, by grinding. This is preferably followed by chemical-mechanical polishing (CMP) to improve the roughness and surface quality of the re-thinned handle wafer. This can also ensure particularly high accuracy with regard to the height of the re-thinned handle wafer. The height of the re-thinned handle wafer, i.e. the extent in a direction perpendicular to the surface to be protected, together with the thickness of the silicon dioxide layer determines the subsequent height of the spacer and can, for example, be in the range from 1 µm to 1000 µm and preferably in the range from 50 µm to 300 µm. The height of the re-thinned handle wafer can therefore be, for example, 100 µm.

[0009] The spacer can have any shape and consist of a single, continuous element or of several spatially separated elements. An element formed in this way from the handle wafer and the silicon dioxide layer, which is part of the spacer, is also referred to as a spacer structure. The spacer can be produced, for example, by forming recesses in the handle wafer and the silicon dioxide layer. The spacer and / or its spacer structures can, for example, have the shape of continuous or interrupted frames, for example with walls, arches, grids, and / or struts. The spacer structures of a spacer can also have the shape of walls, cuboids, cylinders, angles, and / or crosses. Such frames and support structures are preferably arranged in a grid.In particular, the one or more spacer structures may have the shape of one or more rectangular frames and / or a rectangular grid.

[0010] Preferably, during or after the spacer is created, the spacer is passivated in order to protect it, for example, from subsequent silicon sacrificial layer etching (in short: sacrificial layer etching) during further processing of the wafer. The passivation layer thus created can preferably consist of silicon dioxide (SiO2) and / or a silicon nitride (for example, stoichiometric silicon nitride, i.e., Si3N4, and / or a non-stoichiometric silicon nitride, i.e., a silicon nitride with a non-stoichiometric composition) or can comprise silicon dioxide and / or a silicon nitride. In particular, it is conceivable for the passivation layer to consist of a silicon nitride layer as well as a silicon dioxide layer, or to comprise these layers, wherein it is conceivable for the silicon dioxide layer or the silicon nitride layer to be applied first to the functional layer for this purpose.The use of a double layer as a passivation layer comprising a layer of stoichiometric silicon nitride and a layer of non-stoichiometric silicon nitride is also possible. The passivation layer preferably serves as an etch stop layer for subsequent silicon sacrificial layer etching, wherein sulfur hexafluoride (SF6) and / or xenon difluoride (XeF2), for example, can be used as etching gases for this purpose. It is particularly advantageous to carry out the passivation of the spacer after the handle wafer has been removed in regions, since at this point in time the surface to be protected is not yet exposed and therefore cannot be covered again by the passivation layer. In this case, a passivation layer comprising or consisting of a passivation material, for example a silicon dioxide layer or a polymer layer, for example consisting of a polyimide, is formed on the spacer.For passivation, passivation techniques such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), thermal oxidation and / or other methods for depositing a passivation material, for example using tetraethylorthosilicate (TEOS deposition), can be used.

[0011] Preferably, after the spacer is produced, particularly preferably after the spacer is passivated, the produced wafer is placed on a support surface such that only the spacer is in contact with the support surface. The support surface can be, for example, a surface of a chuck.

[0012] Preferably, the first structures in the functional layer and / or the second structures in the functional wafer can comprise MEMS structures, and these can be exposed during the process. The first structures and / or the second structures can be exposed before or after the spacer is created. Such MEMS structures can, for example, be the structures for one or more MEMS components such as MEMS sensors and / or MEMS actuators, for example MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, MEMS resonators, and / or parts of such MEMS components. For example, the second structures can be MEMS structures for actuators of a MEMS micromirror, while the mirror plates of the MEMS micromirrors are realized by MEMS structures in the functional layer.The surface to be protected can be the mirror surface formed by the exposed surface of the functional layer. MEMS structures are typically exposed, at least partially, by silicon sacrificial layer etching and can be performed, for example, using plasma-free and / or plasma-assisted etching. Preferably, in the case of silicon sacrificial regions to be removed, sacrificial layer etching is performed using sulfur hexafluoride (SF6), xenon difluoride (XeF2), chlorine trifluoride (ClF3), and / or nitrogen trifluoride (NF3). Furthermore, deep reactive ion etching (DRIE) can also be used for exposure. In the etching of silicon dioxide, which often follows silicon sacrificial layer etching, hydrogen fluoride (HF) can be used as the etching gas (HF gas-phase etching) and / or BOE (buffered oxide etch) can be used as the wet etching agent.

[0013] Finally, after exposing the MEMS structures, one or more passivation layers, for example a passivation layer formed by passivating the spacer, can be at least partially removed from the spacer wafer. The one or more passivation layers can be, for example, oxide layers, in particular silicon dioxide layers. Removal can be performed, for example, using RF gas-phase etching, plasma etching, and / or wet-chemical etching. If desired, specific areas can be protected from RF gas-phase etching by applying non-stoichiometric silicon nitride.

[0014] According to a second aspect of the invention, a wafer produced by a method as described above is proposed. The produced wafer thus comprises a functional wafer, a functional layer, and a spacer. A connection exists between the functional wafer and the functional layer, which connection was established, for example, by direct silicon bonding, thermocompression bonding, or eutectic bonding. The spacer of the wafer preferably has a plurality of spacer structures, i.e., spatially separated elements, which are preferably frames, particularly preferably rectangular and / or continuous frames.

[0015] According to a third aspect of the invention, a method for processing such a wafer is proposed, wherein the wafer is first provided, wherein the first structures and the second structures in the provided wafer are structures for a plurality of chips, wherein a chip can comprise multiple MEMS components. Subsequently, the wafer is singulated into chips, wherein each chip has a surface to be protected, and the chips are removed from the wafer, for example, using a pick-and-place device, such as a pick-and-place robot.

[0016] Preferably, the wafer has retaining structures and / or retaining structures are formed and / or exposed in the wafer before and / or during the dicing process. Retaining structures are designed to limit possible movements of the chips after dicing in at least one direction perpendicular to the surface of the corresponding chip to be protected.

[0017] Preferably, before the wafer is dicing, a gap structure enclosing individual chips and locally perforating the wafer is formed and / or exposed in the wafer. Furthermore, the dicing takes place at least partially along these multiple columns, wherein the formation and / or exposure of the locally perforating gap structure preferably creates webs between the individual columns, each of which runs horizontally or vertically with respect to the surface of the corresponding chip to be protected, thereby holding the chip in the wafer. Thus, after such partial dicing, the webs connect the chips to the rest of the wafer.

[0018] For the purposes of this invention, a gap structure is understood to mean one or more optionally filled, i.e., non-empty, recesses (gaps) in a layer of a wafer that completely penetrate this layer in the vertical direction. A gap structure can therefore be filled with one or more other substances, such as silicon dioxide, optionally in combination with silicon as a sacrificial region, and exposed for later use by an etching process. A filled gap structure accordingly represents an etching structure, whereby the corresponding recesses are also exposed. Such etching structures can be formed as regions of silicon dioxide, which is subsequently removed by an etching process such as HF gas-phase etching, or the etching structures can comprise sacrificial regions of silicon.For example, etched structures can be designed using the EPyC process to comprise silicon laterally surrounded by silicon dioxide, which is later made accessible for sacrificial layer etching, for example, using SF6 and / or XeF2. Such etched structures represent gap structures filled with silicon and silicon dioxide. After such sacrificial layer etching, the silicon dioxide can also be removed in this case by HF gas-phase etching. All of the aforementioned processes can be used for both complete dicing and partial dicing of the wafer into chips, with partial dicing meaning that the chips are still connected to the rest of the wafer by webs after partial dicing.

[0019] Dicing a wafer along a locally perforating gap structure means dicing such that multiple recesses in the gap structure are used to separate a chip from the remaining wafer by destroying, for example, breaking, any remaining connections (for example, in the form of webs) between the chip and the remaining wafer. Gaps in gap structures can vary from simple gaps running vertically through the wafer, i.e., rectangular recesses and cutouts. For example, horizontal gap regions, i.e., parallel to the first surface of the wafer, are conceivable.In particular, the gaps can be designed in such a way that at least locally retaining structures are formed that, as described above, continue to fix the individual chips in the wafer after singulation, i.e., they specifically restrict the movement of the individual chips in a specific direction after singulation, for example, to prevent the individual chips from accidentally falling out of the wafer when the wafer is moved. Retaining structures can exist both in the presence of a locally perforating gap structure, i.e., using webs, and in a continuously penetrating gap structure.In particular, a combination of webs with holding structures is particularly advantageous if, before the chips are removed, pressure must be exerted on the chips against the later removal direction, for example in the context of a wafer-level test, since the holding structures can be designed and arranged in such a way that they counteract the pressure, thus also taking on the function of a stop.

[0020] Preferably, before or during the dicing of the wafer, a gap structure enclosing individual chips and continuously penetrating the wafer is formed and / or exposed, with one or more gaps in the wafer, wherein the dicing is carried out at least partially by the formation and / or exposure of the gap structure.

[0021] It is conceivable that in a method for processing a wafer according to the invention as described above, the first structures and the second structures comprise MEMS structures for the same MEMS components, and the surfaces of the chips to be protected are part of the MEMS structures, wherein the MEMS structures are exposed before or during the dicing of the wafer. It is conceivable that one chip has multiple MEMS components. Thus, the second structures can be MEMS structures for actuators of one or more MEMS micromirrors, and the first structures can be MEMS structures of the associated mirror plates. The surface to be protected can be the mirror surface formed by the exposed surface of the functional layer.

[0022] Preferably, the gaps and thus also the continuously penetrating gap structure and / or the locally perforating gap structure are formed by means of an etching process. Deep reactive ion etching (DRIE), for example, can be used as the etching method. Such an etching process can also be combined with an etching process for exposing the first and / or second structures of the chips, such as MEMS structures, for example, a silicon sacrificial layer etching, so that in one process step, both the continuously penetrating gap structure and / or the locally perforating gap structure are formed and the structures of the chips are exposed. Alternatively, the gap structures can also be created in previous process steps and filled, for example, with silicon dioxide, and only exposed later, for example, by HF gas-phase etching.In particular, the EPyC process can be used to create gap structures with complex structures, such as support structures. When using the EPyC process, silicon dioxide acts as a separating layer between functional regions (regions with functional silicon) and sacrificial regions (regions with sacrificial silicon) of the gap structures. In this case, the gap structures are exposed using a silicon sacrificial layer etch, which can preferably also be used to expose the first and / or second structures. The silicon dioxide is then removed, for example, using an HF vapor-phase etch. Advantages of the invention

[0023] The invention provides a way to protect chips to be manufactured, such as MEMS chips, from mechanical damage during production. The approach of the invention converts an SOI wafer bonded to a functional wafer into a spacer. This integrates the production of a spacer directly into the production process. This spacer allows the wafer to be turned over and placed on the side with a surface to be protected, which is protected from mechanical damage by the spacer. The wafer can thus be further processed from the other side.

[0024] The spacer can therefore protect particularly sensitive surfaces, such as mirror surfaces, from mechanical damage during subsequent processing steps. In particular, it makes it possible to separate and separate chips from the resulting wafer, as well as connect them to other components such as ASICs (application-specific integrated circuits), FPGAs (field programmable gate arrays), and / or other MEMS components, without fear of mechanical damage to the surfaces to be protected.

[0025] The method's approach allows for a high degree of flexibility for adaptation to the precise conditions of the manufacturing process in which the invention is to be used. For example, the height of the spacer can be selected to ensure safe handling of the wafer. The wafer can be placed with the spacer facing down and thus be further processed in manufacturing systems lying on a chuck without risking chuck or system contamination. Tests within the production process, such as wafer-level tests, are also easily possible. Short description of the drawings

[0026] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0027] They show: Fig. 1A to 1F are schematic representations of cross sections of wafers for explaining a method according to the invention for producing a wafer according to the invention with a spacer and a method for processing a wafer according to the invention; Fig. 2 a schematic representation of a wafer according to the invention with spacer from below; and Fig. 3 shows in schematic form as a flow chart an exemplary method according to the invention for producing a wafer according to the invention with a spacer and an exemplary method according to the invention for processing a wafer according to the invention. Embodiments of the invention

[0028] In the following description of the embodiments of the invention, identical or similar elements are designated by the same reference numerals, whereby a repeated description of these elements is omitted in individual cases. The figures only schematically illustrate the subject matter of the invention.

[0029] The Fig. 1A to 1F show schematic representations of cross sections of wafers to explain a method according to the invention for producing a wafer 100 according to the invention with a spacer and a method for processing a wafer according to the invention.

[0030] The Fig. 1A shows a schematic representation of a cross section of a coupled wafer 101. The coupled wafer 101 comprises an SOI wafer 140 (SOI: Silicon-on-Insulator) and a functional wafer 120, which are connected to one another by bond connections 130. Here, as in the following Fig. 1B to 1F, the functional wafer 120 is shown only in part; it continues to the left and right of the area shown in the figures. The same applies to the Fig. 1B shown manufactured wafer 100.

[0031] The SOl wafer 140 comprises Fig. 1A shows a handle wafer 146 and a functional layer 142, which are connected to one another via a silicon dioxide layer 144. Furthermore, the SOI wafer has first structures 143a, 143b, which in the present example comprise MEMS structures 143a', 143b' for MEMS chips 105a, 105b (hereinafter also referred to as chips 105a, 105b for short), for example for mirror plates of a MEMS micromirror, wherein each of the chips 105a, 105b can comprise a plurality of MEMS micromirrors. Also shown are etching structures 170, which can comprise trenches filled with silicon dioxide and / or silicon, for example, and in the Fig. 1A and serve for later singulation of the wafer 100. The etching structures 170 can be formed, in particular, as regions of silicon dioxide, which is later removed by an etching process such as an RF gas-phase etching, or can comprise sacrificial regions of silicon. The etching structures 170 can also be formed using the EPyC process. They then comprise silicon encased in silicon dioxide, which is made accessible to a sacrificial layer etching, for example, using SF6 and / or XeF2. After such a sacrificial layer etching, the silicon dioxide can then also be removed in this case by an RF gas-phase etching. In regions 143c that are not assigned to the individual chips 105a, 105b, structuring is missing. The functional wafer 120 also has second structures 120a, 120b in certain areas, which in this example also include MEMS structures 120a', 120b' for the MEMS chips 105a, 105b.Here, too, there are unstructured areas in the remainder of wafer 120c that are not part of chips 105a, 105b. Functional wafer 120 has a passivation layer 122, which may, for example, comprise or be a silicon dioxide layer. Covered by this layer are metal contacts 124, which are also part of functional wafer 120. In the finished chips 105a, 105b, metal contacts 124 may serve to establish electrical connections to elements of chips 105a, 105b, for example, actuators and / or sensors. As in the SOI wafer 140, the functional wafer 120 contains etching structures 170, which here, however, also serve to implement horizontal webs 150a and holding structures 150b, which later prevent the chips 105a, 105b from falling out during the singulation of the wafer 100.

[0032] The handle wafer 146 is now thinned back and then provided with a trench mask 160 in the areas that are not to be etched. Fig. Figure 1B shows the result after a corresponding etching process, which stops on the silicon dioxide layer 144 of the SOI wafer 140. The silicon dioxide layer 144 thus functions as an etch stop layer. This etching process creates elements 151 for a spacer. In Fig. 1B shows the recesses in the re-thinned handle wafer 146', which correspond to the areas of the chips 105a, 105b that are to be enclosed by the spacer. In a subsequent step, as in Fig. 1C now illustrates that the trench mask 160 is removed and instead the elements 151 of the spacer are provided with a passivation layer 155, which protects them in the following process steps, in particular a subsequent sacrificial layer etching, for example by means of SF6 and / or XeF2.

[0033] In the next step, the MEMS structures 143a', 143b' in the functional layer 142 as well as the second MEMS structures 120a', 120b' in the functional wafer 120 can be exposed. For this purpose, the wafer 100 is Fig. 1D, with the elements 151 for the spacer 150 facing downwards on a support surface 191 of a chuck 190, with surfaces 110 of the chips 105a, 105b to be protected correspondingly also facing downwards. Subsequently, a silicon sacrificial layer etching is performed, for example using SF6, XeF2, ClF3 and / or NF3, whereby the MEMS structures 120a', 120b', 143a', 143b' are exposed. In order to graphically illustrate such a removal of silicon in the MEMS structures 120a', 120b', 143a', 143b', Fig. 1D and Fig. 1F different hatchings are used for the MEMS structures 120a', 120b', 143a', 143b' than in the preceding Fig. 1A to 1C. Following the actual exposure, the silicon dioxide layer and the passivation material of the etching structures 170 are removed, for example, by means of an RF gas phase etching. Fig. 1D shows the result of such an etching process. In the example shown, the etching process completely removed the passivation layer 122 and the silicon dioxide layer 144 to such an extent that the remaining regions of the silicon dioxide layer 144 have a smaller extent than the elements 151 of the spacer 150. The spacer 150 and corresponding spacer structures are formed by the elements 151 and these remaining regions of the silicon dioxide layer 144. Furthermore, the etching process removes the surfaces 110 of the chips 105a, 105b to be protected, which represent the surfaces of the functional layer 142, as well as the gaps 182a, 182b of the gap structures 180a, 180b, which correspond to the etching structures 170 of the above Fig. 1A to 1C have been exposed. The metal contacts 124 are now also accessible.

[0034] In Fig. 1D still shows different variants of separation.

[0035] So the now in the Fig. 1D, the chip 105a on the right has horizontal webs 150a that connect it to a remainder 120c of the wafer 100. In contrast, the left chip 105b is already completely singulated; it is not held in the wafer 100 by webs. The now exposed gap structures 180a with the gaps 182a are accordingly locally perforating gap structures. The gap structure 180b can be a continuously penetrating gap structure with a gap 182b surrounding the chip 105b, through which the chip 105b was removed from the wafer 100. However, the movement of the chip 105b in a direction 102 perpendicular to the surface 110 of the chip 105b to be protected, illustrated in the drawing by a corresponding arrow, is restricted by means of holding structures 150b in the form of projections in the remainder 120c of the wafer 100, which protrude into the gap 182c.These holding structures 150b block the path of the chip 105b during a movement in the direction 102, wherein the holding structures 150b are designed such that they only come into contact with areas of the chip 105b that are not part of the surface 110 to be protected.

[0036] As in Fig. 1E, the separated chips 105b and the partially separated chips 105a, i.e., still held by horizontal webs 150a, can now be subjected to wafer-level tests and connected to further components 194. Thus, in Fig. 1E shows a wafer-level test for chip 105b with corresponding contact pins 192a that contact the metal contacts 124. For such a wafer-level test, a parallel implementation (not shown) of horizontal webs 150a and holding structures 150b for a single chip is particularly advantageous, since in such a case the holding structures 150b can represent a stop to prevent unwanted breakage of the horizontal webs 150a upon contacting by the contact pins 192a. Following any wafer-level testing, a chip can be tested, as for chip 105a in the Fig. 1E, can be electrically connected to another component 194, such as an ASIC, an FPGA, and / or another MEMS component, via the metal contacts 124, typically by soldering. A chip-component assembly produced in this way can be measured again after such a connection, for example, as shown in Fig. 1F by corresponding measuring needles 192b. A pick-and-place device 196 such as a pick-and-place robot can now remove the chips 105a, 105b from the remainder 120c of the wafer 100. This is shown in the Fig. 1F for the chip 105a. In this case, the horizontal webs 150a are broken. In Fig. 1F therefore shows the remains 150a' of the broken horizontal webs 150a.

[0037] Fig. 2 shows a schematic representation of a wafer 100 according to the invention with spacer 150, viewed from below. Shown here are 20 chips 205, each surrounded by spacer structures 250 of the spacer 150 in the form of rectangular, continuous frames. These frames may alternatively have a non-rectangular and / or interrupted shape. Instead of frames, other shapes for the spacer structures, such as crosses, angles, cylinders, or cuboids, are also conceivable. Alternative or additional spacer structures may be isolated walls, which may, for example, be placed centrally at the edges of the chips 205.

[0038] Fig. 3 shows in schematic form as a flow chart an exemplary inventive method for producing a wafer according to the invention with a spacer and an exemplary inventive method for processing a wafer according to the invention.

[0039] Here, a coupled wafer is provided 310, comprising an SOI wafer and a functional wafer connected to it. The SOI wafer has a handle wafer, a functional layer with first structures, and a silicon dioxide layer arranged between the handle wafer and the functional layer. The functional wafer has second structures. The first and second structures are structures for a plurality of MEMS chips, each of which can comprise a plurality of MEMS components. Each MEMS component is implemented by both a portion of the first structures and a portion of the second structures.

[0040] The handle wafer is thinned back in step 330, for example by grinding. Using appropriate etching processes, the handle wafer and the silicon dioxide layer are then removed in sections in step 340, thereby creating a spacer. More precisely, the handle wafer is first removed in sections 340a (trench) and then the silicon dioxide layer is removed in sections 340b, exposing the surface to be protected, for example, a mirror surface. Between steps 340a and 340b, the separated handle wafer can be passivated in order to protect it in subsequent process steps, such as exposure by etching a silicon sacrificial layer. After creating the spacer, the produced wafer is typically placed 350 on a support surface, for example, a chuck, such that only the spacer is in contact with the support surface.This wafer, prepared by the preceding steps 360, can now be further processed. In step 370, the MEMS structures are typically exposed, typically by etching a silicon sacrificial layer.

[0041] Subsequently, in preparation for the singulation, locally perforating gap structures for forming ridges (step 374) and / or gap structures that continuously penetrate the wafer (step 376) can be formed and / or exposed. By forming and / or exposing 374 locally perforating gap structures, ridges are preferably formed between the gaps, which each run horizontally or vertically with respect to the first surface and hold the MEMS chips in the wafer. Subsequent singulation 380 then takes place at least partially along these multiple gaps. Holding structures can also be formed and / or exposed (step 372), which typically takes place in a common etching process together with steps 374 and / or step 376.Such support structures serve to limit possible movements of the MEMS chips after singulation 380 in a direction perpendicular to the surface of the corresponding chip to be protected. Preferably, all of the aforementioned structures are already formed during the production of the functional wafer (see ). Fig. 1A and the etching structures 170 therein). The gap structures and / or the support structures can be realized by etching structures, wherein the gap structures can be filled, for example, with silicon dioxide and / or silicon, so that only an exposure of the structures needs to be performed in steps 372, 374, 376. This is done, for example, by HF vapor-phase etching and / or silicon sacrificial layer etching, depending on the material to be removed.

[0042] The exposing 370 of MEMS structures can be followed by an at least partial removal 375 of no longer required passivation layers from the spacer wafer, preferably by means of RF vapor-phase etching, which also exposes any gap structures, webs, and support structures that may be present, so that steps 375 and steps 372, 374, 376 can also coincide. Likewise, steps 372, 374, 376 can at least partially coincide with the exposing 370, for example, if silicon sacrificial layer etching is used for steps 372, 374, 376.

[0043] The released wafer can be connected to a component wafer, such as an ASIC wafer, or to individual components, such as ASICs, before singulation. Afterward, singulation 380 can take place to obtain the individual MEMS components. Instead of connecting to a component wafer or individual components prior to singulation 380, singulation 380 can also take place before connecting to individual components. Finally, the MEMS chips are removed from the remaining wafer in step 390, for example, using a pick-and-place device, breaking any webs in the process. Such chips are thus finally singulated at this point in time; singulation 380 and removal 390 coincide in time here.

[0044] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, numerous modifications are possible within the scope of the claims, which are within the scope of one skilled in the art. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 2008 / 0303129 A1

[0002] DE 10 2015 206 996 A1

[0002]

Claims

[1] A method for producing a wafer (100) with a spacer (150) for protecting a surface (110) to be protected, comprising the following steps: a. Providing (310) a coupled wafer (101) comprising a SOI wafer (140) and a functional wafer (120) connected thereto, wherein the SOI wafer (140) has a handle wafer (146), a functional layer (142) with first structures (143a, 143b) and a silicon dioxide layer (144) arranged between the handle wafer (146) and the functional layer (142), and the functional wafer (120) has second structures (120a, 120b); and b. producing (340) the spacer (150) by removing (340a, 340b) the handle wafer (146) and the silicon dioxide layer (144) in regions, thereby exposing the surface (110) to be protected. [2] Method according to claim 1, wherein prior to the production (340) of the spacer (150) a re-thinning (330) of the handle wafer (146) takes place. [3] Method according to one of the preceding claims, wherein after the production (340) of the spacer (150), a placement (350) of the produced wafer (100) on a support surface (191) takes place such that only the spacer (150) is in contact with the support surface (191). [4] Method according to one of the preceding claims, wherein the first structures (143a, 143b) and / or the second structures (120a, 120b) comprise MEMS structures (120a', 120b', 143a', 143b') for one or more MEMS components such as MEMS sensors and / or MEMS actuators, preferably MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, MEMS resonators and / or parts of such MEMS components, and a release (370) of the MEMS structures (120a', 120b', 143a', 143b') is preferably carried out by means of a plasma-less and / or a plasma-assisted etching and / or using SF6, XeF2, ClF3 and / or NF3. [5] Method according to claim 4, wherein after the exposure (370) of the MEMS structures (120a', 120b', 143a', 143b'), an at least partial removal (375) of one or more passivation layers (155) from the spacer (150) is carried out, preferably by means of HF gas phase etching. [6] Wafer (100) produced by a method according to one of claims 1 to 5. [7] Wafer (100) according to claim 6, wherein the spacer (150) comprises a plurality of spacer structures (250) in the form of frames. [8] A method for processing a wafer (100) according to claim 6 or 7, comprising the following steps: a. Providing (360) the wafer (100), wherein the first structures (143a, 143b) and the second structures (120a, 120b) are structures for a plurality of chips (105a, 105b, 205); b. separating (380) the wafer (100) into the chips (105a, 105b, 205), each chip (105a, 105b, 205) having a surface (110) to be protected; and c. Removing (390) the chips (105a, 105b, 205) from the wafer (100). [9] Method according to claim 8, wherein the wafer (100) has holding structures (150b) and / or before and / or during the singulation (380) of the wafer (100) a formation and / or exposure (372) of holding structures (150b) in the wafer (100) takes place, wherein the holding structures (150b) are designed to restrict possible movements of the chips (105b, 205) after the singulation (380) in at least one direction (102) perpendicular to the surface (110) to be protected of the corresponding chip (105b, 205). [10] Method according to claim 8 or 9, wherein, prior to the dicing (380) of the wafer (100), a gap structure (180a) enclosing individual chips (105a, 205) and locally perforating the wafer (100) is formed and / or exposed (374) in the wafer (100), and the dicing (380) is carried out at least partially along these multiple columns (182a), wherein, by forming and / or exposing (374) the locally perforating gap structure (180a), preferably horizontal webs (150a) are formed between the columns (182a), which webs each run horizontally or vertically with respect to the surface (110) of the corresponding chip (105a, 205) to be protected, and the chip (105a, 205) is thereby held in the wafer (100). becomes. [11] Method according to one of claims 8 to 10, wherein before or during the singulation (380) of the wafer (100) a formation and / or exposure (376) of a gap structure (180b) enclosing individual chips (105b, 205) and continuously penetrating the wafer (100) with one or more gaps (182b) in the wafer (100) takes place and the singulation (380) takes place at least partially by the formation and / or exposure (376) of the gap structure (180b). [12] Method according to one of claims 8 to 11, wherein the first structures (143a, 143b) and the second structures (120a, 120b) comprise MEMS structures (120a', 120b', 143a', 143b') for the same MEMS components and the surfaces (110) of the chips (105a, 105b, 205) to be protected are part of the MEMS structures (120a', 120b', 143a', 143b'), wherein a release (370) of the MEMS structures (120a', 120b', 143a', 143b') takes place before or during the singulation (380) of the wafer (100).

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