Electronic gate driver circuit for generating a precise reduced gate voltage

Abstract

Electronic gate driver circuit (100) for generating a precise reduced gate voltage that enables an extension of a detection time for a short-circuit detection, comprising: an input voltage (121), a charging current source (118), wherein the charging current source (118) is connected to a positive terminal of the input voltage (121), a discharging current source (120), wherein the discharging current source (120) is connected to a negative terminal of the input voltage (121), a reference ground (130), a gate driver voltage (114), wherein the gate driver voltage of an internal supply voltage (114) is tapped between the charging current source (118) and the reference ground (130), a transistor gate-source voltage (132), wherein the gate-source voltage (132) is tapped between the gate (126) and the source (128) of the transistor (116).

Description

Technical field

[0001] The invention relates to an electronic gate driver circuit for generating a precise reduced gate voltage, which makes it possible to extend a short-circuit detection time. State of the art

[0002] DE 201310217902 relates to a driver circuit for the transistor to be controlled. The driver circuit comprises an adaptive pulse width generator and an analog-to-digital converter with a resolution of at least one bit, as well as control devices. The adaptive pulse width generator is configured to generate a pulse in a first step, causing charge to flow from the control electrode of the transistor to be controlled, so that the transistor to be controlled is at least partially charged with respect to its input voltage. After charging is complete, the input voltage is converted into a digital signal using the analog-to-digital converter. After this, a control variable for a subsequent pulse is generated from the converted digital signal in the control device in order to be able to control the adaptive pulse width generator.The adaptive pulse width generator is controlled digitally, wherein a switch-off device for the transistor to be controlled is provided in the control device, with which a reduction of the input voltage of the transistor to be controlled is effected after the pulse (discharge of the gate). Disclosure of the invention

[0003] According to the invention, an electronic gate driver circuit for generating a precise reduced gate voltage which enables an extension of a detection time for a short-circuit detection is proposed, comprising: - an input voltage, - a charging current source connected to a positive terminal of the input voltage, - a discharge current source connected to a negative terminal of the input voltage and - a gate drive voltage of an internal supply voltage, the gate drive voltage being tapped between the charging current source and the reference ground.

[0004] A gate driver circuit within the meaning of the inventive solution is an electronic circuit that serves to efficiently and controlledly drive the gate of a transistor. For example, in a gate driver, the gate driver circuit has a function based on controlling the behavior of a charge at the gate and ensuring that the transistor can switch quickly and reliably between the conducting and blocking states.

[0005] A gate voltage in the sense of the inventive solution is a transistor gate voltage, which refers to a voltage applied to the transistor gate terminal. The gate voltage affects, for example, the electrical state of the transistor and is used to switch the transistor back and forth between the conducting and the blocking state.

[0006] A short-circuit detection time of a gate driver circuit within the meaning of the inventive solution refers to the speed with which a circuit is capable of detecting a short circuit in a connected transistor. An efficient short-circuit detection time includes, for example, functionality that prevents damage to a circuit when undesirable conditions, such as a short circuit, occur.

[0007] A transistor according to the inventive solution is an electronic component that amplifies or switches electrical signals. A transistor can, for example, be a metal-oxide-semiconductor field-effect transistor (MOSFET). This is a special type of transistor whose operating principle is based on a field effect. In a MOSFET, the current flow between the drain terminal and the source terminal is controlled by changing the voltage at the gate electrode.

[0008] A reference ground within the meaning of the invention is, for example, a uniform reference point within an electrical system. The reference ground serves, for example, as a reference point for electrical voltages. The reference ground is usually defined as zero potential or grounding point.

[0009] In an advantageous embodiment of the electronic gate driver circuit proposed according to the invention, a gate is maintained at a voltage V1 after a turn-on phase. To reduce the short-circuit current in the event of a short circuit, the voltage V1 is selected such that it is greater than the maximum plateau voltage VPlateau, but less than the nominal gate voltage V2.

[0010] According to the invention, a "cycle-by-cycle" control option analogous to the "cycle-by-cycle" control described in patent DE 201310217902 is used to maintain a high-impedance gate using a current source driver. "Cycle-by-cycle" control of a gate driver within the meaning of the invention corresponds to a regulation method that, for example, monitors transistor operation for stable and efficient power transmission and adjusts it as needed. "Cycle-by-cycle" control refers to the control circuit monitoring transistor operation during each switching operation and making adjustments if necessary. The switching time within the meaning of the invention is the time it takes a circuit to transition from one state to the next.

[0011] In a further advantageous embodiment of the electronic gate driver circuit proposed according to the invention, a saturation current of a voltage V1 is smaller than a saturation current of a voltage V2. A voltage V2 is a nominal gate voltage in a line-end mode, which is preferably set to a level that is considered high compared to conventional voltage sources in order to reduce ohmic losses. The voltage V2 is applied to the transistor gate source voltage.

[0012] After switching on according to the inventive solution, the gate is held at voltage V1. This leads to a significantly lower saturation current than at voltage V2, which means that a longer time is available for short-circuit detection and a higher short-circuit withstand time of the power semiconductor is achieved. It is important that the short-circuit withstand time is longer than the short-circuit detection time so that damage is limited and the inverter is shut down safely without loss of the gate driver. This is particularly important at higher nominal voltages or operating voltages of a DC source, for example at 940 V, in order to be able to keep the RDSON*A (drain-source-on resistance of a specific design or variant) as low as possible, for example with silicon carbide technology.

[0013] In a further advantageous embodiment of the electronic gate driver circuit proposed according to the invention, a gate driver voltage of an internal supply voltage in a gate driver is measured in a holding phase of the voltage V1.

[0014] In a further advantageous embodiment of the electronic gate driver circuit proposed according to the invention, a deviation of the voltage V1 due to the tolerance of a current source and a gate charge can be compensated by adapting a control in the switch-on phase.

[0015] In a further advantageous embodiment of the electronic gate driver circuit proposed according to the invention, the gate driver voltage of an internal supply voltage is used during the holding phase to reduce the saturation current.

[0016] In a further advantageous embodiment of the electronic gate driver circuit proposed according to the invention, the electronic gate driver circuit can be used for a single gate or common gates in a logic switch.

[0017] A logic switch refers to an electronic component or circuit capable of switching between discrete switching states, the 'on' (1) and 'off' (0). The logic switch can be implemented, for example, using transistors or other electronic components.

[0018] A single gate (also known as a single gate) comprises one power transistor per gate driver channel. A common gate, for example, comprises multiple power transistors connected to one gate driver channel.

[0019] In a further advantageous embodiment of the electronic gate driver circuit proposed according to the invention, the electronic gate driver circuit comprises an analog-to-digital converter. Advantages of the invention

[0020] The gate driver circuit according to the invention makes it possible to generate a precisely reduced gate voltage, whereby the detection time for short-circuit detection is advantageously extended.

[0021] The gate driver circuit according to the invention also enables precise adjustment of the voltage V1, which is required for successful implementation of a two-stage switching process (2LTON).

[0022] Furthermore, the gate driver circuit proposed according to the invention advantageously makes it possible to adapt the control in the event of deviations in the switch-on phase. Short description of the drawings

[0023] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0024] They show: Fig. 1 a schematic representation of an electronic gate driver circuit and Fig. 2 a schematic representation of the timing of a two-stage switching process with gate driver current sources. Embodiments of the invention

[0025] In the following description of the embodiments of the invention, identical or similar elements are designated by the same reference numerals, whereby a repeated description of these elements is omitted in individual cases. The figures only schematically illustrate the subject matter of the invention.

[0026] Fig. 1 shows a schematic representation of an electronic gate driver circuit 100 for generating a precise reduced gate voltage to extend a detection time for short-circuit detection. This circuit includes a gate driver 112, an input voltage 121, a charging current source 118 connected to a positive terminal 122 of the input voltage 121, a discharging current source 120 connected to a negative terminal 124 of the input voltage 121, a gate driver voltage of an internal supply voltage 114 tapped between the charging current source 118 and the reference ground 130, and an analog-to-digital converter 110, wherein the analog-to-digital converter 110 taps the gate driver voltage of an internal supply voltage 114.The gate driver circuit 100 further includes a transistor 116, a parasitic inductance in the gate circuit 102, and a parasitic resistor in the gate circuit 106 connected in series with the gate 126 of the transistor 116, and a parasitic inductance in the source circuit 104 and a parasitic source circuit resistor 108 connected in series with the source 128 of the transistor 116. The source 128 is connected to the reference ground 130 through the parasitic inductance in the source circuit 104 and the parasitic resistor in the source circuit 108.

[0027] For example, as in Fig. 1, the analog-to-digital converter 110 of the gate driver 112 can be used for further purposes, such as converting analog signals into digital values ​​or as a communication and interface by transmitting a digital value to a digital interface, so that the analog-to-digital converter 110 does not incur any measurable additional costs.

[0028] According to the Fig. 1, a two-stage switching process solution (2LTON solution) for a current source driver with a sum and single gate can be implemented very cost-effectively. Due to a high pulse width modulation frequency and the stability of the transistor 116, for example, a silicon carbide MOSFET transistor 116, an analog-to-digital converter 110 can also be used and bundled. This means that in the first pulse width modulation of the analog-to-digital converter 110, the first MOSFET is measured, in the second pulse width modulation of the analog-to-digital converter 110, the second MOSFET is measured, and in the third pulse width modulation of the analog-to-digital converter 110, the third MOSFET is measured.

[0029] Fig. Figure 2 shows a schematic representation of the timing 200 of a 2LTON with CS gate driver 112, shown in a diagram, with the horizontal axis representing a time axis 222 and a vertical axis representing a voltage axis 220. The diagram shows a voltage profile curve 214 measured at the transistor gate-source voltage 132, which comprises three phases: a first phase representing a turn-on phase 208 with or without adjustment of the gate 126 to a voltage, a second phase representing a holding phase 210 of a voltage V1 206 with a high-resistance gate 126, and a third phase representing a charging 212 to a voltage V2 207. In Fig. 2, in the switch-on phase 208, a voltage curve 214, starting from a negative terminal 124 of an input voltage 121, initially rises to a threshold voltage Vth 202, wherein the voltage rise occurs through a voltage adjustment. A second voltage rise occurs up to a plateau voltage VPlateau 204, followed by a brief hold of the plateau voltage VPlateau 204, after which a third adjustment takes place, achieving a voltage V1 206. Subsequently, according to Fig. 2, a holding phase 210, wherein the voltage V1 206 is maintained over time. In the third discharge phase 212, the voltage V1 206 is increased to a voltage V2 207.

[0030] The gate driver voltage of an internal supply voltage 114 can then be measured in the gate driver 112 during the hold phase 210 of the voltage V1 206. This makes it possible, for example, to adjust the control in the turn-on phase 208 in the event of any deviations. This enables, for example, the precise adjustment of the voltage V1 206, which is essential for an efficient two-stage switching process implementation.

[0031] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, numerous modifications are possible within the scope of the claims, which are within the scope of expert practice. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] DE 201310217902 [0002, 0010]

Claims

[1] An electronic gate driver circuit (100) for generating a precise reduced gate voltage that allows an extension of a detection time for a short-circuit detection, comprising: - an input voltage (121), - a charging current source (118), wherein the charging current source (118) is connected to a positive terminal (122) of the input voltage (121), - a discharge current source (120), wherein the discharge current source (120) is connected to a negative terminal (124) of the input voltage (121) and - a gate driver voltage of an internal supply voltage (114), wherein the gate driver voltage of an internal supply voltage (114) is tapped between the charging current source (118) and the reference ground (130). [2] The electronic gate driver circuit (100) of claim 1, wherein a gate (126) is maintained at a voltage V1 (206) applied to the transistor gate source voltage (132) after a turn-on phase (208). [3] Electronic gate driver circuit (100) according to claim 2, wherein a saturation current of a voltage V1 (206) is smaller than a saturation current of a voltage V2 (207). [4] Electronic gate driver circuit (100) according to claim 3, wherein a gate driver voltage of an internal supply voltage (114) in a gate driver (112) is measured in a holding phase (210) of the voltage V1 (206). [5] Electronic gate driver circuit (100) according to claims 2 to 3, wherein a deviation of the voltage V1 (206) due to a tolerance of a current source and a gate charge can be compensated by an adaptation of a control in the switch-on phase (208). [6] Electronic gate driver circuit (100) according to claims 2 to 4, wherein the gate drive voltage of an internal supply voltage (114) is used during the hold phase (210) to reduce the saturation current. [7] Electronic gate driver circuit (100) according to claims 2 to 4, wherein the electronic gate driver circuit (100) is applicable to a single gate (126) or common gates in a logic switch. [8] Electronic gate driver circuit (100) according to claims 2 to 7, wherein the electronic gate driver circuit (100) comprises an analog-to-digital converter (110).

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