Semiconductor element with optimized short-circuit capability

Abstract

Transistor component (100), in particular trench power MISFET, comprising a substrate (10) preferably made of silicon carbide (SiC), silicon (Si) or gallium nitride (GaN), a source contact (1), a drain contact (2) and a trench structure (4) with a gate (3).

Description

Technical area

[0001] The invention relates to a transistor component, in particular a trench power MISFET having a source contact with a variable contact area for optimizing short-circuit capability. In particular, the trench power MISFET comprises at least two unit cells that have a different source contact configuration. Furthermore, the invention relates to a method for manufacturing a corresponding transistor component. State of the art

[0002] Power transistors such as power MISFETs (Metal Insulator Semiconductor Field Effect Transistors) represent a special type of MISFET designed to handle high power in electronic circuits. Trench power MISFETs based on silicon carbide (SiC), for example, are one of the preferred solutions for electronic power switches used in high-voltage electromobility applications such as inverters, chargers, etc. The trench structure enables the on-resistance (RDS(on)) to be further reduced and the transistor's performance to be improved.One of the requirements for such power MISFETs is to achieve a low on-resistance to minimize static power losses while ensuring a low saturation current, which is required to reduce the energy dissipated during short-circuit events.

[0003] A disadvantage of the trench power MISFETs known from the state of the art (cf. Fig. 1), is that the saturation current cannot be reduced too much without causing significant losses in the on-state resistivity (RonA) or compromising other important MOSFET parameters. The saturation current is typically limited by the developing conductive channel and the JFET effect resulting from adjacent lateral space-charge zones in the semiconductor structure, which are formed at the junction between lateral regions of the device.

[0004] One way to reduce the saturation current would be to increase the channel resistance, e.g., by increasing the thickness of the trench structure's insulator, increasing the doping or thickness of a body region located beneath a source region, or a combination thereof. However, this would adversely affect the on-state resistivity (RonA) or lead to the degradation of other important MOSFET parameters, such as increasing the threshold voltage beyond the usable range.

[0005] Another approach to reducing the saturation current would be to increase the JFET effect, so that the additional voltage drop in this region limits the increase in the channel voltage and thus reduces the saturation current. This could be achieved by increasing the width of the lateral regions in the device, by reducing the doping of a region located between the lateral regions, or by a combination of both. However, this also leads to an undesirably large increase in the resistance of the region located between the lateral regions and thus to an undesirable increase in the resistivity (RonA).

[0006] The object of the invention is to address the disadvantages described above and to provide an improved transistor component. Disclosure of the invention

[0007] The invention relates to a transistor component, in particular a trench power MISFET, comprising a substrate preferably made of silicon carbide (SiC), silicon (Si) or gallium nitride (GaN), a source contact, a drain contact and a trench structure with a gate, wherein the transistor component comprises a parallel circuit of at least two unit cells, and wherein a contact area of ​​the source contact with a contiguous source region arranged underneath for a second unit cell is designed to be smaller than a first unit cell.

[0008] The inventive design of the transistor component offers the advantage that the variable structuring of the source contact, in particular a local reduction of a metal contact area in one of the adjacent unit cells, increases the series resistance of the regions connected to the source contact, in particular n+ source regions, thereby reducing the saturation current with fewer disadvantages for the overall RdsOn. In particular, the effective voltage between gate and source (VGS) is reduced, which leads to a reduction in the saturation current.

[0009] In a preferred embodiment, the contact surface of the source contact has a contour that varies above the source region of the two unit cells in a plan view. In this case, the contact surface of the source contact can have an at least partially rectangular, polygonal and / or circular contour in a plan view. In deviation from the prior art, in which a respective contact surface is usually formed as a contact strip with a constant width that extends essentially perpendicular to a plurality of unit cells of a semiconductor component arranged parallel to one another, the source contact thus has a contoured contact surface such that a contact surface that varies for each contacted unit cell is formed between the source metallization and a source region arranged underneath.

[0010] In a preferred embodiment, the contact surface of the source contact has at least one local recess in the form of a contact surface reduction, which is formed in at least one of the two unit cells. The contact surface reduction can be in the form of a rectangular, polygonal, and / or circular cutout in the otherwise continuously applied metallization of the source contact. The contact surface of the source contact can preferably have two recesses arranged directly opposite one another or at least partially offset from one another on both sides of the trench structure, as seen in a plan view of the semiconductor component.

[0011] In a preferred embodiment, the source contact is only in contact with the underlying source region of one of the two unit cells, in particular with a first unit cell. Further preferably, a source region of one of the two unit cells, in particular of the second unit cell, is free of a contact surface of a source contact arranged above it. In this case, no current flows through the source region of the second unit cell, which is not connected to the source contact of the transistor component, toward the surface and to the source contact.

[0012] In a preferred embodiment, a contact area of ​​the source contact with the underlying source region of the unit cells has an area equal to or smaller than the area of ​​an adjacent recess in the source contact in a plan view of the unit cells.

[0013] The two unit cells of the transistor component preferably have an otherwise identical structural design except for the source contacting which is designed differently from one another.

[0014] In a preferred embodiment, each unit cell of the transistor component comprises a highly doped n+ substrate on which an n-doped drift region and, optionally, a buffer region arranged therebetween are arranged. The buffer region preferably has a higher n-doping than the drift region.

[0015] Preferably, each unit cell of the transistor component comprises a trench structure or a trench filled with a thin dielectric layer. This can, in particular, comprise or be formed on silicon oxide, hafnium oxide, aluminum oxide-silicon nitride, or a combination of several insulating materials with different dielectric constants. The dielectric layer can have different thicknesses at the bottom and sidewalls of the trench structure. The trench structure is advantageously filled with a highly conductive material, preferably n+-doped polysilicon, and forms a gate or a gate electrode connected to a metallic gate contact.

[0016] Preferably, each unit cell of the transistor device comprises laterally arranged, deep p+-doped regions that extend laterally from the top of the semiconductor structure and deeper than the trench structure into the drift region. An n-doped intermediate region is preferably arranged between the lateral p+-doped regions, the n-doping of which is higher than the n-doping in the drift region, thereby reducing the resistivity of the device in the on-state.

[0017] Preferably, each unit cell of the transistor component comprises a p-doped body region or layer arranged between the trench structure and the lateral, deep p+-doped regions, as well as a source region arranged above it, which is connected to the source contact. The source contact forms a low-resistance contact to the source region and to the lateral, deep p+-doped regions.

[0018] In a preferred embodiment, the source region of the first unit cell is formed as an n+-doped region, and an underlying body region or layer is formed as a p-doped region. Further preferably, the source region of the second unit cell is formed as an n+-doped region, and an underlying body region or layer is also formed as a p-doped region.

[0019] The source contact is preferably formed as a continuous metallization, which fully or partially contacts the lateral, deep p+-doped regions and the source regions of the two unit cells.

[0020] The transistor component according to the invention can be an n-channel MISFET, as described above, or a p-channel MISFET. In the latter case, the corresponding dopings n and p are reversed, and the sign of the voltages changes from positive to negative. This is intended to be equally disclosed and claimable for the device according to the invention.

[0021] The transistor component according to the invention is preferably suitable for a variety of power electronic applications, in particular for inverters for industrial drives, renewable energy generation, automotive applications, train drives and for use in high-voltage rectifiers.

[0022] In a further aspect, the invention relates to a method for producing a transistor component as described above, comprising a plurality of method steps for forming, in particular depositing, a layer sequence on a substrate. With regard to layer growth, layer structuring, and the possible influencing and processing of formed, in particular grown, layers, fundamentally known methods and techniques of semiconductor technology can be used.

[0023] According to the invention, the method comprises the step of forming a source contact differently for two adjacent unit cells of the transistor component, such that a contact area of ​​the source contact with a contiguous source region arranged underneath is formed smaller for a second unit cell than for a first unit cell.

[0024] The method preferably comprises a lithography step with a structured mask, wherein a contact metallization serving as a source contact for a first unit cell is formed differently from the adjacent second unit cell.

[0025] To avoid repetition, with regard to the further features of the method according to the invention, reference should be made to the previously described features of the semiconductor component according to the invention, which should be considered as equally disclosed and claimable for the method according to the invention and vice versa.

[0026] Further advantages, features and details of the invention will become apparent from the following description of preferred embodiments of the invention and from the drawings. Short description of the drawings Fig. 1 shows a section through a unit cell of a trench power MISFET according to the prior art, Fig. 2a shows a plan view of a trench power MISFET according to a first embodiment of the invention, Fig. Figure 2b shows a side sectional view of a first unit cell of the semiconductor device according to Fig. 2a along the section plane A, Fig. 2c shows a side sectional view of a second unit cell of the semiconductor device according to Fig. 2a along the section plane A', Fig. 3a-d show a schematic representation of the manufacturing steps to obtain the semiconductor component according to the invention, Fig. 4a-c show a top view of a trench power MISFET according to further embodiments of the invention. Embodiments of the invention

[0027] Identical elements or elements with the same function are provided with the same reference numerals in the figures.

[0028] Fig. Figure 1 shows a prior art structure of a semiconductor device forming a trench power MISFET 100'. For simplicity, only one unit cell is shown. The specific structure of an edge termination is not shown and can be implemented in various known ways.

[0029] The trench power MISFET 100' comprises a highly doped n+ substrate 10, on which an n-doped drift region 12 is arranged. Optionally, a buffer region 11 can be arranged between substrate 10 and drift region 12. Furthermore, the component comprises a trench structure 4 known per se with a thin dielectric layer 5 and which is filled with a highly conductive material 3, typically n+-doped polysilicon. This forms the gate electrode, which is connected to a metallic gate contact (not shown) and galvanically isolated from a source metallization 1 by an insulation layer (not shown).

[0030] The trench power MISFET 100' further comprises laterally arranged, deep p+-doped regions 8, which extend from the top side of the semiconductor structure deeper than the trench 4 and into the drift region 12. An n-doped region 9, whose n-doping is higher than the n-doping in the drift region 12, is preferably arranged between the p+-doped regions 8. The doping in the region 9 can be constant or varying. Alternatively, the region 9 can also extend below the region 8. Also included are a p-doped body region 6 and an n+-doped source region 7 arranged above it, which are arranged on both sides of the trench 4. The source contact or the source metallization 1 forms a low-resistance contact to the source region 7 and to the p+-doped region 8. The body region(s) 6 are indirectly connected to the source contact 1 via the lateral, p+-doped regions 8.The substrate 10 is connected to the drain contact 2, which forms a low-resistance contact with the n+ substrate 10.

[0031] As soon as a sufficiently high voltage, for example 15-18V, i.e. a voltage higher than the threshold voltage of usually 2-5V, is applied, an electron inversion layer or an electrically conductive channel forms in the p-doped body region 6 at the interface between the p-doped region and the gate dielectric 5, creating an electrical conduction path between the n+ source region 7 and the drain, which consists of the n-doped regions 9, 12, 11, the n+ doped substrate 10 and the drain contact 2. If the drain potential is increased compared to the source potential, current begins to flow from the drain contact 2 through the regions 10, 11, 12, 9, the electrical channel and the source region 7 to the source contact 1.

[0032] When a positive voltage is applied between the drain and source contacts 2,1 while a gate 3 and source 1 electrode are short-circuited, or alternatively, when gate 3 has a negative voltage of a few volts relative to the source in the off-state, a space charge zone develops at the PN junction between the p-doped region 8 and the n-doped region 9, as well as at the structure 3,5,9. With increasing drain potential, the space charge zone extends downward into the regions 9 and the drift region 12 until it finally reaches the n-doped buffer region 11. The n-doped buffer region 11 is intended to prevent the space charge zone from penetrating the substrate 10.A peak of the electric field in blocking mode is located at the bottom of the p+-doped region 8, which shields the trench 4, ensuring a low electric field strength in the gate dielectric 5, typically less than 3 MV / cm for device reliability. In the event of a short circuit, a high positive voltage occurs between the drain and source terminals while the electrical channel is fully switched on, with the gate-source potential higher than the threshold voltage of usually 2-5 V and typically 15-18 V, causing a very high saturation current to flow through the structure. The current is usually limited by the channel but also strongly depends on the distance between neighboring p-doped regions 8. As the voltage between source and drain increases, lateral space-charge zones form at the junction between the p-doped regions 8 and the n-doped regions 9 due to a JFET effect.

[0033] Fig. 2a to 2c show a first preferred embodiment of a transistor component 100 according to the invention comprising at least two unit cells 100a, 100b arranged next to one another (cf. Fig. 2b, Fig. 2c). As in Fig. As shown in Figure 2a, the at least two unit cells 100a, 100b are configured as a parallel circuit. The transistor component may further comprise a plurality of unit cells 100a, 100b, wherein the unit cells 100a, 100b are preferably arranged alternately. The basic structure of the two unit cells 100a, 100b corresponds to the known structure, as shown in Fig. 1 shown.

[0034] According to the invention, it is now provided that the contact metal 1 of the source is structured in such a way that, in comparison with the prior art, Fig. 1 does not form a continuous contact strip over the n+ region 7 in plan view, in particular no continuous contact strip over the contiguous source region 7 of the at least two adjacent unit cells. This results in the current in the component or source regions with reduced contact area and in particular without contact metal 1 above it flowing laterally through the n+ regions 7 in the direction of the contact metal 1, thereby increasing the source series resistance of the component.

[0035] The increased voltage drop in the source region leads to a reduction in the effective voltage VGSeff (VGS eff =VGS-V th ) and thus the saturation current. The decrease in the saturation current is due to the quadratic dependence of the saturation current on VGS eff (ISC~VGS eff 2, cf. B.Jayant Baliga "Silicon Carbide Power Devices", World Scientific, 2005). The impairment of RonA is significantly lower here, since the channel component of Rdson depends only inversely proportionally on VGSeff (Rdson,ch ~ 1 / VGSeff, cf. B.Jayant Baliga "Silicon Carbide Power Devices", World Scientific, 2005).

[0036] As in Fig. As shown in Figure 2a, the source contact 1 or the source metallization for the at least two adjacent unit cells 100a, 100b is designed differently from one another, such that the contact surface 13 of the source contact 1 has a recess 14 at least in a second unit cell 100b, in which the source metallization 1 is removed.

[0037] The semiconductor structure of the unit cell in Fig. 2b works identically to the structure in Fig. 1. In this respect, reference is made to the above description and functionality. However, the current in the structure can be Fig. 2c at gate voltages above the threshold voltage does not flow vertically directly to the overlying source metallization, but has to travel a longer path to the source contact of the neighboring unit cell 100a.

[0038] Fig. 3a to 3d schematically show a simplified process flow for realizing the structures in the unit cells 100a, 100b according to the Fig. 2b,c, with focus on the realization of source contact 1.

[0039] As in Fig. 3a, in a first step the different layers or regions are formed or deposited on a substrate, so that the Fig. 3a is achieved. With regard to layer growth, layer structuring, and the possible influencing and processing of formed, particularly grown, layers, generally known methods and techniques can be used. Regions 8, 6, 9, 3, and 7 in the upper area of ​​structure 101 are already formed in accordance with the subsequent component structure. An insulation layer 16 is also formed on the surface of the semiconductor component.

[0040] As in Fig. 3b and Fig. 3c, which shows a top view of the semiconductor device 101 and a sectional view of the two unit cells 100a, 100b, the method then comprises a lithography step using a patterned mask 102 for patterning the contact areas, in which a selective removal of the insulation layer 16 for the unit cells 100a, 100b takes place. Subsequently, a contact metallization layer 15 is applied to form the source contact 1 of the structure, as shown in Fig. 3d, which is designed differently for the two unit cells 100a, 100b.

[0041] Fig. 4a-c show further preferred embodiments in plan view, analogous to Fig. 2a, in which the source contact 1 is structured differently.

[0042] Fig. 4a shows an embodiment in which the contact area 13 of the source contact 1 with the contacted n+ source region 7 arranged underneath is significantly smaller than the non-contacted source region 7 in the area of ​​the recesses 14. A lower limit of the contacted n+ area can be specified by electromigration limits or by the maximum permissible increase of Rdson.

[0043] Fig. 4b and Fig. 4c show further preferred embodiments for the source contact 1. Here, the source contact 1 can have recesses 14, which taper or enlarge in the component longitudinal direction L, perpendicular to a trench extension direction. Furthermore, the source contact 1 can comprise only point-arranged contact areas 13, which are in contact with the underlying source region 7. These regions are preferably arranged only in a first of two unit cells 100a, 100b. Of the in Fig. Patterns or combinations thereof that differ from the arrangements shown in 4 are also possible.

[0044] As in the Fig. 2a and Fig.4, the source contact 1 on one side of the trench structure 4 can be arranged opposite the source contact 1 on the opposite side of the trench structure 4. Furthermore, it is possible that the correspondingly arranged source contacts on both sides of the trench structure 4 are not arranged exactly opposite one another, ie offset from one another.

[0045] The invention is not limited to the n-channel MISFET described in the exemplary embodiments, but can also be applied to a p-channel MISFET. In this case, the corresponding dopings n and p are reversed, and the sign of the voltages changes from positive to negative. Furthermore, the invention is not limited to SiC-based semiconductor components, but can equally be applied to other semiconductor materials, in particular silicon or gallium nitride. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] B.Jayant Baliga “Silicon Carbide Power Devices”, World Scientific, 2005

[0035]

Claims

[1] Transistor component (100), in particular trench power MISFET, comprising a substrate (10) preferably made of silicon carbide (SiC), silicon (Si) or gallium nitride (GaN), a source contact (1), a drain contact (2) and a trench structure (4) with a gate (3), characterized by in that the transistor component comprises a parallel circuit of at least two unit cells (100a, 100b), wherein a contact area (13) of the source contact (1) with a connected source region (7) arranged underneath is designed to be smaller for a second unit cell (100b) compared to a first unit cell (100a). [2] Transistor component according to claim 1, characterized by that the contact surface (13) of the source contact (1) has a contour which varies above the source region (7) of the two unit cells (100a, 100b) in plan view. [3] Transistor component according to claim 1 or 2, characterized bythat the contact surface (13) of the source contact (1) is at least partially rectangular, polygonal and / or circularly contoured in plan view. [4] Transistor component according to one of the preceding claims, characterized by that the contact surface (13) of the source contact (1) has at least one local recess (14) in the form of a contact surface reduction, which is formed in at least one of the two unit cells (100a, 100b). [5] Transistor component according to claim 4, characterized by that the contact surface (13) of the source contact (1) has two recesses (14) arranged directly opposite one another or at least partially offset from one another on both sides of the trench structure (4). [6] Transistor component (100) according to one of the preceding claims, characterized bythat the source contact (1) is only in contact with the underlying source region (7) of one of the two unit cells (100a, 100b), in particular a first unit cell (100a). [7] Transistor component according to one of the preceding claims, characterized by that a source region (7) of one of the two unit cells, in particular of the second unit cell (100b), is free of a contact surface (13) of a source contact (1) arranged thereabove. [8] Transistor component according to one of the preceding claims, characterized by that the two unit cells (100a,100b) of the transistor component (100) have an otherwise similar structural design except for a different design of the source contact (1). [9] Transistor component according to one of the preceding claims, characterized bythat in a plan view of the unit cells (100a, 100b), a contact area (13) of the source contact (1) with the underlying source region (7) of the unit cells (100a, 100b) has an area equal to or smaller than the area of ​​an adjacent recess (14) in the source contact (1). [10] Method for producing a transistor component (100) which is designed according to one of claims 1 to 8, comprising a plurality of method steps for forming, in particular depositing, a layer sequence on a substrate (10), characterized by that a source contact (1) for two adjacent unit cells (100a, 100b) of the transistor component (100) is designed differently, such that a contact area (13) of the source contact (1) with a connected source region (7) arranged underneath it for a second unit cell (100b) is designed to be smaller than a first unit cell (100a).

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