CORRECTION CIRCUIT

Abstract

A correction circuit (600) for correcting one or more errors in a digitized current signal, wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element (602), wherein the correction circuit (600) is configured to correct an offset error between the digitized current signal and the analog current signal by: a) comparing the digitized current signal with the analog current signal to determine the offset error by: i. detecting a first time step when the digitized current signal crosses a first digital threshold; ii. detecting a second time step when the analog current signal crosses a first analog threshold; iii. calculating a first duration between the first time step and the second time step; iv. determining a first slope of at least one of the digitized current signal and the analog current signal; v.Multiplying the first duration by the first slope to determine the offset error; and b) correcting the digitized current signal using the determined offset error; and / or wherein the correction circuit (600) is configured to correct a relative slope error between the digitized current signal and the analog current signal by: a) comparing the digitized current signal with the analog current signal to determine the relative slope error by: i. detecting a first time step when the digitized current signal crosses a first digital threshold; ii. detecting a second time step when the analog current signal crosses a first analog threshold; iii. detecting a third time step when the digitized current signal crosses a second digital threshold; iv. detecting a fourth time step when the analog current signal crosses a second analog threshold; v.a) Calculate a first digital slope delay between the first time step and the third time step; b) Calculate a first analog slope delay between the second time step and the fourth time step; c) Divide the first analog slope delay by the first digital slope delay to calculate a first delay parameter, then subtract one from the first delay parameter to determine the relative slope error, and d) Correct the digitized current signal using the determined relative slope error.

Description

The present disclosure relates to a correction circuit for correcting one or more errors in a digitized current signal. In particular, the present disclosure relates to a correction circuit that can be applied to a switching converter. BACKGROUND Fig. 1(a) is a schematic representation of a digital step-down converter 100 with a power stage 101, analog-to-digital converters (ADCs) 102, 104, 106 and a control device 108. The power stage 101 comprises switches 110, 112, an inductor 114 and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates an output voltage VOUT. While the power stage 101 and the passive components (the inductor 114 and the capacitor 116) remain the same as in an analog buck converter, the ADC 102 converts the output voltage VOUT into a digital value. Optionally, the inductor current IL of the inductor 114 and the input voltage VIN can also be converted from analog to digital depending on the digital control method. We distinguish between: • The switching frequency (FSW) of the buck converter 100 is, for example, 2 MHz. FSW is equal to 1 / TSW, where TSW is the switching period of the buck converter 100. FSW is the frequency of the power stage. • The processing frequency of the digital control device 108 (FS), for example, approximately 100 MHz. FS is equal to 1 / TS, where TS is the processing time of the control device 108. FS can optionally also be the sampling frequency of the ADC 102. Digital systems, such as the digital step-down converter 100, can use a digital signal representing the current flow through an energy storage element during operation. For example, a digitized current signal may be required by a control device to control the switching operation of the digital switching converter. In the present example, the digitized current signal is a digitized inductor current DIL, as provided by the ADC 104, which converts an analog current signal indicating the inductor current IL into a digital format. It is evident that components and methods other than the ADC 104 can be used to generate the digitized inductor current DIL. The digitized inductor current DIL can be generated using sensor-based or sensorless techniques. The digitized inductor current DIL is provided to the control device 108, which uses the information about the inductor current IL to control the switching operation of the circuit breakers 110 and 112. The dependence of the control scheme on the inductor current means that such a system is called a current-mode converter, which uses current-mode control. For the effective operation of the buck converter or any other digital system that uses a digitized current signal during operation, it is desirable that the digitized current signal DIL accurately represents the analog current signal IL. With regard to the buck converter 100, it is desirable that the digitized inductor current DIL accurately represents the inductor current IL. It should be noted that both the analog current signal and the inductor current can be denoted by the variable "IL" to indicate that the analog current signal represents the current flow through the inductor. It is clear that the analog current signal IL may not itself be a current signal, but could, for example, be a voltage signal representing a current signal. US 2016 / 0359489A1 concerns an adjustable current synthesizer capable of generating a synthesized current representative of an actual current, according to a model of a circuit generating the actual current. The current synthesizer can subsample a current sensing signal derived from the actual current to obtain samples of the actual current, which are then used to adjust the synthesized current, thus ensuring the accuracy of the synthesized current. US 2021 / 0 099 080 A1 relates to an inductor current emulator circuit for use in a switching regulator. SUMMARY It is desirable to provide a system for improving the accuracy of a digitized power signal compared to existing methods. According to a first aspect of the disclosure, a correction circuit is provided for correcting one or more errors in a digitized current signal, wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element, wherein the correction circuit is configured to correct the one or more errors in the digitized current signal by comparing the digitized current signal with the analog current signal and correcting the digitized current signal based on the result of the comparison. Optionally, the digitized power signal is provided by a power synthesizer. Optionally, the correction circuit is configured to generate a correction signal that depends on the result of the comparison and to provide the correction signal to the current synthesizer, wherein the correction signal is suitable for correcting one or more errors in the digitized current signal when received by the current synthesizer, thereby correcting the digitized current signal based on the result of the comparison. Optionally, the correction circuit is configured to correct an offset error between the digitized current signal and the analog current signal. Optionally, the correction circuit is configured to compare the digitized current signal with the analog current signal to determine the offset error and to correct the digitized current signal using the determined offset error. Optionally, the correction circuit is configured to determine the offset error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses a first analog threshold, calculating a first time duration between the first time step and the second time step, determining a first slope of at least one of the digitized current signal and the analog current signal, and multiplying the first duration by the first slope, thereby determining the offset error. Optionally, the first digital threshold is approximately equal to a digitized first analog threshold. Optionally, the correction circuit includes a comparator configured to provide an output indicating that the analog current signal crosses the first analog threshold, with the output being used to determine the second time step. Optionally, the correction circuit is configured to correct a relative slope error between the digitized current signal and the analog current signal. Optionally, the correction circuit is configured to compare the digitized current signal with the analog current signal to determine the relative slope error and to correct the digitized current signal using the determined relative slope error. Optionally, the correction circuit is configured to determine the relative slope error by detecting a first time step when the digitized current signal crosses a first digital threshold, a second time step when the analog current signal crosses a first analog threshold, a third time step when the digitized current signal crosses a second digital threshold, a fourth time step when the analog current signal crosses a second analog threshold, calculating a first digital slope delay between the first and third time steps, calculating a first analog slope delay between the second and fourth time steps, and dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter.and then subtracting one from the first delay parameter, which determines the relative slope error. Optionally, the correction circuit is configured to correct a relative slope error between the digitized current signal and the analog current signal. Optionally, the correction circuit is configured to correct the relative slope error before correcting the offset error. Optionally, the correction circuit is configured to compare the digitized current signal with the analog current signal to determine the relative slope error and offset error, and to correct the digitized current signal using the determined relative slope error and offset error. Optionally, the correction circuit is configured to determine the relative slope error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses a first analog threshold, detecting a third time step when the digitized current signal crosses a second digital threshold, detecting a fourth time step when the analog current signal crosses a second analog threshold, calculating a first digital slope delay between the first and third time steps, calculating a first analog slope delay between the second and fourth time steps, and dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter.Then subtract one from the first delay parameter to determine the relative slope error. Optionally, the correction circuit is configured to determine the offset error by calculating a first duration between the first time step and the second time step, determining a first slope of the analog current signal by calculating an analog threshold difference by subtracting the second analog threshold from the first analog threshold, dividing the analog threshold difference by the first analog slope delay, and multiplying the first slope of the analog current signal by the first duration, thereby determining the offset error. Optionally, the correction circuit is configured to correct one or more errors in the digitized current signal during the operation of a switching converter that includes the energy storage element. Optionally, the switching converter can consist of a buck converter, a boost converter, or a buck-boost converter. Optionally, the energy storage element includes an inductor. Optionally, the correction circuit is configured to correct one or more errors in the digitized current signal two or more times during the operation of the switching converter, or in response to an external signal, or in response to one or more errors exceeding a threshold, or in response to a mode change of the switching converter, or in response to a transition. Optionally, the correction circuit is configured to correct one or more errors in the digitized current signal periodically or non-periodically during operation of the switching converter. According to a second aspect of the disclosure, a method for correcting one or more errors in a digitized current signal using a correction circuit is provided, wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element, and wherein the method comprises comparing the digitized current signal with the analog current signal and correcting the digitized current signal based on the result of the comparison. It is obvious that the procedure of the second aspect can include features set out in the first aspect and can incorporate other features described here. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which: Fig. 1 is a schematic representation of a digital step-down converter; Fig. 2 is a graph of the inductor current varying over time during the operation of the step-down converter of Fig. 1; Fig. 3 is a time graph showing an example of how parameters relating to the operation of the step-down converter vary over time during operation; Fig. 4 shows time graphs illustrating examples of how parameters relating to the operation of the step-down converter vary over time during operation and for different inductor current values; Fig. 5 is a time graph showing representative waveforms of the digital inductor current and the inductor current IL as a result of a load transition during the operation of the step-down converter; Fig.6(a) is a schematic representation of a correction circuit according to a first embodiment of the present disclosure; Fig. 6(b) is a schematic representation of the correction circuit and an energy storage element according to a second embodiment of the present disclosure; Fig. 7 is a timing diagram showing the digitized current signal and the analog current signal during the operation of an exemplary embodiment of the present disclosure, for example, with respect to the device shown in Fig. 6(a); Fig. 8 is a timing diagram showing the digitized current signal and the analog current signal during the operation of an exemplary embodiment of the present disclosure, for example, with respect to the device shown in Fig. 6(a); Fig.9(a) is a time diagram of the digitized inductor current during the operation of an exemplary embodiment of the present disclosure, for example with respect to the device shown in Fig. 6(a); Fig. 9(b) is a time diagram of the digitized inductor current during the operation of an exemplary embodiment of the present disclosure, for example with respect to the device shown in Fig. 6(a); Fig. 10 is a time diagram showing the digitized current signal and the analog current signal during the operation of an exemplary embodiment of the present disclosure, for example with respect to the device shown in Fig. 6(a); Fig. 11 is a schematic representation of a specific embodiment of the correction circuit and the switching converter according to a third embodiment of the present disclosure; Fig.12 is a timing diagram showing the digitized current signal and the analog current signal during the operation of an exemplary embodiment of the present disclosure, for example, with respect to the device shown in Fig. 11; Fig. 13 is a timing diagram showing simulation results of a practical implementation of a known system using a low-bandwidth correction mechanism; Fig. 14(a) is a timing diagram showing simulation results of a practical implementation of the system shown in Fig. 11; Fig. 14(b) is the timing diagram of Fig. 14(a) over a shorter period; and Fig. 15 is a schematic representation of a comparator unit that can be used for one or both of the two comparator units of Fig. 11. DETAILED DESCRIPTION Fig. 2 is a diagram of the inductor current IL, which varies over time during the operation of the buck converter 100 of Fig. 1. During operation, the inductor 114 switches between coupling to the input voltage VIN via switch 110 (the magnetizing phase, designated by digit 202) and coupling to ground PGND via switch 112 (the demagnetizing phase, designated by digit 204). The diagram shows a first curve 206, which depicts an idealized inductor current. The inductor current IL can have an idealized shape consisting of straight lines, as used in US9419627B2 and US9667260B2. The diagram also shows a second curve 208, which shows a more realistic current profile where the slope or edge of each phase has a nonlinear shape (exponential decay for the falling slope or edge). It should be noted that the time diagrams represent continuous time and continuous data, to facilitate clarity of explanation. For some switching current converters, a linear approximation of the inductor current IL may be sufficient for an effective control scheme. However, a more accurate, non-linear, digitized waveform of the inductor current DIL is desirable, as this ensures more precise current control. Furthermore, a digitized inductor current DIL with improved accuracy can be used for applications beyond simple control, such as overcurrent protection. There are several suitable methods for generating the digitized inductor current DIL, as is known to those skilled in the art. For example, the digitized inductor current DIL can be generated using the ADC 104 as described with reference to Fig. 1, or it can be generated using a current synthesizer. The following description refers to the generation of the digitized inductor current DIL using a current synthesizer. In the discrete time domain (clocked as such at TS, which is the processing time of the control device 108), the digitized inductor current DIL during the magnetization phase can be represented as follows: The digitized inductor current DIL during the demagnetization phase can be represented as follows: The variable terms RMAG and RDEMAG are thus the nonlinear corrections of ideal slopes for the magnetization phase and the demagnetization phase, respectively. L is the inductance of inductor 114, DIN is a digital input voltage signal, DOUT is a digital output voltage signal, and n is an integer, where RHS is the on-resistance of transistor 110, RLS is the on-resistance of transistor 112, and DCR is the series resistance of inductor 114. It is obvious that the digitized inductor current DIL can have the profile shown by curve 206 by using a linear approximation by setting RMAG= RDEMAG= 0 for equations (1) and (2). A current synthesizer can be used to generate the digitized inductor current DIL using equations (1) to (4). For example, and with reference to equations (1) - (4), it is evident that achieving an accurate digitized inductor current DIL depends on precise values ​​for the parameters used in the equations (e.g., L, RHS, RLS, DCR, DIN, DOUT). Other sources of error may include, but are not limited to: • Driver speed • Dead times between LS and HS switch lines • Temperature variations of resistors • Inductor aging Temperature-related errors tend to vary slowly. Errors in the digitized inductor current DIL with respect to a driver speed change with a time constant of L / R, where R is given by: where D is the duty cycle of the buck converter. Dead-zone errors can occur within a single clock cycle. The accumulation of these errors can lead to large discrepancies between the digitized inductor current DIL and IL (up to 1.3 A are observed in simulations). Figure 3 is a timing diagram showing an example of how parameters relating to the operation of the buck converter 100 vary over time during operation. Curve 300 shows the inductor current IL as it varies over time; curve 302 shows the pulse width modulation (PWM) signal as it varies over time; and curve 304 shows a voltage across the switching node SW. The PWM signal is used to control the switching operation of the buck converter 100, and the use of PWM in this context is well known to those skilled in the art. The timing diagram in Fig. 3 shows a simplified and exaggerated view of the driver delay (Tdly1, Tdly2) and dead zones (Tdz1, Tdz2) for a given inductor current IL. In this case, there is a delay between the rising edge of the PWM signal and the response of the circuit breakers to this change (Tdly1). A similar (but not identical) delay occurs with the falling edge of the PWM signal (Tdly2). From an analogous perspective, we consider MAG, which denotes the magnetization phase, as the time period in which the inductor current IL increases. The inductor current IL is close to zero. Equations (1) and (2) show that the expressions differ during the magnetization phase from those during the demagnetization phase; therefore, it is desirable to know the exact time of the transition between the phases. If the PWM signal is used to identify the transition time, it is obvious that this will lead to errors due to Tdly1 and Tdly2. Furthermore, the different slope of the inductor current IL during the dead zones Tdz1 and Tdz2 compared to the slope during the remaining magnetization phase (where SW=VIN) is not taken into account in equations (1) and (2). The errors mentioned above are highly dependent on IL, VIN, VOUT, and temperature. Fig. 4 shows time diagrams that illustrate how parameters relating to the operation of the buck converter 100 vary over time during operation and for different values ​​of the inductor current IL. Figure 4 shows how the effective MAG duration changes with the inductor current IL (for a fixed required PWM duration). More precisely, the effective MAG duration changes depending on the valley current (IL_valley) and the peak current (IL_peak) of the inductor current IL at the end of the MAG and DEMAG stages. This is due to the current conduction through the freewheeling diode, which depends on the polarity of the inductor current IL. The change in voltage SW at the switching node depends on the polarity of the inductor current IL at the end of DEMAG and at the end of MAG. It is possible to correct these (and other) errors in a feed-forward manner, which can reduce the size of the (DIL-IL) error. However, small residual errors can also be incorporated and ultimately lead to increasing deviations over time. Fig. 5 is a time diagram showing representative waveforms of the digital inductor current DIL (a curve 500) and the inductor current IL (a curve 502) as a result of a load transition during the operation of the buck converter 100. After the transition, a mismatch exists between the waveforms. For single-phase converters, the DIL and IL errors may still allow the system to function, but are nevertheless undesirable due to degraded performance under transition loads and the unsuitability of the digitized inductor current DIL for use in applications such as overcurrent protection. For multi-phase converters, a mismatch between the phase currents is highly undesirable, as it can degrade transition performance and efficiency. Since the DIL-to-IL errors are independent of each other, the effective mismatch between the inductor current IL of two different converter phases can be doubled compared to a DIL-to-IL mismatch of a single-phase converter. It is desirable that the digitized inductor current DIL has the following properties: • Accurate average value compared to IL • Accurate ripple magnitude compared to IL • Fast correction of introduced errors • No deviation over time with respect to IL • Similar nonlinear shape to IL Fig. 6(a) is a schematic representation of a correction circuit 600 for correcting one or more errors in a digitized current signal DIL according to a first embodiment of the present disclosure. The digitized current signal DIL is a digital representation of an analog current signal IL of a current flow through an energy storage element 602. It should be noted that the variables "IL" and "DIL" are used for consistency with the previous description, where the energy storage element includes an inductor that is part of a buck converter. In the present embodiment, the energy storage element 602 is considered generally. In specific embodiments, the energy storage element 602 may include an inductor or another circuit component, according to the understanding of those skilled in the art. During operation, the correction circuit 600 corrects the one or more errors in the digitized current signal DIL by comparing the digitized current signal DIL with the analog current signal IL and then correcting the digitized current signal DIL based on the result of the comparison. The digitized current signal DIL can be provided by a current synthesizer 612. The correction circuit 600 can be configured to generate a correction signal 601, which depends on the result of the comparison, and to provide the correction signal 601 to the current synthesizer 612. The correction signal 601 is a signal suitable for correcting one or more errors in the digitized current signal DIL when it is received by the current synthesizer 612. Therefore, during operation, the current synthesizer 612 uses the correction signal 601 to correct the digitized current signal DIL based on the result of the comparison. The correction signal 601 can contain information regarding a mismatch between the two signals IL and DIL, such as when the digitized current signal DIL is not an exact digital representation of the analog current signal IL. The current synthesizer 612 can then use the information provided by the comparison signal 601 to adjust or otherwise correct the digitized current signal DIL to reduce the mismatch and ensure that it digitally represents the analog current signal IL more accurately. If the digitized current signal DIL is already a sufficiently accurate representation of the analog current signal IL, as can be defined by a threshold, the mismatch indicated by the correction signal 601 may be sufficiently small so that it is not necessary for a correction to be applied by the actual synthesizer 612. Fig. 6(b) is a schematic representation of the correction circuit 600 and the energy storage element 602 according to a second embodiment of the present disclosure. In the present embodiment, the energy storage element 602 is a component of a switching converter 604, which includes at least one power switch 606. In the present embodiment, the correction circuit 600 corrects one or more errors in the digitized current signal DIL during operation of the switching converter 604. The switching converter 604 can be a buck converter, a boost converter, or a buck-boost converter. The correction circuit 600 can correct one or more errors in the digitized current signal DIL at one or more events. In one specific embodiment, the correction can be performed periodically or non-periodically. In another embodiment, the correction can be performed in response to an external signal; in response to at least one of the errors exceeding a threshold; in response to a transition; or in response to a mode change of the switching converter. In further embodiments, the correction can be applied based on one or more of the conditions mentioned above. It is evident that the correction process can be applied more than once during the operation of the overall system, which includes the energy storage element 602. This may be necessary if an event occurs that leads to an increase in the mismatch between the digitized current signal DIL and the analog current signal IL, for example, a transition. In a specific embodiment, the correction circuit 600 can be configured to correct an offset error between the digitized current signal DIL and the analog current signal IL. Fig. 7 is a timing diagram showing the digitized current signal DIL and the analog current signal IL during the operation of an exemplary embodiment of the present disclosure, for example, with respect to the device shown in Fig. 6(a). In the present example, there is an offset error (denoted by ΔI) between the digitized current signal DIL (a curve 700) and the analog current signal IL (a curve 702). As discussed above, continuous time and value representations are used for the digitized current signal DIL to improve clarity of explanation. In reality, however, the digitized current signal DIL comprises values ​​that vary in discrete time steps. The following description assumes that the energy storage element 602 is an inductor used as part of a buck converter. However, it is obvious that the concept is applicable to other switching converter topologies, including, but not limited to, boost converters, buck-boost converters, and multiple switching converters, according to the understanding of those skilled in the art. With reference to Fig. 7, the waveforms IL and DIL are phase-aligned, since the digitized inductor current DIL is a digital representation of the analog inductor current IL. Furthermore, the slew rates of the digitized inductor current DIL and the analog inductor current IL are the same during the demagnetization phase (denoted "DEMAG"), which is also true during the magnetization phase (denoted "MAG"). The slew rates are denoted by "SR" and have units of amperes per unit of time (e.g., A / s, where "A" denotes amperes and "s" denotes seconds). The slew rates can also be referred to as "slopes". The offset error ΔI indicates a mismatch between the average levels of the digitized current signal DIL and the analog current signal IL, which can be described as their direct current (DC) levels. For an accurate representation of the analog current signal IL by the digitized current signal DIL, the offset error ΔI should be approximately zero. In a specific embodiment of the present disclosure, for correcting the offset error ΔI, the correction circuit 600 compares the digitized current signal DIL with the analog current signal IL to determine the offset error ΔI. Using this information, the correction circuit 600 then applies a correction to the digitized current signal DIL to reduce the offset error ΔI to approximately zero, thereby correcting the digitized current signal DIL. In the present example, a digital threshold DISET1 receives its analog representation ISET1 via a DAC 704, which receives the threshold DISET1 to generate the analog threshold ISET1 shown in Fig. 7. The digital threshold DISET1 is approximately equal to the analog threshold ISET1 because the two signals represent the same quantity in different ranges. Therefore, the thresholds DISET1 and ISET1 are aligned in Fig. 7. The digital threshold DISET1 can be any threshold between the peak of the digitized inductor current DIL and the trough of the digitized inductor current DIL, with the analog threshold ISET1 being defined similarly with respect to the analog inductor current IL. A point P1 is obtained from the digitized inductor current DIL (a digital signal) crossing a digital threshold DISET1. It is obvious that this is a digital comparison. A point P2 is obtained from the analog inductor current IL (a real analog signal) that crosses a real threshold ISET1. This analog comparison leads to a real event (e.g., a comparator output). In a specific embodiment, the correction circuit 600 may include a comparator (not shown) configured to provide an output indicating that the analog current signal IL crosses the threshold I-SET1, the output being used to determine the time step t2. Using the two comparison points P1, P2, the offset or misalignment ΔI between the DIL and IL waveforms can be determined. In a specific embodiment, the offset error ΔI is determined by the correction circuit 600 by first detecting a time step t1 at point P1 when the digitized current signal DIL crosses a digital threshold DISET1; detecting a time step t2 at point P2 when the analog current signal IL crosses an analog threshold ISET1; and then calculating a duration ΔT between the two time steps. ΔT can be calculated by subtracting the time step t2 from the time step t1. Furthermore, the correction circuit 600 is configured to determine a slope SR of one of the signals IL, DIL. In the present embodiment, the slopes are equal, and therefore the slope SR can be determined from either of the signals DIL, IL. In operation, the correction circuit 600 then determines the offset error ΔI using the following relationship between the slope SR and the duration ΔT. If SR and ΔT can be measured (or are otherwise known), the offset between the waveforms can be corrected. If ΔI = 0, the two waveforms DIL and IL are aligned, meaning that the DIL representation of IL is accurate. If the waveforms IL, DIL are spaced apart such that the analog inductor current IL does not cross the threshold ISET1, an accurate value for the offset can be determined by first applying a coarse correction in an attempt to bring the two waveforms DIL, IL close together in order to take a measurement. In another specific embodiment, the correction circuit 600 can be configured to correct a relative slope error between the digitized current signal DIL and the analog current signal IL. Fig. 8 is a timing diagram showing the digitized current signal DIL and the analog current signal IL during the operation of an exemplary embodiment of the present disclosure, for example, with respect to the device shown in Fig. 6(a). In the present example, there is a relative slope error between the digitized current signal DIL (a curve 800) and the analog current signal IL (a curve 802). As in Fig. 7, Fig. 8 shows the digitized current signal DIL with a continuous time representation, and the following example is described in relation to a buck converter. In the present example, the slopes are unequal. The slope of the digitized inductor current DIL is denoted by "SR_DIL" and the slope of the analog inductor current IL is denoted by "SR_IL". In relation to a specific embodiment of the present disclosure, the correction circuit for correcting the relative slope error compares the signals IL and DIL to determine the relative slope error SR_ERR. Using this information, the correction circuit 600 then applies a correction to the digitized current signal DIL to reduce the relative slope error SR_ERR to approximately zero, thereby correcting the digitized current signal DIL. In the present example, the thresholds ISET1 and DISET1 are as described with reference to Fig. 7. In this example, a digital threshold ISET2 receives its analog representations ISET2 via a DAC 804, which receives the threshold DISET2 to generate the analog threshold ISET2 shown in Fig. 8. The digital threshold DISET2 is approximately equal to the analog threshold ISET2 because the two signals represent the same quantity in different ranges. Therefore, the thresholds DISET2 and ISET2 are aligned in Fig. 8. Point P3 is obtained from the digitized inductor current DIL (a digital signal) crossing a digital threshold DISET2. It is obvious that this is a digital comparison. Point P4 is obtained from the analog inductor current IL (a real analog signal) crossing a real threshold ISET2. This analog comparison results in a real event (such as a comparator output). In a specific embodiment, the relative slope error SR_ERR is determined by the correction circuit 600 by detecting the time steps t1 and t2, as described with reference to Fig. 7; detecting a time step t3 at point P3 when the digitized current signal DIL crosses the digital threshold DISET2; detecting a time step t4 at point P4 when the analog current signal IL crosses the analog threshold ISET2; calculating a digital slope delay ΔT_DIL between time steps t1 and t3; calculating an analog slope delay ΔT_IL between time steps t2 and t4; and dividing the slope delays ΔT_DIL and ΔT_IL to calculate the relative slope error SR_ERR. We can define the following equations with respect to the thresholds: As previously described, the three delay measurements ΔT, ΔT_DIL, ΔT_DIL can be derived from the results of the digital comparisons of the digitized inductor current DIL with the digital thresholds DISET1, DISET and the analog comparisons of the analog inductor current IL with the analog thresholds ISET1, ISET2. The relative slope error SR_ERR can be calculated as follows: where SR_DIL is the slope of the digitized inductor current DIL and SR_IL is the slope of the analog inductor current IL. The value of the relative slope rates of the analog inductor current IL and the digitized inductor current DIL is provided by the relative slope error SR_ERR and can be used to apply a correction to the digitized inductor current DIL signal to align its slope SR_DIL with the slope of the analog inductor current SR_IL. Several methods are available to adjust the slope SR_DIL, as is obvious to experts. For example, one option, with reference to equations (1) and (2), is to change the L parameter value used in the expression used to calculate DIL[n]. L denotes the inductance of the inductor of the energy storage element 602. In another embodiment, the correction circuit 600 can be configured to correct the relative slope error and the offset error. For example, the correction circuit 600 can be configured to compare the digitized current signal DIL with the analog current signal IL to determine the offset and relative slope errors, and then correct the digitized current signal DIL based on the determined errors. In a specific embodiment, expressions (1) and (2) can be modified as follows to allow the corrections for error and slope in the generation of the digitized inductor current DIL[n] to be taken into account: Since the expressions provided by equations (10) and (11) are recursive (depending on the previous value), the offset correction only needs to be performed once after the calculation (to avoid integrating this correction). Once the offset error is corrected, all future DIL[n] calculations will be corrected. The relative slope error term SR_ERR can (and should) be used for every subsequent DIL[n] value calculation. The offset error can be determined as described with reference to Fig. 7 or Fig. 8. The relative slope error can be determined as described with reference to Fig. 8. It is desirable that the slopes of the waveforms DIL and IL are equal during the demagnetization phase (DEMAG) and the magnetization phase (MAG), and before the offset error correction. Therefore, in a specific embodiment, the relative slope error can be corrected before the offset error correction. Referring to the labels shown in Fig. 8, the offset error can be determined using the following equation: where: Equations (12) and (13) can be used to correct the offset error ΔI after the relative slope error has been corrected. If there is a relative slope error, it is preferable to apply the correction of the relative slope error before the correction of the offset error. However, embodiments of the present disclosure may apply the offset error correction before the relative slope error correction. Another embodiment may apply only the offset error correction. Fig. 9(a) is a time diagram of the digitized inductor current DIL during the operation of an exemplary embodiment of the present disclosure, for example, with respect to the device shown in Fig. 6(a). In the present example, the offset error was corrected by aligning the digitized inductor current DIL (a curve 900) with the analog inductor current IL (a curve 902). In the present example, the digitized inductor current DIL was aligned with the analog inductor current IL at the threshold values ​​DISET1, ISET1. Fig. 9(b) is a time diagram of the digitized inductor current DIL during the operation of an exemplary embodiment of the present disclosure, for example, with respect to the device shown in Fig. 6(a). In the present example, the offset error was corrected by aligning the digitized inductor current DIL (a curve 904) with the analog inductor current IL (a curve 906). In the present example, the digitized inductor current DIL was aligned with the analog inductor current IL at the threshold values ​​DISET2 and ISET2. If the slopes of DIL (SR_DIL) and IL (SR_IL) are not identical and the offset is corrected, the two waveforms can be aligned to the I-SET1, DISET1 threshold (as in Fig. 9(a)) or to the ISET2, DISET2 threshold (as in Fig. 9(b)). However, the average digitized inductor current (which is <dil>(which can be designated) and the average analog inductor current (which is characterized by <il>(can be described) unequal. Fig. 10 is a timing diagram showing the digitized current signal DIL and the analog current signal IL during the operation of an exemplary embodiment of the present disclosure, for example, with respect to the device shown in Fig. 6(a), wherein the energy storage element 602 is an inductor that is part of a buck converter. The present example can use the offset error correction and relative slope error correction methods as described with respect to Fig. 8. In the present example, the relative slope error and then the offset error are corrected by the correction circuit 600 during operation. A curve 1000 of the digitized inductor current DIL and a curve 1002 of the analog inductor current are shown. In this example, the correction circuit 600 applies a relative slope error correction and an offset error correction at the end of two successive demagnetization phases at time 1006 and time 1008. After time 1008, the signals DIL and IL are considered aligned, and therefore the correction circuit 600 has corrected the digitized current signal DIL. It is evident that in a further embodiment, the correction can be applied at the end of the magnetization phase rather than at the end of the demagnetization phase.It is obvious that in further embodiments the correction can be applied at any time during the switching cycle. In further embodiments, the correction method provided by the correction circuit 600 can be applied based on one or more of the following conditions: • at each switching cycle • every N switching cycles, where N is an integer • non-periodic • as required, as determined either from measured errors or from an external source • when calculated errors exceed a predefined threshold • during mode changes (e.g., when switching from single-phase to multi-phase operation) • when transitions are detected (e.g., load transitions, supply transitions, or temperature changes) These corrections prevent residual errors from accumulating. Although they themselves may still contain some residual errors, the corrections can be enforced if necessary, thus limiting the (DIL-IL) error. Fig. 11 is a schematic representation of a specific embodiment of the correction circuit 600 and the switching converter 604, wherein the switching converter 604 is a buck converter, and according to a third embodiment of the present disclosure. In the present embodiment, the buck converter 604 comprises a capacitor 1100, the power switch 606 is a high-side switch and a low-side switch 1101; the correction circuit 600 comprises a logic block 1102 and two comparator units 1104; an analog-to-digital converter (which, as previously described, can function as a current synthesizer 612, generating DIL based on equations (1) and (2)); The comparator circuit 608 comprises a timing extraction unit 1106, a timing extraction unit 1108, an offset and relative slope error extraction unit 1110 and optionally a filter unit 1112.The timing extraction unit 1108 includes time-to-digital converters 1108a and 1108b. It is evident that the ADC 612 represents a method for generating the digitized inductor current DIL, and that further embodiments may employ alternative methods for generating the digitized inductor current DIL, according to the understanding of those skilled in the art. The digitized inductor current DIL method can, for example, be sensor-based or sensorless. In the present embodiment, each of the comparator units 1104 comprises a comparator. It is obvious that alternative implementations are possible in other embodiments, according to the understanding of those skilled in the art. In the present example, the current flow IL is detected by measuring the voltage drop across the low-side switch LS 1101 and is described in more detail below. In another embodiment, the current flow IL can be detected using the HS switch 606, and the alignment of IL and DIL can then be performed during MAG instead of DEMAG. As discussed previously, the analog current signal IL (used for comparison with the digitized current signal DIL) and the current flow through the inductor 602 are both denoted by the variable "IL" to indicate that the analog current signal IL is representative of the current flow through the inductor. The logic block 1102 is used to generate DISET1 and DISET2 such that they are positioned between the peak and trough of DIL. In the present embodiment, the offset error signal (denoted I_ERR) and the relative slope error (denoted SR_ERR) are examples of the correction signal 601, as previously described. Using the information provided by these signals, the current synthesizer 612 corrects the offset error and the relative slope error when generating the digitized inductor current DIL. Fig. 12 is a timing diagram of the digitized current signal DIL (a curve 1200) and the analog current signal IL (1202) during the operation of an exemplary embodiment of the present disclosure, for example, with respect to the device shown in Fig. 11. Also shown is a first comparator output signal COMP1 (a curve 1204), which is an output from one of the comparators of one of the comparator units 1104; a second comparator output signal COMP2 (a curve 1206), which is an output of the comparator of the other comparator unit 1104; and a clock signal CLKS (a curve 1208). In previous time diagrams, the digitized inductor current DIL was represented as continuous time. As discussed, in practice, the digitized inductor current DIL is a time-discrete, value-discrete digital signal. The analog current signal IL represents the real inductor current and is continuous in both time and value. It is evident that there are several possible methods for determining the timing of the points, as discussed above. The following discussion refers to one such example method, as described with reference to Figures 11 and 12. Points C and D in Fig. 12 refer to the actual current flow IL(t) through the inductor 602. In this example, the comparator units 1104 are used to detect the analog inductor current IL and compare it with the threshold values ​​ISET1 and ISET2. Each of the two comparator units 1104 is configured to compare the analog inductor current IL with one of the threshold values ​​ISET1 and ISET2. In the present embodiment, the comparators would detect the digitized inductor current IL as a voltage drop across the device resistor 1101 of the low-side switch. The threshold values ​​ISET1, ISET2 are voltage references obtained from the digital threshold values ​​DISET1, DISET2 via a DAC 1114. Assuming zero offset and zero delay for the comparators of comparator units 1104, outputs COMP1 and COMP2 are generated. The rising edge of COMP1 represents point C, and the rising edge of COMP2 represents point D. The delay between these signals can then be measured and converted into a digital number via the timing extraction unit 1108, which includes the time-to-digital converters 1108a and 1108b. It is evident that alternative methods for extracting the time delay can be used in further embodiments, according to the understanding of those skilled in the art. Points A and B refer to the digitized inductor current DIL[n], which is a time-discrete, value-discrete signal. A simple way to calculate the T_AB delay is to monitor the values ​​of the digitized inductor current DIL at each clock cycle and determine whether the DISET1 (or DISET2) level has been exceeded. Knowing the values ​​of the digitized inductor current DIL before and after the crossing, an interpolation (e.g., linear interpolation) can be performed to determine the time at which the digitized inductor current DIL exceeded DISET1 or DISET2. Knowing the integer number of clock cycles between A and B, the fraction of a processing period TS, the time step T_A, and the time step T_B, the total T_AB can be calculated. T_AB can correspond to ΔT_DIL, as described with reference to Fig. 8. Determining the delay T_AC uses two reference points on two different signals DIL and IL, located in different areas (digital and analog). One possible solution is to measure the time T_C instead of directly measuring T_CD. This allows T_AC to be calculated as follows: where N is the integer number of clock periods that have elapsed between the end of the T_A measurement and the end of the T_C measurement, and N=2 in Fig. 12. It is obvious that the method used to determine T_AC can also be applied to determine T_BC or T_BD. It is evident that the digitized inductor current DIL and the analog inductor current IL, as shown in Fig. 12, have linear slopes, since their values ​​both rise and fall. It is evident that the method for extracting the time delays T_AB, T_CD, T_AC, T_BD, as described with reference to Fig. 12, can also be applied to nonlinear slopes, for example, including exponentially decaying waveform sections for both IL and DIL. However, the accuracy may be affected compared to the linear examples, since the previously described method uses an approximation of the linear slope. It is obvious that other methods for determining the delays can be used for nonlinear slopes, according to the understanding of those skilled in the art. Figure 13 is a time graph showing simulation results of a practical implementation of a known system using a low-bandwidth correction mechanism. It depicts the output voltage of a buck converter (curve 1300); the analog inductor current IL (curve 1302); the digitized inductor current DIL (curve 1303); and the current error I_ERR, which after filtering is equal to DIL - IL (curve 1304). Curves 1302 and 1303 appear to overlap in the graph. The error I_ERR before the transition, as it occurs at time TA, is small due to a long settling time (more than 500 µs). After the load transition, a large error I_ERR accumulates rapidly. The error I_ERR decreases very slowly over time to a minimum value of -740 mA. Fig. 14(a) is a time graph showing simulation results of a practical implementation of the system shown in Fig. 11, using cycle-by-cycle correction. The simulation results shown here demonstrate the same load transition as shown in Fig. 13, and in this example, the system reaches a stable state more quickly than in the example shown in Fig. 13. The graph shows the output voltage of the buck converter (curve 1400); an analog inductor current IL (curve 1402); a digitized inductor current DIL (curve 1403); a current error I_ERR, which after filtering is equal to DIL - IL (curve 1404); a digitized inductor current slope SR_DIL (curve 1406); and an analog inductor current slope SR_IL (curve 1408). The error I_ERR starts at a similar value (45 mA) and reaches -290 mA due to errors caused by load transitions. The error I_ERR is then quickly corrected. SR_IL and SR_DIL are also shown before and after the load transition. SR_IL and SR_DIL converge quickly, even though filtering is applied to the slope correction. In another embodiment, the relative slope error can be completely corrected in one cycle. Fig. 14(b) is the time diagram of Fig. 14(a) over a shorter timescale. The offset correction is applied at the end of MAG (t = 251 µs). Fig. 15 is a schematic representation of a comparator unit 1500, which can be used for one or both of the two comparator units 1104 of Fig. 11. The comparator unit 1500 comprises switches 1502, 1504, 1506, 1508, 1510, 1512; capacitors 1514, 1516, 1518; an operational amplifier 1520 and a comparator 1522. In the examples above, it was mentioned that a comparator with no delay and no offset is desirable for determining points C and D. For the present disclosure, some approximations can be made that make it possible to effectively emulate a comparator with no delay and no offset. The present example can achieve zero offset and zero delay when used in the embodiments disclosed herein by clarifying that the property of the buck converter (or any other switching converter) allows certain assumptions to be made regarding the inputs of these comparators. When determining T_CD, the absolute comparator delay is not important as long as the delays between the two comparators are the same. However, the absolute comparator delay is important for offset correction (based on point C or D). As shown in Fig. 15, one of the inputs of the comparator 1522 is constant (VN) and the other input has a relatively predictable slope defined by SR_IL. The current sources 1114 are dimensioned such that the comparator 1522 switches when IL=ISET1 or IL=ISET2. This System 1500 can achieve a near-zero offset and, taking into account the IL slope constant, a near-zero delay. The System 1500 samples the residual voltage VOFFS at the time the comparator 1522 switches and, based on this, adjusts an additional offset (VOFFS_COMP) at the input of the comparator 1522 so that VP = (VSW_SNS + VOFFS_COMP). The stable state is reached when comparator 1522, COMP, switches precisely when the residual offset, VOFFS, is zero. This results in a comparator with no delay and no offset. This works as long as the slope of the inductor current SR_IL remains constant. If the slope changes (due to VIN / VOUT, load transitions, or temperature effects), the system will introduce an error until it returns to a new stable state. In summary, embodiments of the present disclosure can be used to correct the DIL-IL error with respect to both offset and ripple (via slope adjustments). Specific embodiments described herein perform offset error correction in a digitized inductor current DIL in a switching-mode power converter by aligning it with one or more measured points of the real inductor current (or a signal derived from the real inductor current) designated “IL”. Embodiments of the present disclosure also perform slope (rise rate) error correction of a digitized inductor current DIL in a switching-mode power converter by aligning it with two or more measured points of the real inductor current (or a signal derived from the real inductor) designated “IL”.Embodiments of the present disclosure perform a correction of offset and slope (rise rate) errors of a digitized inductor current DIL in a switching-mode power converter by aligning it with two or more measured points of the real inductor current (or a signal derived from the real inductor current) designated “IL”. Embodiments of the present disclosure use delay measurements (in the analog domain) and direct delay calculations (in the digital domain) in calculating an offset and slope (rise rate) correction. Various improvements and modifications can be made to the above without altering the scope of the disclosure.< / il> < / dil>

Claims

A correction circuit (600) for correcting one or more errors in a digitized current signal, wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element (602), wherein the correction circuit (600) is configured to correct an offset error between the digitized current signal and the analog current signal by: a) comparing the digitized current signal with the analog current signal to determine the offset error by: i. detecting a first time step when the digitized current signal crosses a first digital threshold; ii. detecting a second time step when the analog current signal crosses a first analog threshold; iii. calculating a first duration between the first time step and the second time step; iv. determining a first slope of at least one of the digitized current signal and the analog current signal; v.Multiplying the first duration by the first slope to determine the offset error; and b) correcting the digitized current signal using the determined offset error; and / or wherein the correction circuit (600) is configured to correct a relative slope error between the digitized current signal and the analog current signal by: a) comparing the digitized current signal with the analog current signal to determine the relative slope error by: i. detecting a first time step when the digitized current signal crosses a first digital threshold; ii. detecting a second time step when the analog current signal crosses a first analog threshold; iii. detecting a third time step when the digitized current signal crosses a second digital threshold; iv. detecting a fourth time step when the analog current signal crosses a second analog threshold; v.a) Calculate a first digital slope delay between the first time step and the third time step; b) Calculate a first analog slope delay between the second time step and the fourth time step; c) Divide the first analog slope delay by the first digital slope delay to calculate a first delay parameter, then subtract one from the first delay parameter to determine the relative slope error, and d) Correct the digitized current signal using the determined relative slope error. The correction circuit according to claim 1, wherein the digitized current signal is provided by a current synthesizer. The correction circuit according to claim 2, wherein the correction circuit is configured to: generate a correction signal which depends on the result of the comparison; and provide the correction signal to the current synthesizer, wherein the correction signal is suitable for correcting one or more errors in the digitized current signal when received by the current synthesizer, thereby correcting the digitized current signal based on the result of the comparison. The correction circuit according to claim 1, which is configured to correct the relative slope error prior to correcting the offset error. Method for correcting one or more errors in a digitized current signal using a correction circuit (600), wherein the digitized current signal is a digital representation of an analog current signal of a current flow through an energy storage element (602), the method comprising: correcting an offset error between the digitized current signal and the analog current signal by: a) comparing the digitized current signal with the analog current signal to determine the offset error by: i. detecting a first time step when the digitized current signal crosses a first digital threshold; ii. detecting a second time step when the analog current signal crosses a first analog threshold; iii. calculating a first duration between the first time step and the second time step; iv. determining a first slope of at least one of the digitized current signal and the analog current signal; v.Multiplying the first duration by the first slope to determine the offset error; and b) correcting the digitized current signal using the determined offset error; and / or correcting a relative slope error between the digitized current signal and the analog current signal by: a) comparing the digitized current signal with the analog current signal to determine the relative slope error by: i. detecting a first time step when the digitized current signal crosses a first digital threshold; ii. detecting a second time step when the analog current signal crosses a first analog threshold; iii. detecting a third time step when the digitized current signal crosses a second digital threshold; iv. detecting a fourth time step when the analog current signal crosses a second analog threshold; v.a) Calculate a first digital slope delay between the first time step and the third time step; b) Calculate a first analog slope delay between the second time step and the fourth time step; c) Divide the first analog slope delay by the first digital slope delay to calculate a first delay parameter, then subtract one from the first delay parameter to determine the relative slope error, and d) Correct the digitized current signal using the determined relative slope error.

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