Lithographic mask with overlay mark and associated process

Abstract

A method comprises the following: generating a designed mask cover mark associated with a real mask cover mark to be generated in a mask; generating the real mask cover mark in the mask based on the designed mask cover mark, wherein the real mask cover mark contains a plurality of cover structures, none of the plurality of cover structures having a dimension greater than approximately 100 nm; generating a device element structure adjacent to the real mask cover mark; performing an alignment of the mask by means of a mask measuring device having a light source with a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of cover structures is not greater than the wavelength divided by twice the numerical aperture;and generating a structure in a layer of a wafer by transferring the device element structure while the mask is aligned.

Description

BackgroundThe IC (semiconductor integrated circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs, each generation having smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the feature size (i.e., the smallest component or line that can be generated with a fabrication process) has decreased. This downsizing process generally offers advantages of increasing production efficiency and decreasing associated costs, but it has also increased the complexity of processing and manufacturing ICs.Brief Description of the DrawingsAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. FIG. 1 is a schematic diagram illustrating an alignment of structural elements of material layers on a semiconductor wafer according to embodiments of the present disclosure.FIGS. 2A to 2D are diagrams of various embodiments for determining a position of a mask overlay mark according to various aspects of the present disclosure. FIG. 3 is a schematic illustration of a mask overlay mark in accordance with various aspects of the present disclosure. FIG. 4 is a sequential illustration of the use of a mask overlay mark in accordance with various aspects of the present disclosure. FIG. 5 is a schematic diagram illustrating in detail a portion of a mask overlay mark according to various embodiments.FIGS. 6A to 12E are schematic diagrams of overlay structures and mask overlay marks according to various embodiments. FIG. 13 is a schematic illustration of a mask measurement apparatus according to various embodiments. FIG. 14 is a flow diagram of a method of manufacturing an IC device according to various embodiments.FIGS. 15A and 15B are schematic diagrams of a mask according to various embodiments.Detailed DescriptionThe following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the description below, the formation of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90° or in another orientation) and the spatially relative descriptors used herein interpreted accordingly.Terms indicating a relative extent, such as the terms "about", "substantially", and the like, should be construed as would be done by one of ordinary skill in the art in view of current technical standards.Although the terms "first(r) / first", "second(r) / second", "third(r) / third", etc. may be used herein to describe an order of events or a sequential order of elements, they may be interchanged or modified in some contexts. For example, a second layer may be formed on (e.g., sequentially after) a first layer, but in some contexts, the first layer may be referred to as a "second layer", "third layer", fourth layer", or the like, and the second layer may be referred to as a "first layer", "third layer", fourth layer", or the like.The term "comprises" may be used herein to describe a structure that fully or partially comprises another element or structure, for example three-dimensionally. For example, a first structure may enclose a second structure on four sides (e.g., left, right, front, and rear) without enclosing the second structure on two vertical sides (e.g., top and bottom). In another example, the first structure may partially enclose the second structure by, for example, enclosing three sides (e.g., top, front, and back), while other sides (e.g., left, right, and bottom) remain uncovered.The present disclosure is generally directed to methods of manufacturing device elements, such as semiconductor devices, interconnect structures (e.g., wires, conductive traces, vias, pins, contacts, and the like), capacitors, memory devices, and the like. The semiconductor devices may be field effect transistors (FETs) such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructure FETs such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAA-FETs), and the like.Scaling distances and / or pitches is becoming more difficult in sophisticated process nodes. Mask coverage is a code to indicate how exactly a positioning of a structure on a mask is. A mask overlay mark is a pattern on the mask that is used to monitor the performance of the mask overlay. Some mask overlay marks are or include single small squares having a size of about several hundred nanometers (nm), e.g., about 400 nm, which increases the difficulty in establishing a robust overlay measurement process. These small overlay structures are still large enough to print on a wafer.In embodiments of the disclosure, a mask overlay mark is provided that includes much smaller elements with a combination of selected pitches and / or sizes. Based on these embodiments, individual elements for a mask fabrication process and associated tools are decomposable, but beyond resolution for mask coverage measurement tools. Contours of the individual elements are therefore recognized by mask coverage measurement tools as a larger solid element. The individual elements are also beyond resolution for a wafer patterning process and associated tools so that the mask overlay mark is not printed on the wafer.By using small elements with a selected range of pitches and / or one or more pitch combinations as the mask overlay mark, improved mask overlay reliability and repeatability performance and robust mask overlay measurement on the mask are achieved without printing the pattern on the wafer.FIG. 1 is a schematic diagram illustrating an alignment of structural elements of material layers on a semiconductor wafer according to embodiments of the present disclosure. In FIG. 1, a semiconductor wafer 100 (or simply "wafer 100") is processed to produce features 101, 102, 103 thereon. The features 101, 102, 103 may be additive features such as dielectric layers, conductive layers, semiconductor layers, epitaxial layers, and the like, and / or may be subtractive features such as openings, trenches, grooves, holes, and the like.A first pattern element 101 is produced on the wafer 100 by transferring a first light transmitting a first pattern 121 of a first mask 111 to one or more layers (e.g. a photoresist) on the wafer 100 or the wafer 100. An upper row of FIG. 1 shows, after the production of the first structural element 101, a production of a subsequent second structural element 102 and a third structural element 103 which are aligned exactly with the first structural element 101. The second pattern element 102 is formed on the first pattern element 101 by transferring a second light transmitting a second pattern 122 of a second mask 112 to one or more layers (e.g., a photoresist) on the wafer 100 or the wafer 100. The second structural member 102 is aligned with the first structural member 101 as shown by broken lines in FIG. 1. The third pattern element 103 is formed on the first pattern element 101 and the second pattern element 102 by transferring a third light transferring a third pattern 123 of a third mask 113 to one or more layers (e.g. a photoresist) on the wafer 100 or the wafer 100. The third structural member 103 is aligned with the second structural member 102 and the first structural member 101 as illustrated by broken lines in FIG. 1.A lower row of FIG. 1 shows the fabrication of the second and third structural elements 102, 103 that are not exactly aligned with the first structural element 101. For example, the second structural member 102 may be offset to the left relative to the first structural member 101 on the sheet in FIG. 1. Then, the third structural member 103 may be displaced to the right with respect to the first and second structural members 101, 102 on the sheet in FIG. 1. This may result in multiple defects. For example, when forming an upper conductive feature on a lower conductive feature embedded in a dielectric layer, an opening in which to form the upper conductive feature offset from the lower conductive feature may be etched into the enclosing dielectric layer. When the upper conductive feature is formed, it may seat on the lower conductive feature, but it may also extend into the dielectric layer below the lower conductive feature. This extension may result in reduced time-dependent dielectric breakdown (TDDB), which may shorten the lifetime of an IC device with the offset upper conductive feature. This is an example of a disadvantageous effect of the offset between the first, second and third structural elements 101, 102, 103. The offset may also result in other types of effects that may decrease circuit performance, increase defects that decrease yield, or the like.FIGS. 2A to 2D are diagrams of various embodiments for determining a position of a mask overlay mark according to various aspects of the present disclosure. The position of a pattern such as the mask registration mark or a pattern of a connector generated thereon as the mask registration mark can be determined by operating a mask measurement apparatus. Exemplary components and functions of a mask measurement device 130 will be described in more detail below with reference to FIG. 13. The description provides a context for understanding the embodiments of the disclosure described with reference to FIGS. 3 to 12E and 14. The mask measurement apparatus 130 of FIG. 13 may perform one or more operations described with reference to FIGS. 2A to 2D.The mask measurement device 130 is operable to measure and verify dimensions, structures, and an orientation of pattern elements on photomasks used in semiconductor manufacturing. High accuracy of these measurements is advantageous in ensuring high yield and performance of the final semiconductor devices. In some embodiments, the mask measurement device 130 may include: an optical microscope 1310; an interferometer 1320; camera and / or detector systems 1330; one or more stages 1340; a light source 1350; a computing device or controller 1360; a user interface 1370, and / or environmental controls 1380, and the like. Some elements of the mask measurement device 130 may be omitted from the illustration of FIG. 13 for convenience of explanation.Light microscope 1310 can be used to enlarge features on the mask for visual inspection and measurement. For sophisticated nodes where structural elements are extremely small, high resolution microscopes can be used. Interferometer 1320 may allow for even higher accuracy, and interferometer methods may be used to measure dimensions and distances between structural elements with increased precision. The camera and / or detector systems 1330 may include high resolution cameras operable to capture images of mask elements and fiducials for analysis. The cameras may be gray scale or color cameras that are advantageous for the mask measurement device. The tables 1340 can hold the mask, move it in the x, y and z directions with high precision, and rotate it for a complete test. The light source 1350 may be a highly stable monochromatic light source that exposes the mask. For mask measurement devices used for sophisticated technology nodes, UV light sources are favorable. The computing unit or processor or controller 1360 may be operable to execute software algorithms that analyze captured images to measure sizes, distances, and any offsets of structural elements. For more accurate and faster analysis, machine learning may be used in the computing unit. The controller 1360 may control the operation of the various elements of the mask measurement device 130, for example, via electrical signals. The user interface 1370 may include a display and / or a control panel that allows operators to input parameters, control the mask measurement device, and view results. The environment controls 1380 may be operable to remove minute contaminants or avoid temperature fluctuations that may affect measurements, wherein the environment controls 1380 may be incorporated into the mask measurement device 130.Operations of the mask measurement device 130 may include size measurement, pattern verification, registration accuracy, defect inspection, recording accuracy, data analysis, feedback for mask production, documentation, and the like. During size measurement, width, height, and other dimensions of the features on the mask may be measured and compared to design specifications. In pattern verification, it can be confirmed that the various shapes, lines, and patterns are formed on the mask as intended. Overlay marks may be used for overlay accuracy, so that mask measurement device 130 may measure how exactly different layers of features on a multilayer mask are aligned with each other. In defect control, defects such as finest holes, cracks or defectively positioned features may be identified, which may affect the semiconductor manufacturing process. For recording accuracy, the exact position of alignment marks is measured to ensure that the mask is properly aligned with the wafer during lithography. Data generated for quality control, mask qualification and process optimization can be used for the data analysis. The data may also be fed back to improve the mask fabrication process itself. The mask measurement device 130 may also generate traceability, conformance, and further analysis protocols.In FIG. 2A, in a first operation 20A, a designed structure 200D having a box shape indicated by a broken line in FIG. 2A may be designed to be disposed at a position that may be associated with a center 210D having coordinates (x, y). A real structure 200A is present in a mask. The designed structure 200D and the real structure 200A may each be referred to simply as a "structure" throughout. The structure 200A may be a capping structure or a device element structure. The pattern 200A is a real pattern present in the mask. Namely, the structure 200A may be a geometric shape present in one or more reflective layers of the mask. A position of the structure 200A in the mask may be unknown first. For example, a center point 210A may be unknown. The mask measurement device may be used to determine the center point 210A of the structure 200A. For example, the mask measurement device may determine the center 210A of the real structure 200A and / or an offset of the center 210A of the real structure 200A from the center 210D of the designed structure 200D.In a second operation 20B, a region of interest (ROI) 220 may be selected to overlap the real structure 200A to detect edges of the real structure 200A. In the example shown in FIG. 2A, the ROI 220 may be selected to detect edges associated with the x-coordinate of the center 210A. In most embodiments, two ROIs, vertical and horizontal, are used to detect edges associated with the x and y coordinates of the center 210A, respectively. For ease of illustration, only one ROI 220 is shown in each of FIGS. 2A and 2B and described with reference thereto. Examples showing horizontal and vertical ROIs will be described below with reference to FIGS. 2C, 2D, and 3.The ROI 220 may be associated with a light or electron micrograph of the mask. For example, when image analysis methods are used to place a mask overlay mark in an image of the mask, selecting an ROI 220 may promote efficiency and accuracy. In some embodiments, a high resolution image of the mask may be captured that may include various elements and marks, such as a representation of the real structure 200A. Instead of processing the entire image, the ROI 220 is selected around a region where the real structure 200A is expected to be present. The ROI 220 may be a rectangular or other shaped region and its size may be selected manually or dynamically based on previous marks or slices.In operation 20C, basic image preprocessing methods, such as noise reduction filters (e.g., a Gaussian unsharp filter), may be used in the ROI 220 to smooth the image and improve edge detection accuracy. Then, algorithms such as Canny, Sobel, or Prewitt algorithms may be used in the ROI 220 to identify edges of the real structure 200A. These algorithms identify regions where a strong intensity gradient occurs, which often corresponds to a boundary of an element. This is illustrated in FIG. 2A by a diagram 230 in which an intensity curve 232 has a left and a right intensity gradient 232L, 232R, which correspond to a left and a right edge 202L, 202R of the real structure 200A, respectively. In some embodiments, the edge detected image in the ROI may then undergo texture matching algorithms to identify the shape or layout of the overlay mark. In some embodiments, the use of structure adaptation algorithms may be omitted, for example, when the real structure 200A is known to have a box or square shape.In FIG. 2B, after the real structure 200A has been identified, its coordinates, e.g., coordinates (A,B), are determined in an operation 20D with respect to the entire mask image. In an example, for a simple geometry, such as a square, the coordinates may be determined based on an equation, such as (Edge1+ Edge2) / 2, where Edge1is a coordinate of a first edge (e.g., right edge 202R) and Edge2is a coordinate of a second edge (e.g., left edge 202L). This calculation may be repeated for the horizontal coordinate (e.g., the x-coordinate) and the vertical coordinate (e.g., the y-coordinate) of the center 210A. The coordinates provide an exact position of the real structure 200A that may be used for alignment or other measurement purposes. Further operations may include cleaning the edges with morphological operations or using curve fitting to represent the detected edges in mathematical form for more precise measurements. The detected position and shape of the real structure 200A may then be checked, for example, by comparing with expected or historical data to ensure accuracy.In operation 20E, a mask registration offset 240 may be calculated as (A,B)-(x,y). The mask registration offset 240 may include a horizontal or x-axis offset (e.g., x-A) and a vertical or y-axis offset (e.g., y-B). The mask registration offset 240 may be associated with the mask and may be feedforwarded for a later process. For example, the mask registration offset 240 associated with the mask may be feedforward for an exposure process such that a wafer stage that controls a position of a wafer exposed by a pattern of the mask may be slightly offset based on the mask registration offset 240 such that the pattern may be accurately aligned with respect to underlying layers and / or features that have already been fabricated.FIGS. 2C and 2D are schematic diagrams illustrating ROIs 220H, 220V used to detect a large or medium-sized real structure 200A (FIG. 2C ) and a small real structure 200S (FIG. 2D ) for the same offset.In FIG. 2C, since the position of the real structure 200A is unknown, ROI settings may be selected based on a design layout. Large mask overlay marks (e.g., real structure 200A) have a large tolerance for process errors and job settings. The horizontal ROI 220H that is selected completely overlaps the real pattern 200A in the x-axis direction, and the vertical ROI 220V that is selected completely overlaps the real pattern 200A in the y-axis direction. Therefore, the mask measurement device successfully determines the coordinates (A, B) of the center 210A.In FIG. 2D, for a small mask overlay mark, the tolerance for process errors and job settings may be small. Thus, for the same overlay offset, one or both of the ROIs 220H, 220V may not overlap the real structure 200S as shown. Since the ROIs 220H, 220V do not cover the real structure 200S, edges of the real structure 200S are not detected, the position of a center 210S of the real structure 200S is not calculated, and the measurement fails. This increases the difficulty in identifying the small real structures 200S, as ROI settings that are misaligned may result in failure to detect the real structure 200S.FIG. 3 is a schematic illustration of a designed mask overlay mark 30D and a real mask overlay mark 30A, in accordance with various aspects of the present disclosure. The designed mask registration mark 30D is associated with dramatically simpler ROI settings, which improves the detection of the real mask registration mark 30A with the mask measurement device 130.The designed mask overlay mark 30D has two or more very small overlay structures 300 that can be arranged in a matrix as shown or in another suitable manner. In the embodiment shown in FIG. 3, the designed mask overlay mark 30D has 49 overlay structures 300 arranged in a 7×7 matrix. The overlay structures 300 may be equally spaced along two axes, such as an x-axis and a y-axis, as shown. The overlay structures 300 may be hollow square structures. In some embodiments, the overlay structures 300 are solid or hollow, and may have a geometric shape, and may be, but are not limited to, a square, a rectangle, a triangle, a circle, a polygon (e.g., a hexagon, an octagon, or the like), an irregular shape, a combination thereof, or the like. Example shapes and arrangements of the overlay structures 300 will be described in more detail below with reference to FIGS. 6A-12E. The designed mask overlay mark 30D may have a shape that is an entirety of the overlay structures 300 and may itself be substantially solid or hollow, and may have a substantially geometric shape and may be, among other things, a square, a rectangle, a triangle, a circle, a polygon (e.g., a hexagon, an octagon, or the like), an irregular shape, a combination thereof, or the like. For example, the designed mask overlay mark 30D having hollow square overlay structures 300 may itself be in the form of a square (as shown), a rectangle, a triangle, another polygon, or the like, which may be "solid" or "hollow.". An example of a "hollow" overlay mark is shown in and described with reference to Figure 4.In FIG. 3, a region 35A of a real mask registration mark 30A corresponds to a region 35D of the designed mask registration mark 30D. The overlay structures 300 are used to generate the real mask overlay mark 30A in a mask. Therefore, the real overlay structures 300 overall form the real mask overlay mark 30A. The real mask registration mark 30A is easily detected using horizontal and vertical ROIs 320H, 320V. However, since the real overlay structures 300A are less than a resolution of the mask measurement device 130 and / or a wafer lithography device (e.g., an EUV step and scan device), the real overlay structures 300A are not resolved. Therefore, the real overlay structures 300A are not printed on a wafer that is exposed to patterned light generated with the mask. This will be described in more detail below with reference to FIG. 4.FIG. 4 is a sequential illustration of the use of a designed mask overlay mark 40D in accordance with various aspects of the present disclosure. FIG. 4 illustrates various operations or stages 42A, 42B, 42C, 42D of a semiconductor fabrication process using a mask having the mask overlay marks 40D, 40A.In a first operation 42A, which may be a mask design operation, a designed mask overlay mark 40D is selected and / or designed that has two or more very small overlay structures or elements 400 arranged in a combined form. The very small elements 400 may be combined with a selected pitch and / or size (e.g., as a hollow square shape). For example, the overlay structures 400 may be combined into a combined shape having an area on the order of several hundred μm 2 and e.g. 20 μm by 20 μm=400 μm 2. In some embodiments, another suitable shape, such as one of the shapes described with reference to FIG. 3, is used instead of the hollow square shape shown in FIG. 4. The overlay structures 400 may be similar in many respects to embodiments of the overlay structures 300 described with reference to FIG. 3.In a second operation 42B, a mask is produced that has real overlay structures 400A included in a real mask overlay mark 40A. FIGS. 15A and 15B illustrate a mask 150 according to various embodiments. The mask 150 may include a substrate 151 that may include a low thermal expansion material for minimizing or reducing distortion under an extreme ultraviolet (EUV) light source. The mask may be a multilayer grid 153, which may include or contain a series of alternating layers of materials such as molybdenum (Mo) and silicon (Si) deposited on the substrate. The layers may form a Bragg reflector that efficiently reflects EUV light. The mask may include an absorber layer 155 in which an absorption material is used for the multilayer grating. The absorber layer 155 may include or contain materials such as tantalum nitride (TaN) that can efficiently absorb EUV light. The mask may include a capping layer (not individually shown), which may be a protective layer used to protect the absorber layer and the multilayer grating from damage and typically includes a material such as ruthenium (Ru). First, a mask blank with the substrate and the multilayer coating, but without selected structures in the absorber layer, can be provided.The real overlay structures 400A generally take over the position, size, and shape of the overlay structures 400 of the designed mask overlay structure 40D. The individual elements 400A are accurately formed on the mask 150 by a mask manufacturing process and equipment. For example, the real-coverage structures 400A may be created with one or more write operations, which may include an electron or ion beam write operation, an etch operation, another suitable write operation, or the like. For high precision, which is advantageous for EUV lithography, electron beam writing is often used to generate patterns (e.g., the overlay patterns 400A) on the mask 150. An electron beam is directed to write the design to a resist layer deposited over the absorber layer 155. After the electron beam exposure, the mask 150 may be developed and exposed or unexposed portions of the resist are removed, leaving behind the structures (e.g., the capping structures 400A) to be etched into the absorber layer 155. The structure is then typically etched into the absorber layer 155 by reactive ion etching (RIE) or similar process, exposing the final structure, exposing the underlying multilayer grid 153 from openings 157 in the absorber layer 155. The mask 150 may undergo a series of cleaning and inspection processes to check whether the mask meets specifications and is error free. Defects found may occasionally be repaired by methods such as focused ion beam milling (FIB milling) or electron beam induced deposition (EBID).In FIG. 25A, the mask 150 may include a device element pattern region 152 including a plurality of device element patterns. The mask 150 may include one or more mask registration marks 154. One or more of the mask overlay marks 154 may be placed outside and adjacent to the device element pattern area 152. One or more of the mask overlay marks 154 may be placed within the device element pattern region 152, for example, adjacent to one or more of the plurality of device element patterns.In a third operation 42C, an image 40I of the mask is captured, which may be a part of an image of the entire mask or an image of a part of the mask. The image 40I may be a digital representation of the real mask registration mark 40A. Individual elements (e.g., the real overlay structures 400A) may be too small to be resolved by the mask measurement device 130, which captures and / or operates the image, such that contours of the real overlay structures 400A are merged into a solid structure 40P, as shown in FIG. 4. Edges of the solid structure 40P may be smoothed in some embodiments.In a fourth operation 42D, a pattern of the mask is transferred to a layer of a wafer or to a layer located on the wafer. The structure may include device element structures. Since the real overlay structures 400A are very small and may be below a resolution limit of a wafer patterning tool (e.g., an EUV step and scan device), the mask real overlay structures 400A are not printed on the wafer by the wafer patterning tool.If the designed mask overlay mark 40D does not include the overlay structures 400, but is a solid continuous structure, such as a hollow square with solid continuous lines having a thickness similar to that shown in FIG. 4, the real mask overlay mark 40A would still be accurately generated on the mask with the mask manufacturing process and the mask manufacturing facility. In the third operation 42C, although the real mask registration mark 40A would be accurately detected by the mask measurement device 130, it may have sharp edges instead of the smooth edges described above. Then, in the fourth operation 42D, the real mask registration mark 40A is transferred to the wafer by the wafer patterning apparatus. The overlay structures 400 (if present) are advantageous to avoid transfer of the real mask overlay mark 40A to the wafer.As has been explained above, pitches and / or sizes of the real masking structures 400A and / or the real mask masking mark 40A can be selected on the basis of the resolution of the mask measuring device 130 such that the real mask masking mark 40A is not resolved by the mask measuring device 130. Based on the configuration of the wafer patterning tool, the spacing and / or size of the real overlay structures 400A and / or the real mask overlay mark 40A may be selected such that the mask overlay mark is not printed on the wafer. For example, dimensions of the capping structures 400A (e.g., width or length) may be less than about 100 nm such that the capping structures 400A do not form a pattern on a wafer after the exposure process using the EUV mask. Example dimensions will be briefly described below with reference to FIG. 5 for various mask measurement devices 130 and wafer patterning tools.FIG. 5 is a schematic diagram illustrating in detail a portion of a designed mask overlay mark 50D having overlay structures 500 according to various embodiments. The designed mask overlay mark 50D may be an embodiment of the designed mask overlay mark 30D of FIG. 3. In some embodiments, as shown, the designed mask overlay mark 50D includes mark elements 510 that each include overlay structures 500. The overlay structures 500 may be embodiments of the overlay structures 300 of FIG. 3. The mark elements 510 may be combinations of the overlay structures 500, and a combination of the mark elements 510 may be the designed mask overlay mark 50D. The overlay structures 500, the mark elements 510, and the designed mask overlay mark 50D may have different shapes. For example, overlay structures 500 may be rectangles, mark elements 510 may be hollow squares, and designed mask overlay mark 50D may be a square.In FIG. 5, the designed mask overlay mark 50D has overlay structures 500 including a first overlay structure 500A, a second overlay structure 500B, a third overlay structure 500C, and a fourth overlay structure 500D.A size of the overlay structures 500 will be described with reference to the fourth overlay structure 500D. A first dimension D_X of the fourth overlay structure 500D may be an x-axis or horizontal dimension. A second dimension D_Y of the fourth overlay structure 500D may be a y-axis or vertical dimension. In some embodiments, the first dimension D_X is equal to the second dimension D_Y, such that the fourth overlay structure 500D has a square shape (or a circular shape or the like). In some embodiments, the first dimension D_X is different from the second dimension D_Y, such that the fourth overlay structure 500D has a rectangular shape (or an oval shape or the like). A size ratio may be a ratio of the first dimension D_X to the second dimension D_Y (i.e., D_X / D_Y), and may be about 0.1 to about 10, about 0.2 to about 5, about 0.33 to about 3, or about 0.5 to about 2, or may be in another suitable range.A pitch of the overlay structures 500 will be described with reference to the first, second and third overlay structures 500A, 500B, 500C. A first pitch P_X of the overlay structures 500 may be an x-axis or horizontal pitch. The first pitch P_X will be described with reference to the first and second overlay structures 500A, 500B. The first pitch P_X may be a distance between the first and second overlay structures 500A, 500B directly adjacent to each other along the horizontal or x-axis direction. The distance may be a distance between corresponding sides or edges of the first and second overlay structures 500A, 500B. For example, as shown in FIG. 5, the first pitch P_X may be a distance between left edges (with respect to the sheet) of the first and second overlay structures 500A, 500B.A second pitch P_Y of the overlay structures 500 may be a y-axis or vertical pitch. The second pitch P_Y is described with reference to the first and third overlay structures 500A, 500C. The second pitch P_Y may be a distance between the first and third overlay structures 500A, 500C directly adjacent to each other along the vertical or y-axis direction. The distance may be a distance between corresponding sides or edges of the first and third overlay structures 500A, 500C. For example, as shown in FIG. 5, the second pitch P_Y may be a distance between lower edges (with respect to the sheet) of the first and third overlay structures 500A, 500C.A pitch ratio may be a ratio of the first pitch P_X to the second pitch P_Y (i.e., P_X / P_Y) and may be about 0.1 to about 10, about 0.2 to about 5, about 0.33 to about 3, or about 0.5 to about 2, or may be in another suitable range. In some embodiments, the pitch ratio is substantially 1.The mask measurement device 130 may operate using light having a wavelength and using a selected numerical aperture (NA). The light may be generated by a light source 1350. A half pitch may be referred to as a theoretical resolution or a theoretical resolution limit of the mask measurement device 130, and may be given by the following equation:In the above equation, λ is the wavelength, σ is the degree of coherence, and NA is the numerical aperture. Based on the half pitch or the theoretical resolution, the first and / or the second pitch P_X, P_Y and / or the first and / or the second dimension D_X, D_Y may be chosen to achieve the benefits described above with reference to FIGS. 2A-4.In a first example, the wavelength of the light source 1350 may be substantially 266 nm and the NA may be substantially 0.8. Under these conditions, the theoretical resolution is about 83 nm. Therefore, the first and / or second pitch P_X, P_Y may be chosen not to exceed about 166 nm (i.e., the half pitch twice of 83 nm).In a second example, the wavelength of the light source 1350 may be substantially 193 nm and the NA may be substantially 0.6. Under these conditions, the theoretical resolution is about 80 nm. Therefore, the first and / or second pitch P_X, P_Y may be chosen not to exceed about 160 nm (i.e., the two-half pitch of 80 nm).For mask or wafer patterning equipment, an EUV light source may be integrated into the equipment that may generate light with a much shorter wavelength than the light source 1350 of the mask measurement device 130. The mask patterning apparatus may be an apparatus operable to produce a mask (e.g., expose a resist layer on the mask corresponding to a pattern), while the mask measurement apparatus 130 is an apparatus operable to analyze the produced mask (e.g., by capturing images of the mask and performing image analysis on the images).In a third example, a wavelength of the EUV light source may be substantially equal to 13.5 nm and a NA may be substantially equal to 0.33. Under these conditions, the theoretical resolution of the mask or wafer patterning equipment may be substantially 10 nm. Therefore, the first and / or second pitch P_X, P_Y may be chosen not to exceed about 20 nm (i.e., the two-half pitch of 10 nm).In a fourth example, for a wavelength of the EUV light source of 12.3 μm and an NA of 1, the theoretical resolution is much smaller than 1 nm.The aforementioned values for the first and / or the second pitch P_X, P_Y and / or the first and / or the second dimension D_X, D_Y can be theoretical instead of real results. In a real configuration and in some embodiments, the resolution of the mask patterning tool is less (i.e., finer) than the resolution of the wafer patterning tool, which may be similar to the resolution of the mask measurement device 130.FIGS. 6A to 12E are schematic diagrams of overlay structures and mask overlay marks according to various embodiments. FIGS. 6A to 9C are schematic views of overlay structures. Figures 10A-10F are schematic representations of individual solid mark elements. Figs. 11A to 11G are schematic views of individual hollow mark members. Figs. 12A to 12E are schematic views of combined mark elements.FIGS. 6A and 6B show covering structures 600. The overlay structures 600 have a square shape. Namely, each of the overlay structures 600 has the same dimension in the x-axis direction (e.g., a width) as in the y-axis direction (e.g., a length). In FIGS. 6A and 6B, four covering structures 600 are shown in each case. In FIG. 6A, the four overlay structures 600 are arranged in two rows R 1, R 2 and two columns C 1, C 2. Corresponding overlay structures 600 in each row R 1, R 2 are aligned with each other, and corresponding overlay structures 600 in each column C 1, C 2 are also aligned with each other. For example, directly adjacent pairs of the overlay structures 600 are aligned with each other along one direction and offset from each other along another direction. The rows R 1, R 2 have the same pitch in the x-axis direction as the columns C 1, C 2 in the x-axis direction.In FIG. 6B, the four overlay structures 600 are arranged in two rows R 1, R 2 that are offset with respect to each other, so that adjacent overlay structures 600 in different adjacent rows R 1, R 2 are not arranged in a column but are offset from each other along the x-axis direction.It is understood that although four overlay structures 600 are shown in each of FIGS. 6A and 6B, more or fewer overlay structures 600 may be used. Although two lines R1, R2 are shown, only one line or more than two lines may be used. Although two columns C1, C2 are shown, only one column or more than two columns may be used.In FIGS. 7A, 7B, and 7C, overlay structures 700 are rectangles elongated along the y-axis direction.In FIG. 7A, six overlay structures 700 are arranged in two rows R 1, R 2 and three columns C 1, C 2, C 3. Corresponding or adjacent overlay structures 700 in rows R 1, R 2 are aligned with one another along a first direction (e.g., the x-axis direction). Corresponding or adjacent overlay structures 700 in the columns C 1, C 2, C 3 are aligned with each other along a second direction (e.g., the y-axis direction) that is transverse or perpendicular to the first direction.In FIG. 7B, the six overlay structures 700 are arranged in two rows R 1, R 2, but they are offset with respect to each other, so that adjacent overlay structures 700 in different adjacent rows R 1, R 2 are not arranged in a column but are offset from each other along the x-axis direction.In FIG. 7C, four overlapping structures 700L are arranged side by side in the x-axis direction, and each extend in the y-axis direction. The four overlay structures 700L may each have a line or strip shape. The line or strip shape may have an aspect ratio (length to width) that is greater than 5 and is, for example, about 6, about 7, about 8, about 9, about 10, or more. The rectangular overlay structures 700 of FIGS. 7A and 7B may have an aspect ratio that does not exceed 5 or another suitable value. Namely, the rectangular overlay structures 700 may have an aspect ratio that is greater than 1 and not greater than 5 or another suitable value.It should be appreciated that although six overlay structures 700 are shown in FIGS. 7A and 7B, respectively, and four overlay structures 700L are shown in FIG. 7C, fewer or more overlay structures 700, 700L may be used. Although two rows R1, R2 are shown in Figs. 7A and 7B, only one row or more than two rows may be used. Although three columns C 1, C 2, C 3 are shown in FIG. 7A, only one column, two columns, or more than three columns may be used.In FIGS. 8A, 8B, and 8C, overlay structures 800 are rectangles elongated along the x-axis direction.In FIG. 8A, six overlay structures 800 are arranged in three rows R 1, R 2, R 3 and two columns C 1, C 2. Corresponding or adjacent overlay structures 800 in rows R 1, R 2, R 3 are aligned with one another along a first direction (e.g., the x-axis direction). Corresponding or adjacent overlay structures 800 in the columns C 1, C 2 are aligned with each other along a second direction (e.g., the y-axis direction) that is transverse or perpendicular to the first direction.In FIG. 8B, the six overlay structures 800 are arranged in two columns C 1, C 2, but they are offset with respect to each other, so that adjacent overlay structures 800 in different adjacent columns C 1, C 2 are not arranged in one row but are offset from each other along the y-axis direction.In FIG. 8C, four overlapping structures 800L are arranged side by side in the y-axis direction, and each extend in the x-axis direction. The four overlay structures 800L may each have a line or strip shape. The line or strip shape may have an aspect ratio (length to width) that is greater than 5 and is, for example, about 6, about 7, about 8, about 9, about 10, or more. The rectangular overlay structures 800 of FIGS. 8A and 8B may have an aspect ratio that is no greater than 5 or does not exceed any other suitable value. Namely, rectangular overlay structures 800 may have an aspect ratio that is greater than 1 and not greater than 5 or another suitable value.It should be appreciated that although six overlay structures 800 are shown in each of FIGS. 8A and 8B and four overlay structures 800L are shown in FIG. 8C, fewer or more overlay structures 800, 800L may be used. Although three rows R1, R2, R3 are shown in FIG. 8A, only one row, two rows, or more than three rows may be used. Although two columns C 1, C 2 are illustrated in FIGS. 8A and 8B, only one column or more than two columns may be used.In FIGS. 9A, 9B and 9C, four overlay structures 900 are illustrated. The overlay structures 900 each have a diamond shape, which may be a square shape rotated by 45° with respect to the x and y axes.In FIG. 9A, directly adjacent pairs of overlay structures 900 are aligned along one of two directions 93, 95 that may be directions 93, 95 rotated 45° and 1350 away from the x-axis, respectively. Two of the overlay structures 900 may be arranged in a row R 1 and another two of the overlay structures 900 may be arranged in a column C 1, as shown.In FIG. 9B, four diamond-shaped overlay structures 900 are arranged in two rows R 1, R 2 and two columns C 1, C 2. The two rows R 1, R 2 extend along the x-axis direction, and the two columns C 1, C 2 extend along the y-axis direction. The overlay structures 900 in the same row are aligned with each other. The overlay structures 900 in the same column are also aligned with each other.In FIG. 9C, four diamond-shaped overlay structures 900 are arranged in two rows R 1, R 2, but rows R 1, R 2 are offset so that overlay structures 900 are not arranged in columns. Namely, the overlay structures 900 are aligned with each other in the same row, but directly adjacent overlay structures 900 are not aligned with each other in the y-axis direction.It should be understood that while four overlay structures 900 are shown in FIGS. 9A-9C, more or fewer overlay structures 900 may be used. Although only one row R1 is shown in FIG. 9A and two rows R1, R2 are shown in FIGS. 9B and 9C, fewer or additional rows may be used. Although only one column C1 is shown in FIG. 9A and two columns C1, C2 are shown in FIG. 9B, fewer or additional columns may be used.Figures 10A-10F are schematic representations of individual solid mark elements 1010, 1020, 1030, 1040, 1050, 1060. Each of the tag elements 1010, 1020, 1030, 1040, 1050, 1060 may include a plurality of overlay structures described with reference to FIGS. 6A-9C and may be arranged in a matrix or other suitable arrangement. For the sake of simplicity of illustration, individual covering structures are not shown in FIGS. 10A to 10F. Embodiments of overlay structures included in a tag element are shown in Figures 11E, 11F and 11G.In FIG. 10A, a mark member 1010 may be a square mark member having the same dimension in the x-axis direction as in the y-axis direction. The tag element 1010 may include any of the overlay structures described with reference to FIGS. 6A-9C. For example, the tag element 1010 may include a matrix of square overlay structures as shown in FIGS. 6A and 6B, one of the rectangular or line / strip overlay structures shown in FIGS. 7A through 8C, one of the diamond-shaped overlay structures shown in FIGS. 9A through 9C, combinations thereof, or the like.In FIG. 10B, a mark element 1020 may be a square mark element having a larger dimension in the x-axis direction than in the y-axis direction. The tag element 1020 may include any of the overlay structures described with reference to FIGS. 6A-9C. For example, the tag element 1020 may include a matrix of square overlay structures as shown in FIGS. 6A and 6B, one of the rectangular or line / strip overlay structures shown in FIGS. 7A through 8C, one of the diamond-shaped overlay structures shown in FIGS. 9A through 9C, combinations thereof, or the like.In FIG. 10C, a mark member 1030 may be a square mark member having a larger dimension in the y-axis direction than in the x-axis direction. The tag element 1030 may include any of the overlay structures described with reference to Figures 6A-9C. For example, the tag element 1030 may include a matrix of square overlay structures as shown in FIGS. 6A and 6B, one of the rectangular or line / strip overlay structures shown in FIGS. 7A through 8C, one of the diamond-shaped overlay structures shown in FIGS. 9A through 9C, combinations thereof, or the like.In FIG. 10D, a tag element 1040 may be a diamond-shaped tag element having a width equal to its length. The tag element 1040 may include one of the overlay structures described with reference to Figures 6A-9C. For example, the tag element 1040 may include a matrix of square overlay structures as shown in FIGS. 6A and 6B, one of the rectangular or line / strip overlay structures shown in FIGS. 7A through 8C, one of the diamond-shaped overlay structures shown in FIGS. 9A through 9C, combinations thereof, or the like.In FIG. 10E, a mark element 1050 may be a triangular mark element having a dimension in the x-axis direction equal to its dimension in the y-axis direction. In some embodiments, the x-axis dimension may be different than the y-axis dimension. The triangle of Fig. 10E is shown as a right triangle. In some embodiments, other triangles (e.g., isosceles, equilateral, non-equilateral, obtuse, acute triangles or the like) instead of the depicted right triangle may be the shape of the tag member 1050. The tag element 1050 may include any of the overlay structures described with reference to FIGS. 6A-9C. For example, the tag element 1050 may include a matrix of square overlay structures as shown in FIGS. 6A and 6B, one of the rectangular or line / strip overlay structures shown in FIGS. 7A through 8C, one of the diamond-shaped overlay structures shown in FIGS. 9A through 9C, combinations thereof, or the like.In Fig. 10F, a tag member 1060 may have an irregular shape. For example, the tag member 1060 shown in FIG. 10F has eight sides, and it may include two square or rectangular shapes that overlap each other. A first square shape 1060A is overlapped by a second square shape 1060B, which is illustrated by various dashed lines in FIG. 10F. The tag member 1060 may include any of the overlay structures described with reference to Figures 6A-9C. For example, the tag element 1060 may include a matrix of square overlay structures as shown in FIGS. 6A and 6B, one of the rectangular or line / strip overlay structures shown in FIGS. 7A through 8C, one of the diamond-shaped overlay structures shown in FIGS. 9A through 9C, combinations thereof, or the like.Figs. 11A to 11G are schematic views of individual hollow mark members. Figures 11A-11E show hollow marker members 1110, 1120, 1130, 1140, 1150, and Figures 11F and 11G are detail views of a portion 1170 of Figure 11E.In FIG. 11A, the tag member 1110 is a hollow square shape that may have a solid portion 1110S and a cut-out portion 1110C. It should be understood that "cut-out" does not require an operation of cutting, but refers to a lack of overlay structures in the cut-out area 1110C, which seems to be cut out from the square solid area 1110S. The cut-out area 1110C may also be referred to as an empty area or the like. The solid region 1110S may be a continuous region including overlay structures. The solid portion 1110S may surround the cut-out portion 1110C on four sides. The solid portion 1110S may include vertically extending parts having a width D 1 and horizontally extending parts having a width D 2. As shown in FIG. 11A, in some embodiments, the width D 1 is equal to or substantially equal to the width D 2.The solid region 1110S may include the overlay structures, and an area fraction of the overlay structures as a portion of a total area of the solid region 1110S may be greater than about 30%, greater than about 40%, or greater than about 50%, or may have another suitable percentage. The overlay structures in the solid region 1110S may be substantially evenly (or uniformly) distributed. In some embodiments, the overlay structures in the solid region 1110S are randomly or pseudo-randomly distributed. For example, each of the overlay structures in the solid region 1110S may be spaced apart from directly adjacent other ones of the overlay structures by a distance in a range from, e.g., a first dimension to a second dimension that is greater than the first dimension. For example, the first dimension may be about 150 nm (e.g., 160 nm, 166 nm, or the like) and the second dimension may be greater than about 200 nm (e.g., greater than 200 nm, 250 nm, 300 nm, or the like). The first and second dimensions may also have different values in some embodiments.In FIG. 11B, the tag member 1120 is a hollow square shape that is similar in many respects to the tag member 1110 of FIG. 11A. In the mark member 1120, the width D 1 of the vertically extending parts is larger than the width D 2 of the horizontally extending parts.In Figure 11C, the tag element 1130 is a hollow square shape that is similar in many respects to the tag element 1110 of Figure 11A. In the mark member 1130, the width D2 of the horizontally extending parts is larger than the width D1 of the vertically extending parts.In Figure 11D, the tag member 1140 is a hollow rectangular shape similar in many respects to the tag member 1110 of Figure 11A. In the mark member 1140, a length L 1 of the horizontally extending parts is greater than a length L 2 of the vertically extending parts. Although not individually illustrated, in some embodiments, the length L 2 of the vertically extending portions may be greater than the length L 1 of the horizontally extending portions. In some embodiments described with reference to FIG. 11D, the widths D 1, D 2 may be the same size or different from each other.In Figure 11E, the tag member 1150 is a hollow diamond shape that is similar in many respects to the tag member 1110 of Figure 11A. The tag member 1150 may be a hollow square shape rotated 45° with respect to the x or y axes as shown. In some embodiments, one of the marker elements described with reference to FIGS. 11A-11D may be rotated by 45° to produce a hollow diamond shape having slightly different dimensions than the marker element 1150 shown in FIG. 11E. The solid portion 1110S of the tag member 1150 is diamond shaped and the cut-out portion 1110C of the tag member 1150 is also diamond shaped. Corner area 1170 is highlighted in phantom in FIG. 11E and detail views of its embodiments are shown in FIGS. 11F and 11G.FIG. 11F is a detailed view of a corner region 1170A, which is an embodiment of the corner region 1170 of FIG. 11E. In the corner area 1170A, overlay structures 1000R, which are rectangles, are arranged as shown. The solid region 1110S of the tag member 1150 may include three concentric rings (e.g., concentric diamonds) of the rectangular overlay structures 1000R. FIG. 11F shows five adjacent rows and five adjacent columns of overlay structures 1000R. In some embodiments, the tag element 1150 includes fewer or additional concentric diamonds of rectangular overlay structures 1000R compared to the three diamonds shown in FIG. 11F.FIG. 11G is a detailed view of a corner region 1170B, which is an embodiment of the corner region 1170 of FIG. 11E. As shown, disposed in the corner region 1170B are overlay structures 1000D that are diamonds (e.g., similar to those shown in FIG. 9A ). The diamond shaped overlay structures 1000D may be arranged in two concentric diamonds. In some embodiments, the tag element 1150 includes fewer or additional concentric diamonds of diamond-shaped overlay structures 1000D compared to the two diamonds shown in FIG. 11G.It should be appreciated that in some embodiments, one of the overlay structures and their arrangements described with reference to FIGS. 6A-9C may be included, individually or in combination, in the tag elements 1110, 1120, 1130, 1140, 1150 of FIGS. 11A-11E.Figures 12A-12E are schematic representations of combined mark elements 1210, 1220, 1230, 1240, 1250. The combined tag elements 1210, 1220, 1230, 1240, 1250 may be a combination of two or more individual tag elements such as those described with reference to Figures 10A to 11G.In FIG. 12A, the combined tag element 1210 includes two or more (e.g., six) square tag elements 121 oS, which may be similar in many respects to the tag element 1010 described with reference to FIG. 10A. The tag elements 1210S may be arranged in rows and columns that are aligned with each other. For example, in Figure 12A, six tag elements 1210S are shown arranged in two rows and three columns. The combined tag element 1210 may include fewer or additional tag elements 1210S compared to those shown in FIG. 12A.In Fig. 12B, the combined mark element 1220 comprises square mark elements 121oS arranged in a staggered manner. Namely, two square mark elements 1210S may be offset from each other in the y-axis direction and may partially or not overlap along the x-axis direction. FIG. 12B shows an embodiment in which the two square mark elements 1210S partially overlap along the x-axis direction. The combined tag element 1220 may include fewer or additional tag elements 1210S compared to those shown in FIG. 12B.In Figure 12C, combined tag element 1230 includes square tag elements 1210S and hollow square tag elements 121oH. In some embodiments, the tag elements 1210S, 1210H are arranged alternately in a matrix as shown. For example, square mark elements 1210S may have one or more hollow square mark elements 1210H directly adjacent to them along the x-axis direction and / or the y-axis direction. The mark elements 1210S, 121oH may be arranged in rows and columns as shown in FIG. 12C (similar to FIG. 12A ). In some embodiments, the tag elements 1210S, 1210H may be staggered similar to FIG. 12B. The combined tag element 1230 may include fewer or additional tag elements 1210S, 1210H compared to those shown in FIG. 12C.In FIG. 12D, the combined tag element 1240 may be similar in many respects to the tag element 1210 described with reference to FIG. 12A. In the combined mark member 1240, one or more of the square mark members 1210S may be replaced with a hollow member 1210V. Namely, no lap structures are provided in the hollow member 1210V. In other words, one or more of the square mark elements 1210S may be omitted. The combined tag member 1240 may include fewer or additional tag members 1210S compared to those shown in FIG. 12D. The combined tag member 1240 may include one or more hollow tag members, such as the hollow tag members 1210H of FIG. 12C, in some embodiments.In FIG. 12E, the combined tag element 1250 may be similar in some respects to the combined tag elements 1210, 1230, 1240. The combined mark element 1250 includes a row of triangular mark elements 1210T and a row of square mark elements 1210S directly adjacent to them in the y-axis direction. The triangular mark elements 1210T may be symmetrical about the y-axis as shown. In some embodiments, the triangular mark elements 1210T may be asymmetric about the y-axis. The triangular mark elements 1210T may be aligned along the x-axis direction with the square mark elements 1210S. The triangular tag elements 1210T may be one of the triangles described with reference to FIG. 10E.In Figures 6A-12E, the real mask registration mark, which may include one of the mark elements or combined mark elements described with reference to Figures 10A-12E, is large enough to be resolved by the mask measurement device 130 to perform alignment correction of the EUV mask. However, since the overlay structures have dimensions and / or pitches that are far below a resolution of the mask measurement device, the individual overlay structures are not resolved by the mask measurement device 130. In addition, the size and / or pitch of the overlay structures are sufficiently small so that the real overlay mark is not printed on the wafer. In some embodiments, the size and / or pitch of the overlay structures may be less than about 100 nm such that after an exposure process using the EUV mask with the real mask overlay mark, the overlay structures do not generate a pattern on the wafer.FIG. 14 is a flow diagram of a method of manufacturing an IC device according to various embodiments. FIG. 14 shows a flow diagram of a method 1400 for manufacturing an IC device or portion thereof from a workpiece, in accordance with one or more aspects of the present disclosure. Method 1400 is merely an example and is not intended to limit the present disclosure to what is expressly stated in method 1400. Additional steps may be provided before, during, and after method 1400, and some described steps may be replaced, omitted, or moved in additional embodiments of the method. For simplicity, not all steps will be described in detail here.The method 1400 begins with an operation 1410 in which a pattern design associated with a mask overlay mark is generated. The pattern design may be one of the designed mask registration marks described above with reference to Figures 2A-5. The designed mask overlay mark may include one or more mask elements, such as those described with reference to Figures 10A-11G. Each of the mask elements may include one or more overlay structures, such as those described with reference to FIGS. 6A-9C. The designed mask overlay mark may be large enough to be resolved by the mask measurement device 130. The overlay structures may be small enough not to be printed on a wafer by an EUV scanner with the mask containing the mask overlay mark.Operation 1410 is followed by operation 1420. In operation 1420, after generating a pattern design associated with a mask overlay mark based on the pattern design, the mask overlay mark is generated in a mask. For example, the real mask registration mark described with reference to Figs. 2A to 5 is printed on the mask by one of the methods described with reference to Fig. 4. The real mask overlay mark can be formed on the mask, for example, by removing portions of an absorber layer over a multilayer grid or reflector with an electron beam or by etching based on the designed mask overlay mark. In most embodiments, more than one mask overlay mark is generated in operation 1420, and the various mask overlay marks may be distributed at selected positions over the surface of the mask.Operation 1430 is typically performed simultaneously with operation 1420. In operation 1430, during the generation of the real mask overlay mark in the mask, a device element structure is generated in the mask adjacent to the real mask overlay mark. The device element structure may include at least a plurality of structures corresponding to device elements (e.g., contacts, vias, conductive traces, epitaxy regions, openings, grooves, holes, or the like) to be printed in one or more circuit regions of the wafer. The mask may be completed after operations 1420 and 1430. Other operations, such as a control operation and / or a repair operation, may be performed after operations 1420, 1430 and before operation 1440.Operation 1430 is followed by operation 1440. In operation 1440, alignment associated with the mask is performed based on the real mask registration mark. The alignment in operation 1440 may be performed by the mask measurement device 130. Since the overlay structures are below the resolution of the mask measurement device 130, the alignment may be performed based on the real mask overlay mark smoothed in a digital image captured by the mask measurement device 130. A real mask overlay mark that is "smoothed" means that because the overlay structures are not resolved by the mask measurement device 130, one or more of its edges in the digital image are smooth rather than sharp.Operation 1440 may include one or more operations. For example, operation 1440 may include an initial alignment. The real mask registration marks on the mask may be used prior to a lithographic exposure process to achieve a rough initial alignment with corresponding marks on the wafer. Then, a fine alignment operation can be performed. For example, the mask measurement device 130 may capture one or more images of the real mask registration marks. The images are then analyzed to calculate registration errors, thereby allowing exact adjustments. Operation 1440 may also include table synchronization, where the real mask overlay marks are used to synchronize a mask table with a wafer table, which may move synchronously for step and scan lithography processes.In some embodiments, operation 1440 includes one or more other processes described herein. In operation 1440, a high resolution imaging system that can use short wavelength light sources or electron beams captures detailed images of the mask that includes the real mask overlay marks. Sophisticated software algorithms can analyze the images to precisely locate the edges of the real mask overlay mark(s). Dimension measurement devices may be used to measure dimensions of the real mask registration mark(s), for example, to determine whether they are within selected tolerances. Gauges, such as the mask measurement device 130, may measure the position(s) of the real mask registration mark(s) with respect to other elements on the mask or with respect to design coordinates intended. Operation 1440 may further include verifying that the real mask overlay marks are exactly where they should be according to design specifications. A high accuracy of the position(s) of the real mask registration mark(s) and their measurement values is advantageous for calibrating mask adjustment systems in lithography apparatuses, so that an exact alignment is made possible during a wafer exposure process. Uniformity in positioning the real mask registration mark(s) is advantageous for maintaining a high yield in the manufacture of semiconductor wafers. In some embodiments, real-time settings may be made at operation 1440, where data may be fed back from the mask measurement device in real-time to remedy discrepancies during mask fabrication. The measurement data can also be used in feedforward systems in order to predict and remedy potential errors in later production steps. Long-term measurement data may contribute to identifying trends or recurrent problems, such that maintenance and process improvements are possible. If small persistent errors are detected, dynamic corrections may be made during the lithography process to compensate for these known errors, thereby improving registration accuracy.Operation 1440 may include a reticle fingerprinting process that generates a "fingerprint" of characteristics of the mask based on measurement data, which may then be used for more accurate alignment during the lithography process. The fingerprint may include positions of the real mask registration marks.Operation 1440 is followed by operation 1450. In operation 1450, when the mask has been installed in a photolithography apparatus, such as an EUV scanner, the device element pattern is transferred to the wafer to create a pattern in a layer of the wafer. The device element structure can be transferred by alignment on the basis of the real mask registration mark(s). For example, EUV light may be directed at the mask and reflected from the device element structure. The reflected light may then be incident directly or indirectly on the layer of the wafer, which may be a photoresist layer.Operation 1450 may be followed by further operations. For example, after exposure of the photoresist layer, exposed or unexposed portions of the photoresist layer may be removed to define a deeper layer of the wafer. The underlying material layer may then be etched through the patterned photoresist layer to create openings in the underlying material layer. Device elements may be formed in the openings, such as epitaxial features, dielectric layers, conductive layers, or the like.Embodiments may provide benefits. By using small overlay structures with a selected range of pitches and / or a pitch size combination as a mask overlay mark, mask overlay reliability and repeatability performance are improved, enabling robust mask overlay measurement on the mask without printing the mask overlay mark pattern on the wafer.According to at least one embodiment, a method comprises: generating a designed mask overlay mark associated with a real mask overlay mark to be generated in a mask; generating the real mask overlay mark in the mask based on the designed mask overlay mark, the real mask overlay mark including a plurality of overlay structures, wherein none of the plurality of overlay structures has a dimension greater than about 100 nm; generating a device element structure adjacent to the real mask overlay mark; performing alignment of the mask using a mask measurement device having a light source with a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of overlay structures is not greater than the wavelength divided by twice the numerical aperture; and creating a pattern in a layer of a wafer by transferring the device element pattern while aligning the mask.According to at least one embodiment, a method comprises: generating a real mask overlay mark in a mask based on a designed mask overlay mark, the real mask overlay mark including a plurality of overlay structures, wherein a dimension of each of the plurality of overlay structures is greater than about a first wavelength divided by twice a first numerical aperture, wherein the first wavelength and the first numerical aperture are associated with a first light source of a lithographic scanner; determining an overlay offset between the real mask overlay mark and the designed mask overlay mark using a mask measurement device having a second light source having a second wavelength and a second numerical aperture, wherein a pitch between adjacent two of the plurality of overlay structures is not greater than the second wavelength divided by twice the numerical aperture; generating patterned light by reflecting light of the first light source using the mask; forming a patterned layer of a wafer by exposing a layer to the patterned light without exposing the layer to a pattern of the real mask overlay mark; and patterning a layer under the patterned layer through openings in the patterned layer.According to at least one embodiment, a mask comprises: a device element structure; and a mask overlay mark adjacent to the device element structure, wherein the mask overlay mark includes a plurality of overlay structures. In a plan view, none of the plurality of overlay structures has a dimension greater than about 100 nm, and a first pitch between two adjacent ones of the plurality of overlay structures is less than about 2. [λ / (4·NA)], where λ is a wavelength of a measurement light of a mask measurement device and NA is a numerical aperture of the measurement light.Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objects and / or to achieve the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

A method comprising: generating a designed mask overlay mark associated with a real mask overlay mark to be generated in a mask; generating the real mask overlay mark in the mask based on the designed mask overlay mark, the real mask overlay mark including a plurality of overlay structures, wherein none of the plurality of overlay structures have a dimension greater than about 100 nm; generating a device element structure adjacent to the real mask overlay mark; performing alignment of the mask using a mask measurement device having a light source with a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of overlay structures is not greater than the wavelength divided by twice the numerical aperture; and creating a pattern in a layer of a wafer by transferring the device element pattern while aligning the mask.The method of claim 1, wherein performing the alignment comprises determining, by the mask measurement device, an overlap offset between the real mask overlap mark and the designed mask overlap mark.The method of claim 2, wherein determining the registration offset comprises: capturing a digital image of the real mask registration mark using the mask measurement device; determining at least two edges of the real mask registration mark in the digital image, wherein the edges are smooth; and determining a coordinate of the real mask registration mark based on the determined edges.The method of any preceding claim, wherein the wavelength is about 266 nm, the numerical aperture is about 0.8, and the pitch is not greater than about 166 nm.The method of any preceding claim, wherein the wavelength is about 193 nm, the numerical aperture is about 0.6, and the pitch is not greater than about 160 nm.The method of any preceding claim, wherein generating the pattern comprises directing EUV light toward the mask, wherein the EUV light has a second wavelength and a second numerical aperture, and dimensions of each of the plurality of overlay patterns are less than about the second wavelength divided by twice the numerical aperture.The method of claim 6, wherein the second wavelength is about 13.5 nm, the numerical aperture is about 0.33, and the dimensions are no greater than about 20 nm.A method comprising: generating a real mask overlay mark in a mask based on a designed mask overlay mark, the real mask overlay mark including a plurality of overlay structures, wherein no dimension of each of the plurality of overlay structures is greater than about a first wavelength divided by twice a first numerical aperture, wherein the first wavelength and the first numerical aperture are associated with a first light source of a lithographic scanner; determining an overlay offset between the real mask overlay mark and the designed mask overlay mark using a mask measurement device having a second light source with a second wavelength and a second numerical aperture, wherein a pitch between adjacent two of the plurality of overlay structures is not greater than the second wavelength divided by twice the numerical aperture; generating structured light by reflecting light of the first light source using the mask; forming a structured layer of a wafer by exposing a layer to the structured light without exposing the layer to a structure of the real mask overlay mark; and structuring a layer under the structured layer through openings in the structured layer.The method of claim 8, wherein each of the plurality of overlay structures has a width and a length, the width having the same size as the length.The method of claim 8 or 9, wherein the real mask overlay mark includes a plurality of mask elements.The method of claim 10, wherein at least one of the plurality of mask members has a hollow shape.The method of claim 10 or 11, wherein the plurality of mask elements are arranged in a plurality of rows.The method of claim 12, wherein two adjacent ones of the plurality of rows are offset from each other.The method of any of claims 10 to 13, wherein the plurality of mask elements are arranged in a matrix, the matrix including at least one empty mask element.A mask comprising: a device element structure; and a mask overlay mark adjacent to the device element structure, wherein the mask overlay mark includes a plurality of overlay structures, wherein, in a plan view, none of the plurality of overlay structures has a dimension greater than about 100 nm, and a first pitch between two adjacent ones of the plurality of overlay structures is less than about 2·[λ / (4·NA)], wherein λ is a wavelength of a measurement light of a mask measurement device and NA is a numerical aperture of the measurement light.The mask of claim 15, wherein the plurality of overlay structures are arranged with the first pitch along a first direction and with a second pitch along a second direction that is transverse to the first direction.The mask of claim 16, wherein the first pitch is different from the second pitch.The mask of claim 16 or 17, wherein the first and second pitches are each not greater than a resolution of the mask measurement device.The mask of claim 18, wherein the resolution is about 160 nm.The mask of any of claims 15 to 19, wherein the plurality of overlay structures are arranged in a plurality of concentric rings.

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