METHOD AND CONTROL CIRCUIT FOR OPERATING A HALF-BRIDGE CIRCUIT

Abstract

A half-bridge (900) comprising a high-side switch (100) and a low-side switch (200). A switching node (150) is located between the high-side switch (100) and the low-side switch (200). A load (300) is electrically connected to the switching node (150). In a first interval TP1, which begins with a current flow through the load (300) in a first direction, the high-side switch (100) is turned on for a first pulse time TL1 and the low-side switch (200) is turned on for a first reverse conduction time TRC1, which begins after an end of the first pulse time TL1.In a second interval TP2 following the first interval TP1 and beginning with a current flow through the load (300) in a second direction opposite to the first direction, the low-side switch (200) is switched on for a second pulse time TL2 and the high-side switch (100) is switched on for a second reverse conduction time TRC2 beginning after an end of the second pulse time TL2.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method for operating a half-bridge circuit and a control circuit for controlling a half-bridge circuit. BACKGROUND

[0002] Half-bridge circuits, each comprising a high-side switch and a low-side switch electrically connected in series between a positive DC supply voltage and a negative supply potential, are used in power conversion applications. A load is connected to a switching node between the high-side switch and the low-side switch. The high-side switch and the low-side switch alternately connect the switching node to the positive DC input voltage and the negative supply potential. A diode operates in parallel with the high-side switch and another diode operates in parallel with the low-side switch, with both diodes blocking during static operation of the half-bridge. The diode can be an integral part of the switch or an additional device. For example, the diode can include the body diode of a MOSFET and / or an external anti-parallel diode (blocking diode).

[0003] When one of the high-side switch and the low-side switch is turned off, an inductive load connected to the switching node maintains a current flow through the inductive load and the diode electrically connected in parallel with the opposite switch.

[0004] The switching times for the high-side switch and the low-side switch, and as a result, the pulse time of a switched voltage at the switching node, are controlled by pulse-time modulation (PWM). By varying the duty cycle of the on-times of the high-side switch and the low-side switch, PWM adapts the half-bridge operation to varying load conditions. For symmetric PWM, the duty cycle for the high-side switch and the low-side switch is identical. At least in some applications, symmetric PWM demonstrates higher efficiency compared to complementary PWM.

[0005] There is a continuing need to improve the operation of half-bridge circuits.

[0006] If the high-side switch and the low-side switch are metal-oxide-semiconductor field-effect transistors (MOSFETs), at least a portion of a loop current sustained by the inductive load can flow through the body diode of one of the MOSFETs. If the MOSFET is a silicon carbide MOSFET (SiC MOSFET), the forward voltage drop of the SiC MOSFET body diode is higher than for a silicon MOSFET (Si MOSFET), affecting the efficiency of the half-bridge. Additionally, the forward current through the SiC MOSFET body diode is a bipolar current, which can induce bipolar degradation of the silicon carbide crystal.

[0007] A method of operating a half-bridge comprising a high-side switch and a low-side switch, comprising: turning on, in a first interval TP1 beginning with a current flow through a load electrically connected to a switching node between the high-side switch and the low-side switch in a first direction, the high-side switch for a first pulse time TL1 and the low-side switch for a first reverse conduction time TRC1, the first reverse conduction time TRC1 beginning after an end of the first pulse time TL1; and turning on, in a second interval TP2 following the first interval TP1 and beginning with a current flow through the load in a second direction opposite to the first direction, the low-side switch for a second pulse time TL2 and the high-side switch for a second reverse conduction time TRC2 beginning after an end of the second pulse time TL2.

[0008] When one of the high-side switch and the low-side switch is turned off, an inductive load connected to the switch node maintains a current flow through the inductive load and the body diode of the opposite switch.

[0009] In contrast, the method according to the present invention provides an alternative current path through the closed MOS channel of the opposite switch. The current through the alternative current path is a unipolar current. The alternative current paths can be provided in addition to the body diodes and / or the antiparallel diodes, whereby the alternative current paths can relieve the diodes of current and relax the requirements on the body diodes and / or the antiparallel diodes.

[0010] Those skilled in the art will recognize additional features and advantages by reading the following detailed description and viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are provided for further understanding of the embodiments and form an integral part of this description. The drawings illustrate embodiments of a method for operating a half-bridge circuit and a control circuit for operating a half-bridge circuit and, together with the description, explain the principles underlying the embodiments. Further embodiments are described in the following detailed description and in the claims. Features of the various embodiments can be combined with one another. Fig. 1A is a simplified circuit diagram of a half-bridge circuit for discussing effects of the method of operation according to one embodiment. Fig. Figure 1B is a simplified timing diagram for discussing effects of the operating method for the half-bridge of Fig. 1A according to one embodiment. Fig. 2A and Fig. 2B are simplified circuit diagrams of a full bridge circuit with two half bridge circuits for discussing effects of an operating method according to one embodiment. Fig. 3A is a simplified circuit diagram of a circuit including a full bridge circuit and a control circuit for the operating method according to one embodiment. Fig. Figure 3B is a simplified timing diagram for discussing effects of the operating method for the circuit of Fig. 3A according to one embodiment. Fig. 4 is a simplified circuit diagram of a circuit with a full bridge circuit and a control circuit for an operating method according to an embodiment relating to low current detection for controlling the blocking times. DETAILED DESCRIPTION

[0012] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which certain embodiments of a method of operating a half-bridge circuit and a control circuit for operating a half-bridge circuit are shown by way of illustration. Structural or logical changes may be made to the illustrated embodiments without departing from the scope of the present invention. For example, features shown or described for one embodiment may be used on or in conjunction with other embodiments, resulting in a different embodiment. The present invention is intended to include such modifications and variations. The embodiments are described in a manner that should not be construed as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference numerals throughout the various drawings unless otherwise indicated.

[0013] The terms "comprising," "containing," "including," "comprising," and the like are open-ended, and the terms indicate the presence of certain structures, elements, or features, but do not preclude the presence of additional elements or features. The articles "a," "an," and "the" include both the plural and the singular, unless the context clearly indicates otherwise.

[0014] MOSFETs (metal-oxide-semiconductor field-effect transistors) are voltage-controlled devices and include all types of IGFETs (insulated-gate field-effect transistors) with gate electrodes based on doped semiconductor material and / or metal and with gate dielectrics made of oxide and / or dielectric materials other than oxides.

[0015] Ranges specified for physical dimensions include the limiting values. For example, a range for a parameter y from a to b is a ≤ y ≤ b. The same applies to ranges with a limiting value such as "at most" and "at least."

[0016] One embodiment of the present invention relates to a method for operating a half-bridge comprising a high-side switch and a low-side switch. The high-side switch and the low-side switch can be electrically connected in series between a positive supply potential VDD and a negative supply potential VSS.

[0017] The high-side switch and the low-side switch may comprise the same type of semiconductor switch. For example, the high-side switch and the low-side switch are or comprise insulated-gate bipolar transistors (IGBTs) with the same or approximately the same switching times, breakdown voltages, and current-carrying capacities. Alternatively, the high-side switch and the low-side switch are or comprise MOSFETs with the same or approximately the same switching times, breakdown voltages, and current-carrying capacities.

[0018] In a first interval TP1, which begins with a current flow through a load electrically connected to a switching node between the high-side switch and the low-side switch in a first direction, the high-side switch is turned on for a first pulse time TL1 and the low-side switch is turned on for a first reverse conduction time TRC1, which begins after an end of the first pulse time TL1.

[0019] The first reverse conduction time TRC1 may follow the first pulse time TL1 directly or after a first dead time, wherein between the end of the first pulse time TL1 and the beginning of the first reverse conduction time TRC1, a body diode of the low-side switch and / or an anti-parallel diode electrically connected in parallel to the body diode of the low-side switch conducts the load current through the load connected to the switching node.

[0020] In a second interval TP2 following the first interval TP1 and beginning with a current flow through the load in a second direction opposite to the first direction, the low-side switch is turned on for a second pulse time TL2 and the high-side switch is turned on for a second reverse conduction time TRC2 beginning after an end of the second pulse time TL2.

[0021] The second reverse conduction time TRC2 may follow the second pulse time TL2 directly or after a second dead time, wherein between the end of the second pulse time TL2 and the beginning of the second reverse conduction time TRC2, a body diode of the high-side switch and / or an anti-parallel diode electrically connected in parallel to the body diode of the high-side switch conducts the load current.

[0022] The first intervals TP1 and the second intervals TP2 may be of the same length, with the first intervals TP1 and the second intervals TP2 alternating. Each second interval TP2 may directly follow a preceding first interval TP1, and each first interval TP1 may directly follow a preceding second interval TP2.

[0023] The first reverse conduction time TRC1 can end within the first interval TP1 or with the start of the next second pulse time TL2. The second reverse conduction time TRC2 can end within the second interval TP2 or with the start of the next first pulse time TL1.

[0024] The second dead time and the first dead time can be the same or different from each other. Each first pulse time TL1 can directly follow a second reverse conduction time TRC2 or can follow the preceding second reverse conduction time TRC2 after a first idle time. Each second pulse time TL2 can directly follow a first reverse conduction time TRC1 or can follow the preceding first reverse conduction time TRC1 after a second idle time. The first and second idle times can be the same or different from each other.

[0025] The first and second idle times can be periods with no current or only negligible current flowing through the load. At any given time, at most one of the switches (high-side switch or low-side switch) is turned on.

[0026] The time interval between the start of two consecutive first pulse times and the time interval between the start of two consecutive second pulse times can be equal and define a total switching period of the half-bridge.

[0027] A total time of the first pulse time TL1 and the first reverse conduction time TRC1 and a total time of the second pulse time TL2 and the second reverse conduction time TRC2 amount to at most 50% of the switching period. The total time of the first pulse time TL1 and the first reverse conduction time TRC1 and the total time of the second pulse time TL2 and the second reverse conduction time TRC2 may amount to 50% or close to 50% of the switching period under heavy load and when the first and second dead times can be ignored. The total time of the first pulse time TL1 and the first reverse conduction time TRC1 and the total time of the second pulse time TL2 and the second reverse conduction time TRC2 may amount to less than 50% of the switching period under light load and / or when the first and second dead times are not negligible.

[0028] In the first intervals TP1, the high-side switch is turned on once or at least twice for a first pulse time TL1, depending on the application. In the second intervals TP2, the low-side switch is turned on once or at least twice for second pulse times TL2, depending on the application.

[0029] During the first pulse times TL1, the switching node between the high-side switch and the low-side switch can be connected to the positive supply potential VDD via the closed high-side switch and to the negative supply potential VSS via the inductive load and another low-side switch of another half-bridge. When the high-side switch and the other low-side switch turn off, the magnetic field of the inductive load maintains a current flow through the inductive load in a first direction, causing the voltage at the switching node to fall below the negative supply potential VSS. Typically, the body diode of the low-side switch and / or an anti-parallel diode parallel to the body diode of the low-side switch allow a current flow from the negative supply potential VSS to the switching node to maintain the current through the inductive load.

[0030] In contrast, the operating method according to the present invention provides an alternative current path through the closed MOS channel of the low-side switch, which is reverse-biased as long as a current flows through the body diode of the low-side switch and / or the parallel antiparallel diode. The current through the alternative current path is a unipolar current. The alternative current path can be provided in addition to the body diode and / or the antiparallel diode, whereby the alternative current path can relieve the thermal and / or current stress on the body diode and / or the antiparallel diode.

[0031] During the second pulse times TL2, the switching node is connected to the negative supply potential VSS via the closed low-side switch and to the positive supply potential VDD via the inductive load and another high-side switch of the further half-bridge. When the low-side switch and the further high-side switch turn off, the magnetic field of the inductive load maintains a current flow through the inductive load in a second direction opposite to the first direction to the switching node, whereby the voltage at the switching node exceeds the positive supply potential VDD. Typically, a body diode of the high-side switch and / or an anti-parallel diode parallel to the body diode of the high-side switch allow a current flow from the switching node to the positive supply potential VDD to maintain the current through the inductive load.

[0032] In contrast, the operating method according to the present invention provides an alternative current path through the closed MOS channel of the high-side switch, which is reverse biased as long as a current flows through the body diode of the high-side switch and / or the anti-parallel diode electrically connected in parallel to the high-side switch.

[0033] The antiparallel diode may be an additional diode electrically connected in parallel to the body diode of the associated switch, the body diode being located between an n-type drain region and a p-type body region of an n-channel MOSFET.

[0034] According to one embodiment, the high-side switch may comprise a silicon carbide field-effect transistor and / or the low-side switch may comprise a silicon carbide field-effect transistor.

[0035] Silicon carbide field-effect transistors are subject to bipolar degradation, i.e., a steady reduction in crystal quality and a steady degradation of device parameters such as the on-resistance RDSon with increasing bipolar current budget. By using the unipolar MOS channel current for at least a large portion of the antiparallel period, bipolar degradation can be significantly slowed.

[0036] According to one embodiment, a length (duration) of the first pulse time TL1 and a length (duration) of the second pulse time TL2 can be controllable.

[0037] According to one embodiment, the length of the first pulse time TL1 and a length of the second pulse time TL2 can be controlled according to load conditions.

[0038] For example, a first output of a pulse time modulator (PWM) circuit is connected to a gate of the high-side switch and a second output of the PWM circuit is connected to a gate of the low-side switch, and the PWM circuit controls the first and second pulse times TL1, TL2 of the high-side switch and the low-side switch according to a symmetric pulse time modulation method.

[0039] According to one embodiment, a first dead time between the first pulse time TL1 and the first reverse conduction time TRC1 and / or a second dead time between the second pulse time TL2 and the second reverse conduction time TRC2 can be preset.

[0040] For example, a minimum duration of the first dead time and / or the second dead time is in a range from 50 ns to 1 µs, for example, 50 ns. The first dead time and / or the second dead time may be fixed or controllable to adapt to specific applications. According to other embodiments, the first dead time and the second dead time may be longer than 1 µs. The first dead time and the second dead time may be the same or different from each other.

[0041] The first dead time can begin with a trailing edge of an active high-side gate signal that is active during the first pulse time TL1. The first dead time can end with the leading edge of an active low-side gate signal that is active during the first reverse conduction time TRC1.

[0042] The second dead time may begin with a trailing edge of an active low-side gate signal that is active during the second pulse time TL2. The second dead time may end with the leading edge of an active high-side gate signal that is active during the second reverse conduction time TRC2.

[0043] The first and second dead times are selected depending on the electrical characteristics of the low-side switch and the high-side switch and the switching frequency.

[0044] For example, IGBTs are known to carry a significant tail current after the gate voltage changes from active to inactive. Therefore, the first and second dead times should be sufficiently long until the tail current decays or drops to a negligible value. For example, the first and second dead times should be 1 µs or longer to ensure that only one of the IGBTs is turned on at any given time.

[0045] Secondly, MOSFETs are known for their fast switching. This means that the first and second dead times can be significantly shorter than 1 µs without the risk of more than one MOSFET turning on simultaneously.

[0046] Additionally, the dead time should not affect the operation of a system including the half-bridge. Thus, the first and second dead times can be selected to be at most 10% of the switching period of the low-side switch and the high-side switch. For example, for a switching frequency of 100 kHz and a switching period of 10 µs, the first and second dead times can be less than 1 µs.

[0047] According to one embodiment, the first conduction time TRC1 and the second conduction time TRC2 can be preset. For example, the first conduction time TRC1 and the second conduction time TRC2 are fixed and independent of application parameters, an operating state, and / or a load condition of the half-bridge circuit.

[0048] According to a further embodiment, the first conduction time TRC1 and the second conduction time TRC2 may be adjustable. In particular, the first conduction time TRC1 and the second conduction time TRC2 are variable and can be adapted or adapted to various application parameters. For example, the first conduction time TRC1 and the second conduction time TRC2 are a function of a resistance of a resistor and / or a capacitance of a capacitor, wherein the first conduction time TRC1 and the second conduction time TRC2 are programmable by selecting a suitable resistor and / or capacitor. Another example is an auxiliary circuit that adjusts the first conduction time TRC1 and the second conduction time TRC2 in response to an application signal, e.g., controlled by user settings. Adjusting the first conduction time TRC1 and the second conduction time TRC2 may follow the following considerations:

[0049] The time T in which a load current through the load drops to zero is a function of the peak load current Imax, the inductance L of the load and the supply voltage U, which is determined by the voltage difference between the positive supply voltage VDD and the negative supply potential VSS according to equation -1: T=L⋅Lmax / U

[0050] The first conduction time TRC1 and the second conduction time TRC2 can be selected by a safety margin ΔT equal to or shorter than T. The higher the inductance L of the load, the higher the peak current Imax and the lower the supply voltage U, the longer the first conduction time TRC1 and the second conduction time TRC2 can be.

[0051] In circuits with a constant inductance L, supply voltage U, and peak current Imax, a suitable first conduction time TRC1 and a suitable second conduction time TRC2 can be selected by the application signal or by a suitable circuit element that influences the first conduction time TRC1 and / or the second conduction time TRC2. The first conduction time TRC1 and / or the second conduction time TRC2 can remain unchanged during operation.

[0052] If at least one of the inductance L, the supply voltage U, and the peak current Imax is variable and changes during operation, the auxiliary circuit can adjust the first conduction time TRC1 and / or the second conduction time TRC2 accordingly over time. Additionally, the safety margin ΔT can be adjusted to circuit parameters and tolerances and / or current operating conditions. The first conduction time TRC1 can be preset to various preset values, and the second conduction time TRC2 can be preset to various preset values, depending on an operating state, a switching period, and / or a load condition of the half-bridge circuit.

[0053] According to one embodiment, the method may further include detecting a first notification condition indicating a time prior to a start of a second interval TP2, and setting an end of the first reverse conduction time TRC1 in response to detecting the first notification condition. A notification signal indicating a change in the first notification condition triggers the deactivation of the low-side switch.

[0054] The first notification state may indicate any event that reliably occurs within the first interval TP1 and before the start of the second interval TP2. For example, the first notification state may be any internal state of a control circuit for the half-bridge before the start of the second interval TP2.

[0055] Additionally, the method may further include detecting a second notification condition indicating a time prior to a start of a first interval TP1 and setting an end of the second reverse conduction time TRC2 in response to detecting the second notification condition. A notification signal indicating a change in the second notification condition triggers the turn-off of the high-side switch.

[0056] The second notification state may indicate any event that reliably occurs within the second interval TP2 and before the start of the first interval TP1. For example, the second notification state may be any internal state of the half-bridge control circuit before the start of the first interval TP1.

[0057] The more the reverse conduction times TRC1, TRC2 cover the time period in which a loop current is maintained through the load, the less bipolar current flows overall through the high-side switch and the low-side switch and the greater the advantage of the method can be.

[0058] According to one embodiment, detecting the notification condition may include detecting a decrease in a current through the load below a preset threshold in the first and second reverse conduction times TRC1, TRC2.

[0059] For example, the first notification condition may be that after the start of the first reverse conduction time TRC1, the amount of load current falls below a first threshold.

[0060] The first threshold is set sufficiently high to prevent the end of the first interval TP1 from being missed due to the detection of current measurement noise. The first threshold can be greater than 0.5%, 1%, or 2% of the maximum load current in the first interval TP1. For example, for a maximum load current of 100 A, the first threshold can be at least 0.5 A, at least 1 A, or at least 2 A to also account for the overall control delay, including the current measurement delay, the filter delay, and the PWM signal delay from the controller to the high-side switch.

[0061] The first threshold is set sufficiently low to achieve a sufficiently positive effect. The first threshold can be a maximum of 10% of the maximum load current in the first interval TP1. For a maximum load current of 100 A, the first threshold can be 10 A or less.

[0062] The second notification condition may be that after the start of the second reverse conduction time TRC2, the amount of load current falls below a second threshold.

[0063] The first and second thresholds can have the same current but opposite signs. For example, if the first threshold is 1 A, the second threshold can be -1 A.

[0064] The reverse conduction times TRC1, TRC2 can adapt to varying operating conditions and the MOSFET channels can be switched on for the entire time that a loop current is maintained through the load.

[0065] According to one embodiment, the start and end of the first reverse conduction time TRC1 may be given by times when a rising voltage ramp exceeds a corresponding threshold voltage or when a falling voltage ramp falls below a corresponding threshold voltage, and / or the start and end of the second reverse conduction time TRC2 may be given by times when a rising voltage ramp exceeds a corresponding threshold voltage or when a falling voltage ramp falls below a corresponding threshold voltage.

[0066] The first and second reverse conduction times can be programmed and / or controlled, for example, by adjusting the slope of the voltage ramp and / or by shifting the threshold voltages.

[0067] Another embodiment of the present invention relates to a control circuit for operating a half-bridge comprising a high-side switch and a low-side switch. The high-side switch and the low-side switch can be electrically connected in series between a positive supply potential VDD and a negative supply potential VSS.

[0068] In a first interval TP1, which begins with a current flow through a load electrically connected to a switching node between the high-side switch and the low-side switch in a first direction, the high-side switch is turned on for a first pulse time TL1 and the low-side switch is turned on for a first reverse conduction time TRC1, which begins after an end of the first pulse time TL1.

[0069] In a second interval TP2 following the first interval TP1 and beginning with a current flow through the load in a second direction opposite to the first direction, the low-side switch is turned on for a second pulse time TL2 and the high-side switch is turned on for a second reverse conduction time TRC2 beginning after an end of the second pulse time TL2.

[0070] According to one embodiment, a length of the first pulse time TL1 and a length of the second pulse time TL2 can be controllable.

[0071] According to one embodiment, a length of the first pulse time TL1 and a length of the second pulse time TL2 may be controllable in response to changing load conditions.

[0072] According to one embodiment, a first dead time between the first pulse time TL1 and the first reverse conduction time TRC1 and / or a second dead time between the second pulse time TL2 and the second reverse conduction time TRC2 may be preset or adjustable or controllable.

[0073] The first conduction time TRC1 and the second conduction time TRC2 can be preset, whereby the first conduction time TRC1 and the second conduction time TRC2 are fixed and independent of application parameters, an operating state and / or a load condition of the half-bridge circuit.

[0074] According to one embodiment, the first conduction time TRC1 and the second conduction time TRC2 can be adjustable. In particular, the first conduction time TRC1 and the second conduction time TRC2 are variable and can be adapted or adapted to different application parameters.

[0075] According to one embodiment, the control circuit may include a processing circuit configured to terminate the first reverse routing time TRC1 in response to receiving information about a first notification state indicating a time before or at the beginning of a second interval TP2. Both the first routing time TRC1 and the second routing time TRC2 may be adjustable and controllable.

[0076] An electrical circuit may include the half-bridge, the control circuit, and a notification circuit that detects the first notification state and transmits a notification signal containing information about the first notification state.

[0077] The processing circuit may be further configured to terminate the second reverse routing time TRC2 in response to receiving information about a second notification state indicating a time before or at the beginning of a next first interval TP1. The notification circuit may detect the second notification state and transmit a notification signal containing information about the second notification state.

[0078] Fig. 1A shows a half-bridge circuit 900 with a high-side switch 100 and a low-side switch 200 electrically connected in series between a positive supply potential VDD and a negative supply potential VSS.

[0079] A first terminal of a load 300 having an inductive component is electrically connected to a switching node 150 between the high-side switch 100 and the low-side switch 200. The load 300 may include capacitive elements and resistive elements in addition to the inductive component, but is configured such that the half-bridge circuit 900 operates in the inductive region.

[0080] A second terminal of the load 300 may, for example, be connected to the switching node of another half-bridge circuit.

[0081] The high-side switch 100 includes a first n-channel SiC MOSFET with an internal body diode 105 between an n-doped drain region and a p-doped base region, separating the n-doped drain region and an n-doped source region. The base region and the source region are electrically connected. A gate of the high-side switch 100 receives a high-side gate signal QH for controlling a MOSFET channel in the base region.

[0082] The low-side switch 200 includes a second n-channel SiC MOSFET with an internal body diode 205 between an n-doped drain region and a p-doped base region, separating the n-doped drain region and an n-doped source region. The base region and the source region are electrically connected. A gate of the low-side switch 200 receives a low-side gate signal QL for controlling a MOSFET channel in the base region.

[0083] Fig. Figure 1B shows that the high-side and low-side gate signals QH, QL alternately turn on the high-side switch 100 and the low-side switch 200, so that none or only one of the high-side switch 100 and the low-side switch 200 is turned on at any given time.

[0084] The on- and off-times of high-side switch 100 and low-side switch 200 are coordinated with first intervals TP1 and second intervals TP2. The solid lines illustrate the light load case. The dashed lines indicate the differences between the heavy load case and the light load case.

[0085] For light inductive loads, each first interval TP1 begins with a rising edge of the high-side gate signal QH, which switches on a load current from the positive supply potential VDD through the high-side switch 100 to the switching node 150 and through the load 300 in a first direction. Each first interval TP1 lasts until a load current begins to flow through the load 300 in the opposite second direction.

[0086] Every second interval TP2 begins with a rising edge of the low-side gate signal QL, which switches on a load current through the load 300, the switching node 150, and the low-side switch 200 to the negative supply voltage VSS. Every second interval TP2 lasts until a load current begins to flow through the load 300 in the first direction.

[0087] Intervals in which no load current (I = 0A) or only a negligible load current flows through the load 300 separate intervals with opposite current directions.

[0088] For strong inductive loads, the first reverse conduction time TRC1 and the second pulse time TL2 combine and merge directly into a single signal pulse. Since the current lags behind the voltage due to operation in the inductive region, the current direction only changes to the second direction after the virtual rising edge of the second pulse time TL2 of the low-side gate signal QL within the combined signal pulse. Every second interval TP2 begins shortly after the virtual rising edge of the second pulse time TL2 and lasts until the load current begins to flow through the load 300 in the opposite first direction.

[0089] Accordingly, the second reverse conduction time TRC2 and the first pulse time TL1 combine and merge directly into a signal pulse. Since the current lags behind the voltage, the current direction only changes to the first direction after the virtual rising edge of the first pulse time TL1 of the high-side gate signal QH. Each first interval TP1 begins shortly after the virtual rising edge of the first pulse time TL1 and lasts until the load current begins to flow through the load 300 in the opposite second direction.

[0090] The current direction changes directly from the first direction to the second direction and vice versa. The length of the time delay depends on the characteristics of the load.

[0091] For light inductive loads, the high-side gate signal QH turns on the high-side switch 100 at the beginning of each first interval TP1 for a first pulse time TL1. For the entire first pulse time TL1, a load current flows from the positive supply potential VDD through the high-side switch 100 to the switching node 150 and passes through the load 300 in the first direction. With a falling edge of the high-side gate signal QH, the load current through the high-side switch 100 is turned off. The magnetic field of the load 300 maintains a loop current flowing through the load 300 in the first direction for at least part of the remainder of the first interval TP1.

[0092] Still in the first interval TP1 and after the high-side switch 100 is turned off, the low-side gate signal QL becomes active and turns on the low-side switch 200 for a first reverse conduction time TRC1. During the first reverse conduction time TRC1, the loop current flows through the MOSFET channel of the low-side switch 200.

[0093] The first reverse conduction time TRC1 may follow the first pulse time TL1 directly or after a first dead time, wherein between the end of the first pulse time TL1 and the beginning of the first reverse conduction time TRC1, the body diode 205 of the low-side switch 200 conducts the loop current flowing through the load 300 in the first direction.

[0094] Even for light inductive loads, the low-side gate signal QL turns on the low-side switch 200 at the beginning of every second interval TP2 for a second pulse time TL2. For the entire second pulse time TL2, a load current flowing through the load 300 in the second direction flows through the switching node 150 and the low-side switch 200 to the negative supply potential VSS. With a falling edge of the low-side gate signal QL, the load current through the low-side switch 200 is turned off. The magnetic field of the load 300 maintains a loop current flowing through the load 300 in the second direction for at least part of the remainder of the second interval TP2.

[0095] Still in the second interval TP2 and after the low-side switch 200 is turned off, the high-side gate signal QH becomes active and turns on the high-side switch 100 for a second reverse conduction time TRC2. For the second reverse conduction time TRC2, the loop current flows through the MOSFET channel of the high-side switch 100.

[0096] The second reverse conduction time TRC2 may follow the second pulse time TL2 directly or after a second dead time, wherein between the end of the second pulse time TL2 and the beginning of the second reverse conduction time TRC2, the body diode 105 of the high-side switch 100 conducts the loop current flowing through the load 300 in the second direction.

[0097] The dashed lines in Fig. 1B relate to an embodiment wherein the second pulse time TL2 directly follows the preceding first reverse conduction time TRC1 and wherein the first pulse time TL1 directly follows the preceding second reverse conduction time TRC2.

[0098] Fig. 2A and Fig. 2B refer to a full bridge with two half bridges 900, as described with reference to Fig. 1A and Fig. 1B, wherein the load 300 is electrically connected between a first switching node 150 assigned to the first half-bridge 900 and a second switching node 450 assigned to the second half-bridge 900. A first gate signal Q1 provides the high-side gate signal for the first half-bridge 900 and the low-side gate signal for the second half-bridge 900. A second gate signal Q2 provides the high-side gate signal for the second half-bridge 900 and the low-side gate signal for the first half-bridge 900.

[0099] Fig. Figure 2A illustrates the switching states and the current direction through the load 300 in the first pulse time TL1 of each first interval TP1. A load current I1 flows from the positive supply potential VDD through the high-side switch 100 of the first half-bridge 900, the load 300, and the low-side switch 420 of the second half-bridge 900 to the negative supply potential VSS. When the high-side switch 100 of the first half-bridge 900 and the low-side switch 420 of the second half-bridge turn off, the magnetic field of the load 300 maintains a loop current through the load 300 in a direction from the first switching node 150 to the second switching node 450, wherein the voltage at the first switching node 150 falls below the negative supply potential VSS and the voltage at the second switching node 450 exceeds the positive supply potential VDD.Typically, the body diode 205 of the low-side switch 200 of the first half-bridge 900 and the body diode 415 of the high-side switch 410 of the second half-bridge 900 allow the loop current to pass through.

[0100] Fig. Figure 2B illustrates the switching states and the current direction through the load 300 in the first reverse conduction times TRC1 of each first interval TP1 after the low-side switch 200 of the first half-bridge 900 and the high-side switch 410 of the second half-bridge 900 are turned on, during a time period when the magnetic field of the load 300 maintains the current flow through the load 300. The MOSFET channels of the low-side switch 200 of the first half-bridge 900 and the high-side switch 410 of the second half-bridge 900 provide an alternative current path. The current through the MOSFET channels is a unipolar current. Since the voltage drop across the MOSFET channels along the current direction is smaller than the forward voltage of the body diodes, the MOSFET channels conduct a larger portion of the loop current than the body diodes. Equivalent considerations apply to the second period TP2 with the second half of the switching period.

[0101] Fig. Figure 3A shows an electronic circuit with the full bridge with two half bridges 900, as in Fig. 2A, and a control circuit 800 that controls both half-bridges 900. The control circuit 800 generates and outputs the first gate signal Q1, which controls the high-side switch 100 of the first half-bridge 900 and the low-side switch 420 of the second half-bridge 900, and the second gate signal Q2, which controls the low-side switch 200 of the first half-bridge 900 and the high-side switch 410 of the second half-bridge 900.

[0102] Fig. 3B shows the first and second gate signals Q1, Q2 output from the control circuit 800.

[0103] The control circuit 800 includes a loop controller 810, such as a PWM circuit, for controlling the start and end of the first and second pulse times TL1, TL2, wherein the duration of the first and second pulse times TL1, TL2 may increase with increasing load. The loop controller 810 controls the first gate signal Q1 and the second gate signal Q2 according to a symmetrical pulse time modulation method.

[0104] The control circuit 800 further includes a processing circuit 820 that controls the start and end of the first and second reverse conduction times TRC1, TRC2. The first reverse conduction time TRC1 follows the first pulse time TL1 after a first dead time TD1. The second reverse conduction time TRC2 follows the second pulse time TL2 after a second dead time TD2. The first and second dead times TD1, TD2 are equal.

[0105] The processing circuit 820 may include a ramp generator circuit configured to output a rising or falling voltage ramp, and an auxiliary circuit configured to control at least the start and end of the first reverse conduction time TRC1 and the start and end of the second reverse conduction time TRC2 at times when the voltage ramp exceeds or falls below a corresponding threshold voltage. The amplitude of the voltage ramp may change linearly. The voltage ramp may increase linearly or decrease linearly.

[0106] The start of the voltage ramp for controlling the first reverse conduction time TRC1 can be triggered by the start or end of the first pulse time TL1. The start of the voltage ramp for controlling the second reverse conduction time TRC2 can be triggered by the start or end of the second pulse time TL2.

[0107] Fig. 4 shows an electronic circuit that uses the full bridge of Fig. 3A is combined with a notification circuit 700 for determining the end of the first and second reverse conduction times TRC1, TRC2 and a processing circuit 820 configured to receive a notification signal from the notification circuit 700. The notification signal includes information about a notification state.

[0108] In the illustrated embodiment, the notification circuit 700 detects a current in one of the branches of the full bridge and outputs a notification signal indicating a decrease in the amount of current below a preset threshold in the first and second reverse conduction times TRC1, TRC2.

[0109] Reference numerals 701 indicate alternative placements for the notification circuit. Alternatively, the notification circuit may include two or more subcircuits placed in two or more different branches of the half-bridge, with processing circuit 820 receiving two or more notification signals and analyzing the received notification signals to determine the end of the first and second reverse conduction times TRC1, TRC2 based on information from more than one branch.

[0110] Processing circuit 820 receives the notification signal and controls the end of the first and second reverse conduction times TRC1, TRC2 in response to the information encoded in the notification signal. The notification signal can directly trigger processing circuit 820 to turn off the low-side or high-side switch, respectively.

[0111] The notification circuit 700 may include, for example, a full-bridge current sensing element, such as a shunt resistor or a Hall probe, and a comparator.

[0112] Although discussed in detail with reference to a simplified full bridge, the method also works in multiphase topologies with symmetric pulse width modulation.

[0113] In a resonant half-bridge converter using two inductors (LL) and one capacitor (C), known as LLC configuration, or two inductors (LL) and two capacitors (CC), known as CLLC configuration, the method of operating a half-bridge as discussed above reduces conduction losses, especially when the high-side switch and the low-side switch are SiC MOSFETs.

[0114] Furthermore, the method of operating a half-bridge as discussed above in a PSFB (phase-shifted full bridge) converter and a DAB (dual active bridge) converter reduces the conduction losses, especially when the high-side switch and the low-side switch are SiC MOSFETs.

Claims

[1] A method for operating a half-bridge (900) comprising a high-side switch (100) and a low-side switch (200), the method comprising: in a first interval TP1, which begins with a current flow through a load (300) electrically connected to a switching node (150) between the high-side switch (100) and the low-side switch (200) in a first direction, switching on the high-side switch (100) for a first pulse time TL1 and switching on the low-side switch (200) for a first reverse conduction time TRC1, which begins after an end of the first pulse time TL1; and in a second interval TP2 following the first interval TP1 and beginning with a current flow through the load (300) in a second direction opposite to the first direction, switching on the low-side switch (200) for a second pulse time TL2 and switching on the high-side switch (100) for a second reverse conduction time TRC2 beginning after an end of the second pulse time TL2. [2] Method according to the preceding claim, wherein the high-side switch (100) comprises a silicon carbide field-effect transistor and / or the low-side switch (200) comprises a silicon carbide field-effect transistor. [3] Method according to one of the preceding claims, wherein a length of the first pulse time TL1 and a length of the second pulse time TL2 are controllable. [4] A method according to any one of the preceding claims, wherein a length of the first pulse time TL1 and a length of the second pulse time TL2 are controlled according to load conditions. [5] Method according to one of the preceding claims, wherein a first dead time between the first pulse time TL1 and the first reverse conduction time TRC1 and / or a second dead time between the second pulse time TL2 and the second reverse conduction time TRC2 are preset. [6] Method according to one of the preceding claims, wherein the first routing time TRC1 and the second routing time TRC2 are preset. [7] Method according to one of the preceding claims, wherein the first conduction time TRC1 and the second conduction time TRC2 are adjustable. [8] Method according to one of claims 1 to 5 and 7, further comprising: detecting a first notification condition indicating a time before a start of a second interval TP2, and setting an end of the first reverse conduction time TRC1 in response to detecting the first notification condition. [9] A method according to the preceding claim, wherein detecting the notification condition includes detecting a decrease in a current through the load (300) below a preset threshold in the first and second reverse conduction times TRC1, TRC2. [10] Method according to one of the preceding claims, wherein the start and end of the first reverse conduction time TRC1 are given by times when a rising voltage ramp exceeds a corresponding threshold voltage or when a falling voltage ramp falls below a corresponding threshold voltage, and / or the start and end of the second reverse conduction time TRC2 are given by times when a rising voltage ramp exceeds a corresponding threshold voltage or when a falling voltage ramp falls below a corresponding threshold voltage. [11] Control circuit (800) for operating a half-bridge (900) including a high-side switch (100) and a low-side switch (200), the control circuit (800) being configured to: in a first interval TP1 beginning with a current flow through a load electrically connected to a switching node (150) between the high-side switch (100) and the low-side switch (200) in a first direction, turning on the high-side switch (100) for a first pulse time TL1 and turning on the low-side switch (200) for a first reverse conduction time TRC1 beginning after an end of the first pulse time TL1; and in a second interval TP2 following the first interval TP1 and beginning with a current flow through the load in a second direction opposite to the first direction, switching on the low-side switch (200) for a second pulse time TL2 and switching on the high-side switch (100) for a second reverse conduction time TRC2 beginning after an end of the second pulse time TL2. [12] A control circuit according to claim 11, wherein a length of the first pulse time TL1 and a length of the second pulse time TL2 are controllable. [13] A control circuit according to any one of claims 11 and 12, wherein a length of the first pulse time TL1 and a length of the second pulse time TL2 are controllable in response to changing load conditions. [14] Control circuit according to one of claims 11 to 13, wherein a first dead time between the first pulse time TL1 and the first reverse conduction time TRC1 and / or a second dead time between the second pulse time TL2 and the second reverse conduction time TRC2 are preset. [15] Control circuit according to one of claims 11 to 14, wherein the first conduction time TRC1 and the second conduction time TRC2 are adjustable. [16] Control circuit according to one of claims 11 to 15, further comprising: a processing circuit (820) configured to terminate the first reverse routing time TRC1 in response to receiving information about a first notification state indicating a time before or at the beginning of a second interval TP2.

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