A PHYSICALLY UNCLONABLE FUNCTION AND A METHOD FOR GENERATING A KEY BASED ON A PHYSICALLY UNCLONABLE FUNCTION

Abstract

A method for generating a key based on a physical unclonable function is described, comprising generating a plurality of key elements of the key by operating each response structure of a plurality of response structures according to a linked challenge / response operation. The linked challenge / response operation comprises applying a first challenge to the respective response structure to cause a first response of the respective response structure as a function of the first challenge. The linked challenge / response operation further comprises applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge.The linked challenge / response operation comprises causing an output that represents a key element of the plurality of key elements of the key corresponding to the respective response structure, the output being a function of the first challenge or the first response and the second challenge or the second response.

Description

Technical area

[0001] Various aspects relate to devices and methods for operating a physical unclonable function and for generating a key based on a physical unclonable function. background

[0002] In general, various data processing applications can rely on transistor technologies. However, it has been discovered that resistor arrays can also be useful for some data processing applications. Such resistor-based technologies have been further developed to enable selective reconfiguration of the electrical resistance of resistors. Such devices with a non-volatile, reconfigurable electrical resistance can be referred to as memristive devices or memristors. Memristor crossbar arrays have been developed to replace transistors and memory cells in some data processing and data storage applications. However, the occurrence of leakage currents in memristor-based crossbar arrays can limit the scalability of such structures.Therefore, several types of memristors with nonlinear resistance behavior have been proposed to reduce leakage currents during reconfiguration and reading of selective memristors compared to non-selective memristors. These feature so-called complementary resistance switches, which comprise two memristive structures connected in series. A disadvantage of this technology can be that the state of the complementary resistance can only be read destructively, and therefore the complementary resistance switch must be rewritten after reading. One approach for non-destructively reading the state of a complementary resistance switch can be based on capacitance measurements. A complementary resistance switch can comprise a two-layer memristive structure with strong nonlinear resistance behavior and a single-layer memristive structure with strong nonlinear resistance behavior. Short description of the drawings

[0003] In the drawings, like reference characters generally refer to the same parts throughout the several views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which: Fig. 1 schematically shows different aspects of a memristive structure; Fig. 2A to Fig. 2F show aspects of electrical properties corresponding to barrier switching of a memristive structure, and Fig. 2G to Fig. 2I show measured I / V properties for various exemplary memristive structures; Fig. 3A shows a respective schematic I / V property of a memristive structure for three different memristive states and Fig. Figure 3B shows a respective I / V property measured for five different memristive states of a memristive structure; Fig. 4A to Fig. 4E show different aspects of reading a memristive structure; Fig. 5A to Fig. 5E show different aspects of reading a memristive structure; Fig. 6A to Fig. 6C show various aspects of operating memristive structures in a Physical Unclonable Functions technology; Fig. 7A to Fig. 7F show various aspects of operating response structures in a Physical Unclonable Functions technology; Fig. 8A to Fig. 8F shows various aspects of operating response structures based on a linked challenge / response operation in a Physical Unclonable Functions technology; Fig. 9A to Fig. 9H show various aspects of operating memristive response structures based on a linked challenge / response operation in a Physical Unclonable Functions technology; Fig. 10 and Fig. 11 shows various aspects of a method for generating a key in a Physical Unclonable Functions technology in a schematic flow diagram; Fig. 12A to Fig. 12H show various aspects of operating response structures based on a linked challenge / response operation in a Physical Unclonable Functions technology; and Fig. 13A to Fig. 13C show various aspects of operating response structures based on a linked challenge / response operation in a Physical Unclonable Functions technology. Description

[0004] The following detailed description refers to the accompanying drawings which, by way of illustration, show specific details and aspects in which the invention may be practiced. These aspects are described in sufficient detail to enable those skilled in the art to practice the invention. Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects are not necessarily mutually exclusive, as some aspects may be combined with one or more other aspects to form new aspects. Various aspects are described in connection with methods, and various aspects are described in connection with devices (e.g., assemblies). It is to be understood, however, that aspects described in connection with methods may equally apply to devices, and vice versa.

[0005] The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., one, two, three, four, [...], etc. The term "a plurality" may be understood to include any integer greater than or equal to two, i.e., two, three, four, five, [...], etc. The term "at least one of" with respect to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the term "at least one of" with respect to a group of elements may be used herein to mean a selection of: one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of more than one listed elements.

[0006] The term "uniquely associated" may be used herein to mean a one-to-one association (e.g., mapping, e.g., correspondence) or a bijective association. As one example, a first element being uniquely associated with a second element may include that the second element is uniquely associated with the first element. As another example, a first group of elements being uniquely associated with a second group of elements may include that each element of the first group of elements is uniquely associated with a corresponding element of the second group of elements, and that corresponding element of the second group of elements is uniquely associated with the element of the first group of elements.

[0007] The term "coupled" may be used herein with reference to nodes, circuit elements, and the like to mean a connection and / or interaction, e.g., a direct or indirect connection and / or interaction. For example, multiple elements may be coupled together along an interaction chain (e.g., an electrically conductive path) along which the interaction (e.g., electrical charges) can be transferred. For example, two coupled elements may interact with each other.

[0008] The term "connected" or "connection" may be used herein with reference to nodes, circuit elements, and the like to mean electrically connected, which may include a direct connection or an indirect connection, where an indirect connection may only include additional structures in the current path that do not affect the essential functioning of the described circuit or device. The term "electrically conductively connected," used herein to describe an electrical connection between one or more terminals, nodes, regions, contacts, etc., may be understood as an electrically conductive connection with, for example, ohmic behavior, provided, for example, by a metal or a degenerate semiconductor in the absence of pn junctions in the current path. The term "electrically conductively connected" may also be referred to as "galvanically connected."

[0009] In some aspects, two physical and / or chemical properties (e.g., an electrical voltage, an electrical current, an electrical conductivity, a thickness, an electrical conductivity, a doping concentration, as examples) may be compared using relative terms such as "greater," "higher," "lower," "less," or "equal." It is understood that in some aspects, a comparison may involve a sign (positive or negative) of a value representing the physical and / or chemical properties, or in other aspects, the absolute values may be considered for comparison. However, a comparison of measured values representing a physical and / or chemical property may typically involve a measurement of such measured values by the same measurement principle or at least by comparable measurement principles.

[0010] According to various aspects, a method for generating a key based on a Physical Unclonable Function and various aspects of a Physical Unclonable Function are described herein, wherein the randomness is generated by variations of a memristive structure in the device. Physical Unclonable Functions (also referred to as physically unclonable functions or PUFs) are hardware structures used to enable unique identification of a device or to secure keys for cryptographic processes. A device incorporating a PUF can be entire electronic smart cards or microprocessors, particularly those with hardware security modules (HSMs) for cryptographic tasks. Like a fingerprint, the PUF is an individual property tied to a physical object. PUFs are classified as physical primitives (based on a cryptographic primitive).PUF is based on the fact that even the smallest variations in the manufacturing process cause certain assemblies to behave differently, even though the manufacturing process should produce absolutely identical parts. Devices with a PUF unit can therefore be manufactured using the same manufacturing process and are not subject to individual processing—at least with regard to the PUF.

[0011] The PUF unit in the hardware can include elements that process an input (challenge, question) and generate a return value (response). Part of this challenge-response process is the PUF, which, through its behavior, causes a change in the return value that is unique to the component. Furthermore, the challenge-response process can be secured using cryptographic hashes, for example, to such an extent that the PUF's behavior cannot be deduced from the input and return values. There are several possibilities in the hardware, some of which are illustrated below.

[0012] For PUF to be used in cryptographic applications, several properties can be advantageous, such as: I) Robustness: i.e., external influences (temperature, voltage, etc.) can change only slightly at the time of reading, so that, with reliable error correction measures, the response always produces the same behavior or leads to a challenge. For example, error correction schemes are used for this purpose; II) Uncopyability: i.e., preventing, for example, a blank smart card from being converted into a clone of another smart card. The PUF can no longer be modified, and if the manufacturing process is appropriately designed, the probability of two identically manufactured smart cards disappears. III) Unpredictability: i.e., the response cannot be predicted from the input (challenge). This leads to the expectation of a high entropy of the response, even when environmental conditions change. Cooling the device (reducing thermal entropy) should not be followed by a reduction in information entropy; IV) Tamper evidence: ie the PUF reacts to an invasive manipulation of the device and thereby reveals it or the response is no longer accepted.

[0013] In contrast to standard devices (transistors, SRAM elements, ring oscillators, for example) used in well-known PUF technologies, memristors are more efficient at providing a source of randomness for PUFs due to their attractive properties (e.g., inherent stochasticity and high density) and remarkable variation. With a compact crossbar array structure, randomness in the conductivity distribution, switching delay, and probabilistic switching can be utilized to create highly random and reliable PUFs.

[0014] According to various aspects, a key element generated by a PUF may be referred to as a PUF bit, since a key is typically represented in a bit sequence. Each key element may be derived from at least one PUF subunit or from multiple PUF subunits to reduce the error rate. According to various aspects, a PUF subunit as described herein may be implemented by a memristive structure including at least one memristive element. Typically, up to 5 PUF subunits may be used to represent a key element (e.g., a PUF bit). Today, PUFs can represent 128-bit or 256-bit keys and consist of up to 5 * 128 PUF subunits or up to 5 * 256 PUF subunits, respectively.

[0015] A problem related to robustness can be caused, for example, by external influences (temperature, voltage, etc.) at the time of determining the response of a PUF subunit to a challenge. External influences can increase the cycle-to-cycle variation of each PUF subunit and thus the error rate in extracting the key bit. The problem of insufficient unpredictability can be caused, for example, by too small and partially correlated fluctuations in the manufacturing process of PUF subunits. The problem of insufficient unpredictability can also be caused by a dependence of information entropy on thermal entropy. The problem of tampering can be caused by using the device-to-device (PUF subunit-to-PUF subunit) variability of the challenge response of all PUF subunits that form the PUF, e.g.all 5*128 PUF subunits or up to 5*256 PUF subunits of the PUF, representing a 128-bit or a 256-bit key, respectively.

[0016] According to various aspects, the PUF described herein may be configured to represent an N-key element key (also referred to as an N-bit key) and is not subject to device-to-device (D2D) variability of the PUF subunits. The PUF described herein exploits the uncorrelated fluctuations in the device-within-device (DiD) variability of each of the PUF subunits or a set of PUF subunits. The PUF described herein exploits the device-within-device variability of individual PUF subunits to extract each key element of the N-key element key from the challenge-response of individual PUF subunits or a set of PUF subunits.

[0017] According to various aspects, a PUF subunit may be characterized by a challenge-response function with different I / V branches j. The PUF subunit may be realized by a memristive structure including one or more memristive elements. A memristive element, and therefore a memristive structure, may include a positive pair of branches (e.g., a positive LRS branch and a positive HRS branch, or more precisely, a positive write branch and one or more positive read branches) and / or a negative pair of branches (e.g., a negative LRS branch and a negative HRS branch, or more precisely, a negative write branch and one or more negative read branches).

[0018] Various aspects relating to a memristive structure and a memristive element are described below. According to various aspects, a memristive structure in an array of memristive structures (e.g., within a crossbar array) may be addressable, e.g., by being uniquely assigned a logical address. The addressability and the logical addresses may be provided by the architecture of the control lines associated with a respective memristive structure. In a crossbar array, two sets of control lines (e.g., a set of word lines and a set of bit lines) may be used to address an array of memristive structures. According to various aspects, an analog memristive structure may be in one of various memristive states (also referred to as resistance states) associated with it.As one example, the actual electrical resistance (or conductivity) associated with a memristive structure can be determined via a read operation to evaluate which of the various memristive states the memristive structure is in. As another example, the actual electrical resistance (or conductivity) associated with a memristive structure can be used in a neural network configuration to influence data or signal processing.

[0019] In some aspects, a plurality of memristive structures may be arranged in a crossbar configuration. In such a crossbar configuration, a portion of memristive material (also referred to as a memristor or memristive device) may be addressed by a corresponding crossover point formed by input lines and output lines of the crossbar arrangement. However, a plurality of memristive structures may be arranged in any other suitable configuration that enables a desired electrical addressing to operate the memristive structures.

[0020] Fig. 1 shows various aspects of a memristive structure 100. A memristive structure 100 may include a first electrode 110 and a second electrode 120. The first electrode 110 and / or the second electrode 120 may include any suitable electrically conductive material, e.g., Al, Cu, Ti, AlCu, TiN, W, Ta, as examples only. The memristive structure 100 may further include a memristive material portion 130 (e.g., a memristive element). The memristive material portion 130 may be disposed between the first electrode 110 and the second electrode 120. Illustratively, the region where the first electrode 110 and the second electrode 120 overlap each other may be filled (e.g., partially or completely) with memristive material. According to various aspects, the memristive material portion 130 may be in electrical contact and in direct physical contact with both the first electrode 110 and the second electrode 120.

[0021] According to various aspects, the memristive structure 100 may be a memristive crosspoint structure included in a memristive crossbar array. The first electrode 110 and the second electrode 120 may each be a portion of a corresponding crossbar control line. As an example, a crossbar array may include a set of first control lines and a set of second control lines in a crossbar configuration, and the first electrode 110 may be a portion of a first control line 111 of the set of first control lines, and the second electrode 120 may be a portion of a second control line 121 of the set of second control lines, as shown in Fig. 1. In this example, the memristive material portion 130 may be in direct physical contact with both the first control line 111 and the second control line 121, and the memristive material portion 130 may be disposed between both the first control line 111 and the second control line 121. Accordingly, a memristive structure 100 may be provided in each of various crosspoint regions of the crossbar array.

[0022] In other aspects, the first electrode 110 may be coupled to a corresponding first control line (e.g., a first control line of a crossbar array) (e.g., electrically conductively connected, e.g., in direct physical contact therewith), and the second electrode 120 may be coupled to a corresponding second control line (e.g., a second control line of a crossbar array) (e.g., electrically conductively connected, e.g., in direct physical contact therewith). As an example, a crossbar array may have a set of first control lines and a set of second control lines in a crossbar configuration, and the first electrode 110 may be coupled to a first control line 111 of the set of first control lines (e.g., electrically conductively connected, e.g., in direct physical contact therewith), and the second electrode 120 may be coupled to a second control line 121 of the set of second control lines (e.g.,electrically conductively connected, e.g., in direct physical contact therewith). In this example, the memristive material portion 130 may not be in direct physical contact with the first control line 111 and the second control line 121. However, the first electrode 110 may be in direct physical contact with the first control line 111, and the second electrode 120 may be in direct physical contact with the second control line 121. The first electrode 110, the second electrode 120, and the memristive material portion 130 may be arranged between the first control line 111 and the second control line 121. Accordingly, a memristive structure 100 may be provided in each of various crosspoint regions of a crossbar array.

[0023] As explained above, the first control line 111 and the second control line 121 may be in a crossbar configuration or in any other suitable configuration to enable electrical addressing of the memristive structure 100 (i.e., the memristive material portion 130) via the first control line 111 and the second control line 121. Electrical addressing of the memristive structure 100 may be used to read information stored in the memristive structure 100 and / or to write (e.g., store) information to the memristive structure 100. In other words, electrical addressing of the memristive structure 100 may be used to determine a state (e.g., a memristive state) in which the memristive structure 100 is located and / or to set (e.g., maintain or change) a state (e.g., a memristive) of the memristive structure 100.

[0024] Possible materials that can be used to form the memristive material section 130 can be, for example, a ternary oxide, a quaternary oxide, and / or a quinary oxide. Examples of ternary oxides are perovskite oxides with a base structure of ABO3 or bixbyite with a base structure of A2O3 or B2O3, or mixtures thereof. Furthermore, mixtures can include various impurities at the A or B site. Examples of elements for A can include La3+, Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yp, Lu, Ca, Pr, Pm, Tm, Tl, Pb, Bi, Sr, Y, Ba, Cr, Pu (e.g., all 3+ such as La3+). Examples of elements for B can include Al3+, Cr, Fe, Ga, In, Sc, V, Ti, Mn, Co, Ni, Sn (e.g., all 3+ like Al3+). Examples of impurities at the A site can include Ca, La, Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, Lu, Pr, Pm, Tm, Tl, Pb, Bi, Sr, Y, La, Ba, Cr, Pu, Al, Cr, Fe, Ga, In, Sc, V, Ti, Mn, Co, Ni, Sn, e.g., with a valence other than 3+.Examples of B-site impurities may include Al, Cr, Fe, Ga, In, Sc, V, Ti, Mn, Co, Ni, Sn, Ca, La, Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, Lu, Pr, Pm, Tm, Tl, Pb, Bi, Sr, Y, La, Ba, Cr, Pu, e.g., with a valence other than 3+. Perovskite oxides can exist in various phases, such as a rhombohedral alpha phase, an orthorhombic beta phase, a hexagonal phase, and / or a cubic bixbyite phase. Examples of suitable crystalline materials may include the ternary oxides CaTiO3, BaTiO3, PbTiO3, LaNiO3, NdAlO3, and / or PrAlO3. The memristive material portion 130 may be or include one or more of the following materials and / or material combinations: Al2O3 / TaOx, SiOx:Ag / TiOx, TaO, HfAl2Ox / TaO, Pr0.7Ca0.3MnO3 (PCMO), Si-In-Zn-O / ion gel, SiInZnO, SiN / TaN, SrFeO3, as examples only.

[0025] In some aspects, at least a portion of the memristive material portion 130 may be modified, e.g., to effect vacancy doping V+ or V-. In some aspects, the memristive material portion 130 may comprise an n-type memristive material having a positive vacancy doping V+, e.g., an anion vacancy. In other aspects, the memristive material portion 130 may comprise a p-type memristive material having a negative vacancy doping V-, e.g., a cation vacancy. In the case that the memristive material forming the memristive material portion 130 is an oxide, e.g., BiFeyOx, the vacancy doping V+ may be effected by oxygen vacancies VO+. In some aspects, at least a portion of the memristive material portion 130 may be modified, e.g., to effect trapping T. Accordingly, the memristive material portion 130 may have traps T.As an example, the traps T can be created by introducing metal ions (e.g., titanium ions) into the memristive material. One function of the memristive material section 130 can be understood in terms of mobile vacancies V+ that can be locally confined in regions of the memristive material section 130. The traps T can be introduced adjacent to the first electrode 110 and the second electrode 120, and the mobile vacancies V+ can selectively move either into the region adjacent to the first electrode 110 or into the region adjacent to the second electrode 120 and be confined there in an electric field, accordingly.This may enable selective creation of a Schottky-type diode either with maximum barrier height at the first electrode 110 or with maximum barrier height at the second electrode 120, such that the memristive structure 100 has nonlinear switching behavior and is self-rectifying.

[0026] A memristive structure (also called a memristive device, memristive element, resistive switch, memristor, memristor element or memristor structure) can be considered as an analog memristive structure in the case that the memristive structure detects a continuous change in current (e.g. in the read current I Lese ) when (e.g. linear) the applied voltage (e.g. from 0 V to +V max and from +V max to 0 V and from 0 V to -V max and from -V max to 0 V) is ramped up, as for example in Fig. 2A and Fig. 2B. This current may be associated with a current through the memristive structure 100. Various aspects will be described below with reference to the memristive structure 100; it is noted that this is for illustrative purposes and that other memristive structures may be used accordingly.

[0027] Until now, a memristive structure has been placed into either a high-resistance state (HRS) or a low-resistance state (LRS). This process of placing the memristive structure into the high-resistance state (HRS) or the low-resistance state (LRS) has often been referred to as writing a memristive state to the memristive structure. However, according to various aspects, an applied write signal (e.g., a maximum applied voltage value or a maximum applied current value, a shape of the write signal, etc.) can define the memristive state into which the memristive structure is written (e.g., in the case of a voltage signal, the memristive state after reducing the voltage to 0 V). This curve associated with changing the memristive states can be referred to as a transition curve. It is noted that this transition curve is common to all memristive states.It is further noted that each memristive state is associated with a corresponding resistance characteristic, so that information about the resistance characteristic allows one to infer the memristive state in which the memristive structure is located. Thus, each resistance characteristic can be uniquely associated with a respective memristive state and vice versa. This resistance characteristic can be independent of how the memristive structure was placed into the corresponding memristive state. It is understood that any memristive structure can be read using one or more reading schemes, and that any type of device including at least one memristive structure can use any of the reading schemes.According to one example, the device may include a read / write circuit configured to read and / or write the memristive state of the at least one memristive structure. According to another example, the device may be coupled (e.g., for analysis) to another device configured to apply a read / write signal to the memristive structure to read and / or write the memristive state of the at least one memristive structure.

[0028] According to various aspects, a read / write signal may be applied to the memristive structure to set a memristive state and / or to read a previously set memristive state. The read / write signal may be, for example, a signal pulse. The memristive structure 100 may be addressed via a voltage-controlled mode or a current-controlled mode. In the case of the voltage-controlled mode, a voltage signal (e.g., a voltage pulse) may be applied to the memristive structure 100, and an induced current through the memristive structure 100 may be determined (e.g., measured). In the case of the current-controlled mode, a current signal (e.g., a current pulse) may be applied to the memristive structure 100, and an induced voltage may be determined (e.g., measured). Various aspects of memristive structures and various reading schemes for the voltage-controlled mode (e.g.,in the case of the I / V characteristics shown). It is noted that this is for illustrative purposes only and that other modes, such as current-controlled mode, may be used accordingly.

[0029] Fig. 2A shows a first example ramp scheme 200a that may be used to place the memristive structure 100 into a high resistance state (HRS) and a second example ramp scheme 200b that may be used to place the memristive structure 100 into a low resistance state (LRS). Fig. 2B shows an exemplary current / voltage (I / V) characteristic of the memristive structure 100 obtained via the two exemplary ramp schemes 200a, 200b, according to various aspects. Fig. Figure 2C shows two equivalent circuits representing the electrical state of a memristive structure for the HRS and the LRS. The memristive structure 100 may be in a self-rectifying configuration. The self-rectifying configuration and / or the desired switching behavior may be caused by forming a diode (e.g., a Schottky junction) and a resistor at the interfaces between the first electrode 110 and the memristive element 130 and between the second electrode 120 and the memristive element 130 (the memristive element 130 may be a memristive material section). The diode and resistor are coupled in series and provide the described HRS and LRS states for a defined polarity.The switching of the memristive structure 100 and therefore the presence of a diode contact or a resistive contact at the respective electrode regions can be defined by the memristive material, e.g., by the presence and / or absence of oxygen vacancies in the electrode regions.

[0030] It is understood that the Fig. 2B are exemplary and serve as a schematic illustration, and the I / V properties of a memristive structure can vary. In particular, many different types of I / V properties are possible for different types of memristive structures (e.g., depending on the material, size, layer thickness, etc.). Fig. 2D to Fig. 2F each show an exemplary measured I / V property of a respective memristive structure.

[0031] So far, the memristive structure 100 can be put into a well-defined memristive state by applying an initialization voltage V ini (referred to in some aspects as a programming voltage or write voltage) is applied and then a desired write voltage scheme is applied to set a memristive state in which the memristive structure 100 is after the write voltage is applied.

[0032] As in Fig. As shown in Figure 2A, the memristive structure 100 can be put into the low-resistance state (LRS, branch 2) by changing the voltage from 0 V to +|V max | (branch 1) is ramped up, and into the low-resistance state (LRS, branch 4) by reducing the voltage from 0 V to -|V max | (Branch 3) is raised like a ramp. As in Fig. As shown in Figure 2B, the memristive structure 100 can be put into the low-resistance state (LRS, branch 2) by reducing the voltage from 0 V to -|V max| (branch 1) is ramped up, and into the low-resistance state (LRS, branch 4) by increasing the voltage from 0 V to +|V max | (Branch 3) is ramped up. The resistance state in branch 2 and branch 4 in Fig. 2A can be determined by applying a read voltage that is smaller than the write voltage and has the same polarity as the write voltage, ie positive polarity in branch 2 and negative polarity in branch 4. The resistance state in branch 2 and in branch 4 in Fig. 2B can be determined by applying a read voltage (value) that is smaller than the write voltage (value) and has the same polarity as the write voltage (value), i.e., a negative polarity in branch 2 and a positive polarity in branch 4. In this case, the state of the memristive structure 100 can be read by applying a positive read voltage with a voltage value between about 0 V and about +V maxDepending on the state of the memristive structure 100, the applied read voltage always causes a larger current flow associated with the low-resistance state compared to the small current flow that flows during the application of the write voltage. Here, the voltage V can be up to a maximum positive voltage value +V max and up to a maximum negative voltage value -V max ramp-like manner. In one example, the respective maximum voltage |V max | be the highest voltage that can be applied so that no breakdown (e.g. the one related to Fig. 2C). In another example, the respective maximum voltage |V max| have any voltage value other than 0. However, as described above, these complex writing schemes may not be required by using the results that the high resistance state (HRS) always corresponds to changing memristive states (branches 1 and 3 in Fig. 2A and branches 1 and 3 in Fig. 2B) and that each memristive state is associated with a corresponding resistance characteristic (branches 2 and 4 in Fig. 2A and branches 2 and 4 in Fig. 2B).

[0033] Fig. 3A shows a schematic I / V characteristic of the memristive structure 100, exemplifying the first quadrant of the IV diagram. The following description may apply similarly to the third quadrant. For example, the first quadrant and the third quadrant may be associated with a respective transition curve. Furthermore, the first quadrant (i.e., positive applied voltages) may be associated with a plurality of (positive) memristive states, and the third quadrant (i.e., negative applied voltages) may be associated with a plurality of (negative) memristive states. It should be understood that in some aspects, the described behavior may only be present in either the first quadrant or the third quadrant. Fig. Figure 3A also shows a voltage signal scheme that includes write (dashed lines) and read (solid lines) memristive states.

[0034] As shown by way of example for the first quadrant, the transition curve 302 (branch 1) may be associated with changing the resistivity of the memristive structure 100 (e.g., via moving traps T), thereby changing the memristive state m s Each current-voltage (IV) data point I(V) on the transition curve 302 can be associated with a corresponding memristive state 1 ≤ m s≤ M (where M is any integer greater than or equal to one (e.g., greater than or equal to 100, e.g., greater than or equal to 200, etc.) of the memristive structure 100. This transition curve 302 may be associated with the HRS state. As described herein, it is noted that when the memristive structure is placed into a respective memristive state, this transition curve 302 is similar for all memristive states (since each data point of the transition curve 302 corresponds to a respective memristive state). Thus, a memristive structure 100 has a transition curve 302 (transition from a lowest memristive state m s = 1 via various memristive intermediate states to a highest memristive state m s = M). For illustrative purposes, the transition curve 302 is shown herein as (substantially) linear. It should be understood that the transition curve 302 may have any shape depending on the memristive structure. Fig. Figure 3B shows an I / V characteristic measured for a fabricated memristive structure, illustrating that the transition curve 302 may have a substantially linear progression. However, it is noted that there may be a highest memristive state m s = M, which is associated with a corresponding voltage value. Within the same quadrant (e.g. the first or the third quadrant), the memristive states (of m s = 2 to m s = M-1) between the lowest memristive state m s = 1 and the highest memristive state m s = M are called memristive intermediate states. If a voltage is applied that has a voltage value that is greater than the voltage value corresponding to the highest memristive state m s= M, the memristive structure 100 can be placed in the highest memristive state. In this case, the transition curve 302 can change (e.g., slowly) from linear behavior to saturation (thus, a substantially stable current) at the voltage value corresponding to the highest memristive state. It should be understood that by further increasing the voltage value beyond this saturation regime, the current value can increase significantly due to the diode nature of the memristive structure 100 (thus, a breakdown of the Schottky-type diode).

[0035] As described herein, each memristive state (thus each data point I(V)) on the transition curve 302) can be associated (e.g., uniquely assigned) with a corresponding resistance characteristic curve (branch 2 in the case of the branch 1 transition curve or branch 4 in the case of the branch 3 transition curve) (as understood up to the highest memristive state). This resistance characteristic curve can be characteristic of a corresponding memristive state (thus characteristic of the resistance corresponding to the memristive state). A resistance characteristic curve can be understood as a respective characteristic LRS curve for each memristive state. Fig. 3A schematically shows a first resistance curve 304 (e.g., a first LRS curve) corresponding to a first memristive state, a second resistance curve 306 (e.g., a second LRS curve) corresponding to a second memristive state different from the first memristive state, and a third resistance curve 308 (e.g., a third LRS curve) corresponding to a third memristive state different from both the first memristive state and the second memristive state. Fig. Figure 3B shows the common transition curve 302 (HRS curve) and a corresponding (individual) resistance characteristic curve (thus a respective LRS curve) for five different memristive states, which are set via a respective programming voltage (6 V, 6.5 V, 7 V, 7.5 V and 8 V).

[0036] Thus, depending on the memristive state in which the memristive structure is located, the I / V characteristic may follow the transition curve 302 (in the case of changing the memristive state) or may follow the resistance characteristic corresponding to a current memristive state (in the case of holding (i.e., not changing) the memristive state). Thus, a measured I / V characteristic may depend on a current memristive state of the memristive structure 100. To program a memristive state and / or to determine the current memristive state of the memristive structure 100, a (e.g., measurement) signal may be applied to the memristive structure 100. For example, the measurement signal may be a measurement pulse (e.g., a voltage pulse or a current pulse).

[0037] As described in detail above, the measurement source / input signal (short measurement signal) is described as a voltage pulse for illustrative purposes, and the measurement output signal is described as a corresponding current pulse for illustrative purposes. Exemplary waveforms and shapes of one or more voltage pulses are shown in Fig. 4A to Fig. 4E. For simplicity, the voltage pulses are shown as a base voltage rising from and falling to 0 V. It is understood that the base voltage may have any suitable voltage value. In some aspects, the voltage may be applied to one of the first electrode 110 or the second electrode 120, and the base voltage may be applied to the other of the first electrode 110 or the second electrode 120. In other aspects, a respective voltage (different from the base voltage) may be applied to the first electrode 110 and the second electrode 120. In this case, the voltage values of the voltages described herein (e.g., the maximum positive read voltage value +V Lese,max , the maximum negative read voltage value +V Lese,maxetc.) voltage drops across the memristive structure 100 (hence a voltage difference between the voltage applied to the first electrode 110 and the voltage applied to the second electrode 120).

[0038] As shown, a voltage pulse can have a linear triangular shape (see e.g. Fig. 4A and Fig. 4B), a stepwise triangular progression (see e.g. Fig. 4C), a sinusoidal curve (see e.g. Fig. 4D) or an exponentially falling / rising curve (see e.g. Fig. 4E) as examples. It is understood that any other waveform and / or shape may be used. Even though these voltage pulses are described as read signals, it is understood that a write signal may have a similar waveform and / or shape. A voltage pulse may be characterized by a rising edge from the base voltage (e.g., 0 V) to a maximum read voltage value and a falling edge from the maximum read voltage value to the base voltage (e.g., 0 V). For example, a first voltage pulse may be characterized by a rising edge 402 from the base voltage (e.g., 0 V) to a maximum positive read voltage value +V Lese,max and a falling edge 404 from the maximum positive read voltage value +V Lese,maxto the base voltage (e.g. 0 V). A second voltage pulse may be characterized by a rising edge 406 from the base voltage (e.g. 0 V) to a maximum negative read voltage value -V Lese,max and a falling edge 408 from the maximum negative read voltage value -V Lese,maxto the base voltage (e.g., 0 V). A rising edge may be associated with (e.g., continuously) increasing (e.g., ramping) a voltage up to the maximum (positive or negative) voltage value (other than zero volts). According to various aspects, only one voltage pulse (e.g., the first voltage pulse or the second voltage pulse) may be applied. According to other aspects, the first voltage pulse and the second voltage pulse (in any order) may be applied consecutively. In this case, the first voltage pulse and the second voltage pulse (in any order) may be applied directly one after the other, or there may be a time delay between them.

[0039] As described herein, a measured I / V property (e.g., branch 2 and / or branch 4) depends on a current (i.e., an actual or present) memristive state of the memristive structure 100. This memristive state of the memristive structure 100 may depend on a previously applied measurement signal (in the present example, a previously applied voltage signal). The memristive state may be set by applying a programming voltage pulse. For simplicity, the maximum voltage (referred to as the programming voltage in some aspects) of the programming voltage pulse is considered hereinafter to define the memristive state to which the memristive structure 100 is placed.It is noted, however, that the memristive state into which the memristive structure 100 is placed by applying the programming voltage pulse may also depend on other aspects, such as the shape and / or the course of the programming voltage pulse.

[0040] Thus, the current / voltage (I / V) characteristic of the memristive structure 100 can be dependent on a previously applied voltage value, V prior, which is associated with a previously applied voltage. Fig. 5A to Fig. 5E schematically show a respective I / V characteristic, which depends on the previously applied voltage value, V prior , depends on the memristive structure 100 with the Fig. 3A. In the case that a previous voltage has a negative voltage value (ie V prior< 0), the memristive structure 100 is either in a (negative) memristive state associated with the third quadrant (i.e., a negative voltage value and a negative current value), since the negative voltage would either write a (negative) memristive state associated with the third quadrant (e.g., in the case that the memristive structure 100 is in a memristive state associated with the first quadrant or in a memristive state associated with a negative voltage value having an absolute value smaller than the voltage value of the applied negative voltage), or would hold the (negative) memristive state in the case that the memristive structure 100 is in a (negative) memristive state associated with a negative voltage value having an absolute value greater than the voltage value of the applied negative voltage.When a first reading voltage pulse is applied (e.g. with a shape and / or a curve as in . Fig. 4A, Fig. 4C, Fig. 4D or Fig. 4E) with a first voltage value, V1, as the maximum positive read voltage value +V Lese,max the rising edge 402 of the first read voltage pulse (continuously) changes the memristive state, m s , (over the memristive states starting with m s = 1) until the memristive structure 100 enters the memristive state m s = m s (V1) which is connected to the first voltage value, V1 (see Fig. 5A). Thus, the I / V characteristic follows the transition curve 302 during the rising edge 402 of the first read voltage pulse. The falling edge 404 of the first read voltage pulse maintains the set (e.g., written) memristive state m s = m s(V1) is maintained (i.e., does not change) because the voltage value is reduced (and not further increased). Thus, the I / V characteristic follows the first resistance curve 304 associated with the first voltage value, V1, during the falling edge 404 of the first read voltage pulse. Upon application of a (subsequent) second read voltage pulse (with the same polarity as the first read voltage pulse) with a different voltage value, V0, (which is smaller than the first voltage value, V1) as the maximum positive read voltage value +V Lese,max the rising edge 402 of the second read voltage pulse maintains the memristive state m s = m s (V1) upright (ie does not change) (see Fig. 5B). Therefore, the rising edge 402 of the second read voltage pulse follows the first resistance curve 304 associated with the first voltage value, V1. Upon application of a third read voltage pulse (with the same polarity as the first read voltage pulse) with the first voltage value, V1, as the maximum positive read voltage value +V Lese,max the rising edge 402 of the third read voltage pulse maintains the memristive state m s = m s (V1) up to the first voltage value, V1, maintained (ie does not change) (see Fig. 5C). Therefore, the rising edge 402 of the third read voltage pulse follows the first resistance curve 304 associated with the first voltage value, V1, up to the first voltage value, V1. Upon application of a fourth read voltage pulse (with the same polarity as the first read voltage pulse) with a second voltage value, V2, (which is greater than the first voltage value, V1) as the maximum positive read voltage value +V Lese,max the rising edge 402 of the second read voltage pulse maintains the memristive state m s = m s (V1) up to the first voltage value, V1, maintained (ie does not change) (see Fig. 5D). Therefore, the rising edge 402 of the second read voltage pulse follows the first resistance characteristic curve 304, which is associated with the first voltage value, V1, up to the first voltage value, V1. As soon as the voltage value of the rising edge 402 exceeds (is greater than) the first voltage value, V1, the memristive state m s of the memristive structure 100 (continuously) changed (starting from the memristive state m s = m s (V1) to the memristive state m s = m s (V2). Thus, the rising edge 402 of the fourth read voltage pulse follows the transition curve 302 from the first voltage value, V1, to the second voltage value, V2. The falling edge 404 of the fourth read voltage pulse maintains the set (e.g., written) memristive state m s = m s(V2) is maintained (i.e., does not change) as the voltage value is reduced. Thus, the I / V characteristic of the second resistance curve 306, associated with the second voltage value, V2, during the falling edge 404 of the fourth read voltage pulse. This applies similarly to the application of any read voltage pulse with a greater voltage value (up to the highest voltage value) than a previously applied read voltage pulse. Thus, the I / V characteristic of the memristive structure 100 upon application of a (subsequent) fifth read voltage pulse (with the same polarity as the second read voltage pulse) with a third voltage value, V3, (which is greater than the second voltage value, V2) as the maximum positive read voltage value follows +V Lese,maxthe second resistance characteristic curve 306, which is connected to the second voltage value, V2, up to the second voltage value, V2, during the rising edge 402 of the fifth read voltage pulse and follows the transition curve 302 from the second voltage value, V2, to the third voltage value, V3. The falling edge 404 of the fifth read voltage pulse maintains the set memristive state m s = m s (V3) and the I / V characteristic therefore follows the third resistance characteristic curve 308 which is associated with the third voltage value, V3.

[0041] According to various aspects, a memristive state of the memristive structure 100 may be read either non-destructively (while maintaining the memristive state) or destructively (which includes changing the memristive state).

[0042] In the case of a non-destructive read, the memristive structure 100 may be in a memristive state m s(+V program ) which has a positive programming voltage value +V program which is equal to or greater than the maximum reading voltage value +V Lese,max of the read voltage pulse. In this case, as described herein (e.g. with respect to Fig. 5A to Fig. 5E), the rising edge 402 of the read voltage pulse causes a current through the memristive structure 100 according to the resistance characteristic corresponding to the memristive state m s (+V program ). Thus, the application of the read voltage pulse can change the memristive state m s (+V program ) associated with the positive programming voltage. This allows, for example, the memristive state m s (+V program ) of the memristive structure 100 several times, as long as the respective maximum reading voltage value +V Lese,maxeach read voltage pulse is equal to or less than the positive programming voltage value +Vprogram (and of course within the same quadrant, ie with the same polarity). If the read voltage is in a range between the base voltage (e.g. 0 V) and the maximum read voltage value +V Lese,max ramp-like, which is smaller than the programming voltage value +V program is, the falling edge 404 of the read voltage pulse also causes a current according to the resistance characteristic corresponding to the memristive state m s (+V program ) (since the memristive state is not affected by the maximum read voltage value +V Lese,max is changed). It should be understood that negative voltages cannot be applied in this example because, as described herein, a negative voltage would write a memristive state in the third quadrant of the I / V characteristic.

[0043] In the case of a destructive read, the memristive structure 100 may be in a memristive state m s (+V program ) connected to a positive programming voltage value +Vprogram that is less than the maximum read voltage value +V Lese,max of the read voltage pulse. In this case, as described herein (e.g. with respect to Fig. 5A to Fig. 5E), the rising edge 402 of the read voltage pulse as soon as the voltage value reaches the positive programming voltage value +V program a current through the memristive structure 100 according to the transition curve (e.g., transition curve 302). Thus, the application of the read voltage pulse can change the memristive state from the memristive state m s (+V program ), which is connected to the positive programming voltage, into the memristive state m s (+V Lese,max ) corresponding to the maximum reading voltage value +V Lese,max is connected.

[0044] Fig. 6A to Fig. 6C each depict a device 600 according to various aspects. Device 600 may be a memory device or a storage device. For example, device 600 may be an n-logic memory. Device 600 may include a plurality of memristive structures 602 (n = 2 to N). "N" may be any integer greater than or equal to two. According to various aspects, "N" may be any integer greater than or equal to twenty (e.g., greater than or equal to one hundred).

[0045] The device 600 may include an operating circuit 600c. As described herein, the operating circuit 600c may be configured to write and read a respective logical state (of two or more logical states) of each memristive structure of the plurality of memristive structures 602 (n = 2 to N) based on a challenge-response scheme as described herein. The device 600 may include one or more processors 604 (the one or more processors 604 may be a controller or part of a controller; the controller may be a PUF controller). The one or more processors 604 may be configured to determine a key 606. The key 606 may be, for example, a private key or an authentication key.In some aspects, the one or more processors 604 may be configured to determine the key 606 based on the logical states determined for the plurality of memristive structures 602 (n = 2 to N). In various aspects, process variations or variances between the plurality of memristive structures 602 (n = 1 to N) may be used to generate the key 606. As a result, the plurality of memristive structures 602 (n = 1 to N) may be a Physical Unclonable Function (PUF). In particular, variations in the manufacturing process may induce variations in the plurality of memristive structures 602 (n = 1 to N). The variations in the manufacturing process introduce randomness into the properties of the plurality of memristive structures 602 (n = 1 to N) and may therefore provide the entropy to generate the key 606.Such variations in the properties of the plurality of memristive structures 602 (n = 1 to N) may result in differences in the I / V properties of the plurality of memristive structures 602 (n = 1 to N).

[0046] According to various aspects, device 600 may include a random number generator, and operating circuitry 600c may be configured to select the memristive state to which a respective memristive element 602 of the plurality of memristive elements is to be written from the plurality of memristive states based on a random number generated by the random number generator. This may further increase randomness and thus security. Device 600 may be any device that can be used or may be used to generate a key (e.g., a cryptographic key 608 derived from key 606), a random number (e.g., a random number 610 derived from key 606), etc. Thus, device 600 may be, or be part of, any suitable security device.For example, device 600 may be or be part of a hardware security module, a security key (e.g., a Universal Serial Bus (USB) security key), and / or a secure cryptoprocessor.

[0047] Various aspects described herein may relate to a memristive structure that can be configured and operated to implement a Physical Unclonable Function (PUF) with a high level of security and reliability. A Physical Unclonable Function, or PUF, can be understood as a physical object (e.g., a hardware device) that, for a given input and conditions (referred to as a challenge), provides a physically defined output (referred to as a response), which serves as a unique identifier. The Physical Unclonable Function described herein is based on unique physical variations that naturally occur during manufacturing.In contrast to conventionally used PUF technology, which relies on device-to-device variations, the PUF described herein utilizes device variations in each of the memristive structures employed. The device variation employed in the novel PUF technology described herein generates a response for a memristive structure, and simultaneously, a reference is provided from the same memristive structure for deriving the secret (e.g., for deriving the key element, e.g., for deriving whether the response represents a first or second logical state (commonly denoted as "0" or "1")) with respect to the memristive structure.

[0048] Various aspects of a method for generating a key based on a physical unclonable function and various aspects of a physical unclonable function are described below by way of example for a memristive structure comprising one or more memristive elements. However, it is clear that any desired number of memristive structures may be included in a physical unclonable function or in a hardware device (e.g., in a security chip, in a device for identification and authentication in a 5G / 6G network environment, etc.) including the physical unclonable function.

[0049] The various aspects of the Physical Unclonable Function described herein can address problems associated with conventional realizations of a Physical Unclonable Function. Classical computers and quantum computers can only compute algebraic functions. Based on a memristive structure as described herein, transcendental functions (e.g., functions that cannot be described by a polynomial equation, e.g., non-algebraic functions) can be implemented as a basis in the Physical Unclonable Function. This enables the development of a quantum-secure hardware solution for implementing zero-trust principles, i.e., for mutual confirmation of identity and authenticity, for trusted exchange of information in unsecured networks, as one example.According to various aspects, the Physical Unclonable Function of the Physical Unclonable Function, which uses a transcendent challenge-input and key-response approach as described herein, provides quantum-secure random and unique secret keys.

[0050] According to various aspects, a cryptographic key generator (see device 600) based on memristive structures as described herein is provided. The memristive structures may have an electrical property (e.g., an I / V property) that enables the generation of at least two different challenge-response pairs based on different I / V branches (see, e.g., Fig. 2B, Fig. 2D, Fig. 2E and Fig. 2F).

[0051] The memristive structures of the PUF described herein can be a passive electronic device with reconfigurable internal resistance states that has a transcendent challenge-key-response function. Therefore, the generation of the key response and the generation of the transcendent input response function are merged in the PUF based on the memristive structures. This enables the realization of a quantum-secure cryptographic key generator with PUFs based on memristive structures that provide quantum-secure random and unique secret keys. Although memristive structures with one or more memristive elements can have some unique advantages for generating a key based on them (e.g.,the response of a memristive structure can be transcendental, the memristive structure can have a multi-branch memristive element to implement more than one challenge / response via the same multi-branch memristive element, the memristive structure can be current-driven and / or voltage-driven such that the challenge can be a current challenge and / or a voltage challenge), as explained herein, any other suitable response structure with one or more response elements can be used in the same or a similar manner to generate a key (e.g., any response structure having one or more response elements that enables entropy generation for generating a key via a PUF).

[0052] Fig. 7A shows a schematic flow diagram of a method for generating a key based on a Physical Unclonable Function 700. According to various aspects, the method may be implemented in the operating circuit 600c of the device 600 such that the device 600 is a Physical Unclonable Function 700, or in other aspects, the method may be implemented in any other suitable operating circuit 700c (the operating circuit may include a PUF controller) of a Physical Unclonable Function device 700. According to various aspects, the method may comprise, at 710, generating a plurality of key elements 730e of a key 730 by operating each response structure 740m of a plurality of response structures 740 according to a linked challenge / response operation 720.The linked challenge / response operation 720 is applied to each response structure 740m of the plurality of response structures 740 and includes a first challenge operation 720-1, which includes applying a first challenge to a respective response structure to cause a first response of the respective response structure as a function of the first challenge. The linked challenge / response operation further includes a second challenge operation 720-2, which includes applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge.The linked challenge / response operation 720 further comprises a result determination operation 720-3 (also referred to as an output determination operation) comprising causing a result (also referred to as an output) representing a respective key element 730e of the key 730 corresponding to the respective response structure, the result being a function of I) the first challenge or the first response and II) the second challenge or the second response.

[0053] According to various aspects, the linked challenge / response operation 720 described herein includes that the output (e.g., based on the result of a comparison of the first challenge or the first response with the second challenge or the second response) of a response structure (illustratively the final response) in a PUF operation is a function of two challenge / response sub-operations that are linked together (e.g., referred to as a linked challenge / response operation).The two challenge / response suboperations can be applied to the same element of a response structure (in this case, the response structure can be implemented, for example, via a single response element) or, alternatively, the two challenge / response suboperations can be applied to two different response elements of the same response structure (in this case, the response structure can be implemented, for example, via two response elements).

[0054] The two challenge / response sub-operations may include a first sub-challenge / response operation and a second sub-challenge / response operation, wherein the first sub-challenge / response operation includes the first challenge and the first response, and the second sub-challenge / response operation includes the second challenge and the second response. According to various aspects, the first challenge may include a first challenge signal (CS1(t,CS1 max)) and the first response may comprise a first response signal (RS1(t,RS1 max )) which is triggered by the first challenge signal (CS1(t,CS1 max )) as a function of a first electrical property of the response structure. Furthermore, the second challenge may include a second challenge signal (CS2(t,CS2 max )) and the second response may be a second response signal (RS2(t,RS2 max )) which is triggered by the second challenge signal (CS2(t,CS2 max )) as a function of a second electrical property of the response structure that differs from the first electrical property of the response structure. According to various aspects, the first sub-challenge / response operation may comprise applying a first challenge signal (CS1(t,CS1 max )) and thereby causing a first response signal (RS1(t,RS1 max)) as a function of a first electrical property of the response structure. Furthermore, the second sub-challenge / response operation may comprise applying a second challenge signal (CS2(t,CS2 max )) and thereby causing a second response signal (RS2(t,RS2 max)) as a function of a second electrical property of the response structure that differs from the first electrical property of the response structure. According to various aspects, in the case that the response structure has a first response element and a second response element that differs from the first response element, the first electrical property of the response structure can be defined by the first response element and the second electrical property of the response structure can be defined by the second response element. According to various aspects, in the case that the response structure has only a single response element, the first electrical property of the response structure can be defined by a first I / V branch of the response element (e.g.the response element can in this case be a memristive multi-branch element) and the second electrical property of the response structure can be defined by a second I / V branch of the same response element (see, for example, branches 1 to 4 in . Fig. 2A to Fig. 2F).

[0055] According to various aspects, as in Fig. 7B in a schematic overview, the Physical Unclonable Function 700 can be configured to: • (in a first configuration 700-1) Providing a relationship (e.g., referred to as a connection) between the first challenge signal (CS1(t,CS1 max )) and the second challenge signal (CS2(t,CS2 max )) and determining the output based on a relationship between the first response signal (RS 1 (t,RS 1", aX )) and the second response signal (RS2(t,RS2 max )); or • (in a second configuration 700-2) providing a relationship (e.g., referred to as a connection) between the first challenge signal (CS1(t,CS1 max )) and the second response signal (RS2(t,RS2 max )) and determining the output based on a relationship between the first response signal (RS1(t,RS1 max )) and the second challenge signal (CS2(t,CS2 max )); or • (in a third configuration 700-3) providing a relationship (e.g., referred to as a connection) between the first response signal (RS1(t,RS1 max )) and the second challenge signal (CS2(t,CS2 max )) and determining the output based on a relationship between the first challenge signal (CS1(t,CS1 rnax )) and the second response signal (RS2(t,RS2 max )); or • (in a fourth configuration 700-4) providing a relationship (e.g., referred to as a connection) between the first response signal (RS1(t,RS1 max )) and the second response signal (RS2(t,RS2 max )) and determining the output based on a relationship between the first challenge signal (CS1(t,CS1 max )) and the second challenge signal (CS2(t,CS2 max )).

[0056] According to various aspects, the response structure may be an electrical response structure having one or more electrical response elements, and the electrical response structure may receive an electrical challenge signal and cause an electrical response signal based on characteristic electrical properties (referred to as I / V) of the electrical response structure. In some aspects, the electrical response structure may be a memristive structure having one or more memristive elements as the one or more response elements. For example, a memristive element may be selectively operated in two different ways, either current-driven or voltage-driven.In this case, the electrical response structure can selectively either receive a current signal as a challenge signal and cause a voltage signal as a response signal, or receive a voltage signal as a challenge signal and cause a current signal as a response signal. In the case where the memristive structure has more than one memristive element, the memristive structure can be configured, for example, to receive a current signal as a challenge signal and cause a current signal as a response signal, or receive a voltage signal as a challenge signal and cause a voltage signal as a response signal.

[0057] According to various aspects, the first challenge signal may be applied to a first response element of the response structure, and the second challenge signal may be applied (e.g., at a same time interval) to a second response element of the response structure to receive the first response signal and the second response signal in the same time interval and directly determine the output based on a comparison of I) the first challenge or the first response with II) the second challenge or the second response in the same time interval. In this configuration, there may be no need to store information for determining the output.However, in another configuration, the first challenge signal may be applied to a response element of the response structure in a first time interval, and the second challenge signal may be applied to the (exactly identical) response element of the response structure in a second time interval that differs from the first time interval, in order to receive the first response signal and the second response signal at different time intervals. Therefore, at least some data representing I) the first challenge or the first response and / or II) the second challenge or the second response must be stored for determining the output based on a comparison of I) the first challenge or the first response with II) the second challenge or the second response in the same time interval.

[0058] According to various aspects, in the case that the response structure is an electrical response structure as in Fig. 7C to Fig. 7F in a schematic view for each of the configurations 700-1, 700-2, 700-3, 700-4, the first challenge signal may be a first voltage signal (CV1(t,CV1 max )) and the first response signal can be a first current signal (RI1(t,RI1 max )); and the second challenge signal may be a second current signal (CI2(t,CI2 max )) and the second response signal can be a second voltage signal (RV2(t,RV2 max )). According to other aspects, in case the response structure is an electrical response structure, the first challenge signal may be a first current signal (CI1(t,CI1 max )) and the first response signal can be a first voltage signal (RV1(t,RV1 max )); and the second challenge signal may be a second voltage signal (CV2(t,CV2 max)) and the second response signal can be a second current signal (RI2(t,RI2 max )). According to other aspects, in case the response structure is an electrical response structure, the first challenge signal may be a first voltage signal (CV1(t,CV1 max )) and the first response signal can be a first current signal (RI1(t,RI1 max )); and the second challenge signal may be a second voltage signal (CV2(t,CV2 max )) and the second response signal can be a second current signal (RI2(t,RI2 max )). According to other aspects, in case the response structure is an electrical response structure, the first challenge signal may be a first current signal (CI1(t,CI1 max )) and the first response signal can be a first voltage signal (RV1(t,RV1 max )); and the second challenge signal may be a second current signal (CI21(t,CI2 max)) and the second response signal can be a second voltage signal (RV2(t,RV2 max )) be.

[0059] Fig. 8A to Fig. 8C shows a schematic circuit diagram of an electrical response structure 800 (e.g., a memristive structure) that enables the linking of two electrical signals in the hardware by using two electrical response elements 800e-1, 800e-2 (e.g., two memristive elements). As shown in Fig. As shown in Figure 8A, two current signals (I1(t,I1 max )), (I2(t,I2 max )) can be linked by a series connection of the electrical response elements 800e-1, 800e-2, since both electrical response elements 800e-1, 800e-2 see the same current provided by a current source. The respective voltage signals (V(t,V1 max )), (V2(t,V2 max)) can be determined for each of the two electrical response elements 800e-1, 800e-2 by a respective parallel connection of voltage determination means (e.g., by a voltmeter). As shown in Fig. As shown in Figure 8B, two voltage signals (V1(t,V1 max )), (V2(t,V2 max )) can be linked by a parallel connection of the electrical response elements 800e-1, 800e-2, since both electrical response elements 800e-1, 800e-2 see the same voltage provided by a voltage source. The respective current signals (I1(t,I1 max )), (I2(t,I2 max )) can be determined for each of the two electrical response elements 800e-1, 800e-2 by a respective series connection of current determining means (e.g., by an ammeter). As in Fig. 8C, a voltage signal (V2(t,V2 max )) and a current signal (I1(t,I1 max)) by using a resistor in addition to the two electrical response elements 800e-1, 800e-2, since a voltage drop (V2(t,V2 max )) across the resistance with the current (I1(t,I1 max )) provided by the current source through the first response element 800e-1, and therefore the voltage drop (V2(t,V2 max )) across the resistor can be used as a voltage source for the second response element 800e-2. The corresponding voltage signal (V1(t,V1 max )) can be determined for the first electrical response element 800e-1 by a respective parallel connection of voltage determination means (e.g. by a voltmeter) and the respective current signal (I2(t,I2 max)) can be determined for the second electrical response element 800e-2 by a respective series connection of current determining means (e.g., by an ammeter). According to various aspects, the resistor configured to detect the voltage signal (V2(t,V2 max )) and the current signal (I1(t,I1 max )) together, a nonlinear resistor, e.g. a memristor, may be used to increase the complexity of the electrical response structure.

[0060] Fig. 8D to Fig. 8E shows a schematic circuit diagram for determining the output of the response structure based on a comparison of I) the first challenge or the first response with II) the second challenge or the second response. As in Fig. As shown in Figure 8D, two voltage signals (V1(t,V1 max )), (V2(t,V2 max)) by any suitable voltage comparator 810, for example, an analog operational amplifier comparator circuit. In the case where the two voltage signals may have opposite polarity, a converting operational amplifier comparator circuit may be used for the comparison. The output V out the operational amplifier comparator circuit 810 may, for example, represent a logical state ("0" or "1", "high" or "low"), which may represent a respective key element 730e of the key 730 according to the respective response structure.

[0061] As in Fig. As shown in Figure 8E, two current signals (I1(t,I1 max )), (I2(t,I2 max )) by any suitable current comparator 820, for example, a CMOS current comparator circuit. The output of the suitable current comparator 820 may be either a voltage output V outor a current output I out and may, for example, represent a logical state ("0" or "1", "high" or "low"), which may represent a respective key element 730e of the key 730 according to the respective response structure. Alternatively, as in Fig. 8E, two current signals (I1(t,I1 max )), (I2(t,I2 max )) by any combination of current integrators 830 (e.g., an operational amplifier integrator) and a voltage comparator 810 coupled to the outputs of the current integrators 830. This allows a comparison of output voltages V1 out , V2 out , which determine the corresponding input currents (I1(t,I1 max )) and (I2(t,I2 max )) by a voltage comparator 810. The use of a current integrator 830 can also represent a comparison of a voltage signal (V(t,V max )) with a current signal (I(t,I max)) enable, as in Fig. 8F.

[0062] According to various aspects, the current signal (I(t,I max )) over a predefined time interval to cause a voltage that represents a dynamic behavior of the current signal (I(t,I max)) represents, increases the complexity of generating an output of the electrical response structure. Short integration times can be used to integrate quasi-static current signals. According to various aspects, a response of the electrical response structure can be determined dynamically, e.g., a dynamic measurement signal can be integrated over a predefined time interval to generate a final measurement result that represents the dynamic response of the electrical response structure caused by the dynamic measurement signal. According to various aspects, a response of the electrical response structure can be determined dynamically, e.g.,a dynamic challenge signal can be used to cause a dynamic response signal, and the dynamic response signal can be integrated over a predefined time interval to generate a final response result that represents the dynamic response of the electrical response structure caused by the dynamic challenge signal.

[0063] According to various aspects, the response structure may be configured as a memristive response structure (also referred to herein as a memristive structure) having one or more memristive response elements (also referred to herein as memristive elements). Fig. 9A and Fig. 9C show a schematic view of a current response (RI(t,RI max )) of a memristive element 900e, which is determined by a voltage-driven challenge (CV(t,CV max)) based on an I / V property (shown as a graphical representation of the current density on linear and logarithmic scales) of a memristive element, and Fig. 9B and Fig. 9D shows a schematic view of a voltage response (RV(t,RV max )) of a memristive element 900e, which is triggered by a current-driven challenge (CI(t,CI max )) based on an I / V characteristic (shown as a graphical representation of the current density on a linear and logarithmic scale) of a memristive element. Various aspects of an I / V characteristic of a memristive structure and a memristive element (e.g., memristive element 900e) are described above, for example, with reference to Fig. 1 to Fig. 5E explained.

[0064] According to various aspects, the current response RI caused by the voltage challenge CV can be calculated as exemplified in Fig. 9A, be defined by a point (I / V) in the I / V property. In this case, the current response is directly caused by the applied voltage challenge. According to various aspects, the voltage response RV caused by the current challenge CI can be determined as exemplified in Fig. 9B, be defined by a point (V / I) in the I / V property. In this case, the voltage response is directly caused by the applied current challenge.

[0065] According to various aspects, the current response RI caused by the voltage challenge CV can be calculated as exemplified in Fig. 9C, be defined by two different points C(I / V) and R(I / V) in the I / V property. In this case, the current response RI is indirectly caused by the applied voltage challenge CV, since the applied voltage challenge CV writes the memristive element 900e into a memristive state, and the current response RI is specific to the written memristive state. In this case, the voltage challenge CV may be a write voltage signal to write the memristive element 900e into a memristive state, and the current response RI may be a read current signal determined by a predefined read voltage V Lese applied to the memristive element 900e. According to various aspects, the voltage response RV caused by the current challenge CI may be determined as exemplified in Fig. 9D, be defined by two different points C(V / I) and R(V / I) in the I / V property. In this case, the voltage response RV is indirectly caused by the applied current challenge CI, since the applied current challenge CI writes the memristive element 900e into a memristive state, and the voltage response RV is specific to the written memristive state. In this case, the current challenge CI may be a write current signal to write the memristive element 900e into a memristive state, and the voltage response RV may be a read voltage signal determined by a predefined read current I Lese applied to the memristive element 900e.

[0066] Furthermore, as in Fig. 9E, Fig. 9F, Fig. 9G and Fig. 9H, an I / V property of a memristive element can have a positive write branch (1) and corresponding positive read branches (2) as well as a negative write branch (3) and corresponding negative read branches (4), see also Fig. 3A and Fig. 3B, where the I / V property of the positive branches differs from the I / V property of the negative branches. Therefore, two different challenge / response suboperations that are linked together can be performed via a single memristive element.

[0067] According to various aspects, a first sub-challenge / response operation may be executed in a first IV operation range (e.g., in a positive voltage and / or positive current range), and a second sub-challenge / response operation may be executed in a second IV operation range (e.g., in a negative voltage and / or negative current range). According to various aspects, a positive write branch (1) and one or more corresponding positive read branches (2) may be used to execute the first sub-challenge / response operation (with first challenge C1 and first response R1), and a negative write branch (3) and one or more corresponding negative read branches (4) may be used to execute the second sub-challenge / response operation (with second challenge C2 and second response R2).

[0068] According to various aspects, a first current response R1I caused by a first voltage challenge C1V may be determined as exemplified in Fig. 9E, may be defined by a first point 1(FV) in the I / V characteristic, and further, a second current response R2I caused by a second voltage challenge C2V may be defined by a second point 2(I / V) in the I / V characteristic of the same memristive element 900e. In this case, the respective current response is directly caused by the corresponding applied voltage challenge. According to various aspects, a first voltage response R1V caused by a first current challenge C1I may be defined, as exemplified in Fig. 9F, may be defined by a first point 1(V / I) in the I / V characteristic, and further, a second voltage response R2V caused by a second current challenge C2I may be defined by a second point 2(V / I) in the I / V characteristic of the same memristive element 900e. In this case, the respective voltage response is directly caused by the corresponding applied current challenge.

[0069] According to various aspects, a first current response R1I caused by a first voltage challenge C1V may be determined as exemplified in Fig. 9G, a second current response R2I caused by a second voltage challenge C2V may be defined by two other different points C2(I / V) and R2(I / V) in the I / V characteristic of the same memristive element 900e. In this case, the respective current response R1I, R2I is indirectly caused by the applied corresponding voltage challenge C1V, C2V, since the applied voltage challenge C1V, C2V writes the memristive element 900e to a respective memristive state, and the current response R1I, R2I is specific to the respective written memristive state. The first current response R1I is specific for the first memristive state and the second current response R2I is specific for the second memristive state.In this case, the first voltage challenge C1V may be a first write voltage signal for writing the memristive element 900e into a first memristive state, and the second voltage challenge C2V may be a second write voltage signal for writing the memristive element 900e into a second memristive state that differs from the first memristive state. The first current response R1I may be a first read current signal determined by a predefined first read voltage V1. Lese applied to the memristive element 900e, and the second current response R2I may be a second read current signal determined by a predefined second read voltage V2 Lese applied to the memristive element 900e.

[0070] According to various aspects, a first voltage response R1V caused by a first current challenge C1I may be determined as exemplified in Fig. 9H, a second voltage response R2V caused by a second current challenge C2I may be defined by two different points C2(V / I) and R2(V / I) in the I / V characteristic of the same memristive element 900e. In this case, the first voltage response R1V is indirectly caused by the applied first current challenge C1I, since the applied first current challenge C1I writes the memristive element 900e to a first memristive state, and the second voltage response R2V is indirectly caused by the applied second current challenge C2I, since the applied second current challenge C2I writes the memristive element 900e to a second memristive state that is different from the first memristive state.The first voltage response R1V is specific to the written first memristive state, and the second voltage response R2V is specific to the written second memristive state. In this case, the first current challenge C1I may be a first write current signal to write the memristive element 900e into a first memristive state, and the first voltage response R1V may be a first read voltage signal determined by a predefined first read current I1. Lese which is applied to the memristive element 900e, and the second current challenge C2I may be a second write current signal to write the memristive element 900e into a second memristive state, and the second voltage response R2V may be a second read voltage signal caused by a predefined second read current I2 Lese applied to the memristive element 900e.

[0071] According to various aspects, two different challenge / response sub-operations that are linked to each other can be executed via a single memristive element using different read / write branches. As exemplified in Fig. 9E to Fig. 9H, the different read / write branches may be located in regions of the I / V property with opposite polarities; however, in other aspects, the different read / write branches may be located in regions of the I / V property with the same polarity using different memristive states of the memristive element for the two different challenge / response sub-operations.

[0072] According to various aspects, the respective response structure can be configured such that the second challenge is defined by a comparison of the first response and the second response with each other. As one example only, the second challenge can be a controlled voltage signal (e.g., a voltage that increases over time), and the controlled voltage signal is deactivated or the voltage of the controlled voltage signal is kept constant from a point in time at which a comparison of the first response and the second response with each other meets a predefined requirement (e.g., the first response and the second response can be voltage signals with the same voltage, e.g., the first response and the second response can be current signals with the same current, e.g., the first response and the second response can be signals with a predefined relationship to each other).In this case, for example, the output representing the key element can be determined based on a comparison of the first challenge and the second challenge.

[0073] According to various aspects, the respective response structure can be configured such that the second challenge is defined by a comparison of the first challenge and the second response with each other. As one example only, the second challenge can be a controlled voltage signal (e.g., a voltage that increases over time), and the controlled voltage signal is deactivated or the voltage of the controlled voltage signal is kept constant from a point in time at which a comparison of the first challenge and the second response with each other satisfies a predefined requirement (e.g., the first challenge and the second response can be voltage signals with the same voltage, e.g., the first challenge and the second response can be current signals with the same current, e.g., the first challenge and the second response can be signals with a predefined relationship to each other).In this case, for example, the output representing the key element can be determined based on a comparison of the first response and the second challenge.

[0074] According to various aspects, the output representing the key element may be determined based on a comparison of signals (e.g., challenge signals and / or response signals, see, for example, Fig. 7A to Fig. 7F). According to various aspects, the comparison of signals can be any suitable comparison. As an example, two voltage signals can be compared by comparing the voltage values of the two voltage signals at the same time or at predefined times. As an example, two current signals can be compared by comparing the current values of the two current signals at the same time or at predefined times. As an example, a voltage signal and a current signal can be compared by comparing the voltage value of the voltage signal with the current value of the current signal (e.g., related to Ohm's law) at the same time or at predefined times. As an example, a voltage signal and a current signal can be compared by transforming the voltage signal into a transformed current signal that represents the voltage signal (e.g.,related to Ohm's law over a resistor) and current values are compared accordingly or by transforming the current signal into a transformed voltage signal that represents the current signal (e.g. related to Ohm's law over a resistor) and voltage values are compared accordingly.

[0075] Fig. 10 shows a schematic flow diagram of a method 1000 for generating a key based on a Physical Unclonable Function, the method comprising in 1010 generating a plurality of key elements of the key by operating each response structure of a plurality of response structures according to a linked challenge / response operation 1020.The linked challenge / response operation 1020 applied to a respective response structure of the plurality of response structures comprises, in 1022, applying a first challenge to the respective response structure to cause a first response of the respective response structure as a function of the first challenge; in 1024, applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge; and, in 1026, causing an output representing a key element of the plurality of key elements of the key corresponding to the respective response structure, the output being a function of the first challenge or the first response and the second challenge or the second response.

[0076] Fig. 11 shows a schematic flow diagram of a method 1100 for generating a key based on a Physical Unclonable Function, the method comprising in 1110 generating a first key element of the key by operating a first response structure according to a linked challenge / response operation and in 1120 generating a second key element of the key by operating a second response structure, which is different from the first response structure, according to the linked challenge / response operation.The linked challenge / response operation applied to the response structure comprises (see 1130) a first challenge / response sub-operation and a second challenge / response sub-operation, wherein the first challenge / response sub-operation comprises a first challenge to cause a first response by the response structure as a function of the first challenge; wherein the second challenge / response sub-operation comprises a second challenge to cause a second response by the response structure as a function of the second challenge; and wherein the linked challenge / response operation comprises an output determination operation to determine an output representing the key element of the key, wherein the output determination comprises a comparison of the first challenge or the first response with the second challenge or the second response.

[0077] According to various aspects, various aspects relate to a response structure in a challenge / response application of a PUF to effect a response of the respective response structure as a function of a challenge. The response structure may be any suitable entropy source (besides electrical response structures, various other types of response structures may be used, such as optical response structures and / or ring oscillators). For ring oscillator PUFs, the respective challenge may be a frequency, and the corresponding response may be the amplitude of the oscillation. For ring oscillator PUFs, the challenge and response cannot be interchanged, as is possible, for example, with memristor PUFs; in other words, the amplitude of the oscillation cannot be the challenge for the frequency as the response.For optical PUFs, the challenge can be the illumination of the PUF (e.g., a scattering medium), and the response can be the scattering intensity. For optical PUFs, the challenge and response cannot be interchanged, as is possible with memristor PUFs, for example; in other words, the scattering intensity cannot be a challenge for the PUF's illumination as a response.

[0078] According to various aspects, it may be advantageous from a security perspective that the response structure is a non-linear response structure and, more preferably, the response structure may be a transcendental response structure, such as can be realized with memristive response elements as described herein.

[0079] Fig. 12A to Fig. 12H show various aspects of an implementation of an electrical response structure 1200 in a schematic circuit diagram. For example, in a first configuration 1200-1, the electrical response structure 1200 may include only a single resistive element 1200e (e.g., a memristor), or in a second configuration 1200-2, the electrical response structure 1200 may include only two resistive elements 1200e (e.g., two memristors). It is understood that the configurations shown include a minimum number of resistive elements 1200e for the respective configuration, and an additional resistive element 1200e may be included in the electrical response structure 1200. According to various aspects, the resistive element 1200e may include a nonlinear resistor, such as a memristor.According to various aspects, the resistive element 1200e may comprise a nonlinear resistor having a transcendental nonlinear I / V characteristic, such as a memristor as described herein.

[0080] According to various aspects, the electrical response structure 1200 may include one or more current sources 1210 and / or one or more voltage sources 1220 to generate one or more electrical signals (e.g., one or more time-resolved current signals and / or one or more time-resolved voltage signals) for the one or more current challenges 1210c and / or the one or more voltage challenges 1220c. According to various aspects, the electrical response structure 1200 may include one or more current measurement entities 1230 (e.g., one or more ammeters) and / or one or more voltage measurement entities 1240 (e.g., one or more voltmeters) to generate one or more electrical signals (e.g.,one or more time-resolved current signals and / or one or more time-resolved voltage signals) representing the one or more current responses 1230r and / or the one or more voltage responses 1240r.

[0081] According to various aspects, the electrical response structure 1200 in the first configuration 1200-1 may be operated such that the second challenge is executed after the first challenge and after the first response is determined. In other words, the second challenge / response sub-operation may be executed after the first challenge / response sub-operation is completed. Therefore, in some aspects, a result of the determined first response may be stored to enable comparison with a result of the determined second response.

[0082] In other aspects, the electrical response structure 1200 in the first configuration 1200-1 may be operated such that the first challenge and the second challenge are executed alternately in steps. As an example, the first challenge and the second challenge may each comprise an electrical signal with a number of n voltage or current steps defining the respective time-dependent challenge, wherein the n voltage or current steps of the first challenge and the second challenge are executed alternately, and the corresponding first response and the corresponding second response are determined alternately for each of the n voltage or current steps. This enables a comparison of the desired current and / or voltage signals after each of the steps. This enables a comparison of the desired current and / or voltage values after each of the steps.

[0083] According to various aspects, the electrical response structure 1200 in the second configuration 1200-2 can be operated such that the first challenge and the second challenge are executed simultaneously, so that the first response and the second response can also be determined simultaneously. In other words, the second challenge / response sub-operation can be executed at the same time as the first challenge / response sub-operation. Therefore, in some aspects, a result of the determined first response can be compared to a result of the determined second response without storing data representing the respective results.

[0084] According to various aspects, the electrical response structure 1200 may be configured to link a first response (e.g., a current response) to a second challenge (e.g., a current challenge) and to determine an output of the electrical response structure 1200 representing a key element of a key based on a comparison of a first challenge (e.g., a voltage challenge) corresponding to the first response and a second response (e.g., a voltage response) corresponding to the second challenge, such as in Fig. 12A. In some aspects, the second challenge may be controlled based on the first response. The first response may be used to define the second challenge. In one example, the first response signal may be used directly as the second challenge signal.

[0085] According to various aspects, the electrical response structure 1200 may be configured to link a first challenge (e.g., a voltage challenge) to a second challenge (e.g., a voltage challenge) and to determine an output of the electrical response structure 1200 representing a key element of a key based on a comparison of a first response (e.g., a current response) corresponding to the first challenge and a second response (e.g., a current response) corresponding to the second challenge, such as in Fig. 12B. In some aspects, the first challenge and the second challenge may include the same challenge signal. According to various aspects, the challenge signal may be a predefined challenge signal.

[0086] According to various aspects, the electrical response structure 1200 may be configured to link a first response (e.g., a current response) to a second response (e.g., a current response) and to determine an output of the electrical response structure 1200 representing a key element of a key based on a comparison of a first challenge (e.g., a voltage challenge) corresponding to the first response and a second challenge (e.g., a voltage challenge) corresponding to the second response, such as in Fig. 12C. In some aspects, at least one of the first challenge and / or the second challenge may be controlled based on a predefined relationship between the first response and the second response (e.g., the first challenge and / or the second challenge may stop at a present voltage value if a predefined relationship between the first response and the second response is satisfied). The first challenge and / or the second challenge may be controlled via a closed-loop control, wherein the closed-loop control is configured to achieve a predefined relationship between the first response and the second response by controlling the first challenge and / or the second challenge.

[0087] According to various aspects, the electrical response structure 1200 may be configured to link a first challenge (e.g., a voltage challenge) to a second response (e.g., a voltage response) and to determine an output of the electrical response structure 1200 representing a key element of a key based on a comparison of a first response (e.g., a current response) corresponding to the first challenge and a second challenge (e.g., a current challenge) corresponding to the second response, such as in Fig. 12D. In some aspects, the first challenge may be controlled based on the second response (e.g., the first challenge may stop at a given voltage value if the second response reaches a predefined voltage value).

[0088] According to various aspects, the electrical response structure 1200 may be configured to link a first challenge (e.g., a current challenge) to a second challenge (e.g., a current challenge) and to determine an output of the electrical response structure 1200 representing a key element of a key based on a comparison of a first response (e.g., a voltage response) corresponding to the first challenge and a second response (e.g., a voltage response) corresponding to the second challenge, such as in Fig. 12E. In some aspects, the first challenge and the second challenge may include the same challenge signal. According to various aspects, the challenge signal may be a predefined challenge signal.

[0089] According to various aspects, the electrical response structure 1200 may be configured to link a first response (e.g., a voltage response) to a second challenge (e.g., a voltage challenge) and to determine an output of the electrical response structure 1200 representing a key element of a key based on a comparison of a first challenge (e.g., a current challenge) corresponding to the first response and a second response (e.g., a current response) corresponding to the second challenge, such as in Fig. 12F. In some aspects, the second challenge may be controlled based on the first response. The first response may be used to define the second challenge. In one example, the first response signal may be used directly as the second challenge signal.

[0090] According to various aspects, the electrical response structure 1200 may be configured to link a first challenge (e.g., a current challenge) to a second response (e.g., a current response) and to determine an output of the electrical response structure 1200 representing a key element of a key based on a comparison of a first response (e.g., a voltage response) corresponding to the first challenge and a second challenge (e.g., a voltage challenge) corresponding to the second response, such as in Fig. 12G. In some aspects, the first challenge may be controlled based on the second response (e.g., the first challenge may stop at a given current value if the second response reaches a predefined current value).

[0091] According to various aspects, the electrical response structure 1200 may be configured to link a first response (e.g., a voltage response) to a second response (e.g., a voltage response) and to determine an output of the electrical response structure 1200 representing a key element of a key based on a comparison of a first challenge (e.g., a current challenge) corresponding to the first response and a second challenge (e.g., a current challenge) corresponding to the second response, such as in Fig. 12H. In some aspects, at least one of the first challenge and / or the second challenge may be controlled based on a predefined relationship between the first response and the second response (e.g., the first challenge and / or the second challenge may stop at a present current value if a predefined relationship between the first response and the second response is satisfied). The first challenge and / or the second challenge may be controlled via a closed-loop control, wherein the closed-loop control is configured to achieve a predefined relationship between the first response and the second response by controlling the first challenge and / or the second challenge.

[0092] Fig. 13A shows two current / voltage timing diagrams 1300a of a linked challenge / response operation according to various aspects for operating a response structure associated with a first response state 1300-1 and a second response state 1300-2. As an example only, the first challenge / response sub-operation may include a first challenge and a first response, in this exemplary case, a first current challenge 1310c-1 and a first voltage response 1340r-1 (see, for example, the current challenge 1210c and the voltage response 1240r in Fig. 12A to Fig. 12H); and the second challenge / response sub-operation may include a second challenge and a second response, in this exemplary case a second current challenge 1310c-2 and a second voltage response 1340r-2 (see, for example, the current challenge 1210c and the voltage response 1240r in Fig. 12A to Fig. 12H). In some aspects, a comparison of the first voltage response 1340r-1 and the second voltage response 1340r-2 with each other may enable identification of a response state 1300-1, 1300-2 (e.g., representing a key element such as a "0" or "1" of a binary key) of the response structure.As an example, in the case that a voltage value of the first voltage response 1340r-1 at the end (after completion) of the first current challenge 1310c-1 is greater than a voltage value of the second voltage response 1340r-2 at the end of the second current challenge 1310c-2, it may be determined that the response structure is in the first response state 1300-1 (the key element may be determined as "0", for example); and in the event that a voltage value of the first voltage response 1340r-1 at the end of the first current challenge 1310c-1 is smaller than a voltage value of the second voltage response 1340r-2 at the end of the second current challenge 1310c-2, it can be determined that the response structure is in the second response state 1300-2 (the key element can be determined as "1", for example).It is noted that other or similar comparison schemes may be used to determine the output of the response structure caused by a respective input and based on the associated challenge / response operation as described herein.

[0093] As exemplified in Fig. 13A, the respective response signals may be present at the same time, e.g., in the same time interval beginning with the start of the two challenges and ending with the end of the two challenges. In this case, a comparison of a voltage value or current value of the respective challenge and / or response signals may be possible at any time within the time interval, e.g., at the end of the time interval or before the end of the two challenges. In the case that data representing the challenge and / or response signals are stored, or in the case that voltage and / or current values of the challenge and / or response signals can be stored in hardware (e.g.,for a time longer than the time interval in which the first challenge is executed), the comparison of a voltage and / or current value of the respective challenge and / or response signals can be performed at any time, and the first challenge / response sub-operation can be performed time-independently before and / or while the second challenge / response sub-operation is performed.

[0094] Fig. 13B shows two current / voltage timing diagrams 1300b of a linked challenge / response operation according to various aspects for operating a response structure associated with a first response state 1300-1 and a second response state 1300-2, wherein the first challenge / response sub-operation is executed before the second challenge / response sub-operation is executed. As an example only, the first challenge / response sub-operation may include a first challenge and a first response, in this exemplary case, a first current challenge 1310c-1 and a first voltage response 1340r-1 (see, for example, the current challenge 1210c and the voltage response 1240r in Fig. 12A to Fig. 12H) executed in a first time interval T1; and the second challenge / response sub-operation may comprise a second challenge and a second response, in this exemplary case a second current challenge 1310c-2 and a second voltage response 1340r-2 (cf., for example, the current challenge 1210c and the voltage response 1240r in Fig. 12A to Fig. 12H), which are executed in a second time interval T2 after the first time interval T1. A comparison of the first voltage response 1340r-1 and the second voltage response 1340r-2 with each other may allow identifying a response state 1300-1, 1300-2 (e.g., representing a key element such as a "0" or "1" of a binary key) of the response structure as described above.

[0095] According to various aspects, instead of comparing a voltage or current value of the respective response signals, it may be useful to compare a time integral over a predefined time interval. A time integral may be more sensitive to variations in the respective response signals.

[0096] Fig. 13C shows two current / voltage timing diagrams 1300b of a linked challenge / response operation according to various aspects for operating a response structure associated with a first response state 1300-1 and a second response state 1300-2, wherein the first challenge is executed for a predefined time T and wherein the second challenge is executed for a variable time t (e.g., t1 and t2) as a function of a comparison of the first response and the second response with each other. As an example, the second challenge is stopped at a time t1, t2 as soon as the first response and the second response are in a predefined relationship to each other (e.g., as soon as the voltage value of the first voltage response 1340r-1 is equal to the voltage value of the second voltage response 1340r-2).As another example, the time t2 of the second challenge is determined as soon as the first response and the second response are in a predefined relationship to each other (e.g., as soon as the voltage value of the first voltage response 1340r-1 is equal to the voltage value of the second voltage response 1340r-2).

[0097] In the case that the time t1, t2 of the second challenge is determined, the time t1, t2 can be compared with a reference time tc to determine a response state 1300-1, 1300-2 (e.g., representing a key element such as a "0" or "1" of a binary key) of the response structure as described above. In the case that the time t1, t2 is greater than the reference time tc, it can be determined that the response state is the first response state 1300-1, and in the case that the time t1, t2 is less than the reference time tc, it can be determined that the response state is the second response state 1300-2, as exemplified in Fig. 13C.

[0098] Various aspects include comparing one or more challenges and / or one or more responses to determine an output of the response structure. The output of the response structure may represent the secret (e.g., a key element) stored in the inherent properties of the response structure. According to various aspects, the comparison may include any suitable type of comparison, e.g., a greater than comparison, a less than comparison, and / or an equal to comparison using the respective signals. In some aspects, the comparison may be based on a mathematical (e.g., arithmetic and / or logical) function that concatenates a first comparison value and a second comparison value.For an arithmetic function, the order in the addition / subtraction of the two response functions can be relevant, so that the arithmetic addition / subtraction operation can also return a number greater than zero (decision criterion for "0" or "1"). For an arithmetic function, the numerator / denominator assignment in the multiplication / division of the two response functions can be relevant, so that the arithmetic multiplication / division operation can also return a number with an absolute value greater than one (decision criterion for "0" or "1"). For a logical function, the input can depend on the applied sequence. As an example, a logical "1" can be assigned to a first comparison value (e.g., the larger value) and a logical "zero" can be assigned to a second comparison value (e.g., the smaller value), and the output of the logical comparison (e.g.,one or more of the possible 16 Boolean functions) can represent the secret (e.g. a logical “0” or a logical “1”).

[0099] Various examples are provided below, which may include one or more aspects described above with reference to a physical unclonable function and / or to a method for generating a key based on a physical unclonable function as described herein.

[0100] Example 1 is a method for generating a key based on a physical unclonable function, the method comprising: generating a plurality of key elements of the key by operating each response structure of a plurality of response structures according to a linked challenge / response operation.The linked challenge / response operation applied to a respective response structure of the plurality of response structures comprises: applying a first challenge to the respective response structure (any suitable entropy source, preferably a non-linear response structure, more preferably a transcendental response structure) to cause a first response of the respective response structure as a function of the first challenge; applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge; and causing an output representing a key element of the plurality of key elements of the key corresponding to the respective response structure, wherein the output is a function of i) the first challenge or the first response and ii) the second challenge or the second response.

[0101] In Example 2, the method according to Example 1 can optionally further comprise that the second challenge and the first challenge are linked to each other in a predefined relationship; or that the second challenge and the first response are linked to each other in a predefined relationship; or that the second response and the first challenge are linked to each other in a predefined relationship; or that the second response and the first response are linked to each other in a predefined relationship.

[0102] In Example 3, the method according to Example 1 may optionally further comprise that the respective response structure is configured such that the first response defines the second challenge, and that the output representing the key element is determined based on a comparison of the first challenge and the second response with each other.

[0103] In Example 4, the method according to Example 1 may optionally further comprise that the respective response structure is configured such that the first challenge has a fixed relationship to the second challenge, and that the output representing the key element is determined based on a comparison of the first response and the second response with each other.

[0104] In Example 5, the method according to Example 1 may optionally further comprise that the respective response structure is configured such that the second challenge is defined by a comparison of the first response and the second response with each other, and that the output representing the key element is determined based on a comparison of the first challenge and the second challenge with each other.

[0105] In Example 6, the method according to Example 1 may optionally further comprise that the respective response structure is configured such that the second challenge is defined by a comparison of the first challenge and the second response with each other, and that the output representing the key element is determined based on a comparison of the first response and the second challenge with each other.

[0106] In Example 7, the method according to any one of Examples 1 to 6 may optionally further comprise that the physical unclonable function is a hardware entity that operates based on the linked challenge / response operation based on a feedback-based determination of a challenge point at which a comparison condition is met or based on a comparison of responses at predefined challenge points.

[0107] In Example 8, the method according to any one of Examples 1 to 7 may optionally further comprise that the respective response structure is a respective electrical response structure having an electrical property.

[0108] In Example 9, the method according to any one of Examples 1 to 8 can optionally further comprise that the first challenge is based on a first time-dependent voltage signal (V(t)) or a first time-dependent current signal (I(t)); and / or that the second challenge is based on a second time-dependent voltage signal (V(t)) or a second time-dependent current signal (I(t)).

[0109] In Example 10, the method according to any one of Examples 8 or 9 can optionally further comprise that the first challenge is based on a first maximum voltage (Vmax) of a first time-dependent voltage signal (V(t)) or on a first maximum current (Imax) of a first time-dependent current signal (I(t)); and / or that the second challenge is based on a second maximum voltage (Vmax) of a second time-dependent voltage signal (V(t)) or on a second maximum current (Imax) of a second time-dependent current signal (I(t)).

[0110] In Example 11, the method according to any one of Examples 8 to 10 may optionally further comprise that the first challenge comprises applying a first challenge signal (CS1(t,CS1 max )); that the first response comprises a first response signal (RS1(t,RS1 max )) which is triggered by the first challenge signal (CS1(t,CS1 max)) as a function of a first electrical property of the respective response structure; that the second challenge comprises applying a second challenge signal (CS2(t,CS2 max )); and that the second response comprises a second response signal (RS2(t,RS2 max )) which is triggered by the second challenge signal (CS2(t,CS2 max )) is effected as a function of a second electrical property of the respective response structure which differs from the first electrical property of the respective response structure.

[0111] In Example 12, the method according to Example 11 can optionally further comprise that the first challenge signal comprises a first voltage signal (CV1(t,CV1 max )); that the first response signal comprises a first current signal (RI1(t,RI1 max )); that the second challenge signal comprises a second current signal (CI2(t,CI2 max)); and that the second response signal comprises a second voltage signal (RV2(t,RV2 max )).

[0112] In Example 13, the method according to Example 11 can optionally further comprise that the first challenge signal comprises a first current signal (CI1(t,CI1 max )); that the first response signal comprises a first voltage signal (RV1(t,RV1 max )); that the second challenge signal comprises a second voltage signal (CV2(t,CV2 max )); and that the second response signal comprises a second current signal (RI2(t,RI2 max )).

[0113] In Example 14, the method according to Example 11 can optionally further comprise that the first challenge signal comprises a first voltage signal (CV1(t,CV1 max )); that the first response signal comprises a first current signal (RI1(t,RI1 max )); that the second challenge signal comprises a second voltage signal (CV2(t,CV2 max)); and that the second response signal comprises a second current signal (RI2(t,RI2 max )).

[0114] In Example 15, the method according to Example 11 may optionally further comprise that the first challenge signal comprises a first current signal (CI1(t,CI1 max )); that the first response signal comprises a first voltage signal (RV1(t,RV1m ax )); that the second challenge signal comprises a second current signal (CI21(t,CI2 max )); and that the second response signal comprises a second voltage signal (RV2(t,RV2 max )).

[0115] In Example 16, the method according to any one of Examples 11 to 15 can optionally further comprise that the physical unclonable function is configured to provide a relationship between the first challenge signal and the second challenge signal and determine the output based on a relationship between the first response signal and the second response signal; or that the physical unclonable function is configured to provide a relationship between the first challenge signal and the second response signal and determine the output based on a relationship between the first response signal and the second challenge signal; or that the physical unclonable function is configured to provide a relationship between the first response signal and the second challenge signal and determine the output based on a relationship between the first challenge signal and the second response signal;or that the Physical Unclonable Function is configured to provide a relationship between the first response signal and the second response signal and to determine the output based on a relationship between the first challenge signal and the second challenge signal.;

[0116] In Example 17, the method according to any one of Examples 11 to 16 may optionally further comprise that the respective response structure comprises a memristive structure having an electrical property, wherein the electrical property of the memristive structure has a branch set with one or more different read branches and one or more different write branches, and wherein the first electrical property is associated with one branch of the branch set and wherein the second electrical property is associated with another branch of the branch set.

[0117] In Example 18, the method of Example 17 can optionally further comprise each of the one or more different read branches having an electrical property as a function of a corresponding applied write signal.

[0118] In Example 19, the method of Example 18 may optionally further comprise that an amplitude of the write signal defines the electrical property.

[0119] In Example 20, the method according to any one of Examples 17 to 19 can optionally further comprise that a positive read branch of the one or more different read branches has an electrical property as a function of a corresponding applied positive write signal, wherein preferably a positive amplitude of the write signal defines the electrical property of the positive read branch; and / or that a negative read branch of the one or more different read branches has an electrical property as a function of a corresponding applied negative write signal, wherein preferably a negative amplitude of the write signal defines the electrical property of the negative read branch.

[0120] In Example 21, the method of any of Examples 17 to 20 can optionally further comprise each of the one or more different write branches having an electrical property as a function of a time-dependent write signal.

[0121] In Example 22, the method according to Example 21 can optionally further comprise that a positive write branch of the one or more different write branches has an electrical property as a function of a corresponding applied positive write signal, wherein preferably a time dependence of the positive write signal defines the electrical property of the positive write branch; and / or that a negative write branch of the one or more different write branches has an electrical property as a function of a corresponding applied negative write signal, wherein preferably a time dependence of the negative write signal defines the electrical property of the negative write branch.

[0122] In Example 23, the method according to any one of Examples 19 to 22 can optionally further comprise that the write signal includes an initialization signal before a setting signal, wherein the setting signal is configured to bring the memristive structure from an initial state defined by the initialization signal to a written state defined by both the initialization signal and the setting signal.

[0123] In Example 24, the method according to any one of Examples 19 to 23 can optionally further comprise that the first electrical property is associated with a read branch of the branch set, and wherein the second electrical property is associated with another read branch of the branch set; or that the first electrical property is associated with a read branch of the branch set, and wherein the second electrical property is associated with a write branch of the branch set; or that the first electrical property is associated with a write branch of the branch set, and wherein the second electrical property is associated with another write branch of the branch set; or that the first electrical property is associated with a write branch of the branch set, and wherein the second electrical property is associated with a read branch of the branch set.

[0124] In Example 25, the method according to any one of Examples 1 to 24 can optionally further comprise that the output is based on a comparison of a first comparison value and a second comparison value, wherein the first comparison value is a representation of a property of the first challenge or the first response and wherein the second comparison value is a representation of a property of the second challenge or the second response.

[0125] In Example 26, the method of Example 25 can optionally further comprise that the comparison includes a comparison greater than a comparison and / or a comparison less than a comparison and / or a comparison equal to a comparison; or that the comparison is based on a mathematical (e.g., arithmetic and / or logical) function that links the first comparison value and the second comparison value.

[0126] In Example 25, the method according to any one of Examples 1 to 26 can optionally further comprise that the response structure includes a memristive structure with a memristive element, and wherein the first challenge / response and the second challenge / response are applied to the memristive element; preferably wherein the first comparison value is obtained from the memristive element before the second comparison value is obtained from the memristive element and is stored in an analog memory or in a digital memory for comparison with the second comparison value.

[0127] In Example 28, the method according to any one of Examples 1 to 27 can optionally further comprise that the memristive structure includes a memristive structure having a first memristive element and a second memristive element, and wherein the first challenge / response is applied to the first memristive element and the second challenge / response is applied to the second memristive element; preferably wherein the first comparison value is obtained from the first memristive element and the second comparison value is obtained from the second memristive element at the same time to compare the first comparison value and the second comparison value with each other.

[0128] In Example 29, the method of any of Examples 1 to 28 can optionally further comprise executing the first challenge for a predefined time to define a reference value based on the first response; executing the second challenge for a variable time as a function of comparing the second response with the reference value; and determining the output based on determining the variable time.

[0129] Example 30 is a method for generating a key based on a physical unclonable function, the method comprising: generating a key element of the key by operating a response structure according to a linked challenge / response operation, wherein the linked challenge / response operation applied to the response structure comprises a first challenge / response sub-operation and a second challenge / response sub-operation, wherein the first challenge / response sub-operation comprises a first challenge to cause a first response by the response structure as a function of the first challenge; wherein the second challenge / response sub-operation comprises a second challenge to cause a second response by the response structure as a function of the second challenge;and wherein the linked challenge / response operation comprises an output determination operation to determine an output representing the key element of the key, wherein the output determination comprises a comparison of I) the first challenge or the first response with II) the second challenge or the second response. According to various aspects, any of examples 2 to 29 may be applied accordingly to method 30.

[0130] Example 31 is a physical unclonable function for generating a key, the physical unclonable function comprising: one or more response structures; and a controller configured to generate the key by operating each of the one or more response structures according to a linked challenge / response operation, the linked challenge / response operation applied to a respective one of the one or more response structures comprising a first challenge / response sub-operation and a second challenge / response sub-operation, the first challenge / response sub-operation comprising a first challenge to cause a first response by the respective response structure as a function of the first challenge;wherein the second challenge / response sub-operation comprises a second challenge to effect a second response by the respective response structure as a function of the second challenge; and wherein the linked challenge / response operation comprises an output determination operation to determine an output representing a key element of the key, the output determination comprising a comparison of I) the first challenge or the first response with II) the second challenge or the second response.

[0131] In Example 32, the physical unclonable function according to Example 31 can optionally further comprise that the second challenge and the first challenge are linked to each other in a predefined relationship; or that the second challenge and the first response are linked to each other in a predefined relationship; or that the second response and the first challenge are linked to each other in a predefined relationship; or that the second response and the first response are linked to each other in a predefined relationship.

[0132] In Example 33, the physical unclonable function according to Example 31 can optionally further comprise that the respective response structure is configured such that the first response defines the second challenge, and that the output representing the key element is determined based on a comparison of the first challenge and the second response with each other.

[0133] In Example 34, the physical unclonable function according to Example 31 can optionally further comprise that the respective response structure is configured such that the first challenge has a fixed relationship to the second challenge, and that the output representing the key element is determined based on a comparison of the first response and the second response with each other.

[0134] In Example 35, the physical unclonable function according to Example 31 can optionally further comprise that the respective response structure is configured such that the second challenge is defined by a comparison of the first response and the second response with each other, and that the output representing the key element is determined based on a comparison of the first challenge and the second challenge with each other.

[0135] In Example 36, the physical unclonable function according to Example 31 can optionally further comprise that the respective response structure is configured such that the second challenge is defined by comparing the first challenge and the second response with each other, and that the output representing the key element is determined based on comparing the first response and the second challenge with each other.

[0136] In Example 37, the physical unclonable function according to any one of Examples 31 to 36 can optionally further comprise that the physical unclonable function is a hardware entity that operates based on the linked challenge / response operation based on a feedback-based determination of a challenge point at which a comparison condition is met or based on a comparison of responses at predefined challenge points.

[0137] In Example 38, the physical unclonable function according to any one of Examples 31 to 37 can optionally further comprise that the respective response structure is a respective electrical response structure having an electrical property.

[0138] In Example 39, the physical unclonable function according to Example 38 can optionally further comprise that the first challenge comprises a first time-dependent voltage signal (V(t)) or a first time-dependent current signal (I(t)); and / or that the second challenge comprises a second time-dependent voltage signal (V(t)) or a second time-dependent current signal (I(t)).

[0139] In Example 40, the physical unclonable function according to any one of Examples 38 or 39 can optionally further comprise that the first challenge is defined by a first maximum voltage (Vmax) of a first time-dependent voltage signal (V(t)) or on a first maximum current (Imax) of a first time-dependent current signal (I(t)); and / or that the second challenge is defined by a second maximum voltage (Vmax) of a second time-dependent voltage signal (V(t)) or on a second maximum current (Imax) of a second time-dependent current signal (I(t)).

[0140] In Example 41, the physical unclonable function according to any one of Examples 38 to 40 can optionally further comprise that the first challenge comprises a first challenge signal (CS1(t,CS1 max )); that the first response comprises a first response signal (RS1(t,RS1 max )) which is triggered by the first challenge signal (CS1(t,CS1 max)) is caused as a function of a first electrical property of the respective response structure; that the second challenge generates a second challenge signal (CS2(t,CS2 max )); and that the second response comprises a second response signal (RS2(t,RS2 max )) which is triggered by the second challenge signal (CS2(t,CS2 max )) is caused as a function of a second electrical property of the respective response structure which differs from the first electrical property of the respective response structure.

[0141] In Example 42, the physical unclonable function according to Example 41 can optionally further comprise that the first challenge signal comprises a first voltage signal (CV1(t,CV1 max )); that the first response signal comprises a first current signal (RI1(t,RI1 max )); that the second challenge signal comprises a second current signal (CI2(t,CI2 max)); and that the second response signal comprises a second voltage signal (RV2(t,RV2 max )).

[0142] In Example 43, the physical unclonable function according to Example 41 can optionally further comprise that the first challenge signal comprises a first current signal (CI1(t,CI1 max )); that the first response signal comprises a first voltage signal (RV1(t,RV1 max )); that the second challenge signal comprises a second voltage signal (CV2(t,CV2 max )); and that the second response signal comprises a second current signal (RI2(t,RI2 max )).

[0143] In Example 44, the physical unclonable function according to Example 41 can optionally further comprise that the first challenge signal comprises a first voltage signal (CV1(t,CV1 max )); that the first response signal comprises a first current signal (RI1(t,RI1 max )); that the second challenge signal comprises a second voltage signal (CV2(t,CV2max )); and that the second response signal comprises a second current signal (RI2(t,RI2 max )).

[0144] In Example 45, the physical unclonable function according to Example 41 can optionally further comprise that the first challenge signal comprises a first current signal (CI1(t,CI1 max )); that the first response signal comprises a first voltage signal (RV1(t,RV1 max )); that the second challenge signal comprises a second current signal (CI21(t,CI2 max )); and that the second response signal comprises a second voltage signal (RV2(t,RV2 max )).

[0145] In Example 46, the physical unclonable function according to any one of Examples 41 to 45 can optionally further comprise that the physical unclonable function is configured to provide a relationship between the first challenge signal and the second challenge signal and determine the output based on a relationship between the first response signal and the second response signal; or that the physical unclonable function is configured to provide a relationship between the first challenge signal and the second response signal and determine the output based on a relationship between the first response signal and the second challenge signal; or that the physical unclonable function is configured to provide a relationship between the first response signal and the second challenge signal and determine the output based on a relationship between the first challenge signal and the second response signal;or that the physical unclonable function is configured to provide a relationship between the first response signal and the second response signal and to determine the output based on a relationship between the first challenge signal and the second challenge signal;

[0146] In Example 47, the physical unclonable function according to any one of Examples 41 to 46 can optionally further comprise that the respective response structure comprises a memristive structure with an electrical property, wherein the electrical property of the memristive structure has a branch set with one or more different read branches and one or more different write branches, and wherein the first electrical property is associated with one branch of the branch set and wherein the second electrical property is associated with another branch of the branch set.

[0147] In Example 48, the physical unclonable function of Example 47 can optionally further comprise each of the one or more different read branches having an electrical property as a function of a corresponding applied write signal.

[0148] In Example 49, the physical unclonable function according to Example 47 or 48 can optionally further comprise that an amplitude of the write signal defines the electrical property.

[0149] In Example 50, the physical unclonable function according to any one of Examples 47 to 49 can optionally further comprise that a positive read branch of the one or more different read branches has an electrical property as a function of a corresponding applied positive write signal, preferably wherein a positive amplitude of the write signal defines the electrical property of the positive read branch; and / or that a negative read branch of the one or more different read branches has an electrical property as a function of a corresponding applied negative write signal, preferably wherein a negative amplitude of the write signal defines the electrical property of the negative read branch.

[0150] In Example 51, the physical unclonable function according to any one of Examples 47 to 50 can optionally further comprise each of the one or more different write branches having an electrical property as a function of a time-dependent write signal.

[0151] In Example 52, the physical unclonable function according to Example 51 can optionally further comprise that a positive write branch of the one or more different write branches has an electrical property as a function of a corresponding applied positive write signal, preferably wherein a time dependence of the positive write signal defines the electrical property of the positive write branch; and / or that a negative write branch of the one or more different write branches has an electrical property as a function of a corresponding applied negative write signal, preferably wherein a time dependence of the negative write signal defines the electrical property of the negative write branch.

[0152] In Example 53, the physical unclonable function according to any one of Examples 49 to 52 can optionally further comprise that the write signal includes an initialization signal before a setting signal, wherein the setting signal is configured to bring the memristive structure from an initial state defined by the initialization signal to a written state defined by both the initialization signal and the setting signal.

[0153] In Example 54, the physical unclonable function according to any one of Examples 49 to 53 can optionally further comprise that the first electrical property is associated with a read branch of the branch set, and wherein the second electrical property is associated with another read branch of the branch set; or that the first electrical property is associated with a read branch of the branch set, and wherein the second electrical property is associated with a write branch of the branch set; or that the first electrical property is associated with a write branch of the branch set, and wherein the second electrical property is associated with another write branch of the branch set; or that the first electrical property is associated with a write branch of the branch set, and wherein the second electrical property is associated with a read branch of the branch set.

[0154] In Example 55, the physical unclonable function according to any one of Examples 31 to 54 can optionally further comprise that the output is based on a comparison of a first comparison value and a second comparison value, wherein the first comparison value is a representation of a property of the first challenge or the first response and wherein the second comparison value is a representation of a property of the second challenge or the second response.

[0155] In Example 56, the physical unclonable function of Example 55 can optionally further comprise that the comparison includes a comparison greater than a comparison and / or a comparison less than a comparison and / or a comparison equal to a comparison; or that the comparison is based on a mathematical function that relates the first comparison value and the second comparison value.

[0156] In Example 57, the physical unclonable function according to any one of Examples 31 to 56 can optionally further comprise that the response structure includes a memristive structure with a memristive element, and wherein the first challenge / response and the second challenge / response are applied to the memristive element; preferably, wherein the first comparison value is obtained from the memristive element before the second comparison value is obtained from the memristive element and is stored in an analog memory or in a digital memory for comparison with the second comparison value.

[0157] In Example 58, the physical unclonable function according to any one of Examples 31 to 56 can optionally further comprise that the memristive structure includes a memristive structure having a first memristive element and a second memristive element, and wherein the first challenge / response is applied to the first memristive element and the second challenge / response is applied to the second memristive element; preferably, wherein the first comparison value is obtained from the first memristive element and the second comparison value is obtained from the second memristive element at the same time to compare the first comparison value and the second comparison value with each other.

[0158] In Example 59, the physical unclonable function according to any one of Examples 31 to 56 can optionally further comprise that the first challenge is executed for a predefined time to define a reference value based on the first response; and that the second challenge is executed for a variable time as a function of a comparison of the second response with the reference value; and that the output is determined based on a determination of the variable time.

[0159] According to various aspects, any of Examples 2 to 29 may be applied accordingly to the physical unclonable function of Examples 31 to 59. Any of the aspects described herein with reference to the method for generating a key based on a physical unclonable function may be implemented in the physical unclonable function described herein, e.g., realized by a controller included in the physical unclonable function or connected to the physical unclonable function.

[0160] Although the invention has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

[1] A method for generating a key based on a Physical Unclonable Function, the method comprising: Generating a plurality of key elements of the key by operating each response structure of a plurality of response structures according to a linked challenge / response operation, the linked challenge / response operation applied to a respective response structure of the plurality of response structures comprising: applying a first challenge to the respective response structure to cause a first response of the respective response structure as a function of the first challenge; Applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge; and Causing an output representing a key element of the plurality of key elements of the key corresponding to the respective response structure, the output comprising a function I) the first challenge or the first response and II) the second challenge or the second response. [2] Method according to claim 1, where the second challenge and the first challenge are linked in a predefined relationship; or where the second challenge and the first response are linked in a predefined relationship; or where the second response and the first challenge are linked in a predefined relationship; or where the second response and the first response are linked in a predefined relationship. [3] Method according to claim 1, where the respective response structure is configured so that the first response defines the second challenge, and where the output representing the key element is determined based on a comparison of the first challenge and the second response. [4] Method according to claim 1, wherein the respective response structure is configured such that the first challenge has a fixed relationship to the second challenge, and wherein the output representing the key element is determined based on a comparison of the first response and the second response. [5] Method according to claim 1, wherein the respective response structure is configured such that the second challenge is defined by a comparison of the first response and the second response with each other, and wherein the output representing the key element is determined based on a comparison of the first challenge and the second challenge. [6] Method according to claim 1, wherein the respective response structure is configured such that the second challenge is defined by a comparison of the first challenge and the second response, and where the output representing the key element is determined based on a comparison of the first response and the second challenge. [7] The method of any one of claims 1 to 6, wherein the physical unclonable function is a hardware entity that operates based on the linked challenge / response operation based on a feedback-based determination of a challenge point at which a comparison condition is met or based on a comparison of responses at predefined challenge points. [8] Method according to one of claims 1 to 7, wherein the respective response structure is a respective electrical response structure having an electrical property. [9] Method according to claim 8, wherein the first challenge is based on a first time-dependent voltage signal (V(t)) or a first time-dependent current signal (I(t)); and / or wherein the second challenge is based on a second time-dependent voltage signal (V(t)) or a second time-dependent current signal (I(t)). [10] Method according to claim 8 or 9, where the first challenge involves applying a first challenge signal (CS1(t,CS1 max )); where the first response is a first response signal (RS1(t,RS1 max )) which is triggered by the first challenge signal (CS1(t,CS1 max )) is effected as a function of a first electrical property of the respective response structure; where the second challenge involves applying a second challenge signal (CS2(t,CS2 max )); where the second response is a second response signal (RS2(t,RS2 max )) which is triggered by the second challenge signal (CS2(t,CS2 max )) is effected as a function of a second electrical property of the respective response structure which differs from the first electrical property of the respective response structure. [11] Method according to claim 10, wherein the physical unclonable function is configured to provide a relationship between the first challenge signal and the second challenge signal and to determine the output based on a relationship between the first response signal and the second response signal; or wherein the physical unclonable function is configured to provide a relationship between the first challenge signal and the second response signal and to determine the output based on a relationship between the first response signal and the second challenge signal; or wherein the physical unclonable function is configured to provide a relationship between the first response signal and the second challenge signal and to determine the output based on a relationship between the first challenge signal and the second response signal; or wherein the physical unclonable function is configured to provide a relationship between the first response signal and the second response signal and to determine the output based on a relationship between the first challenge signal and the second challenge signal. [12] Method according to one of claims 1 to 11, wherein the respective response structure comprises a memristive structure with an electrical property, wherein the electrical property of the memristive structure comprises a branch set with one or more different read branches and one or more different write branches, and wherein the first electrical property is associated with one branch of the branch set and wherein the second electrical property is associated with another branch of the branch set. [13] Method according to claims 10 and 12, wherein the first electrical property is associated with a read branch of the branch set and wherein the second electrical property is associated with another read branch of the branch set; or wherein the first electrical property is associated with a read branch of the branch set and wherein the second electrical property is associated with a write branch of the branch set; or wherein the first electrical property is associated with one write branch of the branch set and wherein the second electrical property is associated with another write branch of the branch set; or wherein the first electrical property is associated with a write branch of the branch set and wherein the second electrical property is associated with a read branch of the branch set. [14] The method of any one of claims 1 to 13, wherein the output is based on a comparison of a first comparison value and a second comparison value, wherein the first comparison value is a representation of a property of the first challenge or the first response and wherein the second comparison value is a representation of a property of the second challenge or the second response. [15] Method according to one of claims 1 to 14, wherein the response structure comprises a memristive structure with a memristive element, and wherein the first challenge / response and the second challenge / response are applied to the memristive element; and wherein preferably the first comparison value is obtained from the memristive element before the second comparison value is obtained from the memristive element and is stored in an analog memory or in a digital memory for comparison with the second comparison value. [16] Method according to one of claims 1 to 14, wherein the memristive structure comprises a memristive structure having a first memristive element and a second memristive element, and wherein the first challenge / response is applied to the first memristive element and the second challenge / response is applied to the second memristive element; and wherein preferably the first comparison value is obtained from the first memristive element and the second comparison value is obtained from the second memristive element at the same time to compare the first comparison value and the second comparison value with each other. [17] Method according to one of claims 1 to 14, wherein the first challenge is executed for a predefined time to define a reference value based on the first response; and wherein the second challenge is executed for a variable time as a function of a comparison of the second response with the reference value; and where the output is determined based on a determination of the variable time. [18] A method for generating a key based on a Physical Unclonable Function, the method comprising: Generating a key element of the key by operating a response structure according to a linked challenge / response operation, wherein the linked challenge / response operation applied to the response structure comprises a first challenge / response sub-operation and a second challenge / response sub-operation, wherein the first challenge / response sub-operation comprises a first challenge to cause a first response by the response structure as a function of the first challenge; wherein the second challenge / response sub-operation comprises a second challenge to cause a second response by the response structure as a function of the second challenge; and wherein the linked challenge / response operation comprises an output determination operation to determine an output representing the key element of the key, the output determination comprising a comparison I) the first challenge or the first response with II) the second challenge or the second response. [19] Physical Unclonable Function (700) for generating a key (730), the Physical Unclonable Function comprising: one or more response structures (740); and a controller (700c) configured to generate the key (730) by operating each of the one or more response structures (740) according to a linked challenge / response operation (720), wherein the linked challenge / response operation (720) applied to a respective response structure (740m) of the one or more response structures (740) comprises a first challenge / response sub-operation (720-1) and a second challenge / response sub-operation (720-2), wherein the first challenge / response sub-operation (720-1) comprises a first challenge to cause a first response by the respective response structure as a function of the first challenge; wherein the second challenge / response sub-operation (720-2) comprises a second challenge to cause a second response by the respective response structure as a function of the second challenge; and wherein the linked challenge / response operation (720) comprises an output determination operation (720-3) to determine an output representing a key element of the key, the output determination comprising a comparison I) the first challenge or the first response with II) the second challenge or the second response. [20] Physical Unclonable Function according to claim 19, wherein the respective response structure (740m) comprises a memristive structure having an electrical property, wherein the electrical property of the memristive structure comprises a branch set with one or more different read branches and one or more different write branches, and wherein the first electrical property is associated with one branch of the branch set and wherein the second electrical property is associated with another branch of the branch set.

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