Deflection modulation through implantation and resulting structures

Abstract

One method comprises depositing a dielectric layer onto a package component that has a first deflection; and performing an implantation process to implant the dielectric layer with a voltage modulation dopant. After the implantation process, the package component has a second deflection that is smaller than the first deflection.

Description

Priority claim and cross-reference

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 532,455, filed August 14, 2023, entitled “Warpage Modulation via Ion Implantation for Bond Yield Improvement,” which is incorporated by reference into this application. background

[0002] Integrated circuit packages may include a plurality of package components, such as device dies and package substrates, bonded together to increase functionality and integration. Due to differences in the materials used for the majority of package components, flexion may occur. This flexion can cause non-bonding problems, and some conductive structural elements intended to be bonded together may not be bonded, resulting in circuit failure. Short description of the drawings

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1A shows contour lines of a die with a deflection according to some embodiments. Fig. 1B shows the deflection of a die measured in two directions according to some embodiments. Fig. 1C shows a cross-sectional view of a die having a concave profile according to some embodiments. Fig. 2A shows contour lines of a die that has undergone a deflection reduction implantation, according to some embodiments. Fig. 2B shows a cross-sectional view of a die that has undergone a deflection reduction implantation, according to some embodiments. The Fig. 3 to 9 show cross-sectional views of intermediate stages in the fabrication of a package by front-to-front bonding according to some embodiments. The Fig. 10 to 13 show cross-sectional views of intermediate stages in the fabrication of a package by front-to-back bonding according to some embodiments. The Fig. 14 to 16 show cross-sectional views of intermediate stages in the manufacture of a package including functional wafer bonding to a carrier wafer, according to some embodiments. Fig. 17 shows a cross-sectional view of a package with two functional wafers bonded together according to some embodiments. The Fig. 18 to 20 show cross-sectional views of intermediate stages in the fabrication of a package having a voltage modulation layer formed on a backside of a wafer, according to some embodiments. The Fig. 21 to 23 show cross-sectional views of intermediate stages in the manufacture of a package that can be used for further encapsulation, according to some embodiments. The Fig. 24A, Fig. 24B, Fig. 25A, Fig. 25B, Fig. 26A, Fig. 26B, Fig. 27A and Fig. 27B show top and cross-sectional views of voltage modulation layers / regions in dies according to some embodiments. The Fig. 28 to 31 show structures and positions of voltage modulation layers / regions in wafers according to some embodiments. The Fig. 32A and Fig. 32B show a vertical and a horizontal stress dopant distribution profile, respectively, according to some embodiments. Fig. 33 illustrates a process flow for fabricating a package with voltage modulation layers or regions according to some embodiments. Detailed description

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] A method for fabricating stress modulation layers and / or regions (hereinafter referred to as layers / regions) for reducing the deflection of package components and the resulting structures are provided. According to some embodiments of the present disclosure, a package component, such as a die or a wafer, is measured to determine the deflection of the package component. Implantation processes are performed to implant a stress modulation dopant and to fabricate stress modulation layers / regions such that the deflection is reduced.Embodiments discussed herein are intended to provide examples of how the subject matter of the present disclosure may be made or used, and one of ordinary skill in the art should readily recognize modifications that may be made without departing from the intended scope of various embodiments. Throughout the illustrations and illustrative embodiments, similar reference numerals are used to refer to similar elements. Furthermore, method embodiments may be discussed as being performed in a particular order, but other method embodiments may be performed in any logical order.

[0007] Fig. 1A shows a top view of a package component 10, which may be a device die according to some embodiments. Contour lines represent a deflection profile, where each contour line represents the positions that lie in the same plane. For example, if the package component is arranged on a planar surface, some points of the package component contact the planar surface and their distance from that surface is zero. Due to the deflection, some parts of the package component may be taller than the planar surface and are spaced apart from it. The contour lines may represent the distances of different parts of the package component from the planar surface.

[0008] Fig. Figure 1B shows an example deflection profile measured from the package component 10. A line 107 in Fig. 1B is made from a cross section 104 of Fig. 1A, and a line 109 in Fig. 1B is made from a cross section 106 of Fig. 1A. Line 107 indicates that edge portions of the package component 10 are lower than a center portion of the package component 10. The corresponding profile is referred to as a concave profile. An exemplary concave profile is shown in Fig. 1C. Line 109 indicates that the edge portion of the package component 10 is higher than its center portion. The corresponding profile is referred to as a convex profile. An exemplary convex profile is shown in Fig. 2B shown.

[0009] The concave profile also means that when the package component 10 is placed over another package component, the center portion of the package component 10 is likely to be spaced apart from the other package component when the edge portions of the package component 10 are in contact with the other package component. While both the concave profile and the convex profile are undesirable, the concave profile is more undesirable than the convex profile. It is even more undesirable that in different cross sections (such as cross sections 104 and 106 in Fig. 1A) the deflection profiles are opposite to each other, one profile being a convex profile and the other being a concave profile.

[0010] The Fig. 3 to 9 show cross-sectional views of intermediate stages in the fabrication of a package by die-to-wafer bonding according to some embodiments of the present disclosure. The corresponding processes are also schematically indicated in the process flow 200, which is shown in Fig. 33 is shown.

[0011] Fig. 3 is a cross-sectional view of a package component 20. In some embodiments, the package component 20 is a portion of a wafer 18 and is a die with active devices and optionally passive devices depicted as integrated circuit devices 25. In the following figures, integrated circuit devices 25 may not be depicted, but they may (or may not) be present. In alternative embodiments, the package component 20 is an interposer die that does not include active devices and may or may not include passive devices. In still other embodiments, the package component 20 is or includes a package, such as an InFO (integrated fan-out) package.

[0012] In some embodiments, the package component 20 includes a semiconductor substrate 24 and structural elements fabricated on a top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be fabricated from or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, a III-V compound semiconductor, or the like. The semiconductor substrate 24 may be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0013] In some embodiments, package component 20 includes integrated circuit devices fabricated on top of semiconductor substrate 24. Integrated circuit devices may, according to some embodiments, be complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like. Details of integrated circuit devices are not discussed here.

[0014] The package component 20 may include vias 26, also referred to as silicon vias (TSVs) or semiconductor vias (also TSVs), extending to an intermediate level of the semiconductor substrate 24, the intermediate level being located between the top and bottom surfaces of the semiconductor substrate 24.

[0015] An interconnect structure 28 is formed over the semiconductor substrate 24. In some embodiments, the interconnect structure 28 includes a plurality of dielectric layers 30 and a plurality of conductive features, such as metal lines / pads 34 and vias 36, in the dielectric layers 30. The dielectric layers 30 may include an interlayer dielectric (ILD; not individually shown) that fills spaces between gate stacks of transistors in the integrated circuit devices 25. In some embodiments, the ILD is formed from phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride, or the like. The ILD may be formed by spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), or the like.

[0016] The dielectric layers 30 may also be low-k dielectric layers, also referred to as intermetal dielectrics (IMDs), in some embodiments. Dielectric constants (k values) of the low-k dielectric layers may be, for example, less than about 3.5 or less than 3.0. The low-k dielectric layers may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like.

[0017] The conductive structural elements may be contact pins in the ILD used for electrical connection to the integrated circuit devices 25. In some embodiments, the contact pins are made of or include a conductive material selected from the group consisting of tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.

[0018] The conductive structural elements may include metal lines 34 and vias 36 formed in the respective dielectric layers 30 and electrically connected to the integrated circuit devices 25 and the vias 26. The metal lines in the same plane are collectively referred to below as a metal layer. In some embodiments, the interconnect structure 28 includes a plurality of metal layers interconnected by the vias 36. The metal lines 34 and the vias 36 may be formed from copper, a copper alloy, and / or another metal.

[0019] The interconnect structure 28 may also include a passivation layer 32 disposed over and in contact with a lower dielectric layer 30. The metal lines / pads 34 in the passivation layer 32 are also referred to below as upper conductive features 34A. The passivation layer 32 may be formed from a non-low-k dielectric material that may include silicon and one or more other elements such as oxygen, nitrogen, carbon, and / or the like. The passivation layer 32 may be SiO x N y C z where x is about 0 to about 2, y is about 0 to about 1.33, and z is about 0 to about 1, and x, y, and z are not all equal to zero. The passivation layer 32 may be made of or include, for example, SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like.

[0020] Fig. 4 illustrates an implantation process 38 for creating voltage modulation regions in passivation layer 32 according to some embodiments. In alternative embodiments, implantation process 38 is not performed, and therefore no voltage modulation regions are created in passivation layer 32.

[0021] Prior to the implantation process 38, the portions of the passivation layer 32 to be implanted are determined. In some embodiments, the deflection of the package component 20 is measured. Alternatively, an exemplary package component having the same structure as the package component 20 is measured. The corresponding process is indicated as a process 201 in the process flow 200 shown in Fig. 33. The measurement can be performed by a moiré measurement, in which a tool is used to measure the package component. The measurement yields a deflection profile of the package component 20, the parts of which have a deflection, and the degree of deflection. For example, Fig. 1A shows an exemplary deflection profile of a package component 10, assuming that the package component 20 has the same structure as the package component 10.

[0022] Based on the deflection profile, the parts of the package component 20 to be implanted are determined. The corresponding process is specified as a process 202 in the process flow 200, which is shown in Fig. 33. For example, in Fig. 1A, parts 110 have the highest deflection values, and the deflection has a concave profile. In some embodiments, regions 110 of package component 10 (which is package component 20) are to be implanted. In some embodiments, the deflection profile along y-direction line 106 is a convex profile, and the deflection is less severe. Accordingly, no implantation is performed in the associated regions, or alternatively, implantation is performed in some of the regions with strong deflections.

[0023] Let us return to Fig. 4. An implantation mask 40 is fabricated, which is subsequently patterned. In some embodiments, the implantation mask 40 is a patterned photoresist. In alternative embodiments, the implantation mask 40 is a three-layer mask having a bottom layer, a middle layer over the bottom layer, and a top layer (photoresist) over the middle layer. In still further embodiments, the implantation mask 40 is a hard mask made of a different material than the passivation layer 32 and patterned using a photoresist. The implantation mask 40 may, for example, include titanium nitride, boron nitride, or the like.

[0024] The material for the implantation mask 40 is selected so that the passivation layer 32 is not damaged during removal in a later process. The remaining parts of the patterned implantation mask 40 cover the parts of the passivation layer 32 that are not to be removed, while the parts to be implanted remain uncovered.

[0025] Let us stay with Fig. 4, in which an (ion) implantation process 38 is carried out. The corresponding process is indicated as a process 204 in the process flow 200, which is shown in Fig. 33. In some embodiments, the implanted ions (hereinafter also referred to as voltage modulation dopants) may be Ge, B, P, As, Ga, or the like, or combinations thereof. The implanted ions may also be H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, or a combination thereof and / or a combination with Ge, B, P, As, Ga. A concentration of the voltage modulation dopants in the passivation layer 32 may be higher than about 1E14 / cm 3 and in some embodiments can be about 1E14 / cm 3 up to about 1E16 / cm 3 be.

[0026] In alternative embodiments, implantation mask 40 is not fabricated, and implantation process 38 is not performed. Implantation mask 40 and implantation process 38 are shown in dashed lines to indicate that they may not be used. Processes 202 and 204 are also shown in dashed lines to indicate that they may be performed or omitted.

[0027] In some embodiments, the implantation process 38 is controlled so that the peak concentration of the implanted voltage modulation dopant occurs in the passivation layer 32. Throughout the description, the regions that are doped with the voltage modulation dopant are denoted using the letter "I" ("I" stands for "implanted"), and the implanted regions of the passivation layer 32 are referred to as "portions 32-I." The regions that are not doped with the voltage modulation dopant are denoted using the symbol "UI" ("UI" stands for "unimplanted"), and therefore the unimplanted portions of the passivation layer 32 are referred to as "portions 32-UI." In some embodiments where the implantation process 38 is performed, the dielectric layer 32 may have a thickness greater than about 1000 Å, so that the deflection reduction effect is significant enough.

[0028] In some embodiments, all upper conductive features 34A are covered by the patterned implantation mask 40 and are not implanted. In some embodiments, a lateral distance S1 between the upper conductive features 34A closest to the implanted region is greater than 0 µm, and may be greater than about 0.5 µm to allow sufficient process margin. Thus, each of the upper conductive features 34A may be enclosed by an unimplanted portion of the passivation layer.

[0029] During the implantation process 38, the material of the passivation layer 32 is modified. Furthermore, the density of the implanted parts is increased. This reduces the deflection of the package component 20, and also modifies the deflection profile. For example, the implantation process 38 and / or the subsequently produced stress modulation layers can individually or collectively lead to a Fig. 2A, which is different from the deflection profile shown in Fig. 1A, wherein the deflection profile in the x-direction is closer to the deflection profile in the y-direction. After implantation, the deflection contour lines can be nearly circular. Furthermore, the deflection can be changed to a convex profile in the x- and y-directions, as shown in Fig. 2B. In an example, a maximum deflection value WP2 is shown in Fig. 2B less than the maximum deflection value WP1 of Fig. 1A.

[0030] Fig. 5 shows the production of a dielectric layer 42. The corresponding process is indicated as a process 206 in the process flow 200, which in Fig. 33. In some embodiments, dielectric layer 42 includes a material similar to that of passivation layer 32 and may include silicon and one or more other elements such as oxygen, nitrogen, carbon, and / or the like. In alternative embodiments, dielectric layer 42 may be an etch stop layer, which may be made of or include AlN, AlO, SiOC, or the like, or multilayers thereof.

[0031] Fig. 6 shows the deposition of a voltage modulation layer 44 according to some embodiments. The corresponding process is indicated as a process 208 in the process flow 200 shown in Fig. 33. In some embodiments, the voltage modulation layer 44 may be made of, or may include, a dielectric material that includes silicon and one or more other elements such as oxygen, nitrogen, carbon, and / or the like. The voltage modulation layer 44 may also be SiO x N y C z where x is about 0 to about 2, y is about 0 to about 1.33, and z is about 0 to about 1, and x, y, and z are not all equal to zero. The stress modulation layer 44 may be made of or include, for example, SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like. A thickness of the stress modulation layer 44 may be, for example, greater than about 1000 Å and may be about 1000 Å to about 2000 Å.

[0032] Then, an implantation process 45 is performed. The corresponding process is indicated as a process 210 in the process flow 200, which is shown in Fig. 33. The implanted ion (voltage modulation dopant) can be selected from the same group of elements considered for the implantation process 38, and it can be the same element used in the implantation process 38 or a different implanted element. Furthermore, the peak concentration of the implanted ions occurs in the voltage modulation layer 44. The concentration of the implanted voltage modulation dopant can be in the same range as that of the voltage modulation dopant implanted in the implantation process 38.

[0033] In some embodiments, the implantation process 45 is a blanket implantation process in which no implantation mask is used and the entire voltage modulation layer 44 is implanted (in the entire wafer or die). In alternative embodiments, the implantation process 45 is selective, wherein an implantation mask 43 is fabricated to mask some portions of the voltage modulation layer 44 while leaving other portions uncovered for implantation. The implanted portions of the voltage modulation layer 44 are referred to below as portions 44-I, and the unimplanted portions of the voltage modulation layer 44 are referred to as portions 44-UI.

[0034] In alternative embodiments where voltage modulation regions 32-I are created, the voltage modulation layer 44 may or may not be formed. The processes 208 and 210 of Fig. 33 are therefore also shown in dashed lines.

[0035] In some embodiments, positions for the selective implantation process 45 are determined by measuring the package component 20 (or another exemplary package component), and this measurement is performed at the Fig. 3. The corresponding determination is essentially the same as the determination of the positions for the implantation process 38. In alternative embodiments, the positions for the selective implantation are determined by measuring the package component 20, and this measurement is carried out at the Fig. 4 (where the voltage modulation regions 32-I are already fabricated). In other words, the implantation process 45 may be performed to further reduce the deflection of the package component that has already been modulated with the implantation process 38.

[0036] The Fig. 24A, Fig. 24B, Fig. 25A, Fig. 25B, Fig. 26A, Fig. 26B, Fig. 27A and Fig. 27B show top and cross-sectional views, respectively, of voltage modulation layers / regions in device dies according to some embodiments. The structural elements adjacent to the illustrated voltage modulation layers / regions are not shown; rather, these structural elements can be found in the cross-sectional views discussed previously. Fig. 24A and Fig. 24B show a cross-sectional view and a top view, respectively, of a blanket voltage modulation layer 44 that is not patterned and that may extend (in top view) over the entire package component 20, which may be a die.

[0037] The Fig. 25A and Fig. 25B show a cross-sectional view and a top view, respectively, of the stress modulation regions 44-I and / or 32-I and the undoped regions 44-UI and / or 32-UI according to some embodiments. The stress modulation regions 44-I and / or 32-I may be created where the stress is high, for example, in corner regions of the package component 20, which are Fig. 25B. The stress modulation regions 44-I and / or 32-I may also be created at other locations where the stress is not high, but by creating the stress modulation regions 44-I and / or 32-I at these locations, the overall deflection profile of the package component 20 may also be modified.

[0038] The Fig. 26A and Fig. 26B show a cross-sectional view and a top view, respectively, of a blanket multilayer stress modulation layer 44. In some embodiments, the multilayer stress modulation layer 44 includes a plurality of sublayers, such as a sublayer 44-1 and a sublayer 44-2. The materials for sublayer 44-1 and sublayer 44-2 may be selected from the same group of materials that are suitable for forming the stress modulation layer 44 discussed above and may be silicon-containing dielectric materials. The materials for sublayer 44-1 and sublayer 44-2 may be the same or different from each other.The voltage modulation dopants for sublayer 44-I and sublayer 44-2 may be selected from the same group of voltage modulation dopants that are suitable for forming voltage modulation layer 44 and voltage modulation regions 32-I, and they may be the same or different from each other.

[0039] In some embodiments, the formation of the multilayer voltage modulation layer 44 may include depositing the sublayer 44-I and performing a first implantation process to implant the sublayer 44-1. A peak concentration PC44-1 of the respective voltage modulation dopant introduced with the first implantation process occurs in the sublayer 44-1. Then, the sublayer 44-2 is deposited on the sublayer 44-I, followed by a second implantation process to implant the sublayer 44-2. A peak concentration PC44-2 of the respective voltage modulation dopant introduced with the second implantation process occurs in the sublayer 44-2.In some embodiments, the peak concentration of PC44-2 is higher or lower than the peak concentration of PC44-1, and a peak concentration ratio of PC44-2 / PC44-1 may be, for example, greater than about 5 or 10 or less than about 0.2 or 0.1.

[0040] The Fig. 27A and Fig. 27B show a cross-sectional view and a top view, respectively, of the multilayer voltage modulation layer 44 according to alternative embodiments. These embodiments are substantially similar to the embodiments shown in FIGS. Fig. 26A and Fig. 26B, except that instead of blanket deposition, selective deposition processes are performed to create voltage modulation regions 44-1-I and 44-2-I. The voltage modulation regions 44-1-I and 44-2-I are again created in separate implantation processes, with the peak concentration occurring in sublayers 44-1 and 44-2, respectively. The peak concentration ratio PC44-2 / PC44-1 may be in a similar range to the aforementioned.

[0041] As in the Fig. 27A and Fig. 27B, the voltage modulation regions 44-2-I may partially overlap the respective underlying voltage modulation regions 44-1-I. Some or all of the voltage modulation regions 44-2-I may also be completely offset from the voltage modulation regions 44-1-I. In addition, voltage modulation regions 44-3-I may also be located below the voltage modulation regions 44-1-I. The voltage modulation regions 44-3-I may be created with a third implantation process. A peak concentration PC44-3 of the voltage modulation dopant introduced with the third implantation process occurs in the sublayer 44-3. The peak concentration PC44-3 may be higher than, equal to, or lower than the peak concentrations PC44-1 and PC44-2, respectively.

[0042] In Fig. 7, vias 49, a bonding layer 46 and bonding pads 48 are produced. The corresponding process is indicated as a process 212 in the process flow 200, which is shown in Fig. 33. Vias 49 may penetrate voltage modulation layer 44. Bond layer 46 may be formed from a silicon-containing dielectric material, which may be selected from the same group of materials used to form voltage modulation layer 44. Bond pads 48 may include copper and may be formed using a damascene process. In alternative embodiments, solder regions may be formed as top-side features of package component 20.

[0043] In some embodiments, the foregoing processes described in the Fig. 3 to 7 are performed at the wafer level, and the package component 20 is a part of the wafer 18. As shown in Fig. 7, the wafer 18 is subsequently separated in a dicing process, which may be performed using a saw blade. This separates the wafer 18 into discrete package components 20. The corresponding process is indicated as a process 214 in the process flow 200 shown in Fig. 33 is shown.

[0044] In Fig. 8, a package component 118 is manufactured. In some embodiments, the package component 118 is a device wafer (a functional wafer), an interposer wafer, a reconfigured wafer containing packaged device dies, a package substrate strip, or the like. Accordingly, a package component 120 may be a device die, an interposer die, a package, a package substrate, or the like.

[0045] In some embodiments, package component 120 has a similar structure to package component 20. The structures and materials of the structural elements in package component 120 can be found by reference to similar structural elements in package component 20, where similar structural elements in package component 120 are designated by adding the numeral "1" before the reference numbers of the corresponding structural elements in package component 20. For example, the substrate in package component 20 is designated "24," and correspondingly, the substrate in package component 120 is designated "124."

[0046] The package component 120 may include integrated circuit devices (not shown), an interconnect structure 128, bond pads 148, and a bond layer 146. The details of these structural elements are similar to those of the corresponding structural elements in the package component 20 and are not repeated here. The package component 120 may or may not include voltage modulation regions and voltage modulation layers. When manufactured, the voltage modulation regions and layers may be substantially the same as in the package component 20. Some example voltage modulation regions and layers in the package component 120 are shown in Fig. 17 can be found.

[0047] The package component 20 is bonded to the package component 120. The corresponding process is specified as a process 216 in the process flow 200, which is Fig. 33. In the illustrated example, a hybrid bonding process is performed such that the bond pads 48 are bonded to the bond pads 148 by metal-to-metal bonding, and the bond layer 46 is bonded to the bond layer 146 by fusion bonding (forming Si-O-Si bonds). In alternative embodiments, other bonding types, such as direct metal-to-metal bonding, solder bonding, or the like, may also be performed. While only one package component 20 is illustrated, a plurality of package components 20 (such as dies) may be bonded to the respective package components 120 in the package component 118.

[0048] Fig. 9 shows a gap filling process for filling gaps between the package components 20 with gap filling areas 50. The corresponding process is indicated as a process 218 in the process flow 200, which in Fig. 33. The gap-filling regions 50 can be formed from inorganic dielectric materials, such as a silicon nitride coating and a silicon oxide region on the silicon nitride coating. Alternatively, the gap-filling regions 50 can be formed from a molding compound.

[0049] Fig. 9 also shows the formation of a backside interconnect structure 52 on a backside of the package component 20. In some embodiments, the gap fill regions 50 and the substrate 24 of the package component 20 are planarized, for example, in a CMP (chemical mechanical polishing) process or a machine polishing process until the vias 26 are exposed. The corresponding process is indicated as a process 220 in the process flow 200 shown in Fig. 33 is shown.

[0050] Then, the backside interconnect structure 52 is fabricated with dielectric layers 54 and redistribution lines (RDLs) 56. The corresponding process is indicated as a process 222 in the process flow 200 shown in Fig. 33. Subsequently, electrical connection elements 58 (such as solder regions) are formed, resulting in a newly configured wafer 82. A dicing process can then be performed to separate the newly configured wafer 82 into discrete packages 82' that are identical. The corresponding process is indicated as a process 224 in the process flow 200, which is shown in Fig. 33 is shown.

[0051] The previous embodiments show a front-to-front bonding process. Fig. 10 to 13 show cross-sectional views of intermediate stages in the fabrication of a package by front-to-back bonding according to alternative embodiments of the present disclosure. Unless otherwise noted, the materials, structures, and fabrication processes for the components in these embodiments are substantially the same as for similar components designated by similar reference numerals in the preceding embodiments. The details of the materials, structures, and fabrication processes provided in each of the embodiments throughout the description may be used for a different embodiment, if appropriate. And, whenever a package component is referred to in the description as having stress modulation layers / regions, the discussion of the fabrication processes applies to stress modulation layers / regions 32-1 and 44.

[0052] The first steps of these embodiments are essentially those described in the Fig. 1 to 7, in which the package components 20 are manufactured. Fig. Figure 10 then shows the bonding / attachment of the package components 20 to a carrier 66. The carrier 66 includes a semiconductor substrate 62, which in some embodiments may be a silicon substrate. A bonding layer 64 is formed on the semiconductor substrate 62. The bonding layer 64 may be formed using a deposition process or a thermal oxidation process and from a silicon-containing dielectric material, which may be selected from the same group of materials used for the bonding layer 46 ( Fig. 7) in the package components 20. Bonding of the bonding layer 64 to the bonding layer 46 can be accomplished by fusion bonding in some embodiments.

[0053] In alternative embodiments, the carrier 66 comprises a transparent substrate (also designated by reference numeral 62), such as a glass substrate, and the package components 20 are attached to the carrier 66 with an adhesive (also designated by reference numeral 64), such as an LTHC (light-to-heat conversion) material configured to decompose upon exposure to heat from light (such as a laser beam). In these embodiments, the layer 46 in the package component 20 may be a polymer layer, such as a polyimide layer, a BCB (benzocyclobutene) layer, or the like.

[0054] Gap-filling regions 68 are then created to fill the gaps between the package components 20. The gap-filling regions 68 can be made from inorganic dielectric materials, for example, including a silicon nitride coating and a silicon oxide layer over the silicon nitride coating. Alternatively, the gap-filling regions 68 can be made from a molding compound.

[0055] In Fig. 11, a backside grinding process is then performed on the gap-filling regions 68 and the semiconductor substrate 24 of the package components 120, thereby exposing the vias 26. Subsequently, a backside interconnect structure 52 is formed on the backside of the package components 20. The backside interconnect structure 52 may include bond pads 96.

[0056] The package components 120 are bonded to the package components 20. The package components 120 may be a device die, a package, an interposer die, or the like. In some embodiments, the package components 120 include active devices, such as transistors. In addition, the package components 120 may include voltage modulation layers / regions 132-I and / or 144. The voltage modulation layers / regions 132-I and / or 144 may be formed using substantially the same methods as the voltage modulation layers / regions in the package components 20 and have the same set of structures that are suitable for them. For example, voltage modulation regions 132-I are created by implantation, while portions 132-UI are not implanted. A voltage modulation layer 144 may also be formed by deposition and implantation.

[0057] Fig. Figure 12 shows the creation of gap-filling regions 70 made of inorganic dielectric materials, such as a silicon nitride coating and a silicon oxide layer over the silicon nitride coating. Alternatively, the gap-filling regions 70 can be made of a molding compound. A back-grinding process is then performed to level the top surfaces of the package components 120 and the gap-filling regions 78.

[0058] Fig. 13 shows the attachment / bonding of a carrier 76 to the package components 120 and the gap-filling regions 70. The carrier 76 includes a substrate 72 and a bond layer 74. The structure and materials for the carrier 76 can be selected from the same group of structures and materials that are suitable for the carrier 66. The attachment / bonding can be achieved by fusion bonding the bond layer 74 to the substrates 124 of the package components 120 and the gap-filling regions 70.

[0059] The carrier 66 ( Fig. 12) is then removed, and an interconnect structure 78 and electrical connection elements 80 (such as solder regions or metal bumps) are formed on the front side of the package components 20. This results in a newly configured wafer 82. In a subsequent process, dicing is performed to separate the newly configured wafer 82 into a plurality of packages 82'. The packages 82' can be used for a further packaging process in which the portions of the carrier 76 can be removed, and the vias in the package components 120 can be exposed for establishing later electrical connections thereon.

[0060] The Fig. 14 to 16 illustrate a wafer-to-wafer bonding process in which a functional wafer containing functional integrated circuits (active devices / circuits) is bonded to a carrier wafer 84. The carrier wafer 84 includes a semiconductor substrate (such as a silicon substrate) 86, a dielectric layer 88, and a voltage modulation layer 90. The voltage modulation layer 90 may be formed by deposition and may include a silicon-containing dielectric material containing silicon and one or more elements selected from the group consisting of N, O, C, and combinations thereof.

[0061] In some embodiments, an implantation process 94 is performed to implant a voltage modulation dopant, which may be selected from the same group of voltage modulation dopants used in processes 38 ( Fig. 4) and 45 ( Fig. 6). The implantation process 94 may be a blanket implantation process in which no implantation mask is used and thus the entire voltage modulation layer 90 is implanted in the entire carrier wafer 84. In alternative embodiments, experiments may be performed to measure the carrier 84 and / or the resulting exemplary reconfigured wafer 82 ( Fig. 16) can be performed to determine deflection values ​​and a deflection profile for the entire carrier wafer 84. Based on the determined deflection profile, selected regions of the stress modulation layer 90 are implanted to reduce the deflection and modify the deflection profile of the resulting reconfigured wafer 82. For example, an implantation mask 93 can be fabricated such that selected regions 90-I are implanted and regions 90-UI are not implanted. Here, too, the peak doping concentration of the implanted stress modulation dopant occurs in the stress modulation layer 90.

[0062] The Fig. 28 to 31 show some wafers (which may be a carrier wafer 84 and / or wafers 18 and 118, which will be discussed in later processes and are referred to below as 84 / 18 / 118) and the implanted parts according to different embodiments. As shown in Fig. 28, the entire carrier wafer 84 / 18 / 118 is implanted. In Fig. 29, only some strip portions of the carrier wafer 84 / 18 / 118 are implanted. The overlapped regions of the implanted strips have longitudinal directions in the x-direction, and the implanted strips that have longitudinal directions in the y-direction may overlap the regions where the deflection value in the carrier wafer 84 / 18 / 118 is highest. Fig. 30 shows an embodiment in which the implanted region is a circular region or may comprise a plurality of circular regions. Fig. Figure 31 shows an embodiment in which selected and isolated regions are implanted.

[0063] In Fig. 15, a bonding layer 92 is deposited on the voltage modulation layer 90. The bonding layer 92 may be made of a silicon-containing dielectric material, which may include silicon and one or more elements selected from the group consisting of N, O, C, and combinations thereof. Fig. 16, the carrier wafer 84 is then bonded to the functional wafer 18 by fusion bonding. The functional wafer 18 can be bonded using the Fig. 3 to 7 shown processes.

[0064] In the Fig. 16, in some embodiments, voltage modulation layers / regions are formed in the carrier wafer 84 but not in the functional wafer 18. In alternative embodiments, voltage modulation layers / regions are formed in the functional wafer 18 but not in the carrier wafer 84. In still other embodiments, voltage modulation layers / regions are formed in the functional wafer 18 and in the carrier wafer 84.

[0065] Fig. 17 shows the fabrication of a package according to alternative embodiments. Encapsulation includes front-to-front bonding of wafers 18 and 118, which include device dies 20 and 120, respectively. The details of device dies 20 and 120 have been discussed in previous embodiments and are therefore not repeated here. Again, voltage modulation layers / regions may be formed in one of device dies 20 and 120 (and wafers 18 and 118) or in both device dies 20 and 120 (and wafers 18 and 118). Furthermore, the fabrication of the voltage modulation layers / regions may occur at the die level, as shown in FIGS. Fig. 24A, Fig. 24B, Fig. 25A, Fig. 25B, Fig. 26A, Fig. 26B, Fig. 27A and Fig. 27B, or it can be done at wafer level, as shown in the Fig. 28 to 31.

[0066] The Fig. 18 to 20 illustrate the fabrication of a voltage modulation layer on a backside of a functional wafer according to some embodiments. Fig. 18, the functional wafer 18 is bonded to the carrier wafer 84. Voltage modulation layers / regions can be formed in the carrier wafer 84 and / or on the front side of the functional wafer 18. The bonding can be a fusion bond in some embodiments. Fig. 19, the semiconductor substrate 24 of the functional wafer 18 is then thinned to expose the vias 26. Backside dielectric layers 98 are formed, and bond pads 96 are formed in the backside dielectric layers 98.

[0067] Then, a voltage modulation layer 110 is deposited, which can be made of a similar material as other voltage modulation layers, such as the voltage modulation layer 44. To introduce a voltage modulation dopant into the voltage modulation layer 110, an implantation process 114 can be performed, wherein the peak concentration of the voltage modulation dopant occurs in the voltage modulation layer 110. The implantation process 114 can be area-wide, as shown in Fig. 28, or it can be selective, as shown in the Fig. 29 to 31. To define the implanted areas in the selective implantation process, an implantation mask 112 is used, which is shown in Fig. 19 is shown.

[0068] Fig. Figure 20 illustrates the fabrication of a bond layer 115 and bond pads 116 that can be used for a hybrid bonding process. This results in the newly configured wafer 82. The newly configured wafer 82 can then be singulated to produce a plurality of discrete packages 82'.

[0069] The Fig. Figures 21 to 23 also show a wafer-to-wafer bonding process for producing packages that can then be encapsulated. Fig. 21, the wafer 18 is bonded to the carrier wafer 84. Then, the substrate 24 of the wafer 18 is thinned to expose the vias 26, and a backside structure is formed on the backside of the wafer 18, as shown in Fig. 22 is shown.

[0070] Furthermore, Fig. 22, the wafer 118 is bonded to the wafer 18. In later processes, the substrate 124 of the wafer 118 is thinned to expose the vias 126, and a backside structure is fabricated on the backside of the wafer 118 to produce the newly configured wafer 82, as shown in Fig. 23. The resulting reconfigured wafer 82 can then be diced to produce discrete packages.

[0071] In the Fig. 22, voltage modulation layers / regions may be fabricated in the carrier wafer 84, the wafer 18, and / or the wafer 118 in any combination.

[0072] Fig. Figure 32A shows a vertical distribution profile of the voltage modulation dopant in a voltage modulation region 140, which embodies all of the voltage modulation layers / regions 32-1, 44, 144, 110, and the like discussed above. Layers 142 and 144 represent dielectric layers above (if present) and below the voltage modulation region 140. Concentrations of the voltage modulation dopant are shown on the right side of Fig. 32A. In some embodiments, the peak concentration of the voltage modulation dopant occurs in the voltage modulation region 140 (and may occur at or near its mid-level). In an upward and downward direction from the location where the peak concentration occurs, the concentrations of the voltage modulation dopant may gradually decrease.

[0073] Fig.32B shows a horizontal distribution of the voltage modulation dopant in an implanted region 150-I in a dielectric layer 150 and in an unimplanted region 150-UI. The dielectric layer 150 may embody some of the selectively implanted voltage modulation layers / regions discussed above. In some embodiments, the peak concentration of the voltage modulation dopant occurs in the implanted region 150-I (and may occur at or near its center). The concentrations of the voltage modulation dopant may gradually decrease upon transitioning into the unimplanted region 150-UI. Some portions of the unimplanted region 150-UI may not contain any voltage modulation dopant.

[0074] In the embodiments presented above, some processes and structural elements are discussed according to some embodiments of the present disclosure for manufacturing a three-dimensional package (3D package). Other processes and structural elements may also be used. For example, test structures may be used to assist in verification testing of a 3D package or 3D IC devices. The test structures may include, for example, test pads fabricated in a redistribution layer or on a substrate that enable testing of the 3D package or 3D IC devices, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures.In addition, the structures and methods disclosed herein may be used in conjunction with test methodologies that include intermediate verification of proven good dies to increase yield and reduce cost.

[0075] Embodiments of the present disclosure have several advantages. By forming stress modulation layers and / or regions in dies and / or wafers through ion implantation, the deflection of the device dies and / or wafers can be reduced, and the deflection profiles can be modified.

[0076] According to some embodiments of the present disclosure, a method comprises: depositing a dielectric layer on a package component having a first deflection; and performing an implantation process to implant the dielectric layer with a voltage modulation dopant, wherein after the implantation process, the package component has a second deflection that is smaller than the first deflection. In one embodiment, the implantation process causes the package component to deflect in a direction opposite to the direction before the implantation process. In one embodiment, the implantation process is a blanket implantation process.

[0077] In one embodiment, the method further comprises: forming a via penetrating the dielectric layer; forming a bond layer over and in contact with the dielectric layer; and forming a bond pad in the bond layer and over and in contact with the via. In one embodiment, the implantation process is a selective implantation process in which a first portion of the dielectric layer is implanted and a second portion of the dielectric layer is masked from the implantation process. In one embodiment, the method further comprises: measuring the first deflection of another package component having the same structure as the package component; and determining locations of the dielectric layer to be implanted, wherein determining the locations is based on the first deflection and the locations are implanted in the implantation process.

[0078] In one embodiment, portions of the sites to be implanted are located in corner regions of the package component, and a center portion of the package component is masked from the implantation process. In one embodiment, the package component includes metal lines in the dielectric layer, the metal lines masked from the implantation process. In one embodiment, the voltage modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. In one embodiment, the voltage modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. In one embodiment, the package component includes active devices, the dielectric layer being disposed on a front side of the package component.In one embodiment, the package component includes active devices, wherein the dielectric layer is disposed on a backside of the package component.

[0079] According to some embodiments of the present disclosure, a structure comprises: a first dielectric layer; a second dielectric layer over and in contact with the first dielectric layer; and a third dielectric layer over the second dielectric layer. The second dielectric layer comprises: a first portion containing a voltage modulation dopant, the first portion having a first peak concentration of the voltage modulation dopant in the second dielectric layer; and a second portion, the second portion having a second peak concentration of the voltage modulation dopant in the second dielectric layer, the second peak concentration being lower than the first peak concentration.

[0080] In one embodiment, concentrations of the voltage modulation dopant continuously decrease from a position where the first peak concentration occurs upward into the third dielectric layer or downward into the first dielectric layer, and the concentrations of the voltage modulation dopant also continuously decrease from the first part to the second part. In one embodiment, the voltage modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof.

[0081] In one embodiment, the voltage modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. In one embodiment, the structure further comprises a metal line in the second dielectric layer, wherein the metal line is disposed in the second portion. In one embodiment, the first, second, and third dielectric layers are included in a die, wherein the first portion is disposed in a corner region of the die and the second portion is disposed in a central region of the die.

[0082] According to some embodiments of the present disclosure, a structure comprises: a semiconductor substrate; active devices in the semiconductor substrate; an interconnect structure over the active devices; and a bond layer over the passivation layer. The interconnect structure comprises: a passivation layer having first and second portions, the first portions containing a voltage modulation dopant and the second portions having at least lower concentrations of the voltage modulation dopant than the first portions; and a plurality of conductive features in the passivation layer, each of the plurality of conductive features being enclosed by one of the second portions of the passivation layer and spaced apart from the first portions.In one embodiment, peak concentrations of the voltage modulation dopant occur in the passivation layer, and concentrations of the voltage modulation dopant gradually decrease in an upward direction and a downward direction from the point at which the peak concentrations occur.

[0083] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 532,455

[0001]

Claims

[1] Method comprising: Depositing a dielectric layer on a package component having a first deflection; and Performing an implantation process for implanting the dielectric layer with a voltage modulation dopant, wherein after the implantation process the package component has a second deflection that is smaller than the first deflection. [2] The method of claim 1, wherein the implantation process causes the package component to bend in a direction opposite to the direction prior to the implantation process. [3] The method of claim 1 or 2, wherein the implantation process is a blanket implantation process. [4] A method according to any one of the preceding claims, further comprising: Creating a via that penetrates the dielectric layer; Producing a bonding layer over and in contact with the dielectric layer; and Creating a bond pad in the bond layer and above and in contact with the via. [5] A method according to any one of the preceding claims, wherein the implantation process is a selective implantation process in which a first part of the dielectric layer is implanted and a second part of the dielectric layer is masked against the implantation process. [6] A method according to any one of the preceding claims, further comprising: Measuring the first deflection of another package component that has the same structure as the package component; and Determining locations of the dielectric layer to be implanted, wherein the determining of the locations is based on the first deflection and the locations are implanted in the implantation process. [7] Method according to one of the preceding claims, wherein parts of the sites to be implanted are located in corner areas of the package component, and a central part of the package component is masked against the implantation process. [8] A method according to any one of the preceding claims, wherein the package component comprises metal lines in the dielectric layer, the metal lines being masked against the implantation process. [9] A method according to any one of the preceding claims, wherein the voltage modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb and combinations thereof. [10] A method according to any one of the preceding claims, wherein the voltage modulation dopant is selected from the group consisting of Ge, B, P, As, Ga and combinations thereof. [11] Method according to one of the preceding claims, wherein the package component has active devices, and the dielectric layer is arranged on a front side of the package component. [12] Method according to one of the preceding claims, wherein the package component has active devices, and the dielectric layer is arranged on a back side of the package component. [13] Structure with: a first dielectric layer; a second dielectric layer over and in contact with the first dielectric layer, the second dielectric layer comprising: a first portion containing a voltage modulation dopant, the first portion having a first peak concentration of the voltage modulation dopant in the second dielectric layer, and a second part, the second part being voltage modulation dopant has a second peak concentration in the second dielectric layer, the second peak concentration being lower than the first peak concentration; and a third dielectric layer over the second dielectric layer. [14] Structure according to claim 13, wherein Concentrations of the voltage modulation dopant continuously decrease from a position where the first peak concentration occurs upwards into the third dielectric layer or downwards into the first dielectric layer, and the concentrations of the voltage modulation dopant also decrease continuously from the first part to the second part. [15] The structure of claim 13 or 14, wherein the stress modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, H, Y, Zr, Xe, In, Sb, Si, N, O, C, F, Ne, He, Ar, Kr, Cl, S, Se, Sn, Al, In, Er, Yb, and combinations thereof. [16] The structure of any one of claims 13 to 15, wherein the voltage modulation dopant is selected from the group consisting of Ge, B, P, As, Ga, and combinations thereof. [17] The structure of any one of claims 13 to 16, further comprising a metal line in the second dielectric layer, the metal line being disposed in the second portion. [18] Structure according to any one of claims 13 to 17, wherein the first, second and third dielectric layers are contained in a die, and the first part is arranged in a corner region of the die and the second part is arranged in a central region of the die. [19] Structure with: a semiconductor substrate; active devices in the semiconductor substrate; an interconnect structure over the active devices, the interconnect structure comprising: a passivation layer having first parts and second parts, wherein the first parts contain a voltage modulation dopant and the second parts have at least lower concentrations of the voltage modulation dopant than the first parts, and a plurality of conductive structural elements in the passivation layer, each of the plurality of conductive structural elements being enclosed by one of the second portions of the passivation layer and spaced from the first portions; and a bonding layer over the passivation layer. [20] Structure according to claim 19, wherein Peak concentrations of the voltage modulation dopant occur in the passivation layer, and Concentrations of the voltage modulation dopant gradually decrease in an upward direction and a downward direction from the point at which the peak concentrations occur.

Images