REAR-SIDED THROUGH-CONTACTING AND DOUBLE-SIDED POWER RAIL FOR EPITAXIAL SOURCE / DRAIN STRUCTURE

Abstract

An exemplary device comprises a front busbar arranged over the front face of a substrate, a rear busbar arranged over the back face of the substrate, and an epitaxial source / drain structure located between the front and rear busbars. The epitaxial source / drain structure is connected to the front busbar by a front source / drain contact. The epitaxial source / drain structure is connected to the rear busbar by a rear source / drain via. The rear source / drain via is located in a substrate, and a dielectric layer is located between the substrate and the rear busbar. The rear source / drain via extends through the dielectric layer and the substrate.A front-side silicide layer can be located between the front-side source / drain contact and the epitaxial source / drain structure, and a back-side silicide layer can be located between the back-side source / drain contact and the epitaxial source / drain structure, such that the epitaxial source / drain structure is located between silicide layers.

Description

[0001] This is a non-provisional application of, and claims priority to, U.S. Provisional Patent Application Serial No. 63 / 510,727, filed June 28, 2023, the entire disclosure of which is hereby incorporated by reference. BACKGROUND

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and IC design have spawned generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected components per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This downsizing process generally realizes benefits by increasing production efficiency and reducing the costs associated with manufacturing.

[0003] Such downsizing has also increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are necessary. For example, to enable further reductions in the density of advanced IC technology nodes, front-side interconnect structures and rear-side interconnect structures may be required to enable electrical connection to, and / or operation of, IC devices. While existing interconnect structures for enabling electrical connection are generally suitable for their intended purposes, they are not satisfactory in all respects. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying figures. It should be understood that, in accordance with common industry practice, various structural elements are not drawn to scale and are for illustrative purposes only. Rather, the dimensions of the various structural elements may be exaggerated or reduced as needed for clarity of discussion. Fig. 1 is a flow diagram of a partial or complete method for fabricating a two-sided interconnect structure for a device according to various aspects of the present disclosure. Fig. 2-15 are cross-sectional views of a partial or complete device at various stages of manufacture, which are used in the method of Fig. 1, according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The present disclosure generally relates to two-sided interconnects for devices, such as multi-gate devices and / or stacked devices, and methods of manufacturing the same.

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not limiting. For example, the formation of a first structural element over a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements are not necessarily in direct contact.In addition, spatially relative terms, for example, "lower," "upper," "horizontal," "vertical," "over," "above," "below," "beneath," "upward," "downward," "above," "below," etc., as well as derivatives thereof (for example, "horizontally," "downwardly," "upwardly," etc.), are used to simplify the present disclosure with respect to the relationship of one structural element to another structural element. The spatially relative terms are intended to cover various orientations of the device incorporating the structural elements. The present disclosure may also repeat reference numbers and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not automatically create a relationship between the various embodiments and / or devices discussed.

[0007] Furthermore, when a number or range of numbers is described with "about," "approximately," and the like, the term is intended to encompass numbers that are within a reasonable range that accounts for variations inherent in each manufacturing process, as one of ordinary skill in the art would understand them. For example, the number or range of numbers encompasses a reasonable range that includes the stated number plus a margin of, for example, ± 10% of the stated number—based on known manufacturing tolerances associated with the manufacture of a structural element having a property associated with the number. For example, a material layer having a thickness of "about 5 nm" may encompass a dimensional range of 4.5 nm to 5.5 nm if one of ordinary skill in the art knows that the manufacturing tolerances associated with the deposition of the material layer are ± 10%.Furthermore, when device structural elements are described as having "essential" properties and / or characteristics, such terms are intended to encompass properties and / or characteristics that are within the tolerances of the manufacturing processes, given the variances inherent in each manufacturing process. For example, "substantially vertical" or "substantially horizontal" structural elements are intended to encompass structural elements that are approximately vertical and horizontal, within given tolerances of the manufacturing processes used to fabricate such structural elements, without being mathematically or perfectly vertical and horizontal.

[0008] Fig. 1 is a flow diagram of a partial or complete method 10 for fabricating a two-sided device-level interconnect structure for a device according to various aspects of the present disclosure. Fig. 2-15 are cross-sectional views of a partial or complete device 100 at various stages of manufacture related to the method 10 of Fig. 1, according to various aspects of the present disclosure. The device 100 may be included in a microprocessor, a memory, another integrated circuit (IC), or a combination thereof. In some embodiments, the device 100 is a portion of an integrated circuit (IC) chip, a system-on-chip (SoC), or a portion thereof that includes various passive electronic devices and / or active electronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.The various transistors can be planar or non-planar transistors, such as fin-type FETs (FinFETs) or gate-all-around transistors (GAA transistors). Fig. 1 and Fig. 2-15 are discussed here simultaneously for ease of description and better understanding. Fig. 1 and Fig. 2-15 have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional steps may be provided before, during, and after the method 10, and some of the described steps may be shifted, replaced, or omitted to obtain additional embodiments of the method 10. The apparatus 100 of Fig. 2-15, additional structural elements may be added, and some of the structural elements described below may be used in other embodiments of the device 100 of Fig. 2-15 may be replaced, modified or omitted.

[0009] With reference to Fig. 1 and Fig. 2, the method 10 includes, in block 15, receiving a workpiece (e.g., a device 100) that has undergone FEOL processing, which may include forming electrically functional devices (e.g., a transistor 104A, a transistor 104B, a transistor 104C, and a transistor 104D) on a substrate (wafer) 102.The device 100 and / or the electrically functional devices include various structural elements / components, such as a mesa 102' (e.g., an extension of the substrate 102), substrate isolation structures 106, semiconductor layers 110, gate structures 112 (each of which includes a respective gate stack 114 and respective gate spacers 116), internal spacers 118, source / drains 120, and a first-level dielectric layer (e.g., an ILDo, which may include a contact etch stop layer (CESL) 122 and an interlayer dielectric (ILD) layer 124). The various structural elements / components and their respective features are merely exemplary.The present disclosure contemplates a device 100 having any combination of structural elements / components and / or devices and any arrangement of such structural elements / components and / or devices that can be manufactured by FEOL processing.

[0010] In the illustrated embodiment, transistors 104A-104D are GAA transistors. For example, each of transistors 104A-104D has three channels (e.g., nanowires, nanosheets, nanorods, etc.) provided by semiconductor layers 110 suspended above substrate 102 and extending between respective source / drains (e.g., source / drains 120). In some embodiments, transistors 104A-104D have more or fewer channels (and thus more or fewer semiconductor layers 110). Each of transistors 104A-104D also has a respective gate stack 114 above its semiconductor layers 110, engaging its semiconductor layers 110, and between its source / drains 120 (e.g., epitaxial source / drains).Along a gate width direction (e.g., in XZ cross-sectional views), the gate stacks 114 are located above top semiconductor layers 110, between semiconductor layers 110, and between bottom semiconductor layers 110 and the substrate 102 (e.g., its mesa 102'). Along a gate length direction (e.g., in YZ cross-sectional views), the gate stacks 114 wrap around and / or surround respective semiconductor layers 110. During operation of the GAA transistors, current can flow through the semiconductor layers 110 and between source / drains 120.

[0011] The substrate 102 and the semiconductor layers 110 include an elemental semiconductor, such as silicon and / or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination thereof. In the illustrated embodiment, the substrate 102 and the semiconductor layers 110 include silicon. In some embodiments, the substrate 102 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate. The substrate 102 (including the mesas 102' extending therefrom) may include various doped regions, such as p-wells and n-wells.The n-wells are doped with an n-dopant such as phosphorus, arsenic, other n-dopants, or a combination thereof. The p-wells are doped with a p-dopant such as boron, indium, other p-dopants, or a combination thereof. In some embodiments, semiconductor layers 110 contain a p-dopant, an n-dopant, or a combination thereof.

[0012] The substrate isolation structures 106 electrically isolate active device regions and / or passive device regions. For example, active regions, such as transistors 104A-104D, are separated and electrically isolated from other device regions and / or devices by substrate isolation structures 106. The substrate isolation structures 106 include silicon oxide, silicon nitride, silicon oxynitride, another suitable insulating material (including silicon, oxygen, nitrogen, carbon, another suitable insulating component, or a combination thereof), or a combination thereof. The substrate isolation structures 106 may have a multi-layer structure. For example, the substrate isolation structures 106 include a bulk dielectric (e.g., an oxide layer) over a dielectric liner layer (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride, or a combination thereof).In another example, the substrate isolation structures 106 include a bulk dielectric over a doped liner layer, such as a borosilicate glass (BSG) liner layer and / or a phosphosilicate glass (PSG) liner layer. The dimensions and / or characteristics of the substrate isolation structures 106 are configured to provide shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, local oxidation of silicon (LOCOS) structures, other suitable isolation structures, or a combination thereof.

[0013] The gate stacks 114 are configured to achieve a desired functionality according to the design requirements of the device 100, and the gate stacks 114 of the transistors 104A-104D may include the same or different layers and / or materials. Each gate stack includes a respective gate dielectric 126 and a respective gate electrode 128. The gate dielectric 126 includes at least one gate dielectric layer, and the gate electrodes 128 include at least one electrically conductive gate layer. For example, the gate dielectric 126 may include an interface layer 130 and a high-k dielectric layer 132, and the gate electrodes 128 may include a work function layer 134, a bulk layer (volume fill layer) 136, and an inter-gate electrode layer 138. The interface layers 130 contain a dielectric material, such as SiO2, SiGeO x, HfSiO, SiON, another dielectric material, or a combination thereof. The high-k dielectric layer 132 contains a high-k dielectric material, which generally refers to dielectric materials with a dielectric constant greater than a dielectric constant of silicon dioxide (k ≈ 3.9), such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, another high-k dielectric material, or a combination thereof. The work function layer 134 is an electrically conductive layer tuned to have a desired work function, such as an n-type work function or a p-type work function. The work function layer 134 contains one or more work function metals and / or alloys thereof, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or a combination thereof. The bulk layer 136 contains Al, W, Co, Cu, polysilicon, another suitable electrically conductive material, alloys thereof, or a combination thereof.The inter-gate electrode layer 138 may include a cap (e.g., a metal nitride cap and / or a silicon cap over the work function layer 134) and / or a barrier layer (e.g., a metal nitride barrier over the cap and / or the work function layer 134). The inter-gate electrode layer 138 may include a material that prevents or eliminates diffusion and / or reaction of constituents between adjacent layers and / or promotes adhesion between adjacent layers, such as between the work function layer 134 and the bulk layer 136. In some embodiments, the inter-gate electrode layer 138 includes metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, another suitable metal nitride, or a combination thereof.In some embodiments, gate stacks 114 also include hard masks over gate electrodes 128 and between gate spacers 116. Hard masks include a material different from the first-level dielectric layer to achieve etch selectivity during subsequent processing. In some embodiments, the hard masks include silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, other silicon nitride, other silicon carbide, or a combination thereof. In some embodiments, hard masks include metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, zirconium aluminum oxide, other metal oxides, other metal nitrides, or a combination thereof.In some embodiments, the interface layer 130, the high-k dielectric layer 132, the work function layer 134, the bulk layer 136, the inter-gate electrode layer 138, another gate stack layer, or a combination thereof have a multi-layer structure.

[0014] Gate spacers 116 are disposed along sidewalls of uppermost portions of gate stacks 114, fin / mesa spacers may be disposed along sidewalls of mesas 102', and inner spacers 118 are disposed beneath gate spacers 116 along sidewalls of gate stacks 114. The inner spacers 118 are located between semiconductor layers 110, between semiconductor layers 110 and mesa 102', and between gate stacks 114 and source / drains 120. The gate spacers 116, the fin / mesa spacers, and the inner spacers 118 include a dielectric material. The dielectric material may contain silicon, oxygen, carbon, nitrogen, another suitable dielectric component, or a combination thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or a combination thereof).The gate spacers 116, the fin / mesa spacers, and the inner spacers 118 may include different materials and / or different features (e.g., different numbers of layers). In some embodiments, the gate spacers 116, the fin / mesa spacers, the inner spacers 118, or a combination thereof have a multi-layer structure. In some embodiments, the gate spacers 116 and / or the fin / mesa spacers include more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or a combination thereof. The different sets of spacers may have different compositions.

[0015] The source / drains 120 include semiconductor material that may be doped with n-type and / or p-type dopants. The source / drains 120 include multiple semiconductor layers and / or semiconductor materials, and each of the semiconductor layers / materials may include the same or different materials and / or the same or different doping concentrations. In some embodiments, the semiconductor material is grown epitaxially from the mesa 102' and / or the semiconductor layers 110, and the source / drains 120 may be referred to as epitaxial source / drains. In some embodiments, the source / drains 120 include silicon doped with carbon, phosphorus, arsenic, another n-type dopant, or a combination thereof (e.g., Si:C source / drains, Si:P source / drains, or Si:C:P source / drains).In some embodiments, the source / drains 120 include silicon germanium or germanium doped with boron, another p-type dopant, or a combination thereof (e.g., Si:Ge:B source / drains). The source / drains 120 may include the same or different compositions and / or materials depending on the devices of their respective transistors. For example, the source / drains 120 of n-type transistors may include silicon doped with phosphorus and / or carbon, and the source / drains 120 of p-type transistors may include silicon germanium doped with boron. In some embodiments, the source / drains 120 include materials and / or dopants that achieve the desired tensile and / or compressive stress in adjacent channel regions (e.g., semiconductor layers 110). As used herein, source / drain region, source / drain, source / drain feature, etc.refer to a source of a device (e.g., a source of one of the transistors 104A-104D), a drain of a device (e.g., a drain of one of the transistors 104A-104D), or a source and / or drain of multiple devices.

[0016] In some embodiments, the source / drains 120 include multiple semiconductor layers and / or semiconductor materials, and each of the semiconductor layers / materials may include the same or different materials and / or the same or different doping concentrations. For example, the source / drains 120 may include semiconductor layers 142, semiconductor layers 144, semiconductor layers 146, and semiconductor layers 148. The semiconductor layers 142 are disposed within the mesa 102', the semiconductor layers 144 are disposed over the semiconductor layers 142, the semiconductor layers 146 are disposed over the semiconductor layers 110 (e.g., along their sidewalls), and the semiconductor layers 148 are disposed between the semiconductor layers 144 and the semiconductor layers 146, and between the semiconductor layers 144 and the internal spacers 118.In some embodiments, semiconductor layers 142, semiconductor layers 144, semiconductor layers 146, and semiconductor layers 148 have different compositions. For example, semiconductor layers 142, semiconductor layers 144, semiconductor layers 146, and semiconductor layers 148 may contain the same semiconductor material but different doping concentrations. In some embodiments, semiconductor layers 142 are undoped. Source / drains 120 may further include a source / drain isolation structure 150, which may be referred to as flexible bottom isolation (FBI). A composition of source / drain isolation structure 150 differs from a composition of semiconductor layers 142 and semiconductor layers 144 to enable selective etching during processing, as described further below.For example, the source / drain isolation structures 150 include silicon and oxygen, nitrogen, carbon, or a combination thereof. In the illustrated embodiment, the source / drain isolation structures 150 are nitride layers, such as silicon nitride layers (e.g., SiN). x -layer). In some embodiments, a thickness of the source / drain isolation structures 150 (e.g., along the z-direction) is about 1 nm to about 10 nm.

[0017] The ILD layer 124 contains a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate (TEOS)-formed oxide, BSG, PSG, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB)-based dielectric material, polyimide, another suitable dielectric material, or a combination thereof. In some embodiments, the ILD layer 124 contains a dielectric material having a dielectric constant less than a dielectric constant of silicon dioxide. The CESL 122 contains a material that is different from a material of the ILD layer 124.For example, if ILD layer 124 includes a low-k dielectric material (e.g., porous silicon oxide), CESL 122 may include silicon and nitrogen and / or carbon, such as silicon nitride, silicon carbonitride, or silicon oxycarbonitride. In some embodiments, CESL 122 may include metal and oxygen, nitrogen, carbon, or a combination thereof. In some embodiments, ILD layer 124 and / or CESL 122 have a multilayer structure.

[0018] With reference to Fig. 1 and Fig. 3, the method 10 includes, in block 20, forming a front-side source / drain contact on a source / drain of a transistor, such as front-side source / drain contacts 160 on sources / drains 120 of transistors 104A-104D. The front-side source / drain contacts 160 include an electrically conductive material, such as tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, another suitable metal, alloys thereof, or a combination thereof. In some embodiments, the front-side source / drain contacts 160 are barrier-free / liner-free metal plugs, such as tungsten plugs, cobalt plugs, or ruthenium plugs. For example, the front-side source / drain contacts 160 may each include a bulk metal layer (i.e.,a metal plug, such as a tungsten plug, that physically directly contacts surrounding dielectric materials, such as contact spacers 166 and / or a second-level dielectric layer (e.g., a CESL 162 and / or an ILD layer 164). In some embodiments, the front-side source / drain contacts 160 include bulk metal layers and one or more barrier / liner layers. The barrier / liner layers are located between the bulk metal layers and surrounding dielectric materials.

[0019] Forming front-side source / drain contacts 160 may include: depositing the second-level dielectric layer (e.g., an ILD1, which may include a CESL 162 and an ILD layer 164) over the first-level dielectric layer (e.g., the ILDo, which may include a CESL 122 and an ILD layer 124), patterning the second-level dielectric layer and the first-level dielectric layer to form front-side source / drain contact openings extending therethrough and exposing source / drains 120 (e.g., their semiconductor layers 144), depositing one or more electrically conductive materials over the second-level dielectric layer filling the front-side source / drain contact openings, and performing a planarization process (e.g., chemical mechanical polishing (CMP)) to form portions of the one or more electrically conductive materials. remove,disposed over the second-level dielectric layer. The CESL 162 and the ILD layer 164 are similar to the CESL 122 and the ILD layer 124 described above. The planarization process may be performed until the second-level dielectric layer is reached and exposed, and remnants of the electrically conductive material(s) form one or more layers of front-side source / drain contacts 160. In some embodiments, prior to deposition of the electrically conductive material(s), one or more insulation layers may be formed and patterned in the front-side source / drain contact openings to form contact spacers 166. The contact spacers 166 are disposed along sidewalls of the front-side source / drain contacts 160.and the contact spacers 166 are located between the front-side source / drain contacts 160 and the surrounding dielectric material (e.g., the second-level dielectric layer and the first-level dielectric layer). The contact spacers 166 comprise dielectric layers and / or air gaps.

[0020] Prior to depositing the electrically conductive material(s), a silicide process may be performed to form front-side silicide layers 168 over top surfaces and front surfaces of source / drains 120, such that front-side silicide layers 168 are located between top surfaces of source / drains 120 (formed, for example, by semiconductor layers 144 and their semiconductor layers 148) and front-side source / drain contacts 160. In embodiments where front-side source / drain contacts 160 include barrier / liner layers, the barrier / liner layers may be located between the bulk metal layers and front-side silicide layers 168.The silicidation process may include depositing a metal layer over source / drains 120 (e.g., their semiconductor layers 144 and semiconductor layers 148) using a suitable deposition process and heating device 100 (e.g., by subjecting it to an annealing process) to cause components of source / drains 120 to react with metal components in the metal layer. In some embodiments, the silicidation process consumes portions of source / drains 120 and converts them into front-side silicide layers 168. The metal layer includes metal components suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, another suitable metal, or a combination thereof.The front-side silicide layers 168 may thus include a metal component and a component of the source / drains 120 (e.g., silicon and / or germanium). In some embodiments, the metal layer is a titanium-containing layer, and the front-side silicide layers 168 include titanium and silicon and / or germanium. In some embodiments, the metal layer is a cobalt-containing layer, and the front-side silicide layers 168 include cobalt and silicon and / or germanium. In some embodiments, the metal layer is a nickel-containing layer, and the front-side silicide layers 168 include nickel and silicon and / or germanium. Any unreacted metal is selectively removed by a suitable process.

[0021] In some embodiments, prior to depositing the electrically conductive material(s), an etch process is performed to extend the front-side source / drain contact openings into the source / drains 120 and beneath top surfaces of the topmost semiconductor layers 110. Such a process may be referred to as a source / drain etch-back and / or a source / drain recess. After recessing, the front-side source / drain contact openings extend a distance beneath the first-level dielectric layer and / or the top surfaces of the topmost semiconductor layers 110. The distance runs between bottom surfaces of the front-side source / drain contact openings and top surfaces of the topmost semiconductor layers 110 (and / or bottom surfaces of the first-level dielectric layer). Furthermore, after recessing, the source / drains 120 may have recessed, concave top surfaces forming bottom surfaces of the front-side source / drain contact openings.In the illustrated embodiment, the recessed, concave top surfaces are formed by semiconductor layers 144 and semiconductor layers 148, and the front-side silicide layers 168 are conformally formed on the recessed, concave top surfaces such that the front-side silicide layers 168 have curved, concave profiles. The source / drain recess increases the contact area between top and front surfaces of source / drains 120 and front-side source / drain contacts 160, which can reduce contact resistance (e.g., that developed between source / drains (epi) and front-side source / drain (MD) contacts (e.g., the epi-to-MD contact resistance)) and thereby improve the performance of the device 100.

[0022] With reference to Fig. 1 and Fig. 4-6, the method 10 may include, in block 25, turning over and thinning the workpiece (e.g., the device 100). With reference to Fig. 4, the flipping / thinning may include bonding and / or attaching a carrier substrate 170 to a front side (FS) of the device 100 formed by front-side source / drain contacts 160 and the second level dielectric layer. With reference to Fig. 5, the flipping / thinning may include flipping the device 100 such that the back side (BS) of the device 100 is oriented upwards, the front side FS of the device 100 is oriented downwards, and the carrier substrate 170 forms a bottom side of the device 100. With reference to Fig. 6, the flipping / thinning may include performing a thinning process to reduce the thickness of the substrate 102 (e.g., along the z-direction). The thinning process is applied to the backside BS of the device 100, and in the illustrated embodiment, the thinning process reduces a thickness of the substrate 102 above source / drains 120. In some embodiments, extensions of the substrate 102 (i.e., mesa 102') remain after the thinning process. The thinning process may be a grinding process, a planarization process (e.g., CMP), an etching process, another suitable process, or a combination thereof. In some embodiments, the thinning process stops upon reaching the substrate isolation structures 106. In some embodiments, the thinning process may reduce a thickness of the substrate isolation structures 106 (e.g., along the z-direction).

[0023] In Fig. 4, bonding may include forming a bonding layer 174 (e.g., a first dielectric layer) over the front side FS of the device 100, forming a bonding layer 176 (e.g., a second dielectric layer) over the carrier substrate 170, flipping and placing the carrier substrate 170 over the front side FS of the device 100 such that the bonding layer 176 contacts the bonding layer 174, and performing an annealing process and / or other suitable process to effect bonding of the bonding layer 174 and the bonding layer 176. In such embodiments, the bonding layer 174 and / or a portion thereof, the bonding layer 176 and / or a portion thereof, a bonded portion of the bonding layer 174 and the bonding layer 176, or a combination thereof may form a bonding layer 178 between the carrier substrate 170 and the front side FS of the device 100.In some embodiments, the bond is a dielectric-to-dielectric bond. In such embodiments, bonding layer 178, bonding layer 176, and bonding layer 174 are dielectric layers, and the dielectric layers may include silicon, oxygen, nitrogen, carbon, other suitable dielectric constituents, or a combination thereof. For example, bonding layer 176 and bonding layer 174 may be nitride layers, such as silicon nitride layers. In another example, bonding layer 176 and bonding layer 174 may be oxide layers. In some embodiments, support substrate 170 includes silicon, soda-lime glass, fused silica, fused silica, calcium fluoride, another suitable support substrate material, or a combination thereof.

[0024] With reference to Fig. 1 and Fig. 7-14, the method 10 includes, in block 30, forming a backside source / drain via on a source / drain of the transistor, such as backside source / drain vias 230 on bottoms and backsides of the sources / drains 120 of the transistors 104A-104D ( Fig. 14). Processing including the formation of backside source / drain vias 230 is performed on the backside BS of the device 100. Referring to Fig. 1 and Fig. 7, the method 10 includes, in block 35, forming a two-layer hard mask over a backside of the workpiece, such as a two-layer hard mask 180 over the backside BS of the device 100 formed by the substrate 102 (e.g., its mesa 102') and substrate isolation structures 106. The two-layer hard mask 180 includes a hard mask layer 182 and a hard mask layer 184. The hard mask layer 182 is disposed on the backside BS of the device 100, and the hard mask layer 184 is disposed on the hard mask layer 182. A thickness of the hard mask layer 182 is less than a thickness of the hard mask 184. In some embodiments, a thickness of the hard mask layer 182 is about 5 nm to about 30 nm. In some embodiments, a thickness of the hard mask layer 184 is about 10 nm to about 100 nm.The hard mask layer 182 and the hard mask layer 184 are formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable process, or a combination thereof. The hard mask layer 182 and the hard mask layer 184 may be formed by the same type of deposition process or by different types of deposition processes. In some embodiments, the hard mask layer 182 is a layer deposited in a furnace. In some embodiments, the hard mask layer 184 is a layer deposited in a furnace.

[0025] A composition of the hard mask layer 182 differs from a composition of the hard mask 184 to enable its selective removal / etching / polishing (e.g., removing the hard mask layer 184 with at most negligible removal of the hard mask layer 182). Furthermore, because (1) the two-layer hard mask 180 functions as a mask for patterning (e.g., etching) the substrate 102 and (2) the hard mask layer 182 electrically isolates a backside of the substrate 102 from one or more subsequently formed backside routing layers, the composition of the hard mask layer 184 differs from a composition of the substrate 102, and the composition of the hard mask layer 182 differs from a composition of the substrate 102.In some embodiments, hard mask layer 182 and hard mask layer 184 each contain silicon and oxygen, nitrogen, carbon, or a combination thereof. For example, hard mask layer 182 may contain a silicon nitride layer (e.g., SiN). x -layer), and the hard mask layer 184 may be a silicon oxide layer (for example, a SiO y -layer). In such embodiments, the hard mask layer 184 and the hard mask layer 182 may be referred to as dielectric layers. In some embodiments, the hard mask layer 182 and the hard mask layer 184 may comprise any combination of compositions that can achieve the patterning functions, etch / polish stop functions, and isolation functions described herein.

[0026] With reference to Fig. 1 and Fig. 8, the method 10 includes, in block 40, patterning the two-layer hard mask to form an opening therein that exposes a portion of a substrate that overlaps the source / drain. For example, the two-layer hard mask 180 is patterned to form openings 190 therein that expose portions of the substrate 102 that overlap the source / drains 120. The openings 190 extend through the hard mask layer 184 and the hard mask layer 182 to expose the substrate 102. Block 40 of the method 10 may be referred to as a hard mask patterning step and / or a hard mask etch (HM) step.

[0027] The two-layer hard mask 180 may be patterned using a lithography process and an etching process. The lithography process may include forming a patterned mask layer 194 over the hard mask layer 184. Openings 196 are located in the patterned mask layer 194, each of which overlaps a backside of a respective one of the source / drains 120. The etching process may include transferring a pattern in the patterned mask layer 194 to the two-layer hard mask 180, for example, by removing portions of the hard mask layer 184 and the hard mask layer 182 exposed by the openings 196. The etching process may selectively remove the two-layer hard mask 180 with respect to the substrate 102. For example, the etching process etches the two-layer hard mask 180 with at most negligible etching of the substrate 102.An etchant of the etching process may etch dielectric material (e.g., hard mask layer 184 and hard mask layer 182) at a higher rate than a semiconductor material (e.g., substrate 102). The etching process may be a dry etch, a wet etch, another suitable etching process, or a combination thereof. In some embodiments, hard mask layer 184 and hard mask layer 182 are removed in a multi-stage process, such as a first etching process that selectively removes hard mask layer 184 with at most negligible etching of hard mask layer 182, and a second etching process that selectively removes hard mask layer 182 with at most negligible etching of substrate 102. For example, different etchants and / or etch parameters may be implemented to etch hard mask layer 184 and hard mask layer 182 separately.In such embodiments, the first etch process may partially remove the hard mask layer 184, or the first etch process may not remove (or may only negligibly remove) the hard mask layer 184. In some embodiments, the etch process partially or completely removes the patterned mask layer 194 over the two-layer hard mask 180. In some embodiments, the patterned mask layer 194 is removed after the etch process over the two-layer hard mask 180, for example, by an etch process and / or a resist stripping process.

[0028] With reference to Fig. 1 and Fig. 9, the method 10 includes, in block 45, patterning the exposed portion of the substrate to form a backside source / drain via opening that exposes the source / drain. For example, exposed portions of the substrate 102 are patterned to form backside source / drain via openings 200 therein that expose backsides of the respective source / drains 120. After patterning the substrate 102, the backside source / drain via openings 200 extend through the substrate 102 to expose the source / drains 120, such as their semiconductor layers 142. In the illustrated embodiment, the method 10 further comprises, in block 45, extending the backside source / drain via openings 200 by removing portions of the exposed source / drains 120, such as their semiconductor layers 142.Removing semiconductor layers 142 exposes source / drain isolation structures 150 from source / drains 120 and extends backside source / drain via openings 200 over bottom surfaces of gate stacks 114 and / or top surfaces of mesa 102'. Block 45 of method 10 may be referred to as a substrate patterning and / or etching step and / or as a source / drain via patterning and / or etching step (VB patterning and / or etching step).

[0029] The substrate 102 and the source / drains 120 may be patterned by an etching process. The etching process may include transferring a pattern in the two-layer hard mask 180 to the substrate 102, for example, by removing portions of the substrate 102 exposed by openings 190. The etching process may further include removing semiconductor layers 142 exposed by backside source / drain via openings 200. The etching process may selectively remove the substrate 102 and semiconductor layers 142 with respect to the two-layer hard mask 180 and the source / drain isolation structures 150. For example, the etching process etches the substrate 102 and / or the semiconductor layers 142 with at most negligible etching of the hard mask 180 and / or the source / drain isolation structures 150.An etchant of the etching process may etch semiconductor material (e.g., substrate 102 and semiconductor layers 142) at a higher rate than a dielectric material (e.g., two-layer hard mask 180 and source / drain isolation structures 150). The source / drain isolation structures 150 act as etch stop layers, and the etching of the substrate 102 and / or the semiconductor layers 142 may stop upon reaching the source / drain isolation structures 150. The etching process may be a dry etch, a wet etch, another suitable etching process, or a combination thereof.In some embodiments, the substrate 102 and the semiconductor layers 142 are removed in a multi-step process, such as a first etch process that selectively removes the substrate 102 with negligible etching of the two-layer hard mask 180 and the source / drains 120 (e.g., their semiconductor layers 142), and a second etch process that selectively removes the semiconductor layers 142 with negligible etching of the source / drain isolation structures 150. For example, different etchants and / or etch parameters may be used to etch the substrate 102 and the semiconductor layers 142 separately.

[0030] With reference to Fig. 1, Fig. 10 and Fig. 11, the method 10 includes, in block 50, forming via spacers in the backside source / drain via opening. For example, via spacers 210 are formed in the backside source / drain via openings 200. Via spacers 210 may electrically isolate subsequently formed backside source / drain vias from the substrate 102 and / or the gate stacks 114, thereby inhibiting and / or preventing electrical coupling of the subsequently formed backside source / drain vias to each other and / or to the gate stacks 114. Referring to Fig. 10, forming via spacers 210 may include forming a via spacer layer 210' over the two-layer hard mask 180, such as over its hard mask layer 184. The via spacer layer 210' lines and partially fills the backside source / drain via openings 200 in the substrate 102. The via spacer layer 210' further lines and partially fills the openings 190 in the two-layer hard mask 180.In the illustrated embodiment, the via spacer layer 210' is disposed directly on a top surface of the hard mask layer 184, on sidewalls of the backside source / drain via openings 200 (formed, for example, by the substrate 102), on sidewalls of the openings 190 (formed, for example, by the two-layer hard mask 180), and on bottoms of the backside source / drain via openings 200 (formed, for example, by the source / drain isolation structures 150). The via spacer layer 210' is formed by CVD, ALD, another suitable process, or a combination thereof. In some embodiments, the via spacer layer 210' is a layer deposited in a furnace.In some embodiments, the via spacer layer 210' is deposited conformally such that the via spacer layer 210' has a substantially uniform thickness across the various surfaces of the device 100. In some embodiments, a thickness of the via spacer layer 210' is about 1 nm to about 10 nm.

[0031] A composition of the via spacer layer 210' differs from a composition of the hard mask layer 184 to enable its selective etching / removal, and the via spacer layer 210' includes an electrically insulating material. For example, the via spacer layer 210' includes a dielectric material that differs from the dielectric material of the hard mask layer 184. The dielectric material includes silicon and oxygen, nitrogen, carbon, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, another suitable dielectric material, or a combination thereof). In some embodiments, such as illustrated here, the via spacer layer 210' includes the same material as the substrate isolation structures 150.For example, the via spacer layer 210' includes silicon and nitrogen, such as silicon nitride or silicon oxynitride. In such embodiments, the via spacer layer 210' may be referred to as a nitride layer, and the process of forming via spacers 210 may be referred to as a backside self-protected nitride redeposition (BSNR) deposition (DP) and etch (ET) step. In some embodiments, the via spacer layer 210' and the substrate isolation structures 150 include different materials and / or different compositions.

[0032] With reference to Fig. 11, an etch process extends the backside source / drain via openings 200 through the source / drain isolation structures 150 and exposes semiconductor layers 144 of the source / drains 120, forming source / drain isolation structure residues 150'. The etch process also removes portions of the via spacer layer 210'. For example, the etch process removes laterally oriented portions of the via spacer layer 210', such as portions of the via spacer layer 210' above the hard mask layer 184 and above the semiconductor layers 144. Remnants of the via spacer layer 210' form via spacers 210 along sidewalls of backside source / drain via openings 200 and along sidewalls of openings 190 in the two-layer hard mask 180.The etching process may reduce a thickness of the via spacer layer 210' such that a thickness of via spacers 210 is less than a thickness of the via spacer layer 210'. In some embodiments, a thickness of via spacers 210 (e.g., along the x-direction and / or the y-direction) is about 1 nm to about 10 nm. Because the backside source / drain via openings 200 are first formed into source / drain isolation structures 150, the source / drain isolation structure residues 150' are located between via spacers 210 and semiconductor portions of the source / drains 120 (e.g., semiconductor layers 144 and their semiconductor layers 148).In the illustrated embodiment, after the etch process, the backside source / drain via openings 200 have sidewalls formed by via spacers 210 and source / drain isolation structure residues 150', and bottoms formed by semiconductor layers 144. Furthermore, the semiconductor layers 144 of the exposed source / drains 120 forming the bottoms of the extended backside source / drain via openings 200 may have recessed, concave surfaces, thereby obtaining source / drains 120 with recessed, convex bottom surfaces when the device 100 is oriented upright (i.e., its backside BS is facing down and its frontside FS is facing up).Removing the backsides of the source / drains 120 increases the contact area between the bottom and backsides of the source / drains 120 and the subsequently formed backside source / drain vias, which may reduce the contact resistance (such as that developed between source / drains (epi) and backside source / drain vias (VB) (e.g., the epi-to-VB contact resistance)) and thereby improve the performance of the device 100.

[0033] The etching process may selectively remove the via spacer layer 210' and source / drain isolation structures 150 with respect to the hard mask layer 184 and semiconductor layers 144. For example, the etching process etches the via spacer layer 210' and source / drain isolation structures 150 with at most negligible etching of the hard mask layer 184 and the semiconductor layers 144. An etchant of the etching process may etch dielectric material having a first composition (e.g., the via spacer layer 210' and the source / drain isolation structures 150) at a higher rate than dielectric material having a second composition (e.g., the hard mask layer 184) and semiconductor material (e.g., the semiconductor layers 144). The etching process is a dry etch, a wet etch, another suitable etching process, or a combination thereof.In some embodiments, the etching process is a reactive ion etch (RIE). In some embodiments, where the via spacer layer 210' and source / drain isolation structures 150 are nitride layers (e.g., silicon nitride layers) and the hard mask layer 184 is an oxide layer (e.g., a silicon oxide layer), an etchant may selectively etch nitride with negligible oxide etching at most. In such embodiments, the etching process may remove portions of the via spacer layer 210' above the hard mask layer 184 and a portion of the via spacer layer 210' above the source / drain isolation structures 150, thereby exposing the source / drain isolation structures 150. The etching process continues with the removal of the exposed source / drain isolation structures 150 until the semiconductor layers 144 are reached and / or exposed.In some embodiments, the etching process may further expand the backside source / drain via openings 200 by removing and / or recessing the semiconductor layers 144. In some embodiments, an etchant for recessing the semiconductor layers 144 is different from an etchant used to etch the via spacer layer 210' and the source / drain isolation structures 150. In some embodiments, an etchant for recessing the semiconductor layers 144 is the same as an etchant used to etch the via spacer layer 210' and the source / drain isolation structures 150.For example, an etchant may selectively etch nitride (e.g., the via spacer layer 210' and the source / drain isolation structures 150) and silicon (or silicon germanium) (e.g., the semiconductor layers 144) with at most negligible etching of oxide (e.g., the hard mask layer 184). In such embodiments, the etchant may have an etch selectivity between nitride and silicon (or silicon germanium) that achieves a desired removal of the semiconductor layers 144. Furthermore, in such embodiments, parameters of the etch process (e.g., etch duration, etch temperature, etc.) may be tuned to achieve a desired recess of the semiconductor layers 144 and a desired removal of the via spacer layer 210' and source / drain isolation structures 150.

[0034] With reference to Fig. 1 and Fig. 12, the method 10 includes, at block 55, forming a silicide layer on the exposed source / drain. For example, a silicide process may be performed to form backside silicide layers 220 over bottom and backsides of exposed source / drains 120, which may be formed by their semiconductor layers 144. In the illustrated embodiment, backside silicide layers 220 are conformally formed on the recessed, convex surfaces of the exposed source / drains 120 such that the backside silicide layers 220 have curved, convex profiles when the device 100 is oriented upright (i.e., its backside BS is facing down and its frontside FS is facing up). In this way, some source / drains 120 are sandwiched between backside silicide layers 220 and frontside silicide layers 168.Because the backside source / drain via openings 200 are extended over the gate stacks 114 and / or tops of the mesa 102', the backside silicide layers 220 are disposed over the source / drain isolation structure residues 150' and via spacers 210 when the device 100 is oriented upright. In the illustrated embodiment, each backside silicide layer 220 is disposed on a respective semiconductor layer 144, between respective semiconductor layers 148, and between respective source / drain isolation structure residues 150'. In some embodiments, a thickness of the backside silicide layers 220 (e.g., along the z-direction) is about 1 nm to about 20 nm. In some embodiments, a thickness of the backside silicide layers 220 is substantially uniform.

[0035] The silicidation process may include depositing a metal layer over the hard mask layer 184, the via spacers 210, the source / drain isolation structure residues 150', and the exposed source / drains 120 (e.g., their semiconductor layers 144) using a suitable deposition process and heating the device 100 (e.g., by subjecting it to an annealing process) to cause constituents of the source / drains 120 to react with metal constituents in the metal layer. The metal layer at least partially fills the backside source / drain via openings 200. In some embodiments, the deposition process is CVD. In some embodiments, the metal layer is a layer deposited in a furnace. In some embodiments, the metal layer is a layer deposited by sputtering.In some embodiments, the silicidation process consumes portions of the source / drains 120 (e.g., their semiconductor layers 144) and converts them into backside silicide layers 220. The metal layer includes metal components suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, another suitable metal, or a combination thereof. The backside silicide layers 220 may thus include a metal component and a component of the source / drains 120 (e.g., silicon and / or germanium). In some embodiments, the metal layer is a titanium-containing layer, and the backside silicide layers 220 include titanium and silicon and / or germanium. In some embodiments, the metal layer is a cobalt-containing layer, and the backside silicide layers 220 include cobalt and silicon and / or germanium.In some embodiments, the metal layer is a nickel-containing layer, and the backside silicide layers 220 contain nickel and silicon and / or germanium.

[0036] Any unreacted metal is selectively removed by a suitable process. In some embodiments, an etching process selectively removes the metal layer and / or unreacted metal with respect to the hard mask layer 184, the via spacers 210, and the source / drain isolation structure residues 150'. For example, the etching process etches the metal layer with negligible etching of the hard mask layer 184, the via spacers 210, the source / drain isolation structure residues 150', and the backside silicide layers 220. An etchant of the etching process may etch metal material (e.g., the metal layer) at a higher rate than dielectric material (e.g., the hard mask layer 184, the via spacers 210, and the source / drain isolation structure residues 150') and metal and semiconductor material (e.g., the backside silicide layers 220).The etching process is a dry etch, a wet etch, another suitable etching process, or a combination thereof. In some embodiments, such as illustrated here, the etching process may be tuned such that the metal layer is selectively etched, but the hard mask layer 184, the via spacers 210, the source / drain isolation structure residues 150', or a combination thereof may only be partially and / or negligibly etched. In such embodiments, a thickness of the via spacers 210 (e.g., along the x-direction and / or the y-direction) and / or a thickness of the hard mask layer 184 (e.g., along the z-direction) may be reduced by the etching process.Accordingly, a thickness of via spacers 210 after forming the backside silicide layers 220 may be less than a thickness of via spacers 210 before forming the backside silicide layers 220, and / or a thickness of the hard mask layer 184 after forming the backside silicide layers 220 may be less than a thickness of the hard mask layer 184 before forming the backside silicide layers 220. Furthermore, a length of via spacers 210 (e.g., along the z-direction) may be reduced during formation of the backside silicide layers 220. In some embodiments, such as illustrated here, portions of via spacers 210 along sidewalls of the hard mask layer 184 that form openings 190 are removed.In some embodiments, a width and / or a length of source / drain isolation structure residues 150' (e.g., along the x-direction and / or the y-direction) may also be reduced by the etching process. A width / length of source / drain isolation structure residues 150' after forming backside silicide layers 220 may thus be smaller than a width / length of source / drain isolation structure residues 150' before forming backside silicide layers 220.

[0037] With reference to Fig. 1, Fig. 13 and Fig. 14, the method 10 includes, in block 60 and block 65, forming backside source / drain vias 230. The backside source / drain vias 230 are formed in backside source / drain via openings 200 and openings 190 such that the backside source / drain vias 230 extend through the hard mask layer 182, through the substrate 102 (e.g., its mesa 102'), and to the bottoms and backsides of source / drains 120 (formed, for example, by their semiconductor layers 144). In the illustrated embodiment, the backside silicide layers 220 are located between the backside source / drain via openings 230 and the bottoms of the source / drains 120.The backside source / drain vias 230 include tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, another suitable metal, alloys thereof, or a combination thereof. In the illustrated embodiment, the backside source / drain vias 230 are barrier-free metal plugs. For example, the backside source / drain vias 230 include bulk metal layers, such as tungsten plugs or cobalt plugs, that directly physically contact the surrounding dielectric materials, such as via spacers 210, source / drain isolation structure residues 150', the hard mask layer 182, or a combination thereof.In some embodiments, one or more backside source / drain vias 230 include a bulk metal layer and a metal liner, with the metal liner located between the bulk metal layer and the surrounding dielectric materials. In such embodiments, the metal liner may be located between the bulk metal layer and backside silicide layers 220. In some embodiments, a thickness of the backside source / drain vias 230 (e.g., along the z-direction) is about 100 nm to about 500 nm.

[0038] With reference to Fig. 1 and Fig. 13, the method 10 includes, in block 60, depositing electrically conductive material (e.g., source / drain via material 230') in the backside source / drain via opening (e.g., backside source / drain via openings 200) over the silicide layer (e.g., backside silicide layers 220) and the via spacers (e.g., via spacers 210). Source / drain via material 230' is formed over the hard mask layer 184, fills backside source / drain via openings 200, and fills openings 190 in the two-layer hard mask 180. The source / drain via material 230' includes tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, another suitable metal, alloys thereof, or a combination thereof.The source / drain via material 230' is formed by physical vapor deposition (PVD), CVD, ALD, sputter deposition, electroplating, electroless plating, another suitable deposition process, or a combination thereof. In the illustrated embodiment, the source / drain via material 230' (e.g., tungsten or cobalt) is formed by a blanket deposition process (e.g., blanket CVD or blanket PVD), which may include introducing a metal-containing precursor (e.g., a tungsten-containing precursor, such as WF6 and / or WCl5, or a cobalt-containing precursor) and a reactant precursor (e.g., H2, another suitable reactant gas, or a combination thereof) into a process chamber.A carrier gas may be used to deliver the metal-containing precursor gas and / or the reactant gas into the process chamber. The carrier gas may be an inert gas, such as an argon-containing gas, a helium-containing gas, a xenon-containing gas, another suitable inert gas, or a combination thereof. In some embodiments, a bottom-up deposition process is implemented to fill backside source / drain via openings 200 with source / drain via material 230' (e.g., tungsten or cobalt) from the bottom up.The bottom-up deposition process (e.g., selective CVD) may include introducing a metal-containing precursor (e.g., a tungsten-containing precursor such as WF6 and / or WCl5, or a cobalt-containing precursor), a reactant precursor (e.g., H2, another suitable reactant gas, or a combination thereof), and a carrier gas into a process chamber, and tuning deposition parameters to selectively grow source / drain via material 230' from backside silicide layers 220 and / or metal seed layers while limiting the growth of source / drain via material 230' from dielectric materials (e.g., via spacers 210).The deposition parameters may include deposition precursors (e.g., metal precursors and / or reactant precursors), precursor flow rates, deposition temperature, deposition time, deposition pressure, source power, bias voltage, bias power, other suitable deposition parameters, or a combination thereof. In some embodiments, the bottom-up deposition process includes multiple deposition / etch cycles.

[0039] With reference to Fig. 1 and Fig. 14, the method 10 includes, at block 65, performing a planarization process (e.g., CMP) to remove excess source / drain via material 230', such as that disposed over the dual-layer hard mask 180. Residual source / drain via material 230' filling the backside source / drain via openings 200 and openings 190 form backside source / drain vias 230. The planarization process further removes a top layer of the dual-layer hard mask, such as the hard mask layer 184 of the dual-layer hard mask 180, such that backside source / drain vias 230 and the hard mask layer 182 form the backside BS of the device 100.In such embodiments, the planarization process may be performed until the hard mask layer 182 is reached and / or exposed, and the hard mask layer 182 may function as a planarization stop layer (e.g., a CMP stop layer). Bottom surfaces of the backside source / drain vias 230 may be planarized such that a bottom surface of the hard mask layer 182 and the bottom surfaces of the backside source / drain vias 230 form a substantially planar surface.

[0040] The processing associated with forming front-side source / drain contacts 160 and back-side source / drain vias 230 may generally be referred to as middle-of-line (MOL) processing, which generally refers to the fabrication of MOL interconnects that physically and / or electrically connect FEOL features (e.g., electrically active features of a device) to first metallization layers (levels) formed during back-end-of-line (BEOL) processing. The processing may further include BEOL processing to form front-side routing layers and / or back-side routing layers (generally referred to as BEOL features) that are electrically connected to front-side source / drain contacts 160 and back-side source / drain vias 230. For example, with reference to Fig. 1 and Fig.15 - the method 10 in block 80, forming a front side power rail (e.g., a front side power rail 240) connected to the front side source / drain contact (e.g., one or more of the front side source / drain contacts 160) and a back side power rail (e.g., a back side power rail 250) connected to the back side source / drain via (e.g., one or more of the back side source / drain vias 230). The backside power rail is formed on a lower layer of the two-layer hard mask, such as hard mask layer 182 of the two-layer hard mask 180. The frontside power rail 240 is electrically connected to frontside source / drain contacts 160 through frontside source / drain vias 260, and the backside power rail 250 is electrically and physically connected to backside source / drain vias 230.Accordingly, some of the source / drains 120 are electrically connected to both the front power rail 240 (e.g., through front source / drain contacts 160 and front source / drain vias 260) and the back power rail 250 (e.g., through back source / drain vias 230) such that power may be supplied to the transistors 104A-104D through the front power rail 240 (via front source / drain vias 260 and front source / drain contacts 160) and / or the back power rail 250 (via back source / drain vias 230). Equipping transistors 104A-104D with double-ended power rails lowers the resistance associated with power supply, which can reduce IR drop and improve the performance of device 100.Furthermore, because the hard mask layer 182 (e.g., a dielectric layer such as a silicon nitride layer) remains between the backside power rail 250 and the substrate 102, the electrical isolation between the backside power rail 250 and the gate stacks 114 and between the backside power rail 250 and source / drains 120 is improved, which may improve the performance of the device 100. Furthermore, providing two-sided power rails reduces an area occupied by the device 100. In some embodiments, the frontside power rail 240 is electrically connected to the backside power rail 250. In some embodiments, the source / drains 120 that are electrically connected to both the frontside power rail 240 and the backside power rail 250 are sources of the transistors 104A-104D.In such embodiments, other source / drains 120 of transistors 104A-104D may be their drains, which may be electrically connected to ground. Different embodiments may have different advantages, and no specific advantage is required for each embodiment.

[0041] In some embodiments, processing prior to forming the front-side power rail 240 may include flipping the device 100 such that the device 100 is oriented upright (e.g., the front side FS of the device faces up and the back side BS of the device faces down), and may include performing a thinning process and / or a debonding process to remove the carrier substrate 170 and the bonding layer 178 from the front side FS of the device structure 100. For example, a planarization process (e.g., CMP) and / or an etch process removes the carrier substrate 170 and the bonding layer 178, exposing the front-side source / drain contacts 160 and the second-level dielectric layer (e.g., the ILD layer 164).The planarization process may stop upon reaching the front-side source / drain contacts 160 and / or the second-level dielectric layer. In some embodiments, the carrier substrate 170 and the bonding layer 168 are removed after forming the back-side source / drain vias 230. In some embodiments, the carrier substrate 170 and the bonding layer 168 are removed after forming the back-side power rail 250.

[0042] The front-side power rail 240 and the front-side source / drain vias 260 may form a portion of a first front-side metallization layer / level of a front-side multilayer interconnect (FMLI). Forming the first front-side metallization layer / level may include forming a dielectric layer 270 over the second-level dielectric layer (e.g., ILD1, such as the ILD layer 164 and / or the CESL 162), patterning the dielectric layer 270 to form openings therein that expose front-side source / drain contacts 160, and forming one or more electrically conductive materials in the openings to form vias 260, a front-side power rail 240 (e.g., a metal line), other metal lines, or a combination thereof.The metal lines of the first front-side metallization layer (e.g., the front-side power rail 240 and / or other metal lines) may be collectively referred to as a front-side metal zero (FMo) layer (and may be individually referred to as FMo metal lines). The vias of the first front-side metallization layer (e.g., the source / drain vias 260) may be collectively referred to as a front-side via zero (FVo) layer (and may be individually referred to as FVo (or VF) vias). In such embodiments, the first front-side metallization layer is a bottom routing layer of the front-side MLI, the FMo layer is a bottom front-side metal routing layer of the front-side MLI, and the FVo layer is a bottom via layer of the front-side MLI.In some embodiments, the dielectric layer 270 is a third-level dielectric layer (e.g., an ILD2, which may include an ILD layer over a CESL). In some embodiments, the dielectric layer 270 comprises a third-level dielectric layer (e.g., an ILD2) and a fourth-level dielectric layer (e.g., an ILD3, which may include an ILD layer over a CESL), with vias 260 formed in the third-level dielectric layer and the front-side bus bar 240 formed in the fourth-level dielectric layer.

[0043] The backside power rail 240 may form a portion of a first backside metallization layer / level of a backside interconnect (BI) structure, which may be a backside power delivery network (PDN) (e.g., a routing structure for powering the device 100 from a backside). Forming the first backside metallization layer / level may include forming a dielectric layer 280 over a hard mask 182, patterning the dielectric layer 280 to form openings therein that expose backside source / drain vias 230, and forming one or more electrically conductive materials in the openings to form a backside power rail 250 (e.g., a metal line) and / or other metal lines.The metal lines of the first backside metallization layer (e.g., backside power rail 250 and / or other metal lines) may be collectively referred to as a backside metal zero (BMo) layer (and may individually be referred to as BMo metal lines). In such embodiments, the first backside metallization layer is a bottom backside routing layer, which may be a portion of a backside MLI and / or other backside interconnect structure, and the BMo layer is a bottom backside metal line layer. In some embodiments, the dielectric layer 280 comprises an ILD layer and may include a CESL.

[0044] The front-side BEOL processing may include forming additional metallization layers (levels) 290 of the front-side MLI over the first front-side metallization layer, and the back-side BEOL processing may include forming additional metallization layers (levels) 295 of the BI structure over the first back-side metallization layer.For example, front-side BEOL processing includes forming a second front-side metallization layer (i.e., a front-side metal one layer (FM1 level) and a front-side via one layer (FV1 level)), a third front-side metallization layer (i.e., a front-side metal two layer (FM2 level) and a front-side via two layer (FV2 level)), a fourth front-side metallization layer (i.e., a front-side metal three layer (FM3 level) and a front-side via three layer (FV3 level)), and so on, up to a top front-side metallization layer (i.e., a front-side metal X layer (FMX level) and a front-side via X layer (FVX level)). X is an integer of at least 1.Each level of the front-side MLI includes a respective patterned electrically conductive layer (e.g., lines, conductive vias, conductive contacts, or a combination thereof) disposed within a respective isolation layer (e.g., an ILD layer and / or a CESL). For example, the FVo level includes a portion of the dielectric layer 270 in which FVo vias are disposed, and the FMo level includes a portion of the dielectric layer 270 in which FMo lines are disposed. Backside BEOL processing may further include forming various backside metallization layers, such as a second backside metallization layer including a backside metal one (BM1) layer and a backside via one (BV1) layer connected to the first backside metallization layer.For example, one or more BM1 lines may be electrically connected to the backside power rail 250 through BV1 vias. Although the frontside MLI and BI structure is illustrated with a given number of metallization layers within a given number of dielectric layers, the frontside MLI and BI structure may also include more or fewer line layers, via layers, and dielectric layers depending on the design requirements. In some embodiments, the frontside MLI has seven to fourteen frontside metallization layers (e.g., FMo to FM14 and FV1 to FV14), and the BI has fewer backside metallization layers than the frontside MLI.

[0045] FMo-FMX lines, BMo lines, and other backside lines may be referred to as BEOL lines, and FVo-FVX vias and backside vias may be referred to as BEOL vias. BEOL lines and BEOL vias are formed by any suitable process and include any suitable materials, layers, features, etc. In some embodiments, BEOL interconnect structures, such as a metal line and a metal via of a given metallization level (e.g., an FMo interconnect structure may include a respective FVo via and a respective FMo line connected thereto), may be formed by a dual damascene process, which includes simultaneously depositing materials for the metal via and the metal line.In such embodiments, the metal via and the metal line may share a liner and a metal plug, rather than each having its own liner and metal plug. In some embodiments, the dual damascene process includes performing a patterning process to form an interconnect opening extending through a dielectric layer (e.g., dielectric layer 270) to expose an underlying interconnect structure (e.g., a metal line thereof).The patterning process may include a first lithography step and a first etching step to form a trench opening of the interconnect opening (corresponding to the metal line) in the dielectric layer, a second lithography step and a second etching step to form a via opening of the interconnect opening (corresponding to the metal via) in the dielectric layer, and—in some embodiments—a third etching step to remove a portion of the dielectric layer to expose the underlying interconnect structure. The first lithography step / first etching step and the second lithography step / second etching step may be performed in any order (e.g., trench-first, via-last, or via-first, trench-last).In some embodiments, the first etching step and the second etching step are each configured to selectively remove an ILD layer with respect to a patterned mask layer and a CESL, while the third etching step is configured to selectively remove the CESL with respect to the ILD and the underlying BEOL interconnect structure. After performing the patterning process, the dual damascene process may include performing a first deposition process to form a barrier / liner material partially filling the interconnect opening, performing a second deposition process to form a bulk metal material over the barrier / liner material, wherein the bulk metal material fills the remainder of the interconnect opening, and performing a planarization process to remove excess bulk metal material and barrier / liner material.The barrier / liner material and the bulk metal material fill the trench opening and the via opening of the interconnect opening without interruption, such that the liner and the metal plug each extend continuously without interruption from the metal line to the via.

[0046] The front-side MLI connects devices of device 100 (e.g., transistors 104A-104D), components of device 100, devices (e.g., a memory device) within the front-side MLI, components of the front-side MLI, or a combination thereof to each other and / or to external devices / components such that the various devices and / or components can operate as needed. The front-side MLI includes a combination of insulation layers and electrically conductive layers (e.g., patterned metal layers formed by lines, conductive vias, conductive contacts, or a combination thereof) arranged to form interconnect / routing structures.The conductive layers form vertical interconnect structures, such as device-level contacts, vias, and through-holes, that connect horizontal interconnect structures, such as lines, in different layers / planes (or different levels) of the front-side MLI. In some embodiments, the interconnect structures route electrical signals between devices and / or components of device 100 and / or the front-side MLI. In some embodiments, the interconnect structures route electrical signals to and / or from the devices and / or device components of the front-side MLI and / or the front-side MLI.During operation of the device 100, the front-side source / drain contacts 160, the back-side source / drain vias 230, the first front-side metallization layer (e.g., the FMo level including the front-side power rail 240 and the front-side source / drain vias 260), the first back-side metallization layer (e.g., the BMo level including the back-side power rail 250), other metallization layers of the front-side MLI, other metallization layers of the back-side interconnect structure, or a combination thereof may route signals between the devices and / or their components and / or distribute signals (e.g., clock signals, voltage signals, ground signals, other signals, or a combination thereof) to / from the devices, the components of the devices, external devices, or a combination thereof.For example, transistors 104A-104D may be powered by front-side power rail 240 (via front-side source / drain vias 260 and front-side source / drain contacts 160) and / or back-side power rail 260 (via back-side source / drain vias 230). In some embodiments, MOL features / structures form a portion of the front-side MLI.

[0047] The present disclosure allows for many different embodiments. An exemplary method includes forming a two-layer hard mask over a backside of a substrate. The two-layer hard mask includes a first hard mask layer over the backside of the substrate and a second hard mask layer over the first hard mask layer.The method further comprises: patterning the two-layer hard mask to form a hard mask opening therein exposing a portion of the substrate overlapping a source / drain, forming a backside source / drain via opening in the substrate exposing the source / drain by patterning the exposed portion of the substrate using the two-layer hard mask, forming a backside source / drain via in the backside via opening and the hard mask opening, and, after removing the second hard mask layer, forming a backside metallization layer over the first hard mask layer and the backside source / drain via.

[0048] In some embodiments, the method further comprises: extending the backside source / drain via opening by removing a first semiconductor portion of the source / drain to expose a source / drain isolation structure of the source / drain, and extending the backside source / drain via opening through the source / drain isolation structure of the source / drain when forming via spacers along sidewalls of the backside source / drain via opening.In some embodiments, forming via spacers comprises depositing a dielectric layer over the second hardmask layer, along sidewalls of the hardmask opening formed by the two-layer hardmask, along sidewalls of the backside source / drain via opening formed by the substrate, and over a bottom of the backside source / drain via opening formed by the exposed source / drain, and etching the dielectric layer. The etching may remove the dielectric layer over the second hardmask layer and the bottom of the backside source / drain via opening. In some embodiments, the first hardmask layer, the source / drain isolation structure, and the via spacers include silicon and nitrogen.

[0049] In some embodiments, the method further comprises forming a backside silicide layer over the exposed source / drain prior to forming the backside source / drain via. In some embodiments, removing the second hard mask layer comprises performing a planarization process that stops upon reaching the first hard mask layer. In some embodiments, forming the backside source / drain via opening comprises depositing an electrically conductive material over the second hard mask layer, filling the backside source / drain via opening, and performing the planarization process to remove excess electrically conductive material.

[0050] In some embodiments, the method further comprises applying a thinning process to the backside of the substrate prior to forming the two-layer hard mask. In some embodiments, the method further comprises forming a front-side source / drain contact and forming a front-side metallization layer over the front-side source / drain contact.

[0051] Another exemplary method includes forming a front-side source / drain contact on a source / drain of a transistor, forming a back-side source / drain via on the source / drain of the transistor, forming a front-side power rail over the front-side source / drain contact, and forming a back-side power rail over the back-side source / drain via. The front-side power rail is electrically connected to the front-side source / drain contact, and the back-side power rail is physically and electrically connected to the back-side source / drain via.Forming the backside source / drain via may include forming a first hard mask layer over a backside of a substrate, forming a second hard mask layer over the first hard mask layer, patterning the first hard mask layer and the second hard mask layer, patterning the substrate using the patterned first hard mask layer and the patterned second hard mask layer, and removing the patterned second hard mask layer. The patterned first hard mask layer may remain between the backside power rail and the backside of the substrate. In some embodiments, the method further includes applying a thinning process to the backside of the substrate prior to forming the backside source / drain via. In some embodiments, the source / drain is a source of a transistor.

[0052] In some embodiments, forming the first hard mask layer comprises depositing a nitride layer over the backside of the substrate, and forming the second hard mask layer comprises depositing an oxide layer on the nitride layer. In some embodiments, a first thickness of the first hard mask layer is less than a second thickness of the second hard mask layer.

[0053] In some embodiments, forming the back source / drain via comprises depositing an electrically conductive material in the patterned substrate, the patterned first hard mask layer, and the patterned second hard mask layer, and performing a planarization process that removes the patterned second hard mask layer. The planarization process may stop upon reaching the patterned first hard mask layer. In some embodiments, forming the back source / drain via comprises forming a back silicide layer, and forming the front source / drain contact comprises forming a front silicide layer. In such embodiments, the source / drain is located between the back source / drain via and the front source / drain contact.

[0054] In some embodiments, forming the backside source / drain via comprises recessing the source / drain, and forming the backside source / drain via comprises etching the source / drain isolation structure of the source / drain to expose a semiconductor portion of the source / drain. The recessing may stop upon reaching a source / drain isolation structure of the source / drain.

[0055] An exemplary device includes a front-side power rail disposed over a front side of a substrate, a back-side power rail disposed over a back side of the substrate, and an epitaxial source / drain structure disposed between the front-side power rail and the back-side power rail. The epitaxial source / drain structure is connected to the front-side power rail through a front-side source / drain contact, the epitaxial source / drain structure is connected to the back-side power rail through a back-side source / drain via, and the back-side source / drain via is disposed in a substrate. The device further includes a dielectric layer disposed between the substrate and the back-side power rail, wherein the back-side source / drain via extends through the dielectric layer.

[0056] In some embodiments, the device further comprises a backside silicide layer disposed between the backside source / drain via and a backside of the epitaxial source / drain structure, and a frontside silicide layer disposed between the frontside source / drain contact and a frontside of the epitaxial source / drain structure. In such embodiments, the source / drain of the epitaxial source / drain structure is disposed between the backside silicide layer and the frontside silicide layer.

[0057] In some embodiments, the backside source / drain via extends through a source / drain isolation structure of the epitaxial source / drain structure, and the source / drain isolation structure is disposed between the via spacers and the epitaxial source / drain structure. The via spacers are disposed along sidewalls of the backside source / drain via.

[0058] The above outlines features of various embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as those achieved by the embodiments presented herein. It should also be appreciated that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications to the present invention without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 510,727

[0001]

Claims

[1] Procedure which includes: Forming a two-layer hard mask over a backside of a substrate, the two-layer hard mask comprising a first hard mask layer over the backside of the substrate and a second hard mask layer over the first hard mask layer; Patterning the two-layer hard mask to form a hard mask opening therein that exposes a portion of the substrate overlapping a source / drain; Forming a backside source / drain via opening in the substrate exposing the source / drain by patterning the exposed portion of the substrate using the two-layer hard mask; Forming a backside source / drain via in the backside via opening and the hard mask opening; and after removing the second hard mask layer, forming a backside metallization layer over the first hard mask layer and the backside source / drain via. [2] The method of claim 1, further comprising: Extending the rear source / drain via opening by removing a first semiconductor portion of the source / drain to expose a source / drain isolation structure of the source / drain, and Extending the backside source / drain via opening through the source / drain isolation structure of the source / drain when forming via spacers along sidewalls of the backside source / drain via opening. [3] The method of claim 2, wherein forming via spacers comprises: Depositing a dielectric layer over the second hard mask layer, along sidewalls of the hard mask opening formed by the two-layer hard mask, along sidewalls of the backside source / drain via opening formed by the substrate, and over a bottom of the backside source / drain via opening formed by the exposed source / drain; and Etching the dielectric layer, removing the dielectric layer over the second hard mask layer and the bottom of the backside source / drain via opening. [4] The method of claim 2 or 3, wherein the first hard mask layer, the source / drain isolation structure and the via spacers comprise silicon and nitrogen. [5] The method of any preceding claim, further comprising forming a backside silicide layer over the exposed source / drain prior to forming the backside source / drain via. [6] A method according to any one of the preceding claims, wherein removing the second hard mask layer comprises performing a planarization process that stops upon reaching the first hard mask layer. [7] The method of claim 6, wherein forming the backside source / drain via opening comprises depositing an electrically conductive material over the second hard mask layer filling the backside source / drain via opening and performing the planarization process to remove excess electrically conductive material. [8] A method according to any one of the preceding claims, further comprising applying a thinning process to the backside of the substrate prior to forming the two-layer hard mask. [9] A method according to any one of the preceding claims, further comprising: Forming a front-side source / drain contact at the source / drain; and Forming a front-side metallization layer over the front-side source / drain contact. [10] Procedure which includes: Forming a front-side source / drain contact on a source / drain of a transistor; Forming a backside source / drain via on the source / drain of the transistor; Forming a front-side power rail over the front-side source / drain contact, the front-side power rail being electrically connected to the front-side source / drain contact; Forming a rear power rail over the rear source / drain via, the rear power rail being physically and electrically connected to the rear source / drain via; and wherein forming the backside source / drain via comprises forming a first hard mask layer over a backside of a substrate, forming a second hard mask layer over the first hard mask layer, patterning the first hard mask layer and the second hard mask layer, patterning the substrate using the patterned first hard mask layer and the patterned second hard mask layer, and removing the patterned second hard mask layer, wherein the patterned first hard mask layer remains between the backside power rail and the backside of the substrate. [11] The method of claim 10, wherein forming the first hard mask layer comprises depositing a nitride layer over the backside of the substrate and forming the second hard mask layer comprises depositing an oxide layer on the nitride layer. [12] The method of claim 10 or 11, wherein a first thickness of the first hard mask layer is less than a second thickness of the second hard mask layer. [13] The method of any one of the preceding claims 10 to 12, wherein forming the backside source / drain via comprises depositing an electrically conductive material in the patterned substrate, the patterned first hard mask layer and the patterned second hard mask layer and performing a planarization process removing the patterned second hard mask layer, wherein the planarization process stops upon reaching the patterned first hard mask layer. [14] The method of any one of the preceding claims 10 to 13, wherein forming the backside source / drain via comprises forming a backside silicide layer, forming the frontside source / drain contact comprises forming a frontside silicide layer, and the source / drain is located between the backside source / drain via and the frontside source / drain contact. [15] A method according to any one of the preceding claims 10 to 14, wherein: forming the backside source / drain via comprises recessing the source / drain, wherein the recessing stops upon reaching a source / drain isolation structure of the source / drain; and forming the backside source / drain via comprises etching the source / drain isolation structure of the source / drain to expose a semiconductor portion of the source / drain. [16] The method of any one of the preceding claims 10 to 15, further comprising applying a thinning process to the backside of the substrate prior to forming the backside source / drain via. [17] A method according to any one of the preceding claims 10 to 16, wherein the source / drain is a source of a transistor. [18] Device comprising: a front-side bus bar disposed over a front side of a substrate; a rear power rail disposed over a back surface of the substrate; an epitaxial source / drain structure disposed between the front-side power rail and the rear-side power rail, wherein the epitaxial source / drain structure is connected to the front-side power rail by a front-side source / drain contact, the epitaxial source / drain structure is connected to the rear-side power rail by a rear-side source / drain via, and the rear-side source / drain via is disposed in a substrate; and a dielectric layer disposed between the substrate and the rear power rail, wherein the rear source / drain via extends through the dielectric layer. [19] The apparatus of claim 18, further comprising: a backside silicide layer disposed between the backside source / drain via and a backside of the epitaxial source / drain structure; and a front-side silicide layer disposed between the front-side source / drain contact and a front side of the epitaxial source / drain structure, wherein the source / drain of the epitaxial source / drain structure is disposed between the back-side silicide layer and the front-side silicide layer. [20] The device of claim 18 or 19, wherein the backside source / drain via extends through a source / drain isolation structure of the epitaxial source / drain structure, and the source / drain isolation structure is disposed between the via spacers and the epitaxial source / drain structure, the via spacers being disposed along sidewalls of the backside source / drain via.

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