Low-capacitance, high-thermal-conductivity interconnect structure and manufacturing process

Abstract

Contact structure, including: an etch stop layer, ESL (214); a first column structural element (222) and a second column structural element (222) arranged on the ESL (214); a metal structural element (230) disposed between the first column structural element (222) and the second column structural element (222), the metal structural element (230) comprising a first sidewall, a bottom surface, a second sidewall, and a top surface; a dielectric liner (228) extending continuously from a top surface of the first column structure element (222) along the first sidewall, the bottom surface, and the second sidewall of the metal feature (230) and onto a top surface of the second column feature (222); and a gap (240) between the first column structure element (222) and a portion of the dielectric liner (228) extending along the first sidewall of the metal structure element (230).

Description

STATE OF THE ART

[0001] The electronics industry is experiencing ever-increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting a larger number of increasingly complex and demanding functions. Accordingly, there is a continuing trend in the semiconductor industry toward producing lower-cost, higher-performance, and lower-power integrated circuits (ICs). To date, these goals have largely been achieved by reducing the dimensions of semiconductor ICs (e.g., minimum feature size), thereby improving production efficiency and reducing associated costs. However, such scaling has also led to increased complexity in the semiconductor manufacturing process. Therefore, realizing continued advances in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0002] As device dimensions become increasingly smaller, the performance requirements of back-end-of-line (BEOL) interconnect structures are becoming more stringent. For example, low-dielectric constant (low-k) materials have been incorporated into interconnect structures to reduce capacitance. While low-k materials serve their purpose of reducing capacitance, their poor thermal conductivities pose challenges for heat dissipation in front-end-of-line (FEOL) devices. JP 2002-050683 A describes a hollow wiring structure. A SiO2 insulation film and a bottom wiring layer containing semiconductor components such as transistors are provided above a silicon substrate.A columnar wiring via made of copper (Cu) connects the lower wiring layer to an upper wiring layer, which is supported by additional columnar structures made of aluminum nitride (AlN). A gas is located between the wiring layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure can best be understood by reference to the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 is a flowchart of a method 100 for forming a contact structure according to one or more aspects of the present disclosure. Fig. 2-19 are fragmentary cross-sectional views of a workpiece in various stages of manufacture according to the method in Fig. 1 according to one or more aspects of the present disclosure. Fig. 20 is a flowchart of a method 300 for forming a contact structure according to one or more aspects of the present disclosure. Fig. 21 - 26 are fragmentary cross-sectional views of a workpiece in various stages of manufacture according to the method in Fig. 20 according to one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, for ease of description, spatially relative terms such as "below," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one structural element or feature to another structural element or feature, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0006] Furthermore, when a number or range of numbers is described with "approximately" and the like, the term is intended to include numbers that are within a reasonable range, taking into account variations that inevitably occur during manufacturing, as understood by those of ordinary skill in the art. For example, the number or range of numbers includes a reasonable range, including the described number, approximately within + / - 10% of the described number, based on known manufacturing tolerances associated with the manufacture of a feature having a characteristic associated with the number. For example, a material layer having a thickness of "about 5 nm" may include a dimensional range of 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with the deposition of the material layer are known to be + / - 15% to those of ordinary skill in the art.(A) source / drain region(s) may refer to a source or a drain individually or collectively, depending on the context.

[0007] As front-end-of-line (FEOL) devices become smaller, back-end-of-line (BEOL) interconnect structures play a greater role in meeting current, power, and area requirements. BEOL interconnect structures can incorporate low-k dielectric material to keep parasitic capacitance low. In general, low-k dielectric materials have lower thermal conductivity than high-k dielectric materials, metals, or semiconductor materials. For example, the thermal conductivity of silicon oxide is two orders of magnitude lower than that of silicon. The low thermal conductivity of low-k dielectric materials prevents them from effectively dissipating the heat generated by FEOL devices.When it comes to dielectric materials in BEOL interconnect structures, the industry is looking for a solution to achieve high thermal conductivity while maintaining low parasitic capacitance.

[0008] The present disclosure provides methods for forming a contact structure including pillar features with high thermal conductivity for heat dissipation and low-k dielectric structures for capacitance reduction. In one example process, pillar structures are formed over an etch stop layer. The pillar elements are made of diamond or aluminum nitride. A sacrificial polymer layer is then deposited over the pillar features. The sacrificial polymer layer is then patterned to form contact openings. A liner is then conformally deposited over the contact openings. After conductive features are formed in the contact openings, a heat treatment is performed to selectively remove the sacrificial polymer layer, leaving air gaps in the spaces defined by the pillar features and the liner. The pillar elements are made of materials with good thermal conductivity and facilitate heat dissipation.The air gaps between the conductive structural elements help to keep the capacitance low.

[0009] The various aspects of the present disclosure will now be described in more detail with reference to the figures. In this context, Fig. 1 and Fig. 20 Flowcharts illustrating method 100 and method 300 for forming a contact structure on a workpiece 200. Methods 100 and 300 are merely examples and are not intended to limit the present disclosure to what is explicitly depicted in method 100 or method 300. Additional steps may be provided before, during, and after method 100 or method 300, and some of the described steps may be replaced, eliminated, or shifted for additional embodiments of method 100 or method 300. For clarity and simplicity, not all steps are described in detail here. Method 100 is described below in connection with the Fig. 2-19, which are fragmentary cross-sectional views of a workpiece 200 at various stages of manufacture according to embodiments of the method 100. The method 300 is described below in connection with the Fig. 2-9, 11-12, and 21-26, which illustrate fragmentary cross-sectional views of a workpiece 200 at various stages of fabrication according to embodiments of the method 300. Since the workpiece 200 is processed into a semiconductor structure 200 after completion of the manufacturing processes, the workpiece 200 may be referred to as a semiconductor structure 200, as the context requires. Furthermore, throughout this application and in various embodiments, like reference numerals refer to like features with similar structures and compositions unless otherwise indicated. Source / drain region(s) may refer individually or collectively to a source or a drain, depending on the context.

[0010] Referring to Fig. 1 and Fig. 2, the method 100 includes a block 102 in which a workpiece 200 is received. The workpiece 200 includes a bottom etch stop layer (ESL) 202, a first dielectric layer 204 disposed over the bottom ESL 202, and first conductive features 208 extending through the first dielectric layer 204 and the bottom ESL 202. The workpiece 200 is representative of a metallization layer in a BEOL interconnect structure, and the first conductive features 208 represent a metal line, a contact via, or a dual damascene feature comprising a metal line and a contact via. In some embodiments, the bottom ESL 202 includes aluminum oxide, aluminum nitride, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof.The first dielectric layer 204 may comprise a low-k dielectric material having a dielectric constant less than that of silicon oxide, which is approximately 3.9. For example, the first dielectric layer 204 may comprise a porous organosilicate thin film (e.g., SiOCH), tetraethylorthosilicate oxide (TEOS oxide), undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxycarbonitride (SiOCN), boron carbonitride, spin-coated silicon-based polymeric dielectrics, or combinations thereof. In some cases, the first dielectric layer 204 may be referred to as an inter-level dielectric (ILD) layer or an inter-metal dielectric (IMD) layer.Each of the first conductive features 208 includes a barrier layer 205 to connect the first dielectric layer 204 and the lower ESL 202, and a metal fill layer 206 via the barrier layer 205. The barrier layer 205 may include titanium nitride (TiN), cobalt nitride (CoN), manganese nitride (MnN), nickel nitride (NiN), tungsten nitride (WN), or tantalum nitride (TaN). The first metal fill layer 206 may include copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W), or molybdenum (Mo), or a combination thereof.

[0011] Referring to Fig. 1 and Fig. 3, the method 100 includes a block 104 in which a first cap layer 212 is selectively deposited over the first conductive feature 208. The first cap layer 212 may also be referred to as a metal cap 212 or conductive cap layer 212 and is formed from a metal different from the metal forming the barrier layer 205 and the metal fill layer 206. In embodiments in which the metal fill layer 206 is formed from copper, the first cap layer 212 may comprise titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), cobalt (Co), ruthenium (Ru), or tungsten (W), or other refractory metals. In the illustrated embodiment, the first cap layer 212 includes cobalt (Co).In some implementations, at block 104, the first capping layer 212 is selectively deposited on the top surfaces of the first conductive features 208 by metal-organic chemical vapor deposition (MOCVD) using metal-organic precursors, each having a metal ion and coordinating ligands. An exemplary metal-organic cobalt precursor may be cyclopentadienylcobalt dicarbonyl ((C5H5)Co(CO)2). As shown in FIG. Fig. 3, the first capping layer 212 is deposited only on the upper surfaces of the barrier layer 205 and the metal fill layer 206 due to the selective nature of the formation and is absent from the surfaces of the first dielectric layer 204. Furthermore, it has been observed that the first capping layer 212 may be thicker in the central region than around the edge, which gives the first capping layer 212a a slight dome profile in a Fig. 3. The first cap layer 212 serves to suppress electromigration, or hillock formation, of the metal fill layer 206. The first cap layer 212 not only serves to reduce electromigration but can also repair damage inflicted on the metal fill layer 206 during a planarization process.

[0012] Referring to Fig. 1 and Fig. 4, the method 100 includes a block 106 in which an etch stop layer (ESL) 214 is deposited over the first conductive feature 208. In some embodiments, the ESL 214 may comprise a metal nitride, such as aluminum nitride (AlN). When the ESL 214 comprises aluminum nitride (AlN), the ESL 214 may be deposited using atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma-enhanced CVD (PECVD). The deposition of the ESL 214 may include the use of an aluminum-containing precursor, such as trimethylaluminum (Al(CH3)3), and a nitrogen-containing precursor, such as ammonia (NH3). In some implementations, the deposited ESL 214 may be subjected to a plasma treatment comprising helium (He), argon (Ar), or a combination thereof. Plasma treatment can improve the integrity and density of ESL 214.In some cases, the ESL 214 may have a thickness between about 2.0 nm and about 5.0 nm.

[0013] Referring to Fig. 1 and Fig. 5, the method 100 includes a block 108 in which a semiconductor layer 216 is disposed over the ESL 214. In some embodiments, the semiconductor layer 216 is a layer of amorphous silicon (a-Si) deposited using CVD, PECVD, or low-pressure CVD (LPCVD). The deposition of the semiconductor layer 216 may include the use of trichlorosilane (SiCl3), silane (SiH4), or a combination thereof. In some implementations, the semiconductor layer 216 has a thickness between approximately 80 nm and approximately 100 nm.

[0014] Referring to Fig. 1 and 6-8, the method 100 includes a block 110 in which the semiconductor layer 216 is patterned to form pillar openings 220. The patterning of the semiconductor layer 216 may include photolithography processes and etching processes. In the illustrated embodiment, block 110 includes the deposition of a photoresist layer 218 (in Fig. 6), the photolithographic patterning of the photoresist layer and the etching of the semiconductor layer 216 using the patterned photoresist layer 218 as an etching mask (in Fig. 7) and selectively removing the photoresist layer 218 (in Fig. 8). The photoresist layer 218 may contain hydrocarbons and may be deposited using spin-on deposition. Etching the semiconductor layer 216 at block 110 may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Because the pillar openings 220 are formed to accommodate pillar features that land on the ESL 214, the etching of the semiconductor layer 216 ends on or adjacent to a top surface of the ESL 214. After patterning the semiconductor layer 216 to form the pillar openings 220, the photoresist layer 218 may be removed by ashing or selective etching.

[0015] Referring to Fig. 1 and Fig. 9, the method 100 includes a block 112 in which a dielectric material 222 is deposited over the column openings 220. In some embodiments, the dielectric material 222 may comprise diamond, diamond-like carbon, or aluminum nitride (AlN). If the dielectric material 222 comprises diamond or diamond-like carbon, the dielectric material 222 may be deposited using CVD or spin-on coating. If the diamond-based dielectric material 222 is deposited using CVD, a carbon-containing gas and hydrogen (H2) may be used, and the process temperature may be below 450°C. The carbon-containing gas may comprise methane, dichloromethane, trichloromethane, or a combination thereof. If the diamond-based dielectric material 222 is deposited using spin-on coating, a dispersed diamond precursor solution with a pH between 4.0 and 7.0 may be used.

[0016] If the dielectric material 222 comprises aluminum nitride (AlN), the dielectric material 222 may be a single continuous layer or a sequential layer. If the dielectric material 222 is a single continuous layer, aluminum nitride (AlN) may be deposited using ALD or CVD to fill the pillar openings. The aluminum nitride deposited by ALD or CVD is amorphous or polycrystalline. If the dielectric material 222 is a sequential layer, aluminum nitride (AlN) may be deposited in multiple cycles, each cycle comprising a PVD deposition step and an ultraviolet (UV) annealing step. In some embodiments, each PVD deposition step deposits aluminum nitride to a thickness between approximately 5.0 nm and approximately 10.0 nm. The PVD deposition may include a sputtering process and a high-purity aluminum nitride target.Following PVD deposition, the deposited aluminum nitride layer is annealed in a UV annealing step at a temperature below 450°C. In some embodiments, the UV annealing step is performed in an oxygen- or air-containing environment, thereby forming an aluminum oxynitride layer (or an oxygen-doped aluminum nitride layer) prior to PVD deposition of the next aluminum nitride layer. As representatively shown in FIG. Fig. 10, the dielectric material 222 is multilayered when the dielectric material 222 is a sequential layer and is formed using multiple cycles mentioned above. For further illustration, a portion of the dielectric material 222 is shown in Fig. 9 enlarged and in Fig. 10. The multilayer structure may include aluminum nitride sublayers 2220 and aluminum oxynitride sublayers 2222 that interdigitate the aluminum nitride sublayers 2220. When aluminum nitride is deposited using PVD, the deposited aluminum nitride tends to be single-crystal, which increases leakage. The aluminum oxynitride sublayers 2222 serve to reduce leakage due to the crystallinity of the aluminum nitride sublayers 2220.

[0017] Referring to Fig. 1 and Fig. 11, the method 100 includes a block 114 in which the workpiece 200 is planarized to form pillar features 222 in the pillar openings 220. The planarization in block 114 may include chemical mechanical polishing (CMP). As shown in Fig. As shown in Figure 10, the workpiece 200 is planarized until a top surface of the semiconductor layer 216 is exposed. For ease of reference, the reference numeral of the dielectric material 222 is used to designate the pillar features 222.

[0018] Referring to Fig. 1 and Fig. 12, the method 100 includes a block 116 in which the semiconductor layer 216 is selectively removed. In some embodiments, the semiconductor layer 216 may be selectively removed using a selective wet etching process or a selective dry etching process. An exemplary selective wet etching process may include the use of ethylenediamine catechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), hydrogen peroxide (H2O2), and ammonium fluoride (NH4F), or a suitable wet etchant. An exemplary selective dry etching process for etching the semiconductor layer 216 may include sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrogen fluoride (HF), carbon tetrafluoride (CF4), hydrogen bromide (HBr), argon, or a mixture thereof. As shown in Fig. 12, the selective removal of the semiconductor layer 216 exposes a top surface of the ESL 214.

[0019] Referring to Fig. 1 and Fig. 13, the method 100 includes a block 118 in which a polymer layer 224 is deposited over the workpiece 200. While the polymer layer 224 serves as a sacrificial layer and must be removed in a subsequent step, it is selected to withstand the deposition of a second dielectric layer 228 (described further below) without being structurally compromised. For this reason, the polymer layer 224 must be easy to remove yet remain stable at least up to a temperature of approximately 300°C, which is approximately the deposition temperature of the second dielectric layer 228. Based on these criteria, the polymer layer 224 may comprise polyvinyl alcohol (PVA), polyacrylate, polydimethylsiloxane (PDMS), polycarbonate (PC), or a suitable polymer. In general, polymers containing benzene rings in their monomers may not be suitable because they tend to decompose at high temperatures.In one embodiment, the polymer layer 224 comprises PVA, which has a decomposition temperature between 300°C and approximately 450°C. The polymer layer 224 can be deposited by flowable CVD (FCVD), CVD, spin-on coating, or sol-gel processes. After the polymer layer 224 is deposited, a curing process can be performed to harden the polymer layer 224. In some cases, the curing process can include a baking process, an annealing process, a drying process, or a UV radiation process.

[0020] Referring to Fig. 1 and Fig. 14, the method 100 includes a block 120 in which the polymer layer 224 is patterned to form contact openings 226. In some embodiments, the patterning of the polymer layer 224 may be performed using lithography processes and dry etching. The lithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin-drying and / or hard baking), and other suitable lithography techniques and / or combinations thereof. The dry etching process may include reactive ion etching (RIE) or plasma etching using an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), or a bromine-containing gas (e.g., HBr and / or CHBr3).The contact openings 226 extend through the ESL 214 to expose the first cap layer 212.

[0021] Referring to Fig. 1 and Fig. 15, the method 100 includes a block 122 in which a second dielectric layer 228 is deposited over the contact openings 226. In some embodiments, the second dielectric layer 228 may comprise diamond, diamond-like carbon, or aluminum nitride (AlN). If the second dielectric layer 228 comprises diamond or diamond-like carbon, the second dielectric layer 228 may be deposited by CVD using a carbon-containing gas and hydrogen (H2). The process temperature for the CVD deposition of the second dielectric layer 228 may be lower than 450°C. The carbon-containing gas may comprise methane, dichloromethane, trichloromethane, or a combination thereof. If the second dielectric layer 228 comprises aluminum nitride (AlN), the second dielectric layer 228 may be deposited using ALD, CVD, or plasma-enhanced CVD (PECVD).It should be noted that the second dielectric layer 228 is not formed using PVD, or the crystallinity of the second PVD dielectric layer 228 may promote leakage. The deposition of the second dielectric layer 228 may include the use of an aluminum-containing precursor such as trimethylaluminum (Al(CH3)3) and a nitrogen-containing precursor such as ammonia (NH3). In some implementations, the deposited second dielectric layer 228 may be subjected to a plasma treatment comprising helium (He), argon (Ar), or a combination thereof. The plasma treatment may improve the integrity and density of the second dielectric layer 228. As shown in FIG. Fig. 15, the second dielectric layer 228 may serve as an etch stop layer and as a liner since the second dielectric layer 228 is conformally deposited over the sidewalls of the contact openings 226.

[0022] Referring to Fig. 1 and Fig. 16, the method 100 includes a block 124 in which a metal fill layer is deposited over the contact openings to form a second conductive feature 230. In some embodiments, the metal fill layer (and the second conductive feature 230 formed therefrom) comprises copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W), molybdenum (Mo), or a combination thereof. In one embodiment, the metal fill layer comprises copper (Cu). The metal fill layer may be deposited using ALD, CVD, PVD, electrochemical plating (ECP), or electroless deposition (ELD). In one example, the metal fill layer may be deposited by electrochemical plating. In this example process, a seed layer may be deposited over the second dielectric layer 228 using PVD or CVD.The seed layer may contain titanium (Ti), copper (Cu), or both. Copper is then deposited over the seed layer by electroplating. After the metal fill layer is deposited, a planarization process, such as a CMP process, is performed to remove excess metal fill layer and expose the top surface of the second dielectric layer 228. After the planarization process, the second conductive features 230 are formed in the contact openings 226. As shown in FIG. Fig. As shown in Figure 16, the upper surfaces of the second conductive feature 230 may be lower than the upper surface of the second dielectric layer 228 by a height difference D due to the strain effect. In some cases, the height difference D may be between approximately 0 and approximately 1.0 nm. The second dielectric layer 228 above the first cap layer 212 is removed by anisotropic etching to expose the first cap layer 212 prior to forming the second conductive feature 230.

[0023] Referring to Fig. 1 and Fig. 17, the method 100 includes a block 126 in which the polymer layer 224 is selectively removed. In some embodiments, a thermal treatment, such as an annealing process or a baking process, may be performed to decompose the polymer layer 224 into a volatile compound that can be removed from the thermal treatment chamber. In some embodiments, the thermal treatment may have a temperature between approximately 300°C and approximately 450°C. This temperature range is not insignificant. If the temperature is below 300°C, the decomposition may occur too slowly, which can increase the process time and cost. If the temperature is higher than 450°C, the threshold voltage of the already formed FEOL devices may begin to drift.If the polymer layer 224 contains PVA, the thermal treatment may cause the polymer layer 224 to decompose, producing water and carboxylic acid as volatile byproducts that must be removed by applying a vacuum. After the polymer layer 224 is selectively removed, the air gap 240 may be formed in spaces defined by the pillar features 222, the second dielectric layer 228, and the ESL 214. Since air has a dielectric constant close to 1, the air gaps 240 reduce the effective dielectric constant of the dielectric structures beneath the second conductive features 230.

[0024] Referring to Fig. 1 and Fig. 18, the method 100 includes a block 128 in which a second capping layer 232 is formed over the second conductive structure 230. In some embodiments, the second capping layer 232 comprises cobalt (Co). In some implementations, at block 128, the second capping layer 232 may be selectively deposited on the upper surfaces of the second conductive structure 230 by metal-organic chemical vapor deposition (MOCVD) using metal-organic precursors, each having a metal ion and coordinating ligands. An example of a metal-organic cobalt precursor may be cyclopentadienylcobalt dicarbonyl ((C5H5)Co(CO)2). As shown in Fig. 18, the second capping layer 232 is deposited only on the upper surfaces of the second conductive features 230 due to the selective nature of the formation and is absent from the surfaces of the second dielectric layer 228. If the second capping layer 232 contains cobalt (Co), it may have a slight dome shape similar to that shown in Fig. 3. In alternative embodiments, the second cap layer 232 may comprise silicon nitride.

[0025] It will now Fig. 19. In some embodiments, the method 100 is performed on a workpiece 200 that is formed using the method 100. In Fig. 19, the ESL 214 is deposited on a lower dielectric layer 228', similar to the second dielectric layer 228. The lower dielectric layer 228' contacts the lower pillar features 222', which are similar to the pillar features 222. A low dielectric constant is provided by the lower air gaps 240', similar to the air gaps 240.

[0026] The method 100 of the present disclosure selectively removes the polymer layer 224 to form air gaps 240 to lower the effective dielectric constant and reduce capacitance. The method 300 in Fig. 20 includes an alternative embodiment in which a low-k dielectric material is deposited in place of the polymer layer 224 and the low-k dielectric material is not subsequently removed.

[0027] Referring to Fig. 20 and Fig. 2, the method 300 includes a block 302 in which a workpiece 200 is received, which includes a first conductive structure 208 disposed in a first dielectric layer 204. The operations in block 302 are similar to those in block 102. In particular, the workpiece 200 undergoing the method 300 may be the same as the workpiece 200 undergoing the method 100. For this reason, a detailed description of the operations in block 302 is omitted for the sake of brevity.

[0028] Referring to Fig. 20 and Fig. 3, the method 300 includes a block 304 in which a first cap layer 212 is selectively deposited over the first conductive feature 208. The operations in block 304 are similar to those in block 104. For this reason, a detailed description of the operations in block 304 is omitted for brevity.

[0029] Referring to Fig. 20 and 4, the method 300 includes a block 306 in which an etch stop layer (ESL) 214 is deposited over the first conductive feature 208. The operations in block 306 are similar to those in block 106. For this reason, a detailed description of the operations in block 306 is omitted for brevity.

[0030] Referring to Fig. 20 and Fig. 5, the method 300 includes a block 308 in which a semiconductor layer 216 is deposited over the ESL 214. The operations in block 308 are similar to those in block 108. For this reason, a detailed description of the operations in block 308 is omitted for brevity.

[0031] Referring to Fig. 20 and 6-8, the method 300 includes a block 310 in which the semiconductor layer 216 is patterned to form pillar openings 220. The operations in block 310 are similar to those in block 110. For this reason, a detailed description of the operations in block 310 is omitted for brevity.

[0032] Referring to Fig. 20 and Fig. 9, the method 100 includes a block 312 in which a dielectric material 222 is deposited over the pillar openings 220. The operations in block 312 are similar to those in block 112. For this reason, a detailed description of the operations in block 312 is omitted for brevity.

[0033] Referring to Fig. 20 and Fig. 11, the method 300 includes a block 314 in which the workpiece 200 is planarized to form pillar features 222 in the pillar openings 220. The operations in block 314 are similar to those in block 114. For this reason, a detailed description of the operations in block 314 is omitted for brevity.

[0034] Referring to Fig. 20 and Fig. 12, the method 300 includes a block 316 in which the semiconductor layer 216 is selectively removed. The operations in block 316 are similar to those in block 116. For this reason, a detailed description of the operations in block 316 is omitted for the sake of brevity.

[0035] Referring to Fig. 20 and Fig. 21, the method 300 includes a block 318 in which a low-k dielectric layer 2240 is deposited over the pillar features 222. The low-k dielectric layer 2240 may comprise a porous organosilicate thin film (e.g., SiOCH), tetraethylorthosilicate oxide (TEOS oxide), undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxycarbonitride (SiOCN), boron carbonitride (BCN), spin-coated silicon-based polymeric dielectrics, or combinations thereof. In one embodiment, the low-k dielectric layer 2240 comprises boron carbonitride (BCN). The low-k dielectric layer 2240 can be deposited using CVD, flowable CVD, or spin-on deposition.

[0036] Referring to Fig. 20 and Fig. 22, the method 300 includes a block 320 in which the low-k dielectric layer 2240 is patterned to form contact openings 226. In some embodiments, the patterning of the low-k dielectric layer 2240 may be performed using lithography processes and dry etching. The lithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin-drying and / or hard baking), and other suitable lithography techniques and / or combinations thereof. The dry etching process may include reactive ion etching (RIE) or plasma etching using an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), or a bromine-containing gas (e.g., HBr and / or CHBr3).The contact openings 226 extend through the ESL 214 to expose the first cap layer 212.

[0037] Referring to Fig. 20 and Fig. 23, the method 300 includes a block 322 in which a second dielectric layer 228 is conformally deposited over the contact openings 226. In some embodiments, the second dielectric layer 228 may comprise diamond, diamond-like carbon, or aluminum nitride (AlN). If the second dielectric layer 228 includes diamond or diamond-like carbon, the second dielectric layer 228 may be deposited by CVD using a carbon-containing gas and hydrogen (H2). The process temperature for the CVD deposition of the second dielectric layer 228 may be lower than 450°C. The carbon-containing gas may include methane, dichloromethane, trichloromethane, or a combination thereof. If the second dielectric layer 228 includes aluminum nitride (AlN), the second dielectric layer 228 may be deposited using ALD, CVD, or plasma-enhanced CVD (PECVD).It should be noted that the second dielectric layer 228 is not formed using PVD, as otherwise the crystallinity of the second PVD dielectric layer 228 may promote leakage. The deposition of the second dielectric layer 228 may include the use of an aluminum-containing precursor such as trimethylaluminum (Al(CH3)3) and a nitrogen-containing precursor such as ammonia (NH3). In some implementations, the deposited second dielectric layer 228 may be subjected to a plasma treatment comprising helium (He), argon (Ar), or a combination thereof. The plasma treatment may improve the integrity and density of the second dielectric layer 228. As shown in FIG. Fig. 23, the second dielectric layer 228 may serve as an etch stop and as a liner since the second dielectric layer 228 is conformally deposited over the sidewalls of the contact openings 226.

[0038] Referring to Fig. 20 and Fig. 24, the method 300 includes a block 324 in which a metal fill layer is deposited over the contact openings 226 to form second conductive features 230. In some embodiments, the metal fill layer (and the second conductive feature 230 formed therefrom) includes copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), osmium (Os), tungsten (W), molybdenum (Mo), or a combination thereof. In one embodiment, the metal fill layer includes copper (Cu). The metal fill layer may be deposited using ALD, CVD, PVD, electrochemical plating (ECP), or electroless deposition (ELD). In one example, the metal fill layer may be deposited by electrochemical plating. In this example process, a seed layer may be deposited over the second dielectric layer 228 using PVD or CVD.The seed layer may contain titanium (Ti), copper (Cu), or both. Copper is then deposited over the seed layer by electroplating. After the metal fill layer is deposited, a planarization process, such as a CMP process, is performed to remove excess metal fill layer and expose the top surface of the second dielectric layer 228. After the planarization process, the second conductive features 230 are formed in the contact openings 226. As shown in FIG. Fig. As shown in Figure 24, the upper surfaces of the second conductive features 230 may be lower than the upper surface of the second dielectric layer 228 by a height difference D due to the strain effect. In some cases, the height difference D may be between approximately 0 and approximately 1.0 nm. The second dielectric layer 228 above the first capping layer 212 is removed by anisotropic etching to expose the first capping layer 212 prior to forming the second conductive feature 230.

[0039] Referring to Fig. 20 and Fig. 25, the method 300 includes a block 326 in which a second capping layer 232 is formed over the second conductive features 230. In some embodiments, the second capping layer 232 includes cobalt (Co). In some implementations, at block 326, the second capping layer 232 may be selectively deposited on the upper surfaces of the second conductive features 230 by metal-organic chemical vapor deposition (MOCVD) using metal-organic precursors, each having a metal ion and coordinating ligands. An example of a metal-organic cobalt precursor may be cyclopentadienylcobalt dicarbonyl ((C5H5)Co(CO)2). As shown in Fig. As shown in Figure 25, due to the selective nature of the formation, the second capping layer 232 is deposited only on the upper surfaces of the second conductive features 230 and is absent from the surfaces of the second dielectric layer 228. In some implementations, the second conductive features 230 are selectively etched or recessed prior to the formation of the second capping layer 232. In some alternative embodiments, the second capping layer 232 may comprise silicon nitride.

[0040] It will be Fig. 25. In some embodiments, the method 300 is performed on a workpiece 200 that is formed using the method 300. In Fig.25, the ESL 214 is deposited on a bottom dielectric layer 228', similar to the second dielectric layer 228. The bottom dielectric layer 228' contacts the bottom pillar features 222', which are similar to the pillar features 222. A low dielectric constant is provided by a low-k bottom dielectric layer 2240', similar to the low-k dielectric layer 2240.

[0041] Thus, one of the embodiments of the present disclosure provides a contact structure. The contact structure includes an etch stop layer (ESL), a first pillar feature and a second pillar feature disposed on the ESL, a metal feature disposed between the first pillar feature and the second pillar feature and including a first sidewall, a bottom surface, a second sidewall, and a top surface, a dielectric liner extending continuously from a top surface of the first pillar feature along the first sidewall, the bottom surface, and the second sidewall of the metal feature and onto a top surface of the second pillar feature, and a gap between the first pillar feature and a portion of the dielectric liner extending along the first sidewall of the metal feature.

[0042] In some embodiments, the ESL comprises aluminum nitride (AlN). In some embodiments, the first pillar feature and the second pillar feature include diamond, aluminum oxynitride, or aluminum nitride. In some implementations, the dielectric liner includes aluminum nitride or diamond. In some embodiments, the contact structure further includes a metal cap disposed on the top surface of the metal feature. In some embodiments, the metal feature includes copper (Cu) and the metal cap includes cobalt (Co). In some embodiments, the first pillar feature and the second pillar feature contact the ESL.

[0043] In another embodiment, a method is provided. The method includes depositing a semiconductor layer over an etch stop layer (ESL), patterning the semiconductor layer to form pillar openings exposing the ESL, depositing a dielectric material over the pillar openings and the semiconductor layer, planarizing the dielectric material to form pillar structures in the pillar openings, after planarizing, selectively removing the semiconductor layer, after selectively removing, depositing a polymer layer over the pillar structures, patterning the polymer layer to form contact openings between the pillar structures, conformally depositing a dielectric liner over the contact openings, forming a conductive feature over the contact openings, and after forming the conductive feature, selectively removing the polymer layer.

[0044] In some embodiments, the semiconductor layer comprises amorphous silicon (a-Si). In some implementations, the dielectric material comprises diamond, aluminum oxynitride, or aluminum nitride. In some embodiments, selectively removing the polymer layer comprises performing a heat treatment at a temperature between approximately 300°C and approximately 450°C. In some embodiments, after selectively removing the polymer layer, the method further comprises applying a capping layer over the conductive feature. In some embodiments, the polymer layer includes polyvinyl alcohol (PVA), polyacrylate, polydimethylsiloxane (PDMS), or polycarbonate (PC). In some embodiments, the dielectric liner comprises diamond or aluminum nitride.In some embodiments, depositing the dielectric material comprises performing a plurality of cycles, each of the plurality of cycles comprising depositing an aluminum nitride layer by physical vapor deposition and performing an ultraviolet (UV) anneal on the aluminum nitride layer. In some embodiments, the aluminum nitride layer has a thickness between approximately 5.0 nm and approximately 10.0 nm.

[0045] In yet another embodiment, a method is provided. The method includes depositing a silicon layer over an etch stop layer (ESL), patterning the silicon layer to form pillar openings exposing the ESL, depositing a dielectric material over the pillar openings and the silicon layer, and planarizing the dielectric material to form pillar features in the pillar openings; after planarizing, selectively removing the silicon layer; after selective removal, depositing a low-k dielectric layer over the pillar features; patterning the low-k dielectric layer to form contact openings between the pillar features; conformally depositing a dielectric liner over the contact openings; depositing a metal fill layer over the contact openings; and selectively depositing a metal cap over the metal fill layer.

[0046] In some embodiments, the dielectric material includes diamond, aluminum oxynitride, or aluminum nitride. In some embodiments, the dielectric liner includes diamond or aluminum nitride. In some implementations, the low-k dielectric layer includes boron carbonitride (BCN) or silicon oxycarbonitride.

[0047] The foregoing sets forth features of several embodiments to help those skilled in the art better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same benefits as the embodiments presented herein.

Claims

[1] Contact structure, including: an etch stop layer, ESL (214); a first column structural element (222) and a second column structural element (222) arranged on the ESL (214); a metal structural element (230) disposed between the first column structural element (222) and the second column structural element (222), the metal structural element (230) comprising a first sidewall, a bottom surface, a second sidewall, and a top surface; a dielectric liner (228) extending continuously from a top surface of the first column structure element (222) along the first sidewall, the bottom surface, and the second sidewall of the metal feature (230) and onto a top surface of the second column feature (222); and a gap (240) between the first column structure element (222) and a portion of the dielectric liner (228) extending along the first sidewall of the metal structure element (230). [2] The contact structure of claim 1, wherein the ESL (214) contains aluminum nitride (AlN). [3] The contact structure according to claim 1 or 2, wherein the first column structure element (222) and the second column structure element (222) contain diamond, aluminum oxynitride or aluminum nitride. [4] Contact structure according to one of the preceding claims, wherein the dielectric liner (228) contains aluminum nitride or diamond. [5] Contact structure according to one of the preceding claims, further comprising: a metal cap (232) disposed on the upper surface of the metal member (230). [6] Contact structure according to claim 5, wherein the metal structural element (230) contains copper (Cu), wherein the metal cap (232) contains cobalt (Co). [7] Contact structure according to one of the preceding claims, wherein the first column structure element (222) and the second column structure element (222) are in contact with the ESL (214). [8] Method (100) comprising: Depositing (108) a semiconductor layer (216) over an etch stop layer, ESL (214); Structuring (110) the semiconductor layer (216) to form pillar openings (220) exposing the ESL (214); Applying (112) a dielectric material (222) over the column openings (220) and the semiconductor layer (216); Planarizing (114) the dielectric material (222) to form column structure elements (222) in the column openings (220); after planarization, selective removal (116) of the semiconductor layer (216); after the selective removal, depositing (118) a polymer layer (224) over the column structure elements (222); Structuring (120) the polymer layer (224) to form contact openings (226) between the column structure elements (222); conformally applying (122) a dielectric liner (228) over the contact openings (226); Forming (124) a conductive structural element (230) over the contact openings (226); and after forming the conductive structural element (230), selectively removing (126) the polymer layer (224). [9] The method of claim 8, wherein the semiconductor layer (216) contains amorphous silicon (a-Si). [10] The method of claim 8 or 9, wherein the dielectric material (222) comprises diamond, aluminum oxynitride or aluminum nitride. [11] The method of any one of the preceding claims 8 to 10, wherein the selective removal (126) of the polymer layer (224) comprises performing a thermal treatment at a temperature between approximately 300°C and approximately 450°C. [12] Method according to one of the preceding claims 8 to 11, further comprising: after the selective removal (126) of the polymer layer (224), depositing (128) a cover layer over the conductive structural element (230). [13] Method according to one of the preceding claims 8 to 12, wherein the polymer layer (224) contains polyvinyl alcohol (PVA), polyacrylate, polydimethylsiloxane (PDMS), polycarbonate (PC). [14] A method according to any one of the preceding claims 8 to 13, wherein the dielectric liner (228) contains diamond or aluminum nitride. [15] The method of any one of the preceding claims 8 to 14, wherein depositing (112) the dielectric material (222) comprises performing a plurality of cycles, each of the plurality of cycles comprising: Applying an aluminum nitride layer (2220) by physical vapor deposition; and Performing an ultraviolet (UV) anneal on the aluminum nitride layer (2220). [16] The method of claim 15, wherein the aluminum nitride layer (2220) has a thickness between about 5.0 nm and about 10.0 nm. [17] Method (300) comprising: Depositing (308) a silicon layer (216) over an etch stop layer, ESL (214); Structuring (310) the silicon layer (216) to form pillar openings (220) exposing the ESL (214); Depositing (312) a dielectric material (222) over the column openings (220) and the silicon layer (216); Planarizing (314) the dielectric material (222) to form column structure elements (222) in the column openings (220); after planarization, selectively removing (316) the silicon layer (216); after the selective removal, depositing (318) a low-k dielectric layer (224) over the column structure elements (222); Structuring (320) the low-k dielectric layer (224) to form contact openings (226) between the column structure elements (222); conformally applying (322) a dielectric liner (228) over the contact openings (226); Applying (324) a metal fill layer (230) over the contact openings (226); and selectively depositing (326) a metal cap (232) over the metal fill layer (230). [18] The method of claim 17, wherein the dielectric material (222) comprises diamond, aluminum oxynitride, or aluminum nitride. [19] The method of claim 17, wherein the dielectric liner (228) contains diamond or aluminum nitride. [20] The method of any one of the preceding claims 17 to 19, wherein the low-k dielectric layer (224) comprises boron carbonitride (BCN) or silicon oxycarbonitride.

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