Manufacturing process for a monolithic multi-aperture plate and monolithic multi-aperture plate for a multi-beam electron beam system
Patent Information
- Application Number
- DE102024105793
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-07-31
- Estimated Expiration
- 2044-02-29
Smart Images

Figure 00000000_0000_ABST
Abstract
Claims
[1] A monolithic multi-aperture plate (306) for a multi-beam electron beam system (1) having a plurality of apertures (85) forming continuous connections between a first side or top side (313) and a second side or bottom side (315) of the multi-aperture plate (306), wherein the multi-aperture plate (306) is formed from a sequence of functional layers (175, 177, 181) and an embedded structured metal layer (51) with embedded metallic connecting channels (51.11, 51.12), wherein each functional layer (175, 177, 181) consists of a doped semiconductor material and an insulating semiconductor compound. [2] Monolithic multi-aperture plate (306) according to claim 1, wherein the multi-aperture plate (306) includes at least two active functional layers (181a, 181b), and wherein the embedded structured metal layer (51) is arranged between the first active functional layer (181a) and the second active functional layer (181b). [3] Monolithic multi-aperture plate (306) according to claim 1 or 2, wherein an active functional layer (181a, 181b) has at least one electrode (81, 81.1a, 81.1b, 81.2a, 81.2b, 81.1, 81.2, 81.3, 81.4, 81.5, 81.6, 81.7, 81.8) at each of the plurality of apertures (85), each individually connected to an external voltage supply (830) via the embedded structured metal layer (51). [4] Monolithic multi-aperture plate (306) according to one of claims 1 to 3, further comprising an absorber layer (99) on the upper side (313) directed towards an incident electron beam. [5] Monolithic multi-aperture plate (306) according to claim 4, wherein a material of the absorber layer (99) is gold, aluminum or tungsten. [6] Monolithic multi-aperture plate (306) according to one of claims 1 to 5, wherein the insulating semiconductor compound is formed by silicon dioxide. [7] Monolithic multi-aperture plate (306) according to one of claims 1 to 6, wherein the inner surfaces of an electrode (81, 81.1a, 81.1b, 81.2a, 81.2b, 81.1, 81.2, 81.3, 81.4, 81.5, 81.6, 81.7, 81.8) in an aperture (85) are coated with a thin layer (67) of low conductivity. [8] Monolithic multi-aperture plate (306) according to one of claims 1 to 7, wherein the monolithic multi-aperture plate (306) has a thickness T between the first side or top side (313) and the second side or bottom side (315) of not less than 75µm, not less than 100µm, in particular not less than 200µm. [9] Monolithic multi-aperture plate (306) according to one of claims 1 to 8, wherein the monolithic multi-aperture plate (306) has openings (97) on at least one upper side (313) or lower side (315) for electrically contacting the embedded metallic connecting channels (51, 51.11, 51.12). [10] Monolithic multi-aperture plate (306) according to one of claims 1 to 9, wherein the embedded structured metal layer (51) separates a first sub-substrate (49.1) of the monolithic multi-aperture plate (306) from a second sub-substrate (49.2) of the monolithic multi-aperture plate (306), and wherein the first sub-substrate (49.1) projects beyond the second sub-substrate (49.2) in a lateral direction, and the projecting surface of the otherwise embedded structured metal layer (51) of the first sub-substrate (49.1) contains contact points (53.1, 53.2) for electrically contacting the embedded metallic connecting channels (51, 51.11, 51.12). [11] A method for producing a monolithic multi-aperture plate (306) having a plurality of apertures (85) forming continuous connections between a first side or top side (313) and a second side or bottom side (315) of the multi-aperture plate (306), comprising - manufacturing steps VA1 for producing and structuring a first substrate (49.1) made of doped silicon and silicon dioxide, - forming a first connecting plane (57.1) by applying a first structured metal layer (51.1) to the first substrate (49.1), wherein individual structures of the first structured metal layer (51.1) are separated from one another by silicon dioxide structures (169.6), so that the first connecting plane (57.1) contains a surface portion formed by silicon dioxide structures (169.5), - manufacturing steps VA2 for producing and structuring at least one second substrate (49.2) made of doped silicon and silicon dioxide, - forming a second connecting plane (57.2) by applying a second structured metal layer (51.2) to the second substrate (49.2), wherein individual structures of the second structured metal layer (51.2) are separated from one another by silicon dioxide structures (169.5), so that the second connecting plane (57.2) contains a surface portion formed by silicon dioxide structures (169.6), and wherein the second structured metal layer (51.2) is formed at least partially as a mirror image of the first structured metal layer (51.1), - materially connecting the first and second substrates (49.1) and (49.2) so that the first and second structured metal layers (51.1, 51.2) form a structured metal layer (51) embedded in doped silicon and silicon dioxide with embedded metallic connecting channels (51.11, 51.12). [12] Method according to claim 11, further comprising integrally joining the silicon dioxide structures (169.5, 169.6) which are arranged in the connecting planes (57.1, 57.2) between the structures of the first and second structured metal layers (51.1, 51.2). [13] The method of claim 11 or 12, further comprising - applying and structuring an absorber layer (99) on a top side (313), and - Etching of the apertures (85). [14] Method according to one of claims 11 to 13, wherein each of the manufacturing steps VA1, VA2 contains at least two repetitions of a sequence of steps consisting of - a first lithographic structuring of a polished silicon dioxide layer, - a deposition of a doped polysilicon layer, - a second lithographic structuring of the polished doped polysilicon layer, - an etching to structure the polished doped polysilicon layer, - a coating of the surfaces with silicon dioxide. [15] The method of claim 14, further comprising chemical mechanical polishing (CMP) of the doped polysilicon layer. [16] The method of claim 14 or 15, further comprising chemical mechanical polishing (CMP) of a silicon dioxide surface. [17] Method according to one of claims 11 to 16, wherein a surface area formed by silicon dioxide structures (169.5, 169.6) in a connecting plane (57.1, 57.2) is at least 70%, for example 75%, 80% or 90%. [18] Multi-beam electron beam system (1) comprising a monolithic multi-aperture plate (306) according to one of claims 1 to 10. [19] Multi-beam electron beam system (1) according to claim 18, further comprising a first filter plate (304) arranged in the beam path of the electron beam (309) between the particle source (301) and the monolithic multi-aperture plate (306). [20] Multi-beam electron beam system (1) according to claim 18 or 19, wherein at least one active functional layer (183.1, 183.2, 183.3) of the monolithic multi-aperture plate (306) is formed as a multipole element with a plurality of electrodes (81.1 to 81.8) at each aperture (85).
Citation Information
Patent Citations
MEMS image forming element with built-in voltage generator
US20200317504A1