Wire bonding using a floating pad

Abstract

A semiconductor device module for use in high-performance applications includes a lead frame and a wire bonding scheme designed to improve reliability and reduce cost. A combination of aluminum wire bonds and gold wire bonds can be used to connect dies of different sizes, dies formed on different substrates, or dies using different bonding materials to a common underlying structure. Instead of creating direct connections between the dies, the different types of wire bonds can be connected with an intervening floating pad.

Description

TECHNICAL FIELDThis description relates to the assembly and encapsulation of semiconductor device modules, semiconductor device assemblies, and semiconductor devices. In particular, this description relates to the reliability of wire bonds forming connections between chips in a semiconductor module.BACKGROUNDSemiconductor device packages, e.g., chip packages including power semiconductor devices, may be implemented using multiple semiconductor dies, substrates (e.g., die attach pads (DAPs)), electrical connections, and a molding compound. Power transistors may include, for example, insulated gate bipolar transistors (IGBTs), power metal oxide semiconductor field effect transistors (MOSFETs), etc. Fast recovery diodes (FRDs) may be used in conjunction with power transistors. Electrical connections within a high-power semiconductor device module may include, for example, bond wires, conductive spacers, and conductive clips. A polymeric molding compound may serve as an encapsulant to protect components of the device assembly. Such high-power chip packages encapsulated as semiconductor device modules may be used in various applications, including electric vehicles (EVs), hybrid electric vehicles (HEVs), and industrial applications.SUMMARYIn some aspects, the techniques described herein relate to a device comprising: a substrate; a first die on the substrate, the first die having a current sensing region; a first wire bond coupled to the first die at a plurality of bonding points; and a second die on the substrate, the second die coupled to the current sensing region by a second wire bond.In some aspects, the techniques described herein relate to a device wherein the second die is attached to the substrate by a polyimide tape.In some aspects, the techniques described herein relate to a device where one of the plurality of bonding points is in the current sensing region.In some aspects, the techniques described herein relate to a device wherein the first die is an insulated gate bipolar transistor (IGBT) and the current sensing region is within the IGBT.In some aspects, the techniques described herein relate to a device wherein one of the plurality of bonding points is at an emitter of the IGBT.In some aspects, the techniques described herein relate to a device wherein the first wire bond is configured to carry a current between the emitter and ground and no current between the emitter and the current sensing region.In some aspects, the techniques described herein relate to a device wherein a first bonding pad at the current sensing region for the first wire bond is separated from a second bonding pad at the current sensing region for the second wire bond.In some aspects, the techniques described herein relate to a device wherein a material of the first wire bond comprises aluminum.In some aspects, the techniques described herein relate to a device wherein a material of the second wire bond comprises gold.In some aspects, the techniques described herein relate to a device wherein the first wire bond is grounded to a leadframe.In some aspects, the techniques described herein relate to a device, wherein the controller is configured to sense current in the first wire bond.In some aspects, the techniques described herein relate to a device wherein the current sensing portion is configured to operate without current flow.In some aspects, the techniques described herein relate to a device wherein the current sensing region is electrically floating.In some aspects, the techniques described herein relate to a device wherein the first wire bond and the second wire bond are coupled to bonding pads by gold balls.In some aspects, the techniques described herein relate to a method comprising: coupling an emitter of an insulated gate bipolar transistor (IGBT) on a substrate to a current sensing region via a first wire bond; coupling a controller adjacent to the IGBT device on the substrate to the current sensing region via a second wire bond; monitoring a voltage at the emitter by the controller using the first wire bond; and determining an emitter current from the voltage.In some aspects, the techniques described herein relate to a method wherein coupling to a current sensing region comprises coupling to a floating pad.In some aspects, the techniques described herein relate to a method further comprising coupling the emitter to ground via the first wire bond.In some aspects, the techniques described herein relate to a device comprising: a first integrated circuit (IC) chip coupled to a leadframe, the first IC chip attached to a substrate using solder; a second IC chip attached to the substrate using polyimide tape; a first wire bond connecting the leadframe to the first IC chip; and a second wire bond connecting the first IC chip to the second IC chip.In some aspects, the techniques described herein relate to a device wherein the second IC chip is configured to monitor and control the first IC chip via a current sense floating pad.In some aspects, the techniques described herein relate to a device wherein the first wire bond and the second wire bond are both coupled to the current sense floating pad.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a general schematic diagram of a semiconductor device module according to some implementations of the present disclosure. FIG. 2 is a pictorial perspective view of the semiconductor device module shown in FIG. 1, in accordance with some implementations of the present disclosure. FIG. 3 is a top view of the semiconductor device module illustrated in FIG. 2, in accordance with some implementations of the present disclosure. FIG. 4 is a pictorial perspective view of the semiconductor device module illustrated in FIG. 1, in accordance with some implementations of the present disclosure. FIG. 5 is a pictorial perspective view of the semiconductor device module illustrated in FIG. 1, in accordance with some implementations of the present disclosure. FIG. 6 is a flow chart illustrating a method of configuring a semiconductor device module according to some implementations of the present disclosure.Aspects of the present disclosure will be best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with general practice in the art, various features are not necessarily drawn to scale. The dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. In the drawings, like reference numerals may indicate like and / or similar components (elements, structures, etc.) throughout the several views. The drawings illustrate, by way of example and not limitation, various implementations discussed in the present disclosure. Reference numerals shown in a drawing may not be repeated for the same and / or similar elements in related views. Reference numerals repeated in multiple drawings may not be discussed specifically with respect to each of these drawings, but are provided for the context between related views. Likewise, not all the same elements in the drawings are specifically referenced with a reference numeral when multiple instances of an element are illustrated.DETAILED DESCRIPTIONInter-integrated circuit (IC) chips wiring in a semiconductor module is inherently susceptible to damage or breakage. Consequently, a suboptimal wire bond arrangement may cause yield and / or reliability errors, which may result in reduced yield and increased IC manufacturing costs. This problem is especially important for high power modules that transfer high currents and include expensive materials such as silicon carbide (SiC), high-tech ceramics of silicon nitride (Si 3 N 4) and direct bond metal (DBM) structures, e.g., direct bond copper (DBC) structures. When these high performance modules are manufactured in large volumes, even a small reduction in unit cost can add up to significant savings.The present disclosure relates to implementations of a high-power semiconductor module efficiently configured on a multilayer copper structure having a carefully designed wire bonding configuration. The selective use of aluminum and gold wire bonds as well as proper placement of a current sensing floating pad provides a solution that is both cost effective and highly reliable. Although the implementations described herein are directed to a circuit for use in high power applications, a similar wire bond configuration may be used in other types of circuits to achieve similar advantages as described herein.FIG. 1 is a general block diagram of a semiconductor device module 100, in accordance with some implementations of the present disclosure. The semiconductor device module 100 includes a substrate in the form of a die attach pad (DAP) 102 and at least two electronic components, e.g., semiconductor dies or chip packages 104 (two are shown, a first chip package 104 aand a second chip package 104 b). The chip assemblies 104 may be attached, e.g., mounted on or coupled to a top surface of the die attach pad (DAP) 102 by a bonding agent, e.g., an epoxy, a solder, a silver (Ag) sinter, and / or an adhesive. In some implementations, the first die package 104 aand the second die package 104 bmay be coupled to the DAP 102 by two different bonding means.In some implementations, the first die package 104 ais a controller and the second die package 104 bis an insulated gate bipolar transistor (IGBT). The controller controls the IGBT and serves as a protection device for the IGBT. For example, the controller may provide temperature protection and / or overvoltage protection for the IGBT. The controller may also limit the amount of current supplied to the IGBT, which requires a current sensing function. The controller may be configured to monitor the IGBT over the sensing region 116. In some implementations, the controller includes a current sensing pad 112. The IGBT is a three terminal device that includes an emitter 106, a gate 108, and a collector 110. However, other types of semiconductor dies, e.g., MOSFETs, diodes, etc., may be used as one or more of the die assemblies 104.The die assemblies 104 may be fabricated on various types of semiconductor substrates, e.g., semiconductor wafers, for example, silicon (Si), silicon carbide (SiC), gallium (Ga), gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), glass substrates, sapphire substrates, etc. In some implementations, the die assemblies 104 may be fabricated on different substrates. For example, the IGBT may be fabricated on a silicon substrate, while the controller may be fabricated on a SiC substrate. In some implementations, the chip packages 104 are both fabricated on a SiC substrate.The semiconductor device module 100 may further include a ground 114 and a floating pad for use as the sensing region 116. The ground 114 may be separately disposed from both chip assemblies 104. The ground 114 may be coupled to the current sensing pad 112 on the controller. The ground 114 may also be coupled to the emitter 106 of the IGBT. The ground 114 may be coupled to the emitter 106 by a wire bond of length d, with an extension connecting the emitter 106 to the sensing region 116. The controller may be coupled to sensing region 116 through wire bond 122. The sensing region 116 may be disposed on the chip package 104 bas illustrated in FIG. 1, or on an island between the chip package 104 band the chip package 104 aas illustrated in FIG. 4.FIG. 2 is a pictorial perspective view of the semiconductor device module 100, in accordance with some implementations of the present disclosure. FIG. 2 shows that the chip package 104 bof the IGBT die has a much larger footprint (e.g., area, viewed from above), e.g., about 2 to 3 times larger, than the chip package 104 aof the control die. In some implementations, the emitter 106 of the IGBT is extensive (e.g., has a relatively large area) and has an irregular shape. The IGBT die may include auxiliary devices such as temperature sensors and electrostatic discharge (ESD) detectors in addition to the power transistor.In addition to the components illustrated in FIG. 1, the pictorial view shown in FIG. 2 illustrates features of the semiconductor device module 100, such as a direct connection metal (DBM) structure 202, a leadframe 204, and an encapsulant 212. The leadframe 204 provides signal paths from the semiconductor device module 100 to external devices, powers, and ground connections. The leadframe 204 as shown in FIG. 2 includes elements such as the ground 114 and a rigid S-shaped connector 207. In some embodiments, the leadframe 204 may be arranged in a different level than the DBM structure 202, for example, the leadframe 204 may be located at a height above the DBM structure 202.FIG. 2 shows that the DBM structure 202 is substantially square. In some implementations, the DAP to which the chip packages 104 are mounted may be disposed on top of the DBM structure 202. In some implementations, the die assemblies 104 may be coupled to the leadframe 204 by wire bonds 206. In this implementation, three wire bonds 206 are shown: 206a, 206b, and 206c. In some implementations, the wire bond 206 cis larger in diameter than the wire bonds 206 aand 206 b. In some implementations, the wire bond 206 cincludes multiple portions, e.g., 206 c- 1, 206 c- 2, and 206 c- 3, coupled by multiple connectors, as shown in more detail in FIG. 3. In some implementations, the semiconductor device module 100 has overall dimensions of about 10.0 to 10.5 mm x about 8.5 to 9.0 mm or an area in the range of about 85.0 mm 2 to about 95.0 mm 2. In some implementations, the semiconductor device module 100 has a thickness in a range from about 4.0 mm to about 5.0 mm.In some implementations, the leadframe 204 may be cut or stamped from a thin, rolled metal sheet, e.g., copper. In some implementations, portions of the leadframe 204 are non-coplanar with the die attach pad 102, e.g., some portions of the leadframe 204 may be disposed over the die assemblies 104. Some portions of the leadframe 204 may be directly attached to the DBM structure 202, e.g., by the rigid S-shaped connector 207. Some portions of the leadframe 204 may be coupled to the die assemblies 104 through the wire bonds 206. Accordingly, some or all of the wire bonds 206 may be medium or large scale wire bonds made of, for example, aluminum. In some implementations, the ground 114 may be accessible via such wire bonds 206 on the leadframe 204.In some implementations, the DBM structure 202 may be a direct bond copper (DBC) structure, a direct plate copper (DPC) structure, or a direct bond aluminum (DBA) structure. The DBM structure 202 may be referred to as a heat spreader that provides for single-sided or double-sided cooling of the chip packages 104. In some implementations, the DBM structure 202 has a thickness in a range from about 0.5 mm to about 3.0 mm. In some implementations, the DBM structure 202 is constructed as a three-layer DBM structure that includes an inner dielectric layer (not shown) disposed between upper and lower metal layers. In some implementations, the dielectric layer serves as a thermal mass disposed between the two outer metal layers to draw in and absorb heat. The dielectric layer may also provide electrical isolation between the upper and lower metal layers of the DBM structure. In some implementations, the dielectric layer may be a ceramic, e.g., silicon nitride (Si 3 N 4) or aluminum oxide (Al 2 O 3), where Si 3 N 4 is a much more expensive ceramic material than Al 2 O 3.In some implementations, the die attach pad 102 may be formed by the top metal layer of the DBM structure 202. In some implementations, the dielectric layer and / or the bottom metal layer of the DBM structure 202 may have a larger footprint than the DAP 102. In some implementations, the IGBT may be attached to the DAP 102 by solder 208 while the controller is attached to the DAP 102 by polyimide tape 210.In some implementations, the controller may be configured to monitor an emitter voltage of the IGBT to determine an emitter current. Monitoring the emitter 106 may be accomplished using the sensing region 116 as an interconnection point, wherein the emitter 106 and the current sensing pad 112 are both coupled to the sensing region 116 rather than being directly coupled. For example, emitter 106 may be coupled to sensing region 116 through a first wire bond 206 c- 3. In some implementations, the first wire bond 206 c- 3 may be a continuation of the wire bond 206 cof length d connecting the emitter 106 to the ground 114. The current sensing pad 112 may be coupled to the sensing region 116 by a second wire bond 122.In some implementations, the second wire bond 122 connecting the controller to the sensing region 116 is a gold wire while the first wire bond 206 c- 3 connecting the IGBT to the sensing region 116 is an aluminum wire. In other words, the material of the first wire bond 206 c- 3 is different from the material of the second wire bond 122.In some implementations, the semiconductor device module 100 may be encapsulated by an encapsulant 212, e.g., a polymeric material such as an epoxy molding compound (EMC) that serves to seal and protect the various components of the semiconductor device module 100. Encapsulant 212 is indicated by an exemplary dotted box in FIG. 2, however encapsulant 212 may have a different shape. The encapsulation can be effected, for example, by a process of injection molding or a process of transfer molding. In some implementations, encapsulant 212 may expose DBM structure 202 through openings in encapsulant 212 (not shown). In some implementations, the DBM structure 202 may be disposed in an opening in the encapsulant 212 such that the upper DBM layer serving as the DAP 102 is exposed on the top surface of the semiconductor device module 100. In some implementations, the DBM structure 202 may radiate heat from both the back side and the front side, acting as a double-sided heat sink to dissipate heat generated by the semiconductor device module 100.FIG. 3 is a top view of the semiconductor device module 100 showing the layout, relative sizes, and connections between the various components thereof, in accordance with some implementations of the present disclosure. For example, FIG. 3 shows the relative size of the IGBT die (chip package 104 b) and the control die (chip package 104 a). In some implementations, the IGBT die has a much larger footprint than the footprint of the control die. FIG. 3 also shows the relative sizes of the aluminum wire bonds, e.g., 206c-3, and the gold wire bonds, e.g., 122.FIG. 3 further provides an enlarged view of the wire bonds 206, e.g., large scale aluminum wires, extending between different heights of the semiconductor device module 100. In some implementations, such wire bonds 206 may be segmented to facilitate bending around a bend.In addition to the components illustrated in FIGS. 1 and 2, FIG. 3 provides an enlarged view of multiple bonding points 300 a, 300 b, and 300 calong the first wire bond 206 c- 3 and an enlarged view of gold wires coupling the controller to the IGBT including the second wire bond 122. The first wire bond 206 c- 3, which is a large aluminum wire bond, requires a large bonding pad, while gold wires such as the second wire bond 122 can be easily coupled to a small bonding pad by gold ball bonding. Aluminum wire bonds, such as the first wire bond 206 c- 3, may carry large currents, for example currents exceeding 10 A. Each of the plurality of bonding points 300 a, 300 b, and 300 cmay have a loop shape to provide a secure contact with the emitter 106 of the IGBT and the current sensing region 116. The use of gold wires with gold balls at the connection points on the control die avoids challenges coupled to aluminum wire bonds, e.g., wedge bonds, that are prone to errors, particularly when the polyimide tape 210 is used as the die bonding agent. That is, aluminum wedge bonds may be incompatible with the polyimide tape 210 used to bond the control die to the DAP so that over time, increased resistance of the aluminum wedge bond degrades the electrical connection. The combination of an aluminum wedge type wire bond and a polyimide tape can be weakened when subjected to vibrations occurring during an ultrasonic cleaning process. This failure mode is not likely to occur on the IGBT die that is solder attached to the DAP rather than the polyimide tape 210.FIG. 3 further shows that the first wire bond 206 c- 3 terminates at the sensing region 116 while the second wire bond 122 terminates at a pad 302. The pad 302 may be outside the sensing region 116, but still inside the IGBT. The pad 302 may be coupled to the sensing area 116 via the DAP 102 or through a dedicated connection below the top surface of the DAP 102. The separation between these two connection points helps prevent deterioration of the surface of the sensing region 116 while maintaining electrical connection between the first wire bond 206 c- 3 and the second wire bond 122.FIG. 3 further provides an enlarged view of the sensing region 116 disposed within the IGBT or chip package 104 b. There are several reasons for this placement of the sensing area 116. In some implementations, it may be less expensive to increase the IGBT die to accommodate the sensing area 116 than to increase the control die because the control die is usually more expensive due to the gold wire bonds. Further, the second wire bond 122, which is a gold wire bond, may be shorter when the sensing region 116 is on the IGBT than when it was on the lead frame 204. Thus, the second wire bond 122 may be stronger and less expensive in the disclosed configuration. In some implementations, it may also be less expensive to place the sensing area on the IGBT rather than on the leadframe 204 because the leadframe structure would have to be modified to accommodate a sensing pad. In addition, if the sensing region 116 is to be disposed on the leadframe 204, the leadframe 204 would likely require additional isolation. For at least these reasons, it may be desirable to place the sensing region 116 on the IGBT die on the chip package 104 b.FIG. 4 is a pictorial perspective view of a semiconductor device module 400, in accordance with some implementations of the present disclosure. The implementation shown in FIG. 4 has some differences from the implementation shown in FIGS. 2 and 3. In the implementation illustrated in FIG. 4, the components and the electrical connections of the semiconductor device module are substantially the same as those illustrated in FIGS. 2 and 3, but the sizes and the arrangement of the components and the wiring are different. For example, in the implementation illustrated in FIG. 4, the sensing region 116 may be arranged on an island, e.g. on a third chip package 104 carranged between the first chip package 104 aand the second chip package 104 b. The third chip package 104 cincluding the sensing region 116 may be attached to the DAP 102 by solder 208.FIG. 5 is a pictorial perspective view of a semiconductor device module 500 in accordance with some implementations of the present disclosure. FIG. 5 has some differences from the implementations shown in FIGS. 2, 3, and 4. In the implementation illustrated in FIG. 5, the components and the electrical connectivity of the semiconductor device module are substantially the same as in the previous implementations, but the sizes and the arrangement of the components and the wiring are different. For example, in the implementation illustrated in FIG. 5, the top surface of a leadframe 504 may be brought to the same height as the top surface of the DBM structure 202, i.e., the DAP 102, such that a substantially straight leadframe connector 507 may replace the rigid S-shaped connector 207. The leadframe 504 is coplanar with the DAP 102, rather than being at a height above the DBC structure 202. In some implementations of FIG. 5, the placement of the die assemblies 104 aand 104 bmay be the same as the implementation shown in FIGS. 2 and 3 where the sensing area 116 is on the die assembly 104 b. Alternatively, in some implementations, the placement of the die packages may be the same as the implementation shown in FIG. 4 where sensing area 116 is on die package 104 c.Although various implementations illustrated in FIGS. 2, 3, 4, and 5 are presented herein, other implementations may be used in which circuit components are arranged differently and the wire bonds are routed differently accordingly. It should be noted that in each of these possible implementations, the electrical connectivity of the semiconductor device module 100 is substantially equivalent to that illustrated in FIGS. 2, 3, 4 and 5 and described below with reference to FIG. 6.FIG. 6 is a flow diagram illustrating a method 600 of electrically monitoring a chip package 104, e.g., the IGBT of the semiconductor device module 100, in accordance with some implementations of the present disclosure. Operations 602- 610 of method 600 may be performed as described below with reference to FIGS. 1, 2, and 3 above, in accordance with some implementations. The operations of method 600 may or may not be performed in a different order depending on particular applications. Note that in method 600, the die package 104 may not be fully monitored. Accordingly, it should be appreciated that additional processes may be provided before, during, or after the method 600, and that some of these additional processes may be briefly described herein.At 602, the method 600 includes coupling an emitter of the IGBT to the sensing region 116 using a first wire bond 206 c- 3. The first wire bond 206 c- 3 may be an aluminum bond wire attached to the sensing region 116 using solder, for example.At 604, the method 600 includes coupling the emitter 106 of the IGBT to ground at the leadframe 204. The ground connection may be made by a bonding wire of length d, as illustrated in FIG. 1. In some implementations, the first wire bond 206 c- 3 may be a portion of the wire bond 206 c. The wire bond 206 cmay have a resistance in a range of about 1 to 5 mΩ.At 606, the method 600 includes coupling the controller to the sensing region 116 via a second wire bond 122. The second wire bond 122 may be a small diameter wire because it is not necessary to transmit a large current. Thus, the second connection wire may be a gold wire.At 608, the method 600 includes monitoring the voltage at the emitter 106 on the first wire bond 206 c- 3.At 610, method 600 includes determining an emitter current from the emitter voltage. For example, the emitter current may be calculated from the emitter voltage and the resistance of the wire bond coupled to the emitter 106. In some implementations, the IGBT current is at least 10 A and the voltage generated at the emitter 106 is in a range of about 20 to 40 mV. Wire bond 206 cincluding first wire bond 206 c- 3 is therefore desirably a large diameter wire capable of transferring a large current. In some implementations, the diameter of the wire bonds 206 cmay be about 200 μm, while the wire bonds 206 aand 206 bmay have diameters of about 155 μm.As described above, various implementations of a semiconductor device module for use in high power applications include a lead frame and a wire bonding scheme configured to improve reliability and reduce cost. A combination of aluminum wire bonds and gold wire bonds may be used when the coupled IC chips have different sizes and when different materials are used to bond the chips to a substrate. Instead of making direct connections between the chips, the different wire bonds may be coupled with a floating pad therebetween.It will be understood that in the foregoing description, when an element such as a layer, region, or substrate is referred to as being "on," "connected to," "electrically connected to," "coupled to," or "electrically coupled to" another element, it may be directly disposed on, connected to, or coupled to the other element, or one or more intervening elements may be present. In contrast, there are no intervening elements or layers when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer. Although the terms "directly on", "directly connected to", or "directly coupled to" may not be used in the detailed description, elements shown as "directly on", "directly connected", or "directly coupled" may be referred to as such. The claims of the application may be altered to indicate example relationships described in the specification or shown in the figures.As used in this specification, unless the context clearly indicates a particular case, a singular form may include a plural form. Spatially relative terms (e.g., above, above, upper, below, below, below, lower, above, below, and the like) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms "above" and "below" may include "vertically above" and "vertically below", respectively. In some implementations, the term "adjacent" may include "laterally adjacent to" or "horizontally adjacent to.".Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor device processing techniques in conjunction with semiconductor substrates including, but not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and / or the like.While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now be apparent to those skilled in the art. For example, features illustrated with respect to an implementation may also be included in other implementations where appropriate. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of implementations. It is to be understood that they have been presented by way of example only, and not limitation, and that various changes in form and details may be made. Each portion of the apparatus and / or method described herein may be combined in any combination, except for mutually exclusive combinations. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the various implementations described.

Claims

A device, comprising: a substrate; a first die coupled to the substrate and having a current sensing region; a first wire bond coupled to the first die at a plurality of bonding points; and a second die coupled to the substrate, wherein the second die is coupled to the current sensing region by a second wire bond.The device of claim 1, wherein the second die is attached to the substrate by a polyimide tape.The device of claim 1, wherein one of the plurality of bonding points is in the current sensing region.The device of claim 1, wherein the first die comprises an insulated gate bipolar transistor (IGBT), and the current sensing region is within the IGBT.The device of claim 4, wherein one of the plurality of bonding points is at an emitter of the IGBT.The device of claim 5, wherein the first wire bond is configured to transfer a current between the emitter and ground and no current between the emitter and the current sensing region.The device of claim 1, wherein a first bonding pad at the current sensing region for the first wire bond is separated from a second bonding pad at the current sensing region for the second wire bond.The device of claim 1, wherein a material of the first wire bond comprises aluminum.The device of claim 1, wherein a material of the second wire bond comprises gold.The device of claim 1, wherein the first wire bond is coupled to ground at a lead frame.The apparatus of claim 1, wherein the second die is configured to sense current in the first wire bond.The device of claim 1, wherein the current sensing portion is configured to operate without current flow.The device of claim 1, wherein the current sensing area is electrically floating.The device of claim 1, wherein the first wire bond and the second wire bond are coupled to bonding pads by gold balls.A method comprising: coupling an emitter of an insulated gate bipolar transistor (IGBT) on a substrate to a current sensing region via a first wire bond; coupling a controller adjacent to the IGBT device on the substrate to the current sensing region via a second wire bond; monitoring a voltage at the emitter by the controller using the first wire bond; and determining an emitter current from the voltage.The method of claim 15, wherein coupling to a current sensing region comprises coupling to a floating pad.The method of claim 15, further comprising coupling the emitter to ground via the first wire bond.A device, comprising: a first integrated circuit (IC) chip coupled to a lead frame, the first IC chip attached to a substrate using solder; a second IC chip attached to the substrate using polyimide tape; a first wire bond connecting the lead frame to the first IC chip; and a second wire bond connecting the first IC chip to the second IC chip.The apparatus of claim 18, wherein the second IC chip is configured to monitor and control the first IC chip via a current sensing floating pad.The device of claim 19, wherein the first wire bond and the second wire bond are both coupled to the current sensing floating pad.

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