Semiconductor packages and associated manufacturing processes

Abstract

A method includes a step of providing a first leadframe panel including a plurality of first leadframes, the first leadframes including a plurality of first diepads coated with a first coating material. The method further includes a step of providing a second leadframe panel separate from the first leadframe panel and including a plurality of second leadframes, the second leadframes including a plurality of second diepads coated with a second coating material different from the first coating material. The method further includes a step of mechanically joining the first leadframe panel and the second leadframe panel to form a combined leadframe panel. The method further includes a step of mounting a plurality of first semiconductor chips of a first type on the first leadframe panel.The method further includes a step of mounting a plurality of second semiconductor chips of a second type different from the first type on the second lead frame panel.

Description

Technical FieldThe present disclosure relates to semiconductor packages and associated fabrication methods.BackgroundSemiconductor packages may include various types of semiconductor chips that may be mounted on one or more leadframes of the package. The lead frames may be of different designs and may be made of different materials. Integrating different semiconductor chips in a same package may present a challenge and in some cases requires different leadframe surfaces for appropriately mounting the semiconductor chips. This may require expensive coating technologies, which greatly increase the overall cost of the package. In view of this, it would be desirable to provide simple and cost effective methods for manufacturing advantageous semiconductor packages.US 5 792 676 A relates to a method for manufacturing a power semiconductor device comprising a power semiconductor chip such as a power transistor or a power MOSFET and a control semiconductor chip for controlling the power semiconductor chip, which are accommodated in the same package, and a lead frame. The publication US 2009 / 0 014 848 A1 relates to a mixed-wire semiconductor leadframe housing and a method for producing the housing. US 5 313 095 A relates to a multichip semiconductor device in which the same package includes a power semiconductor chip, namely a power transistor or a power MOSFET, and a control semiconductor chip for controlling the power semiconductor chip.SummaryOne aspect of the present disclosure relates to a method. The method comprises a step of providing a first leadframe panel comprising a plurality of first leadframes, wherein the first leadframes comprise a plurality of first die pads coated with a first coating material. The method further comprises a step of providing a second leadframe panel separate from the first leadframe panel and comprising a plurality of second leadframes, wherein the second leadframes comprise a plurality of second die pads coated with a second coating material different from the first coating material. The method further comprises a step of mechanically connecting the first lead frame panel and the second lead frame panel to form a combined lead frame panel. The method further comprises a step of mounting a plurality of first semiconductor chips of a first type on the first leadframe panel. The method further includes a step of mounting a plurality of second semiconductor chips of a second type different from the first type on the second lead frame panel.Another aspect of the present disclosure relates to a semiconductor package (semiconductor package). The semiconductor package includes a first leadframe including a first die pad coated with a first coating material and a second leadframe including a second die pad coated with a second coating material different from the first coating material. The semiconductor package further includes a first semiconductor chip of a first type mounted on the first lead frame and a second semiconductor chip of a second type different from the first type mounted on the second lead frame.Brief Description of the DrawingsMethods and apparatuses according to the disclosure will be described in more detail below based on the drawings. The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals may designate corresponding like parts. The technical features of the various illustrated examples may be combined unless they are mutually exclusive and / or may be selectively omitted unless described as necessarily required. FIG. 1 illustrates a flow diagram for a method according to the disclosure. FIG. 2 includes FIGS. 2A to 2H schematically illustrating a method according to the disclosure. FIG. 3 includes FIGS. 3A through 3C schematically illustrating leadframe panels that may be used in a method according to the disclosure. FIG. 4 schematically illustrates a cross-sectional side view of a semiconductor package 400 according to the disclosure.Detailed DescriptionIn the following detailed description, reference is made to the accompanying drawings, in which is shown by way of illustration specific aspects under which the disclosure may be practiced. In this context, directional terms such as "top", "bottom", "front", "rear", etc. may be used with respect to the orientation of the described figures. Since the components of the described devices may be arranged in different orientations, the directional terminology is for the purpose of illustration only and is in no way limited. Other aspects may also be utilized and structural or logical changes may be made without departing from the concept of the present disclosure. Therefore, the following detailed description is not to be taken in a limited sense, and the concept of the present disclosure is defined by the appended claims.Referring now to FIG. 1, a flowchart of a method according to the disclosure is illustrated. The method is described in general form to qualitatively specify aspects of the disclosure. The method may be used to manufacture semiconductor packages according to the disclosure, such as semiconductor package 400 of FIG. 4 described later. For example, the method may be extended by any of the aspects described in connection with the method of FIG. 2 or any other example described herein.In a step 2, a first lead frame panel may be provided, which includes a plurality of first lead frames. The first leadframes may include a plurality of first die pads coated with a first coating material. In step 4, a second lead frame panel may be provided, which is separate from the first lead frame panel and includes a plurality of second lead frames. The second leadframes may include a plurality of second die pads coated with a second coating material different from the first coating material. In a step 6, the first lead frame panel and the second lead frame panel may be mechanically connected to form a combined lead frame panel. In a step 8, a plurality of first semiconductor chips of a first type may be mounted on the first lead frame panel. In a step 10, a plurality of second semiconductor chips of a second type different from the first type may be mounted on the second lead frame panel.It should be noted that the above steps need not necessarily be performed in the predetermined order, but may be interchanged at least partially in order if technically possible. For example, the steps 8 and 10 of mounting the first and second semiconductor chips on the first and second leadframe panels may be performed before or after the step 6 of mechanically connecting the first and second leadframe panels to form the combined leadframe panel.Referring now to FIGS. 2A to 2H, another method according to the disclosure will be described. The method of FIG. 2 may be considered, at least in part, as a more detailed version of the previously described method of FIG. 1. For example, the method of FIG. 2 may be used to fabricate the semiconductor package 400 of FIG. 4 described later.In FIG. 2A, a first lead frame panel 12A including a plurality of individual first lead frames 14A may be provided. For example, the step of FIG. 2A may correspond to step 2 of FIG. 1. The first leadframes 14A may include a plurality of first die pads 16A. In the illustrated example, the first leadframe panel 12A may include a first peripheral frame 18A, where multiple rows of the first die pads 16A may be connected to opposing sides of the first peripheral frame 18A and separated by first column 20A. For example, each row of the first die pads 16A may extend in the y-direction. The number of first die pads 16A per leadframe 14A may depend on the type of semiconductor package to be manufactured. In the case shown, each individual leadframe 14A may include a single first die pad 16A. However, in other cases, a single leadframe 14A may also include two or even more first die pads 16A.It should be appreciated that the method of FIG. 2 may correspond to a batch process in which multiple leadframes and semiconductor chips may be processed in a single batch, as opposed to separately processing each individual leadframe and semiconductor chip. Therefore, the first lead frame panel 12A may include a large number of individual lead frames 14A, for example, dozens to hundreds. In a non-limiting and purely illustrative example, the first leadframe panel 12A may include 25 rows of 5 individual first leadframes 14A each, i.e., a total of 125 individual first leadframes 14A.The first die pads 16A may be coated with a first coating material, which may depend on the type of semiconductor chips to be mounted on the first die pads 16A and / or the material of the electrical connection elements to be connected to the first die pads 16A, for example. For example, an electrical connection element may include or correspond to at least one of a wire, a strap, a clip, or the like. For the sake of simplicity, wires can be referred to in particular as electrical connection elements in this description. It will be appreciated, however, that the wires described herein in connection with a particular example may be replaced by other types of electrical connection elements, such as straps, clamps, or the like. In other words, the examples described herein are not limited to electrical connection elements in the form of wires. For example, the first coating material may include or correspond to at least one of Ni, NiP, NiNiP, Cu, or Ag. In one case, the first die pads 16A may be fully coated with the first coating material. In other cases, only a portion of a respective first die pad 16A may be coated with the first coating material while another portion of the die pad may remain uncoated.The first leadframes 14A may further include a plurality of first leads (or pins or lead fingers) 22A, which may or may not be mechanically and / or electrically connected to an associated first die pad 16A. The number of first leads 22A per individual first lead frame 14A may depend on the type of semiconductor package to be manufactured. In the case shown, each individual first leadframe 14A may include a plurality of first leads 22A arranged to the right of a respective first die pad 16A. However, in other cases, the number and arrangement of the first leads 22A may be different for a single first lead frame 14A.The first leads 22A may be coated with a third coating material (a second coating material will be discussed later in connection with FIG. 2B ). The third coating material may depend on a material of the wires that may be connected to the first leads 22A, for example. For example, the third coating material may include or correspond to at least one of Ni, NiP, NiNiP, Cu, or Ag. For example, the third coating material on the first leads 22A may be different than the first coating material on the first die pads 16A. In another example, the first coating material and the third coating material may be the same.The first leadframe panel 12A may include a core on which the first coating material of the first die pads 14A and / or the third coating material of the first leads 22A may have been deposited. The core of the first lead frame panel 12A may include a first core material. For example, the first core material may include or be made of Cu or a Cu alloy.In FIG. 2B, a second lead frame panel 12B including a plurality of individual second lead frames 14B may be provided. For example, the step of FIG. 2B may correspond to step 4 of FIG. 1. The second leadframes 14B may include a plurality of second die pads 16B. In the illustrated example, the second leadframe panel 12B may include a second peripheral frame 18B, where multiple rows of the second die pads 16B may be connected to opposite sides of the second peripheral frame 18B and separated by second column 20B. For example, each row of the second die pads 16B may extend in the y-direction. The number of second die pads 16B per individual second leadframe 14B may depend on the type of semiconductor package to be manufactured. In the case shown, each individual second leadframe 14B may include two second die pads 16B. However, in other cases, a single second leadframe 14B may also include only one or even more than two second die pads 16B.The second die pads 16B may be coated with a second coating material, which may depend on the type of semiconductor chips to be mounted on the second die pads 16B and / or the material of the wires to be connected to the second die pads 16B, for example. For example, the second coating material may include at least one of Cu or Ag. Additionally or alternatively, the second leadframes 14B may be pre-plated frames (PPF) or micro-pre-plated frames (μ). In one case, the second die pads 16B may be fully coated with the second coating material. In other cases, only a portion of a respective second die pad 16B may be coated with the second coating material, while another portion of the die pad may remain uncoated.The second leadframes 14B may further include a plurality of second leads 22B, which may or may not be mechanically and / or electrically connected to an associated second die pad 16B. The number of second leads 22B per individual second lead frame 14B may depend on the type of semiconductor package to be manufactured. In the case shown, each individual second leadframe 14B may include a plurality of second leads 22B arranged to the left of a respective second die pad 16B. However, in other cases, the number and arrangement of the second leads 22B may be different for a single second lead frame 14B.The second leads 22B may be coated with a fourth coating material depending on, for example, the material of the wires that may be connected to the second leads 22B. For example, the fourth coating material may include or correspond to at least one of Cu or Ag. In an example, the fourth coating material on the second leads 22B may be different than the second coating material on the second die pads 16B. In another example, the fourth coating material and the second coating material may be the same.The second leadframe panel 12B may include a core onto which the second coating material of the second die pads 16B and / or the fourth coating material of the second leads 22B may have been deposited. The core of the second lead frame panel 12B may include a second core material. In particular, the second core material of the second lead frame panel 12B may be different from the first core material of the first lead frame panel 12A. For example, the second core material may include or be made of Al or an Al alloy.In FIG. 2C, a plurality of first semiconductor chips 24A of a first type may be mounted on the first lead frame panel 12A. For example, the step of FIG. 2C may correspond to step 8 of FIG. 1. In the illustrated example, the first semiconductor chips 24A may be mounted on the first die pads 16A. However, in further examples, the first semiconductor chips 24A may be at least partially mounted on the first leads 22A. In the non-limiting case shown, a single first semiconductor die 24A may be mounted on each first die pad 16A. However, it should be appreciated that the number and arrangement of the second semiconductor chips 24B may depend on the type of semiconductor package to be manufactured and may vary in other examples.In general, the semiconductor chips described herein may be made of an elementary semiconductor material (e.g., Si) or a wide band gap semiconductor material or a compound semiconductor material (e.g., SiC, GaN, SiGe, GaAs). The semiconductor chips may be of any kind and may include integrated circuits with active electronic components and / or passive electronic components. The integrated circuits may be configured as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits, passive integrated devices, etc. The terms "chip", "semiconductor chip", "die", "semiconductor die" may be used interchangeably in this specification.The first semiconductor chips 24A can be, in particular, power semiconductor chips. In this context, the term "power semiconductor chip" may refer to a semiconductor chip that may provide at least one of high voltage blocking or high current carrying capabilities. A power semiconductor chip may be configured to transmit high currents with a maximum current value of several amperes, such as 10A, or a maximum current value of up to or more than 100A. Similarly, the voltages associated with such current values may have values from a few volts to a few tens or hundreds, or even thousands of volts, such as about 1200V, about 1600V, about 2400V, or the like. Power semiconductor chips may be used in any type of power application, such as MOSFETs (metal oxide semiconductor field effect transistors), half bridge circuits, power modules with gate drivers, etc. For example, power semiconductor chips may include or be part of a power device such as a power MOSFET, a low voltage power MOSFET, a power IGBT (insulated gate bipolar transistor), a power diode, a superjunction power MOSFET, etc.The first semiconductor chips 24A may be mounted on the first leadframe panel 12A based on a process or technique, which may in particular be configured for mounting power semiconductor chips on a leadframe or a die pad. For example, mounting the first semiconductor chips 24A on the first leadframe panel 12A may be based on at least one of a diffusion soldering process, a soft soldering process, a preform soldering process (preform soldering), a sintering process or a solder paste process.After mounting the first semiconductor chips 24A on the first leadframe panel 12A, further steps may be performed in connection with FIG. 2C, which are not explicitly illustrated for the sake of simplicity. For example, the first semiconductor chips 24A may be electrically connected to the first lead frame panel 12A via first electrical connectors. In particular, the first semiconductor chips 24A may be electrically coupled to at least one of the first die pads 16A or the first leads 22A. For example, the first electrical connection elements may include or correspond to first wires including a first wire material.The characteristics of the first wires and the wire bonding methods used may be particularly adjusted to the type of first semiconductor chips 24A and the characteristics of the first and third coating materials, which may be disposed on the first die pads 16A and the first leads 22A, respectively. For example, the first wire material may include Al or alloys thereof. The electrical coupling of the first semiconductor chips 24A to the first leadframe panel 12A via the first wires may be based on a wedge bonding method.In FIG. 2D, a plurality of second semiconductor chips 24B of a second type different from the first type may be mounted on the second lead frame panel 12B. For example, the step of FIG. 2D may correspond to step 10 of FIG. 1. In the illustrated example, the second semiconductor chips 24B may be mounted on the second die pads 16B. However, in further examples, the second semiconductor chips 24B may be at least partially mounted on the second leads 22B. In the non-limiting case shown, a single second semiconductor die 24B may be mounted on each second die pad 16B. However, it should be appreciated that the number and arrangement of the second semiconductor chips 24B may depend on the type of semiconductor package to be manufactured and may vary in other examples.In particular, the second semiconductor chips 24B may be at least one of logic or driver semiconductor chips. For example, a logic or driver semiconductor chip may be configured to drive and / or control, e.g., one or more power semiconductor chips, such as via a gate terminal of a power transistor chip. Some logic semiconductor chips can thus also be referred to as driver semiconductor chips (or drivers) or control semiconductor chips (or controllers). In particular, in a manufactured semiconductor package, a logic or driver semiconductor die 24B may be configured to drive or control one or more power semiconductor dies 24A.The second semiconductor chips 24B may be mounted on the second leadframe panel 12B based on a method or technique, which may in particular be configured for mounting logic or driver semiconductor chips on a leadframe or diepad. For example, mounting the second semiconductor chips 24B on the second leadframe panel 12B may be based on at least one of an adhesion process, a die attach film process, or a sintering process. Since the first semiconductor chips 24A and the second semiconductor chips 24B may be of different types, mounting the first semiconductor chips 24A on the first leadframe panel 12A and mounting the second semiconductor chips 24B on the second leadframe panel 12B may be based on different methods.After the second semiconductor chips 24B have been mounted on the second leadframe panel 12B, further steps may be performed in connection with FIG. 2D, which are not explicitly illustrated for the sake of simplicity. For example, the second semiconductor chips 24B may be electrically connected to the second leadframe panel 12B via second electrical connectors. In particular, the second semiconductor chips 24B may be electrically coupled to at least one of the second die pads 16B or the second leads 22B. For example, the second electrical connection elements may include or correspond to second wires including a second wire material different from the first wire material of the first wires.The characteristics of the second wires and the wire bonding methods used may be particularly matched to the type of second semiconductor chips 24B and the characteristics of the second and fourth coating materials, which may be disposed on the second die pads 16B and the second leads 22B, respectively. For example, the second wire material may include Cu or alloys thereof. In addition, the electrical coupling of the second semiconductor chips 24B to the second leadframe panel 12B via the second wires may be based on a ball bonding method. Since the first semiconductor chips 24A and the second semiconductor chips 24B may be of different types, electrically coupling the first semiconductor chips 24A to the first leadframe panel 12A via the first wires and electrically coupling the second semiconductor chips 24B to the second leadframe panel 12B via the second wires may be based on different methods.In FIG. 2E, the first leadframe panel 12A and the second leadframe panel 12B may be mechanically connected to form a combined leadframe panel 26. For example, the step of FIG. 2E may correspond to step 6 of FIG. 1. The leadframe panels 12A and 12B may be connected using any suitable method or technique. For example, mechanically joining the first leadframe panel 12A and the second leadframe panel 12B to form the combined leadframe panel 26 may include at least one of clamping, gluing, or welding. As can be seen from the example of FIG. 2E, in the combined leadframe panel 26, the rows of the first die pads 16A of the first leadframe panel 12A may be arranged at the second columns 20B of the second leadframe panel 12B, and the rows of the second die pads 16B of the second leadframe panel 12B may be arranged at the first columns 20A of the first leadframe panel 12A.In one case, the first lead frame panel 12A and the second lead frame panel 12B may be aligned with each other such that the first peripheral frame 18A and the second peripheral frame 18B may overlap when viewed in the z direction. After such alignment, the first peripheral frame 18A and the second peripheral frame 18B may be secured together based on at least one of the following methods: clamping, bonding, or welding. That is, a mechanical connection between the first lead frame panel 12A and the second lead frame panel 12B may include only a mechanical connection between the first peripheral frame 18A and the second peripheral frame 18B, while the first individual lead frames 14A of the first lead frame panel 12A are not necessarily connected to the second individual lead frames 14B of the second lead frame panel 12B.In the example of FIG. 2, the mounting of the first semiconductor chips 24A on the first leadframe panel 12A as shown in FIG. 2C and the mounting of the second semiconductor chips 24B on the second leadframe panel 12B as shown in FIG. 2D may be performed before mechanically connecting the first leadframe panel 12A and the second leadframe panel 12B to form the combined leadframe 26. In this case, the mounting of the first semiconductor chips 24A and the second semiconductor chips 24B may be performed separately in different production lines. However, it should be appreciated that in further examples, the first leadframe panel 12A and the second leadframe panel 12B may be first connected to form the combined leadframe panel 26, and then the first semiconductor chips 24A and the second semiconductor chips 24B may be mounted at the respective positions on the combined leadframe 26.Similarly, the electrical coupling of the first semiconductor chips 24A to the first leadframe panel 12A via the first wires and the electrical coupling of the second semiconductor chips 24B to the second leadframe panel 12B via the second wires may be performed before mechanically connecting the first leadframe panel 12A and the second leadframe panel 12B to form the combined leadframe 26. In this case, the electrical coupling of the semiconductor chips 24A and 24B to the lead frame panels 12A and 12B, respectively, may be performed separately in different production lines. However, it should be appreciated that in further examples, the first leadframe panel 12A and the second leadframe panel 12B may be first connected to form the combined leadframe 26, and then the first semiconductor chips 24A and the second semiconductor chips 24B may be electrically connected to the respective locations on the combined leadframe 26 via respective wires.In a further optional step of FIG. 2E, at least one of the first semiconductor chips 24A may be electrically coupled to at least one of the second semiconductor chips 24B via one or more electrical connection elements, such as at least one of wires, straps, clips, or the like. In this connection, at least one of a wire bonding method, a clip attachment, or the like may be performed. In particular, an electrical coupling may be provided between first semiconductor chips 24A and second semiconductor chips 24B, which will be included in the same semiconductor package to be manufactured. An example of such a semiconductor package and an electrical connection between a first semiconductor chip 24A and a second semiconductor chip 24B is shown and discussed in connection with FIG. 4.FIG. 2F illustrates the combined leadframe 26 of FIG. 2E when viewed in the y-direction. In the illustrated example, the two leadframe panels 12A and 12B may have different thicknesses, particularly when measured in the z-direction. In particular, a first thickness of the first lead frame panel 12A may be greater than a second thickness of the second lead frame panel 12B. If the first semiconductor chips 24A are power semiconductor chips, a greater first thickness of the first leadframe panel 12A may increase the dissipation of heat and allow the transport of high electrical currents. A lesser second thickness of the second leadframe panel 12B may provide finer routing of the signals when the second semiconductor chips 24B are logic and / or driver semiconductor chips.FIG. 2G illustrates a cross-sectional side view of the combined leadframe 26 of FIG. 2E with respect to a sectional plane A-A' and viewed in the x-direction. As can be seen from the examples of FIGS. 2F and 2G, the first leadframe panel 12A and the second leadframe panel 12B (in particular the first die pads 16A and the second die pads 16B) in the combined leadframe panel 26 may be arranged at different heights with respect to the z-direction (the first leadframe panel 12A may be arranged below the second leadframe panel 12B). As further seen from FIG. 2G, due to these different heights of the leadframe panels 12A and 12B, a free or empty area or space 28 may be provided below the second die pads 16B of the first leadframe panel 12B, the function of which will be described later.In FIG. 2H, an encapsulation process may be performed, wherein the first semiconductor chips 24A, the second semiconductor chips 24B and the combined leadframe panel 26 may be at least partially encapsulated in an encapsulation material 30. For example, the method of FIG. 1 may be extended by the step of FIG. 2H. The encapsulation material 30 may include or be made from at least one of epoxy, a filled epoxy, a fiberglass filled epoxy, an imide, a thermoplastic, a thermoset polymer, a polymer blend, a laminate, a mold compound, or the like. Various techniques may be used to encapsulate components in the encapsulation material 30, for example, at least one of compression molding, injection molding, powder injection molding, liquid casting, map molding, laminating, or the like.In the illustrated example, a plurality of rods (or strips) may be formed from the encapsulation material 30, wherein each rod may encapsulate a row of first die pads 16A and an adjacent row of second die pads 16B. In the case shown, the rods of encapsulating material 30 may extend in the y-direction between the peripheral frames 18A and 18B. The peripheral frames 18A and 18B may remain uncovered by the encapsulation material 30.Returning to the side view of FIG. 2G, after performing the encapsulation, the lower main surface of the first leadframe panel 12A opposite the upper main surface on which the first semiconductor chips 24A may be mounted may remain uncovered by the encapsulation material 30. In contrast, the lower main surface of the second lead frame panel 12B opposite to the upper main surface on which the second semiconductor chips 24B may be mounted may be covered with the encapsulation material 30. In other words, the previously empty region 28 may have been filled with the encapsulation material 30. Accordingly, the second leadframe panel 12B may be electrically insulated by a dielectric encapsulation material 30. In this way, by selecting a corresponding thickness of the first leadframe panel 12A, a defined insulation thickness may be provided for the covered second leadframes 14B and the second semiconductor chips 24B arranged thereon.It is understood that the method of FIG. 2 may include further steps, which are not explicitly illustrated for simplicity. In an exemplary further step, the semiconductor chips 24A, 24B and the combined leadframe panel 26 embedded in the encapsulation material 30 may be singulated into a plurality of semiconductor packages. In this regard, the rods of encapsulation material 30 may be separated from each other as shown in FIG. 2H by cutting or scrambling the array along the y-direction between the individual rods. Moreover, each separate rod of encapsulation material 30 may be divided into a plurality of semiconductor packages by slicing or dicing the respective rod in the x-direction.For example, a singulated semiconductor package may include an individual first leadframe 14A including a first die pad 16A coated with the first coating material and an individual second leadframe 14B including a second die pad 16B coated with the second coating material. A first semiconductor chip 24A of the first type may be mounted on the first lead frame 14A, and a second semiconductor chip 24B of the second type may be mounted on the second lead frame 14B. A more detailed example of a semiconductor package 400 according to the disclosure that may be manufactured according to the methods of FIGS. 1 and 2 will be shown and described later in connection with FIG. 4.The methods of FIGS. 1 and 2 have been described based on example and non-limiting types of leadframe panels 12A and 12B. However, it is to be understood that the methods may also be performed with other types of leadframe panels. In general, the design and material properties of the leadframe panels used may depend on the type of semiconductor package to be manufactured by the respective method. In this regard, FIGS. 3A through 3C schematically illustrate leadframe panels having an alternative design that may also be used in a method according to the disclosure. The leadframe panels of FIG. 3, as described below, may include some or all of the features of the leadframe panels of FIG. 2.A first lead frame panel 12A shown in FIG. 3A may include two different types of individual first lead frames 14A and 14A'. The first type of individual leadframe 14A may include a plurality of leads 22A and die pads 16A, which may be arranged in rows connected to opposite sides of the first peripheral frame 18A. Similarly, the individual second type leadframes 14A' may include multiple leads 22A' and die pads 16A', which may also be arranged in rows connected to opposite sides of the first peripheral frame 18A. A row of die pads 16A of the first type may be separated from a right-adjacent row of die pads 16A' of the second type by a wide gap 20A. In addition, the same row of first type die pads 16A may be separated from a left adjacent row of second type die pads 16A' by a narrower gap 20A'. Similar to previous examples, the first die pads 14A and 14A' may be coated with a first coating material.A second lead frame panel 12B shown in FIG. 3B may include only one type of single second lead frames 14B. The individual second leadframes 14B may include a plurality of second die pads 16B, which may be arranged in rows connected to opposite sides of the second peripheral frame 18B. In the illustrated example, the individual second leadframes 14B do not necessarily include leads. The rows of second die pads 16B may be separated by second column 20B. Similar to previous examples, the second die pads 16B may be coated with a second coating material different from the first coating material.FIG. 3C shows a combined leadframe 26 that may have been formed by mechanically connecting the first leadframe panel 12A and the second leadframe panel 12B of FIGS. 3A and 3B. In the combined leadframe panel 26, the rows of the second die pads 16B of the second leadframe panel 12B may be arranged at the first columns 20A of the first leadframe panel 12A. Similar to the example of FIG. 2, semiconductor chips may be mounted on the leadframe panels 12A and 12B and electrically connected to the individual leadframes, as discussed above in connection with FIGS. 2C and 2D. In further steps, the semiconductor chips and the combined leadframe 26 may be encapsulated and singulated to obtain a plurality of semiconductor packages. In this regard, a dicing process may include, for example, cutting or dicing along the second column 20A', as indicated by dashed lines in FIG. 3C. For example, a singulated semiconductor package may include a first die pad 16A of the first type, a first die pad 16A' of the second type, and a second die pad 16B.In a more specific and non-limiting example, the combined leadframe 26 of FIG. 3C may be used to fabricate semiconductor packages including three semiconductor chips that may be electrically connected together to form a half bridge circuit. In this case, each of the manufactured semiconductor packages may contain a first power semiconductor chip and a second power semiconductor, which correspond, for example, to a low-side switch and a high-side switch of the half-bridge circuit, respectively. The two power semiconductor chips may be mounted on first die pads 16A and 16A' originating from the first leadframe panel 12A. Additionally, a manufactured semiconductor package may include a logic semiconductor chip that may be configured to drive and / or control at least one of the first power semiconductor chip and the second power semiconductor chip. The logic semiconductor die may be mounted on a second die pad 16B originating from the second leadframe panel 12B. In particular, the logic semiconductor chip may include a driver circuit configured to control the high-side switch and the low-side switch of the half bridge circuit.FIG. 4 schematically illustrates a cross-sectional side view of a semiconductor package 400 according to the disclosure. For example, the semiconductor package 400 may be manufactured based on any of the methods described above according to the disclosure. Accordingly, the explanations given above according to one of FIGS. 1 to 3 can also apply to the example of FIG. 4.The semiconductor package 400 may include a first leadframe 14A including a first die pad 16A, which may be (in particular fully) coated with a first coating material 32A. For example, the first leadframe 14A (or more specifically a core of the first leadframe 14A) may include or be made from Cu or a Cu alloy, and the first coating material 32A may include or be made from NiNiP or Ni. Additionally, the semiconductor package 400 may include a second leadframe 14B including a second die pad 16B that may be (particularly fully) coated with a second coating material 32B different from the first coating material 32A. For example, the second lead frame 14B (or more specifically, a core of the second lead frame 14B) may include or be made of Cu or a Cu alloy, and the second coating material 32B may include or be made of Ag or Cu. In the illustrated example, possible leads of leadframes 14A and 14B are not shown for simplicity.A first semiconductor chip 24A of a first type may be mounted on the first leadframe 14A (or, in particular, on the first die pad 16A). Additionally, a second semiconductor chip 24B of a second type different from the first type may be mounted on the second leadframe 14B (or, more particularly, on the second die pad 16B). The first semiconductor chip 24A may include a back side metallization 34 and may be mounted on the first leadframe 14A via the back side metallization 34. The backside metallization 34 may be comprised of a metal stack including various metals configured to provide suitable electrical and / or mechanical contact between the first leadframe 14A and the first semiconductor die 24A. For example, the back side metallization 34 may include or correspond to at least one of a multi-layered back side metallization, a copper back side metallization, a silver back side metallization, or the like.Similarly, the second semiconductor die 24B may be mounted on the second leadframe 14B via its backside or backside material 36. In an example, the backside material 36 of the second semiconductor die 24B may include or correspond to a non-metallic material such as bare silicon, silicon oxide, or the like. In the illustrated example, the backing material 36 may be attached to the second leadframe coating 32B via a die attach material 38, such as an adhesive. In another example, the backside material 36 may include or correspond to a backside metallization similar to the backside metallization 34 of the first semiconductor chip 24A.The first semiconductor chip 24A may include at least one first contact pad 42A, which may be disposed on top of the first semiconductor chip 24A. For example, the first contact surface 42A may include or be made of Al(Si)Cu. Similarly, the second semiconductor die 24B may include at least one second contact pad 42B, which may be disposed on top of the second semiconductor die 24B. For example, the second contact pad 42B may include or be made of at least one of PdAu or Cu.The semiconductor package 400 may include at least one first electrical connection element 40A electrically connecting the first semiconductor chip 24A and the first lead frame 14A. In the illustrated example, the first electrical connection element 40A may include or correspond to a first wire 40A including a first wire material. In other examples, and depending on the particular application, the first wire 40A may be replaced with another type of electrical connection element, such as a strap, clip, or the like. In particular, a first wire 40A may be in direct contact with a first contact pad 42A and the first coating material 32A of the first die pad 16A. Alternatively or additionally, a first wire 40A may be in direct contact with a first contact pad 42A and a third coating material of a first lead (not illustrated) of the first lead frame 14A.In addition, the semiconductor package 400 may include at least one second electrical connection element 40B. In the illustrated example, the second electrical connection member 40B may include or correspond to a second wire 40B including a second wire material different than the first wire material. In further examples, and depending on the application under consideration, the second wire 40B may be replaced with another type of electrical connection element, such as a strap, clip, or the like. For example, a second wire 40B may electrically couple the second semiconductor die 24B and the second lead frame 14B. In particular, a second wire 40B may be in direct contact with a second contact pad 42B and the second coating material 32B of the second die pad 16B. Alternatively or additionally, a second wire 40B may be in direct contact with a second contact pad 42B and a fourth coating material of a second lead (not illustrated) of the second lead frame 14B. Additionally, a second wire 40B may electrically couple the second semiconductor die 24B and the first semiconductor die 24A. In particular, the second wire 40B may be in direct contact with a second contact pad 42B of the second semiconductor chip 24B and a first contact pad 42A of the first semiconductor chip 24A. It should be appreciated that in other examples, and depending on the application contemplated, one or more of the wires 40B may be replaced with another type of electrical connection element, such as a strap, clip, or the like.It should be appreciated that the components of the semiconductor package 400 are made of different materials and may be processed based on different techniques. In this context, four exemplary scenarios are described below. In any scenario, the first semiconductor die 24A may be a power semiconductor die and the second semiconductor die 24B may be a driver or logic semiconductor die.In a first scenario, based on diffusion soldering, the first semiconductor die 24A may be connected to the first leadframe 14A (or the first die pad 16A) via its back side metallization 34. The first wire 40A may be made of Al and bonded based on a wedge-wedge bonding method. The first lead frame 32A may be coated with NiP or Ni on the die pad 16A and on the wire bonding region. The second semiconductor chip 24B may be attached to the second lead frame 14B (or to the second die pad 16B) via its silicon back 36 using an Ag adhesive. The second wire 40B may be made of Cu or Au and bonded based on a ball bonding method. In an Au ball bond, the second lead frame 32B may be coated with Ag or the second lead frame 14B may be a micro-precoated frame (μPF). In the case of a Cu ball joint, the second lead frame coating 32B may be made of Cu or Ag, or the second lead frame 14B may be a micro-precoated frame (μPF).In a second scenario, based on diffusion soldering, the first semiconductor die 24A may be connected to the first leadframe 14A (or the first die pad 16A) via its back side metallization 34. The first wire 40A may be made of Cu and bonded based on a wedge-wedge bonding method. The first lead frame 32A may be coated with NiP or Ni on the die pad 16A and Cu on the wire bond region. The second semiconductor chip 24B may be attached to the second lead frame 14B (or to the second die pad 16B) via its silicon back 36 using an Ag adhesive. The second wire 40B may be made of Cu or Au and bonded based on a ball bonding method. In an Au ball bond, the second lead frame coating 32B may be made of Ag or the second lead frame 14B may be a micro-precoated frame (μPF). In the case of a Cu ball joint, the second lead frame coating 32B may be made of Cu or Ag, or the second lead frame 14B may be a micro-precoated frame (μPF).In a third scenario, the first semiconductor die 24A may be connected to the first leadframe 14A (or the first die pad 16A) via a 4-layer backside metallization 34 based on a solder paste process. The first wire 40A may be made of Al and bonded based on a wedge-wedge bonding method. The first lead frame 32A may be coated with bare Cu or Ag on the die pad 16A and NiP or Ni on the wire bond pad. The second semiconductor chip 24B may be attached to the second lead frame 14B (or to the second die pad 16B) via its silicon back 36 using an Ag adhesive. The second wire 40B may be made of Cu or Au and bonded based on a ball bonding method. In an Au ball bond, the second lead frame coating 32B may be made of Ag or the second lead frame 14B may be a micro-precoated frame (μPF). In the case of a Cu ball joint, the second lead frame coating 32B may be made of Cu or Ag, or the second lead frame 14B may be a micro-precoated frame (μPF).In a fourth scenario, the first semiconductor die 24A may be connected to the first leadframe 14A (or the first die pad 16A) via a 4-layer backside metallization 34 based on a solder paste process. The first wire 40A may be made of Cu and bonded based on a wedge-wedge bonding method. The first lead frame 32A may be coated on the die pad 16A and the wire bonding region of Cu or Ag. The second semiconductor chip 24B may be attached to the second lead frame 14B (or to the second die pad 16B) via its silicon back 36 using an Ag adhesive. The second wire 40B may be made of Cu or Au and bonded based on a ball bonding method. In an Au ball bond, the second lead frame coating 32B may be made of Ag or the second lead frame 14B may be a micro-precoated frame (μPF). In the case of a Cu ball joint, the second lead frame coating 32B may be made of Cu or Ag, or the second lead frame 14B may be a micro-precoated frame (μPF).The concepts according to the disclosure described herein may exceed conventional concepts in various ways, as described below. In this regard, the following statements should not be considered exhaustive.The concepts described herein may provide for the use of leadframes having different thicknesses in a same semiconductor package. In this case, in particular, no cost-intensive processing (such as, for example, selective etching) is required. The possibility of a semiconductor package having a thick leadframe for power semiconductor chips and a thin leadframe for logic or driver semiconductor chips may be advantageous for the realization of SIPs (Systems in a Package). In this regard, the thick leadframe may provide the dissipation of heat and an appropriate transport of high electric currents, while the thin leadframe allows fine routing of signals.The concepts described herein may provide semiconductor packages including exposed die pads and unexposed die pads having a particular isolation thickness. Complex and cost-intensive insulation concepts (such as, for example, TIM plates, foils) are not necessarily required.The concepts described herein may provide cost-effective methods for using different leadframes and different coating materials in a same semiconductor package. For example, a first leadframe may be a copper leadframe with a first coating material, while a second leadframe may be an aluminum leadframe with a second coating material different from the first coating material.The concepts described herein may provide cost effective integration of different semiconductor chips into one and the same package using leadframes with different coating materials. In particular, each of the lead frames contained can be produced as a completely coated lead frame, so that no spot coating is required. The concepts presented do not necessarily require expensive coating technologies (such as spot coating), which may greatly increase the overall cost of the package.ExamplesHereinafter, methods and semiconductor packages according to the disclosure will be described by way of examples.Example 1 is a method comprising: providing a first leadframe panel comprising a plurality of first leadframes, the first leadframes comprising a plurality of first die pads coated with a first coating material; providing a second leadframe panel separate from the first leadframe panel and comprising a plurality of second leadframes, the second leadframes comprising a plurality of second die pads coated with a second coating material different from the first coating material; mechanically connecting the first leadframe panel and the second leadframe panel to form a combined leadframe panel; mounting a plurality of first semiconductor chips of a first type on the first leadframe panel; and mounting a plurality of second semiconductor chips of a second type different from the first type on the second leadframe panel.Example 2 is a method according to example 1, wherein: the first leadframes further comprise a plurality of first lead wires coated with a third coating material, and / or the second leadframes further comprise a plurality of second lead wires coated with a fourth coating material.Example 3 is a method according to example 2, wherein: the third coating material is different from the first coating material and / or the fourth coating material is different from the second coating material.Example 4 is a method according to example 2, wherein: the first coating material and the third coating material are the same, and / or the second coating material and the fourth coating material are the same.Example 5 is a method according to any of the preceding examples, wherein: the first die pads are fully coated with the first coating material and the second die pads are fully coated with the second coating material.Example 6 is a method according to any of the preceding examples, wherein: the first coating material comprises at least one of Ni, NiP, NiNiP, Cu, Ag and the second coating material comprises at least one of Cu, Ag and / or the second leadframe panel is a precoated frame (PPF) or a micro-precoated frame (μ).Example 7 is a method according to any of the preceding examples, wherein: the first semiconductor chips are power semiconductor chips and the second semiconductor chips are at least one of logic semiconductor chips or driver semiconductor chips.Example 8 is a method according to any of the preceding examples, wherein the first leadframe panel has a first thickness and the second leadframe panel has a second thickness that is less than the first thickness.Example 9 is a method according to one of the preceding examples, wherein the mounting of the first semiconductor chips on the first leadframe panel and the mounting of the second semiconductor chips on the second leadframe panel are based on different methods.Example 10 is a method according to any of the preceding examples, wherein mounting the first semiconductor chips on the first leadframe panel is based on at least one of a diffusion soldering process, a soft soldering process, a pre-form soldering process, a sintering process or a solder paste process, and mounting the second semiconductor chips on the second leadframe panel is based on at least one of an adhesion process, a die attach film process, a soldering process, a soft soldering process or a sintering process.Example 11 is a method according to any of the preceding examples, wherein: the mounting of the first semiconductor chips on the first leadframe panel and the mounting of the second semiconductor chips on the second leadframe panel are performed before the first leadframe panel and the second leadframe panel are mechanically connected.Example 12 is a method according to one of the preceding examples, wherein the mounting of the first semiconductor chips on the first leadframe panel and the mounting of the second semiconductor chips on the second leadframe panel are carried out in different production lines.Example 13 is a method according to any of the preceding examples, wherein: the first leadframe panel comprises a first peripheral frame and a plurality of rows of the first die pads, wherein the rows of the first die pads are connected to opposite sides of the first peripheral frame and separated by first columns, the second leadframe panel comprises a second peripheral frame and a plurality of rows of the second die pads, wherein the rows of the second die pads are connected to opposite sides of the second peripheral frame and separated by second columns, and in the combined leadframe panel, the rows of the first die pads of the first leadframe panel are arranged at the second columns of the second leadframe panel and the rows of the second die pads of the second leadframe panel are arranged at the first columns of the first leadframe panel.Example 14 is a method according to any of the preceding examples, wherein the first die pads and the second die pads in the combined leadframe panel are arranged at different heights.Example 15 is a method according to any of the preceding examples, further comprising: performing an encapsulation process in which the first semiconductor chips, the second semiconductor chips and the combined leadframe panel are at least partially encapsulated in an encapsulation material, and singulating the encapsulated semiconductor chips and the combined leadframe panel into a plurality of semiconductor packages.Example 16 is a method according to example 15, wherein: a singulated semiconductor package comprises a first leadframe comprising a first die pad coated with the first coating material and a second leadframe comprising a second die pad coated with the second coating material; a first semiconductor chip of the first type is mounted on the first leadframe; and a second semiconductor chip of the second type is mounted on the second leadframe.Example 17 is a method according to example 15 or 16, wherein: the first semiconductor chips are mounted on a first main surface of the first leadframe panel, the second semiconductor chips are mounted on a second main surface of the second leadframe panel, and after performing the encapsulation process, a main surface of the first leadframe panel opposite the first main surface is uncovered by the encapsulation material and a main surface of the second leadframe panel opposite the second main surface is covered by the encapsulation material.Example 18 is a method according to any of the preceding examples, further comprising: electrically coupling the first semiconductor chips to the first leadframe panel via first electrical connectors comprising a first electrical connector material, and electrically coupling the second semiconductor chips to the second leadframe panel via second electrical connectors comprising a second electrical connector material different from the first electrical connector material.Example 19 is a method according to Example 18, wherein: the first electrical connection elements comprise first wires comprising a first wire material, and the second electrical connection elements comprise second wires comprising a second wire material.Example 20 is a method according to example 19, wherein: the material of the first electrical connection element comprises Al and the material of the second electrical connection element comprises Cu.Example 21 is a method according to example 19 or 20, wherein the electrical connection of the first semiconductor chips to the first leadframe panel via the first electrical connection elements and the electrical connection of the second semiconductor chips to the second leadframe panel via the second electrical connection elements are based on different methods.Example 22 is a method according to any of Examples 19 to 21, wherein: the electrical connection of the first semiconductor chips to the first leadframe panel via the first electrical connection elements is based on a wedge bonding process, and the electrical connection of the second semiconductor chips to the second leadframe panel via the second electrical connection elements is based on a ball bonding process.Example 23 is a method according to any of the preceding examples, wherein mechanically connecting the first leadframe panel and the second leadframe panel to form the combined leadframe panel comprises at least one of clamping, gluing or welding.Example 24 is a method according to any of the preceding examples, wherein: a core of the first leadframe panel comprises a first core material and a core of the second leadframe panel comprises a second core material different from the first core material.Example 25 is a method according to Example 24, wherein: the first core material comprises Cu and the second core material comprises Al.Example 26 is a semiconductor package, comprising: a first leadframe comprising a first die pad coated with a first coating material; a second leadframe comprising a second die pad coated with a second coating material different from the first coating material; a first semiconductor chip of a first type mounted on the first leadframe; and a second semiconductor chip of a second type different from the first type mounted on the second leadframe.Example 27 is a semiconductor package according to example 26, wherein: the first semiconductor chip comprises a back side metallization and is mounted on the first leadframe via the back side metallization, and the second semiconductor chip is mounted on the second leadframe via its back side formed by a nonmetallic material.Example 28 is a semiconductor package according to example 26 or 27, wherein: the first semiconductor chip is a power semiconductor chip, and the second semiconductor chip is at least one of a logic semiconductor chip or a driver semiconductor chip.Example 29 is a semiconductor package according to any one of Examples 26 to 28, further comprising: a first electrical connection element comprising a first electrical connection element material and electrically connecting the first semiconductor chip and the first lead frame; and a second electrical connection element comprising a second electrical connection element material different from the first electrical connection element material and electrically connecting the second semiconductor chip and the second lead frame.Example 30 is a semiconductor package according to example 29, wherein: the first electrical connection element comprises a first wire comprising a first wire material, and the second electrical connection element comprises a second wire comprising a second wire material.Example 31 is a semiconductor package according to any of Examples 26 to 30, wherein: the first die pad is fully coated with the first coating material and the second die pad is fully coated with the second coating material.The terms "connected", "coupled", "electrically connected" and / or "electrically coupled" used in this description do not necessarily mean that the elements must be directly connected or coupled to one another. Intermediate elements may be provided between the "connected", "coupled", "electrically connected" and "electrically coupled" elements, respectively.Further, the words "over" and "on" used, e.g., with respect to a layer of material formed or disposed "over" or "on" a surface of an object may be used herein to mean that the layer of material may be disposed (e.g., formed, deposited, etc.) "directly on", i.e., in direct contact with the implied surface. The words "over" and "on" used, for example, with respect to a layer of material formed or disposed "over" or "on" a surface may also be used herein such that the layer of material may be disposed (e.g., formed, deposited, etc.) "indirectly on" the indicated surface, e.g., with one or more additional layers disposed between the indicated surface and the layer of material.As used in the detailed description or claims, the terms "having," "containing," "including," "with," or variants thereof, are intended to be inclusive in a manner similar to the term "comprising.". That is, as used herein, the terms "having," "including," "including," "with," "comprising," or the like are open ended terms that indicate the presence of certain elements or features, but do not exclude additional elements or features. The articles "a", "an", and "the / s" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.Moreover, the word "exemplary" is used herein to serve as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be considered advantageous over other aspects or designs. Rather, the use of the word "exemplary" is intended to represent concepts in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or.". That is, unless otherwise stated or apparent from context, by "X uses A or B" is meant any of the natural, inclusive permutations. That is, if X employs A, X employs B, or X employs both A and B, then the condition "X employs A or B" is satisfied in each of the previous instances. In addition, the articles "a" and "an" as used in this application and the appended claims may generally be construed to mean "one / e or more" unless otherwise stated or clearly understood from context to be related to a singular form. In addition, at least one of A and B or the like generally means A or B or both of A and B.Described herein are devices and methods for making devices. Remarks made in connection with a described device may also apply to a corresponding method and vice versa. For example, when a particular component of a device is described, a corresponding method of manufacturing the device may include a step of providing the component as appropriate, even though such a step is not expressly described or illustrated in the figures.Although the disclosure has been shown and described with respect to one or more embodiments, other persons skilled in the art will make equivalent changes and modifications based at least in part on the reading and understanding of this specification and the accompanying drawings. The disclosure includes all such modifications and variations and is limited only by the concept of the following claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), the terms used to describe such components, unless otherwise indicated, are intended to correspond to any component that performs the indicated function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiments of the disclosure illustrated herein. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of the other embodiments as desired and advantageous for a particular application.

Claims

A method comprising: providing a first leadframe panel (12A) comprising a plurality of first leadframes (14A), the first leadframes (14A) comprising a plurality of first die pads (16A) coated with a first coating material (32A); providing a second leadframe panel (12B) separate from the first leadframe panel (12A) and comprising a plurality of second leadframes (14B), the second leadframes (14B) comprising a plurality of second die pads (16B) coated with a second coating material (32B) different from the first coating material (32A); Mechanically connecting the first leadframe panel (12A) and the second leadframe panel (12B) to form a combined leadframe panel (26); mounting a plurality of first semiconductor chips (24A) of a first type on the first leadframe panel (12A); and mounting a plurality of second semiconductor chips (24B) of a second type different from the first type on the second leadframe panel (12B).The method of claim 1, wherein: the first leadframes (14A) further comprise a plurality of first leads (22A) coated with a third coating material, and / or the second leadframes (14B) further comprise a plurality of second leads (22B) coated with a fourth coating material.The method of claim 2, wherein: the third coating material is different from the first coating material (32A), and / or the fourth coating material is different from the second coating material (32B).The method of claim 2, wherein: the first coating material (32A) and the third coating material are the same, and / or the second coating material (32B) and the fourth coating material are the same.The method of any preceding claim, wherein: the first die pads (16A) are fully coated with the first coating material (32A), and the second die pads (16B) are fully coated with the second coating material (32B).The method of any preceding claim, wherein: the first coating material (32A) comprises at least one of Ni, NiP, NiNiP, Cu, Ag, and the second coating material (32B) comprises at least one of Cu, Ag, and / or the second leadframe panel (12B) is a precoated frame (PPF) or a micro-precoated frame (μP).The method of any preceding claim, wherein: the first semiconductor chips (24A) are power semiconductor chips, and the second semiconductor chips (24B) are at least one of logic semiconductor chips or driver semiconductor chips.The method of any preceding claim, wherein: the first leadframe panel (12A) has a first thickness, and the second leadframe panel (12B) has a second thickness that is less than the first thickness.The method of any preceding claim, wherein mounting the first semiconductor chips (24A) on the first leadframe panel (12A) and mounting the second semiconductor chips (24B) on the second leadframe panel (12B) are based on different processes.The method of any preceding claim, wherein: mounting the first semiconductor chips (24A) on the first leadframe panel (12A) is based on at least one of a diffusion soldering process, a soft soldering process, a pre-form soldering process, a sintering process, or a solder paste process; and mounting the second semiconductor chips (24B) on the second leadframe panel (12B) is based on at least one of an adhesion process, a die attach film process, a soldering process, a soft soldering process, or a sintering process.The method of any preceding claim, wherein: mounting the first semiconductor chips (24A) on the first leadframe panel (12A) and mounting the second semiconductor chips (24B) on the second leadframe panel (12B) are performed before mechanically connecting the first leadframe panel (12A) and the second leadframe panel (12B).The method of any preceding claim, wherein: mounting the first semiconductor chips (24A) on the first leadframe panel (12A) and mounting the second semiconductor chips (24B) on the second leadframe panel (12B) are performed in different production lines.The method of any preceding claim, wherein: the first leadframe panel (12A) comprises a first peripheral frame (18A) and a plurality of rows of the first die pads (16A), the rows of the first die pads (16A) being connected to opposing sides of the first peripheral frame (18A) and separated by first column (20A), the second leadframe panel (12B) comprises a second peripheral frame (18B) and a plurality of rows of the second die pads (16B), the rows of the second die pads (16B) being connected to opposing sides of the second peripheral frame (18B) and separated by second column (20B), and in the combined leadframe panel (26), the rows of the first die pads (16A) of the first leadframe panel (12A) are arranged at the second columns (20B) of the second leadframe panel (12B), and the rows of the second die pads (16B) of the second leadframe panel (12B) are arranged at the first columns (20A) of the first leadframe panel (12A).The method of any preceding claim, wherein the first die pads (16A) and the second die pads (16B) in the combined leadframe panel (26) are arranged at different heights.The method of any preceding claim, further comprising: performing an encapsulation process, wherein the first semiconductor chips (24A), the second semiconductor chips (24B), and the combined leadframe panel (26) are at least partially encapsulated in an encapsulation material (30), and singulating the encapsulated semiconductor chips (24A, 24B) and the combined leadframe panel (26) into a plurality of semiconductor packages.The method of claim 15, wherein: a singulated semiconductor package comprises a first leadframe (14A) comprising a first die pad (16A) coated with the first coating material (32A) and a second leadframe (14B) comprising a second die pad (16B) coated with the second coating material (32B); a first semiconductor chip (24A) of the first type is mounted on the first leadframe (14A); and a second semiconductor chip (24B) of the second type is mounted on the second leadframe (14B).The method according to claim 15 or 16, wherein: the first semiconductor chips (24A) are mounted on a first main surface of the first lead frame panel (12A), the second semiconductor chips (24B) are mounted on a second main surface of the second lead frame panel (12B), and after performing the encapsulation process, a main surface of the first lead frame panel (12A) opposite to the first main surface is uncovered by the encapsulation material (30) and a main surface of the second lead frame panel (12B) opposite to the second main surface is covered by the encapsulation material (30).The method of any preceding claim, further comprising: electrically coupling the first semiconductor chips (24A) to the first leadframe panel (12A) via first electrical connectors (40A) comprising a first electrical connector material, and electrically coupling the second semiconductor chips (24B) to the second leadframe panel (12B) via second electrical connectors (40B) comprising a second electrical connector material different from the first electrical connector material.The method of claim 18, wherein: the first electrical connection elements (40A) comprise first wires (40A) comprising a first wire material, and the second electrical connection elements (40B) comprise second wires (40B) comprising a second wire material.The method of claim 19, wherein: the first electrical connector material comprises Al, and the second electrical connector material comprises Cu.The method of claim 19 or 20, wherein electrically connecting the first semiconductor chips (24A) to the first leadframe panel (12A) via the first electrical connectors (40A) and electrically connecting the second semiconductor chips (24B) to the second leadframe panel (12B) via the second electrical connectors (40B) are based on different processes.The method of any of claims 19 to 21, wherein: electrically coupling the first semiconductor chips (24A) to the first leadframe panel (12A) via the first electrical connectors (40A) is based on a wedge bonding process, and electrically coupling the second semiconductor chips (24B) to the second leadframe panel (12B) via the second electrical connectors (40B) is based on a ball bonding process.The method of any preceding claim, wherein mechanically joining the first leadframe panel (12A) and the second leadframe panel (12B) to form the combined leadframe panel (26) comprises at least one of clamping, gluing, or welding.The method of any preceding claim, wherein: a core of the first leadframe panel (12A) comprises a first core material, and a core of the second leadframe panel (12B) comprises a second core material different from the first core material.The method of claim 24, wherein: the first core material comprises Cu, and the second core material comprises Al.A semiconductor package comprising: a first lead frame (14A) comprising a first die pad (16A) coated with a first coating material (32A); a second lead frame (14B) comprising a second die pad (16B) coated with a second coating material (32B) different from the first coating material (32A); a first semiconductor chip (24A) of a first type mounted on the first lead frame (14A); and a second semiconductor chip (24B) of a second type different from the first type mounted on the second lead frame (14B).The semiconductor package of claim 26, wherein: the first semiconductor chip (24A) comprises a back side metallization (34) and is mounted on the first lead frame (14A) via the back side metallization (34), and the second semiconductor chip (24B) is mounted on the second lead frame (14B) via its back side formed of a non-metallic material (36).The semiconductor package according to claim 26 or 27, wherein: the first semiconductor chip (24A) is a power semiconductor chip, and the second semiconductor chip (24B) is at least one of a logic semiconductor chip or a driver semiconductor chip.The semiconductor package of any of claims 26 to 28, further comprising: a first electrical connector (40A) comprising a first electrical connector material and electrically connecting the first semiconductor die (24A) and the first lead frame (14A); and a second electrical connector (40B) comprising a second electrical connector material different from the first electrical connector material and electrically coupling the second semiconductor die (24B) and the second lead frame (14B).The semiconductor package of claim 29, wherein: the first electrical connection element (40A) comprises a first wire (40A) comprising a first wire material, and the second electrical connection element (40B) comprises a second wire (40B) comprising a second wire material.The semiconductor package of any one of claims 26 to 30, wherein: the first die pad (16A) is fully coated with the first coating material (32A), and the second die pad (16B) is fully coated with the second coating material.

Images