NETWORK ADAPTER THAT PROVIDES ADDRESS TRANSLATION AS A SERVICE

Abstract

A network adapter comprising a host interface, a network interface, a packet processing circuit, and a translation-as-a-service (TaaS) circuit. The host interface is used for communication with a host via a peripheral bus. The network interface is used for sending and receiving packets to and from a network for the host. The packet processing circuit is used for processing the packets. The TaaS circuit is integrated into the network adapter and is used to (i) receive a request from a requesting device to translate an input address into a requested address within a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.

Description

AREA OF INVENTION

[0001] The present invention relates generally to network adapters and in particular to network adapters that offer address translation services. BACKGROUND OF THE INVENTION

[0002] Network adapters often operate in accordance with communication or memory access protocols that involve address translation. For example, in Remote Direct Memory Access (RDMA), a network adapter can transfer data directly between local host memory and a remote host. Physical address ranges (PAs) in the host memory are mapped to corresponding virtual address ranges (VAs). The network adapter receives memory access commands, which are specified as VAs, and translates the VAs into corresponding PAs.

[0003] Another example is single-root input-output virtualization (SR-IOV), where a host runs one or more virtual machines (VMs), each assigned its own machine address (MA) range. Memory access in such an environment can involve translation not only between VAs and PAs, but also between PAs and MAs. This latter translation can be performed by an input-output memory management unit (IOMMU) on the host. The network adapter and the host can use an address translation service (ATS), which allows the network adapter to query the IOMMU for address translations and cache them in a local address translation cache (ATC). SUMMARY OF THE INVENTION

[0004] The invention is defined by the claims. To illustrate the invention, aspects and embodiments that may or may not fall within the scope of the claims are described here.

[0005] One embodiment described here comprises a network adapter with a host interface, a network interface, a packet processing circuit, and a translation-as-a-service (TaaS) circuit. The host interface is used for communication with a host via a peripheral bus. The network interface is used for sending and receiving packets to and from a network for the host. The packet processing circuit is used for processing the packets. The TaaS circuit is integrated into the network adapter and is used to (i) receive a request from a requesting device to translate an input address into a requested address in a requested address space, (ii) translate the input address into the one or more requested addresses, and (iii) return the one or more requested addresses to the requesting device.

[0006] In some embodiments, the TaaS circuit serves to translate the input address into the one or more requested addresses independently of any actual memory access operation. In other embodiments, the TaaS circuit receives a translation request specifying an input address for which no translation exists and responds to the translation request with a translation response indicating that no translation exists. In one embodiment, the request specifies a requested size, and the TaaS circuit is intended to return a memory area of ​​that size in the response.

[0007] In some embodiments, the input address comprises a virtual address (VA) of a network adapter. In one embodiment, the VA comprises a network adapter VA. In another embodiment, the input address comprises a key-address pair. In yet another embodiment, the input address comprises a transport address.

[0008] In one disclosed embodiment, the TaaS circuit, in addition to returning the one or more requested addresses, also returns metadata corresponding to those addresses. In various embodiments, the one or more requested addresses comprise one of (i) a virtual address (VA), (ii) a physical address (PA), and (iii) a machine address (MA). In one embodiment, the TaaS circuit serves to receive the request as a work request, which is entered on a queue pair (QP), and to return the one or more requested addresses by entering a completion message on the QP that specifies the one or more requested addresses.

[0009] In one embodiment, the input address refers to one of (i) a contiguous memory area and (ii) a pattern of memory addresses. In some embodiments, the request is received in response to an on-demand paging (ODP) page fault notification, where the network adapter notifies the requesting device of an unallocated memory page, and the request requests an input address to which the unallocated memory page should be allocated.

[0010] In another embodiment, the request specifies a virtual address (VA) in a logical volume defined on a storage device, with the request requesting a corresponding address on the storage device. In yet another embodiment, the request requests the translation of a virtual address (VA) to a physical address (PA) in response to receiving a memory command from a remote storage access protocol, with the command specifying the VA.

[0011] In yet another embodiment, the request calls for the translation of the input address (VA) into a physical address (PA) in response to an authorization error from the Address Translation Service (ATS). In another embodiment, the request calls for the translation of the input address into a machine address (MA).

[0012] Additionally, according to one embodiment described herein, a method is provided in a network adapter. The method comprises communicating with a host via a peripheral bus and sending and receiving packets to and from a network for the host. Using a translation-as-a-service (TaaS) circuit integrated into the network adapter: (i) a request to translate an input address into a requested address in a requested address space is received from a requesting device, (ii) the input address is translated into the one or more requested addresses, and (iii) the one or more requested addresses are returned to the requesting device.

[0013] In one embodiment, the translation of the input address into one or more requested addresses is performed independently of an actual memory access operation.

[0014] In one embodiment, receiving the request includes receiving a translation request specifying an input address for which no translation exists, and includes responding to the translation request with a translation response indicating that no translation exists.

[0015] Each feature of one aspect or embodiment can be applied to other aspects or embodiments in any suitable combination. In particular, each feature of one process aspect or embodiment can be applied to one device aspect or embodiment, and vice versa.

[0016] The present invention will be better understood from the following detailed description of the embodiments in conjunction with the drawings in which it is illustrated: BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram schematically representing a computer system with a network adapter that performs translation-as-a-service (TaaS) according to an embodiment of the present invention; Fig. Figure 2 is a message flow diagram that schematically illustrates the use of TaaS in on-demand paging (ODP) according to an embodiment of the present invention; Fig. Figure 3 is a block diagram that schematically illustrates the use of TaaS in the Page Request Interface (PRI) according to an embodiment of the present invention; Fig. 4 is a block diagram schematically illustrating the use of TaaS for storage in a storage device accessible via physical addresses, according to an embodiment of the present invention; and Fig. Figure 5 is a block diagram that schematically illustrates the use of TaaS in the translation of virtual addresses (VAs) to machine addresses (MAs) according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EXECUTION FORM OVERVIEW

[0017] The embodiments of the present invention described herein provide improved techniques for address translation and memory access in computer systems. In the disclosed embodiment, a network adapter, e.g., an Ethernet network interface controller (NIC) or InfiniBand™ host channel adapter (HCA), connects a host to a network. In addition to sending and receiving packets for the host, the network adapter offers address translation as a service to a requesting device.

[0018] The requesting device can be located outside the network adapter, for example, in the host or remotely on a network. Alternatively, the requesting device can be located within the network adapter, for example, if the network adapter is a "Smart NIC" or Data Processing Unit (DPU).

[0019] In a typical Translation-as-a-Service (TaaS) transaction, the network adapter receives a request from a requesting device to translate an input address into a requested address in a different address space. The input address might be, for example, a virtual address (VA) or a transport address. The network adapter performs the requested translation and returns the requested address to the requesting device. In various embodiments, the network adapter can translate the input address into another VA, a physical address (PA), or a physical address (MA). In one embodiment, the requested address is a VA or PA in an address space of the network adapter (as opposed to an address space of the host).

[0020] This section describes various use cases for different types of TaaS transactions. The TaaS techniques described here decouple the address translation process from the actual memory access. The disclosed techniques also improve memory access performance. Furthermore, the disclosed techniques relieve the requesting device (e.g., the host) of the need to constantly maintain a parallel copy of the underlying address translation structure and logic. For example, a host can be relieved of the need to emulate a translation protection table (TPT) maintained in the network adapter. SYSTEM DESCRIPTION

[0021] Fig. Figure 1 is a block diagram schematically representing a computer system 20 with a host 24 and a network adapter that performs translation-as-a-service (TaaS) according to an embodiment of the present invention.

[0022] Host 24 can be, for example, a server, a workstation, or any other suitable computer. Network adapter 28 can be, for example, a NIC or an InfiniBand HCA. Network adapter 28 connects host 24 to a network 32, such as an Ethernet or InfiniBand network. The following description refers to a NIC as a non-restrictive example.

[0023] Host 24 and NIC 28 communicate with each other via a peripheral bus. In this example, the peripheral bus comprises a PCIe bus 36. However, in alternative embodiments, any other suitable type of peripheral bus can be used, e.g., CXL, Nvlink, or Nvlink-C2C.

[0024] Host 24 comprises a central processing unit (CPU) 40 and host memory 44. Device 28 may include device-based memory (not shown in the figure). Host 24 and NIC 28 run a virtualized environment according to SR-IOV. CPU 40 runs one or more virtual machines (VMs) 48. CPU 40 also runs an IOMMU 52.

[0025] The NIC 28 includes a host interface for communication with the host 24 via bus 36 and a network interface for sending and receiving packets to and from network 32 for the host 24 (the two interfaces are in Fig. (1 omitted for clarity). The NIC 28 includes a packet processor 54, also referred to as a "packet processing circuit," which is responsible for sending and receiving packets over the network 32 for the host 24. Furthermore, the NIC 28 includes a TaaS unit, also referred to as a "TaaS circuit" or "TaaS controller," which provides address translation services for one or more translation requesters 70 using methods that are described in detail below.

[0026] A particular translation requester (also referred to here as the “requesting device” or simply “requester”) can be inside or outside the NIC 28.

[0027] An external requester could be, for example, software running on host 24, i.e., via PCIe bus 36. Another example would be a remote host or network device communicating with NIC 28 over network 32. An internal requester could be any software or hardware located within NIC 28.

[0028] In some embodiments, access to host memory involves 44 different address translations. The following description refers primarily to memory access that is part of an RDMA transaction initiated by a remote host and handled by NIC 28.

[0029] Typically, an RDMA transaction (e.g., read or write) accesses a specific virtual address (VA) belonging to a virtual address space. The virtual address space is identified by a unique key, also known as the MKEY. Therefore, the RDMA transaction will usually specify a {VA, key} pair. The NIC 28 includes a Memory Translation Table (MTT) 60 and one or more keys 56. For each key 56, the MTT 60 contains a table that translates {VA, key} pairs into corresponding virtual addresses (PAs). In this context, the term "VA" also refers to a {VA, key} pair. The MTT 60 is an example of the Translation Protection Table (TPT) implementation in the NIC 28. Alternatively, any other suitable TPT implementation can be used.

[0030] In environments that do not use virtualization (sometimes referred to as "bare metal" environments), the PAs specify the actual physical storage spaces in host memory 44. When using SR-IOV, as in the example of Fig. 1. The PAs should undergo an additional translation into MAs. The translation of PAs into MAs is performed by the IOMMU 52. In some embodiments, the NIC 28 includes an Address Translation Service (ATS) 64, which sends translation requests (requests to translate PAs into MAs) to the IOMMU 52, receives the requested translations, and temporarily stores the translations in an Address Translation Cache (ATC).

[0031] In embodiments of the present invention, the TaaS unit 68 in the NIC 28 provides address translation services to 70 internal and / or external requesters. The address whose translation is requested is referred to here as the "input address." The following description mainly relates to embodiments in which the input address is a VA. However, in some embodiments, the input address is a transport address, e.g., a {Queue Pair (QP), Work Queue Element (WQE) index, byte offset} triple. Examples of the use of transport addresses are given below.

[0032] In some embodiments, a requester 70 sends a TaaS request to NIC 28 in the format ANF(key, VA, size, flags). The TaaS request instructs NIC 28 to translate a memory area that starts at the specified VA and has the specified size. The VA belongs to a virtual address space with the specified key. The TaaS unit 68 in NIC 68 responds to the request with a TaaS response in the format ANTW(*key, *VA, *PA, *MA), where the operator "*" represents "zero or more". The response returns the requested address, which, depending on the implementation and use case, can be a VA, a PA, or an MA.

[0033] In one embodiment, the TaaS unit 68 can operate in batch mode. In this embodiment, the TaaS unit 68 receives a list of translation requests and returns a series of translation responses. This implementation is efficient with respect to the input of auxiliary data (overhead).

[0034] In some cases, a given translation result may comprise multiple translation sets to cover the requested VA range. In some embodiments, the Taas unit 68 translates the input address into a non-contiguous range of addresses (e.g., VAs or PAs) with a somewhat compact representation (e.g., a regularly spaced address pattern).

[0035] In various embodiments, the TaaS unit 68 includes metadata relating to the requested address in a TaaS response, in addition to the requested address itself. This metadata may include, for example, an access authorization, one or more PCIe ordering rules, a key, a Process Address Space Identifier (PASID), a requester identifier, a device identifier, a namespace identifier, a destination host identifier, a virtual hop identifier, and / or any other suitable metadata. In some embodiments, a given TaaS response may contain multiple translations returned for a specific request. A given TaaS response may also include a length specification indicating a subset of the TaaS request to which the response relates.

[0036] In some implementations, the VA whose translation is requested is also referred to as the "network adapter VA" or "NIC VA." When translating one VA to another, the latter VA could be, for example, another NIC VA (e.g., a {key, address} pair), a host VA (e.g., a {PASID, address} pair), a guest VA (e.g., a {requestor_id, PASID, address} pair), or another type of VA. In addition to TaaS requests of the form {KEY, VA}, TaaS Unit 68 can also receive requests in other appropriate namespaces, such as a request to translate a {PASID, VA} to a PA.

[0037] In various embodiments, the requester 70 and the TaaS unit 68 can use different interfaces for exchanging TaaS requests and TaaS responses. In one embodiment, the interface comprises a queue pair (QP) with a work queue (WQ) and a completion queue (CQ). In this implementation, the requester 70 inserts a TaaS request as a work queue element (WQE) into the WQ. The TaaS unit 68 reads the WQE, executes it, and inserts the TaaS response as a completion queue element (CQE) into the CQ. In other embodiments, the requester 70 and the TaaS unit 68 exchange TaaS requests and responses via a command interface or a dedicated interface established between them.

[0038] In some embodiments, the TaaS unit 68 may detect, while processing a TaaS request, that the requested translation does not currently exist. In such a case, the TaaS unit 68 typically returns the location (e.g., the input address) of the missing translation entry along with an indication that the translation does not exist. In one embodiment, the TaaS unit 68 returns, upon request, all translated addresses and locations of the missing translations for the specified VA range. This function is useful for the requester to pre-retrieve all missing translation entries for a particular translation request.

[0039] In some embodiments, the MTT 60 comprises multiple mapping tables arranged in two or more nesting levels. In other words, an entry in a particular mapping table in the MTT 60 can reference a different {Key, VA} pair. In these embodiments, the TaaS unit 68 can return missing translations found at any of the nesting levels.

[0040] It is important to distinguish between ATS and TaaS. ATS is specified as part of the PCIe specification, for example, in Chapter 10 of the PCI Express® Base Specification, Revision 5.0, Version 1.0, May 2019. With ATS, address translation is performed by the host as a service for NIC 28. An ATS transaction (either with the IOMMU or with the ATC) is typically performed as part of an actual memory access operation (e.g., read or write). In contrast, with TaaS, address translation is performed on NIC 28 as a service for a requesting device. A TaaS transaction is not necessarily part of a specific memory access operation (and is often independent of one).

[0041] The in Fig. The configurations of system 20, host 24, and network adapter 28 shown in Figure 1 are example configurations chosen solely for conceptual clarity. Any other suitable system, host, and / or network adapter configuration can be used in alternative embodiments. Elements not essential for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits, and debugging circuits, have been omitted from the figures for clarity.

[0042] The various elements of the system 20, the host 24, and the network adapter 28 can be implemented in hardware, for example, in one or more application-specific integrated circuits (ASICs) or FPGAs. Additionally or alternatively, elements of the system 20, the host 24, and / or the network adapter 28 can be implemented by software or using a combination of hardware and software elements. The host memory 44 can comprise any suitable memory type, such as one or more random-access memory (RAM) devices.

[0043] In some embodiments, the CPU 40 and / or TaaS unit 68 can be implemented wholly or partially by one or more general-purpose processors programmed in software to perform the functions described herein. The software can be downloaded to the processors electronically, e.g., via a network, or alternatively or additionally, it can be provided and / or stored on non-volatile, tangible media, such as magnetic, optical, or electronic storage. VA-VA translation examples

[0044] In some implementations, the TaaS unit 68 translates one VA (or a {VA, key} pair) into another VA. The two VAs typically belong to different virtual address spaces, i.e., they are associated with different keys.

[0045] An exemplary use case for VA-VA translation is on-demand paging (ODP). With ODP, the MTT 60 initially contains no translations for the entire virtual address space. Instead, PAs are assigned, and the translations are provided as needed. When NIC 28 receives a memory access request (e.g., an RDMA instruction) addressing a VA that is not yet assigned to a PA, the NIC notifies host 24 of a "page fault." To resolve the page fault and assign the VA to a new PA, the host typically needs to continuously emulate the structure and logic of the VA-PA address translation implemented in the NIC.

[0046] In some embodiments of the present invention, the need for such emulation is eliminated by using TaaS. In these embodiments, after receiving a page fault message from NIC 28, host 24 sends a TaaS request back to the NIC. The TaaS unit 68 responds to the TaaS request with a TaaS response that specifies a new VA to which a different key is assigned, the new VA referencing the currently non-existent PA.

[0047] Fig. Figure 2 is a message flow diagram that schematically illustrates the use of TaaS in on-demand paging (ODP) according to an embodiment of the present invention. The figure describes the processing of an RDMA write command received from a remote NIC 72. The command is processed by a NIC ODP driver 76 and by the TaaS unit 68, both of which are located in the NIC 28. The driver 76 and the unit 68 communicate with a host software driver 80, which runs on the CPU 40 of the host 24. The host software driver 80 acts as a translator requester 70.

[0048] The process begins with remote NIC 72 sending an RDMA write command ("Write_REQ") to NIC 28 during a write request phase 84. The write command specifies (i) a VA and (ii) a key labeled keyA. In this example, NIC 28 looks for the pair {VA, keyA} in MTT 60 and finds that this VA is currently unassigned.

[0049] Therefore, NIC 28 sends a page fault notification (“RES_FAIL”) to NIC ODP driver 76 in a page fault notification phase 88. The notification specifies the {VA, keyA} pair where the page fault occurred. In an ODP request phase 92, NIC ODP driver 76 sends an ODP request (“ODP_REQ”) to host software driver 80. The ODP request specifies the {VA, keyA} pair for which a new PA mapping is requested.

[0050] Host software driver 80 responds to the ODP request by sending a TaaS request (“TaaS REQ”) to TaaS unit 68 in NIC 28 during a TaaS request phase 96. The TaaS request specifies the relevant {VA, keyA} pair. During a TaaS response phase 100, TaaS unit 68 responds with a TaaS response (“TaaS RES”) that specifies (i) a (same or different) key labeled keyB and (ii) an offset relative to the starting address of keyB's address space that points to the requested PA.

[0051] In registration phase 104, host software driver 80 registers the {keyB, PA} pair in NIC 28. Host software driver 80 notifies NIC ODP driver 76 in ODP completion phase 108 that the assignment is complete. In data spreading resumption phase 112, NIC ODP driver 76 notifies NIC 28 that data spreading of the write command (spreading the data to memory 44) can resume. When NIC 28 has completed the RDMA write command, it sends a completion message to remote NIC 72 in acknowledgment phase 116.

[0052] The ODP use case described above is chosen only as an example. In alternative implementations, the TaaS unit can provide 68 VA-VA translation services as part of any other scenario. One alternative example relates to Logical Volume Management (LVM) in storage applications. With LVM, a host (e.g., a storage controller) typically translates between two virtual address spaces defined for a storage device, one referred to as the Logical Volume (LV) and the other as the Physical Volume (PV). In one implementation, the translation is from a logical {device, namespace, Logical Block Address (LBA)} of the client frontend to a {device, namespace, address} of the physical server backend.The TaaS unit 68 can relieve the host of these VA-VA translation tasks by providing the translation as a service to the host.

[0053] As noted above, in some embodiments the input address for the TaaS unit 68 is a transport address comprising a {Queue Pair (QP), Work Queue Element (WQE) index, byte offset} triple. The translation of a transport address can be used, for example, for error handling in ODP, for pre-fetching in ODP (e.g., scanning pending WQEs and ensuring that all translations are present, and if not, proactively handling errors), and for error correction (e.g., listing all translations accessed by a particular WQE). VA-PA translation examples

[0054] In some implementations, the TaaS unit 68 translates a VA (or a {VA, key} pair) into a PA. In a virtualized environment, the PA may also be referred to as a Guest PA (GPA). An example use case for VA-PA translation is the Page Request Interface (PRI). PRI is implemented, for example, in section 10.1.2 of the aforementioned PCI Express® Base Specification, Revision 5.0, Version 1.0. The terms "PRI" and "Page Request Service" are used interchangeably in PCIe terminology.

[0055] Fig. Figure 3 is a block diagram schematically illustrating the use of TaaS in the PRI according to one embodiment of the present invention. For clarity, only the relevant components of Host 24 and NIC 28 are shown in the figure. In this example, NIC 28 comprises, in addition to the TaaS unit 68, a PRI module 120 and a scatter engine 124 (which is shown outside the NIC in the figure for simplicity).

[0056] The PRI scenario begins when NIC 28 receives an RDMA write command over network 32. The write command specifies a VA range into which the data should be scattered, for example, using the format Write(VA, key, size, flags). The write command is sent to scatter engine 124 for execution. In this example, scatter engine 124 detects that the requested VA is currently unallocated, for example, because it receives an ATS translation error. The scatter engine therefore sends an error message in the format FAIL(VA, key) to PRI module 120.

[0057] In response to the error message, PRI module 120 sends a TaaS request in the format ANF(VA, key, size, flags)) to TaaS unit 68. The TaaS request requests a translation of the VA into a corresponding PA. TaaS unit 68 performs the translation and returns the requested PA in a TaaS response in the format ANTW(PA). The PRI process can now continue, with PRI module 120 sending a PRI request to IOMMU 52, and IOMMU 52 returning a MA in a PRI response. At this stage, NIC 28 can retry the RDMA write command, this time successfully.

[0058] In another exemplary use case, the TaaS Unit 68 provides a VA-PA translation service for software that stores and retrieves data from a storage device that only supports PAs. For example, with NVMe-over-Fabrics (NVMe-oF), a {NIC-key, VA} pair is specified for a buffer to which / from which an NVMe storage device should write. The NVMe device may need to receive a list of physical addresses (“PRPs”). The NVMe-oF driver must translate the {KEY, VA} from a remote request into a list of physical addresses. However, this configuration is already present in the network device because the translation was used for distributing (for I / O writes) or collecting (for I / O reads) from the buffer passed to the NVMe device.In some implementations, TaaS can be used to eliminate the need to duplicate the page table, which in turn can lead to higher throughput due to savings in computing power.

[0059] Fig. Figure 4 is a block diagram schematically illustrating the use of TaaS for storing and querying data in a storage device accessible via physical addresses, according to an embodiment of the present invention. In this example, a specific software (SW) 128 in the host 24 communicates via the PCIe bus 36 with both the NIC 28 and a storage device 132 (e.g., a solid-state drive - SSD). The storage device 132 is accessed via PAs, but the SW 128 receives (or generates) storage commands specified in the form of VAs.

[0060] In some embodiments, the TaaS unit 68 translates the {VA, key} pairs into corresponding PAs as a service for the SW 128. The SW 128 and the TaaS unit 68 can communicate via the TaaS request and response interface described above. This technique eliminates the need for the SW 128 to maintain a dictionary that maps {VA, key} PAs.

[0061] Furthermore, the TaaS unit 68 can alternatively provide VA-PA translation services as part of any other scenario. VA-MA TRANSLATION EXAMPLES

[0062] In some embodiments, the TaaS unit 68 translates a VA (or a {VA, key} pair) into an MA.

[0063] Fig. Figure 5 is a block diagram that schematically illustrates the use of TaaS in the translation of virtual addresses (VAs) to machine addresses (MAs) according to an embodiment of the present invention. For clarity, only the relevant components of Host 24 and NIC 28 are shown in the figure.

[0064] In the example of Fig. System 20 comprises several ATS clients 136 that access (read or write) data 140 in host memory 44. A specific ATS client 136 can be located inside or outside of NIC 28. Typically, but not necessarily, each ATS client 136 maintains its own ATC independently of other ATS clients.

[0065] To access data 140, in one embodiment, the ATS client 136 sends a TaaS request to the TaaS unit 68 in the NIC 28. The TaaS request (referred to in the figure as "VA2MA req") specifies a VA and requests a translation of the VA into a corresponding MA. The TaaS unit 68 forwards the request to the IOMMU 52, which in turn returns a translation response (referred to in the figure as "MA resp") specifying the requested MA. The TaaS unit 68 forwards the translation response to the ATS client 136. In other words, the TaaS unit 68 may have the requested translation in its ATC, and if not, it forwards an ATS request to the IOMMU. After the ATS client 136 receives the MA, it can now access data 140 in memory 44 using the MA.

[0066] Note that the ATS client 136 uses the scheme of Fig.5. It should monitor the ATC invalidation messages sent by NIC 28 and update its ATCs accordingly.

[0067] It is therefore understandable that the embodiments described above are given as examples and that the present invention is not limited to what has been specifically shown and described here. Rather, the scope of the present invention includes combinations and subcombinations of the various features described here, as well as variations and modifications thereof that would occur to a person skilled in the art upon reading the foregoing description and that are not disclosed in the prior art.Documents incorporated by reference into the present patent application shall be regarded as an integral part of the application, except that, to the extent that terms in these incorporated documents are defined in a manner that contradicts the definitions made explicitly or implicitly in the present description, only the definitions in the present description shall be taken into consideration.

[0068] It is understood that the aspects and embodiments described above are only examples and that changes in detail can be made within the scope of the claims.

[0069] Each device, method and feature disclosed in the description and (where applicable) in the claims and drawings can be provided independently or in any suitable combination.

[0070] The reference numerals included in the claims are for illustrative purposes only and do not restrict the scope of the claims.

Claims

[1] Network adapter, comprising: a host interface for communicating with a host via a peripheral bus; a network interface for sending and receiving packets to and from a network for the host; a packet processing circuit for processing the packets; a Translation-as-a-Service (TaaS) circuit integrated into the network adapter that serves to: receive from a requesting device a request to translate an input address into a requested address in a requested address space; translate the input address into the one or more requested addresses; and return the one or more requested addresses to the requesting device. [2] The network adapter of claim 1, wherein the TaaS circuitry is to translate the input address into the one or more requested addresses independent of an actual memory access operation. [3] The network adapter of claim 1 or 2, wherein the TaaS circuit is for receiving a translation request indicating an input address for which no translation exists and for responding to the translation request with a translation response indicating that no translation exists. [4] The network adapter of claim 1 or 2, wherein the request specifies a requested size, and wherein the TaaS circuit is to return a memory area having the requested size in the response. [5] The network adapter of claim 1, 2 or 3, wherein the input address comprises a virtual address (VA) of a network adapter. [6] The network adapter of claim 5, wherein the VA comprises a network adapter VA. [7] A network adapter according to any preceding claim, wherein the input address comprises a key-address pair. [8] A network adapter according to any one of the preceding claims, wherein the input address comprises a transport address. [9] A network adapter according to any preceding claim, wherein the TaaS circuit is to return, in addition to returning the one or more requested addresses, metadata corresponding to the one or more requested addresses. [10] A network adapter according to any preceding claim, wherein the one or more requested addresses comprise one of (i) a virtual address (VA), (ii) a physical address (PA), and (iii) a machine address (MA). [11] A network adapter according to any preceding claim, wherein the TaaS circuit is to receive the request as a work request posted on a queue pair (QP) and to return the one or more requested addresses by posting a completion message on the QP indicating the one or more requested addresses. [12] A network adapter according to any preceding claim, wherein the input address points to one of (i) a contiguous memory range and (ii) a pattern of memory addresses. [13] A network adapter according to any preceding claim, wherein the request is received in response to an on-demand paging (ODP) notification in which the network adapter notifies the requesting device of an unallocated memory page, the request requesting an input address to which the unallocated memory page is to be allocated. [14] A network adapter according to any preceding claim, wherein the request specifies a virtual address (VA) in a logical volume defined on a storage device, the request requesting a corresponding address on the storage device. [15] A network adapter according to any preceding claim, wherein the request requests translation of a virtual address (VA) into a physical address (PA) in response to receiving a memory command of a remote memory access protocol, the command specifying the VA. [16] A network adapter according to any preceding claim, wherein the request requests translation of the VA into a physical address (PA) in response to encountering an Address Translation Service (ATS) authorization error. [17] Network adapter according to one of the preceding claims, wherein the request requests the translation of the input address into a machine address (MA). [18] A method in a network adapter, the method comprising: Communicating with a host via a peripheral bus; Sending and receiving packets to and from a network for the host; and Using a Translation-as-a-Service (TaaS) circuit integrated into the network adapter: receive from a requesting device a request to translate an input address into a requested address in a requested address space; translate the input address into the one or more requested addresses; and return the one or more requested addresses to the requesting device. [19] The method of claim 18, wherein translating the input address into the one or more requested addresses is performed independently of an actual memory access operation. [20] The method of claim 18 or 19, wherein receiving the request comprises receiving a translation request indicating an input address for which no translation exists, and responding to the translation request with a translation response indicating that no translation exists.

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