STORAGE DEVICE AND METHOD FOR OPERATING A STORAGE DEVICE

Abstract

A semiconductor device is provided. The storage device comprises a plurality of storage elements, each of which is designed to store a data value; and a controller designed to read a plurality of stored data values ​​from the plurality of storage elements; to process the stored data values ​​using an error detection code to generate a first erase vector; to map an address list of permanently dysfunctional storage elements, generated during the initial testing of the storage device, to the plurality of storage elements to generate a second erase vector; and to process the plurality of stored data values ​​using an error correction code, taking into account the first and second erase vectors.

Description

Technical field

[0001] Various embodiments generally relate to a storage device and methods for operating a storage device. background

[0002] A storage array may, after production, exhibit any, some, or all of the following types of defects: bit group failures, word line-oriented failures, and single-cell failures.

[0003] Fig. Figure 1 schematically illustrates an array of memory cells 102 that can be part of a storage device 100.

[0004] A flashing symbol marked "1" indicates bit group failures. Here, the failure affects all memory cells connected to the failing bit line 104, which is located in Fig. 1 runs vertically. A flashing symbol marked "2" indicates the failures oriented along word line 106. Here, the failure affects all memory cells along a word line 106, which is in Fig. 1 runs horizontally. A flashing symbol marked "3" indicates a failure of individual cell 102. In all cases, a "failing" memory cell (regardless of whether it fails individually or as part of a bit line or word line failure) can be permanently "stuck" in one of its possible programming states, e.g., either in a "1" state or in a "0" state.

[0005] All these defects can reduce the yield of storage device production unless they are repaired.

[0006] Single defects and word-line-oriented defects can be repaired, for example, with a classic word-line redundancy mechanism.

[0007] However, repairing bit group failures with redundancy is more costly: the repair may need to address an entire bit group (the bit group might, for example, comprise eight bits (one byte)). For this repair: according to a state of the art, as shown in Fig. 2A , wherein elements of a storage device 200 are depicted in the prior art, and Fig. 2B, which describes data and data handling in the storage device 200. Read amplifier or SA circuits may need to be extended. Additional / redundant bit groups BG r can be provided in the hard macro of the non-volatile memory (NVM) to be used as a "reserve" in the event of a failed bit line 104, which affects an entire column of bit groups BG mThe effect is that although the terms "additional bit groups" and "redundant bit groups" are used somewhat interchangeably here, the term "additional" emphasizes the aspect that the memory elements are provided in case they may be required, and the term "redundant" emphasizes the aspect that the additional / redundant memory cells redundantly store certain data that should be stored in the memory elements affected by the failing bit line 104.

[0008] As in Fig. 2A indicates the additional bit groups BG r with their own respective addresses (in Fig. 2A (specified as "Sec Addr"). If it is intended to read data from a bit group BGm affected by the failing bit line 104 of the storage device 200, a digital controller 220 instructs the raw data 226 to be read from the addressed memory part 222 and the failing bit group BGm , as specified in a configuration file 230, by a data part 228 from the additional bit groups BG r to replace, thereby forming a repaired bit group 231. Data processing such as the transformation 232 and error correction by an ECC 234 are performed on the repaired bit group 231.

[0009] This type of repair can come at the cost of a significant amount of additional required space, for example because for each permanently dysfunctional memory element 102, an entire group of memory elements is required (e.g., eight memory elements 102 in the case of the group consisting of eight memory elements, one byte).

[0010] US 9,946,598 B1 describes systems, devices, and methods that can provide the recording of open-circuit position information associated with the NVM position when a non-volatile memory (NVM) position satisfies an open-circuit condition. Additionally, a shift of one or more bits can be performed while writing a codeword to the NVM position to avoid an open-circuit condition at the NVM position. Furthermore, the end of a parity section of the codeword can be punctuated by the shift. Summary

[0011] A storage device and a method according to the invention are specified in the independent claims. Additional features for advantageous embodiments are specified in the dependent claims. Brief description of the drawings

[0012] In the drawings, identical reference numerals in the different views generally refer to the same parts. The drawings are not necessarily to scale; instead, the emphasis is generally placed on illustrating the principles of the invention. The following description details various embodiments of the invention with reference to the following drawings. These show: Fig. 1 schematically a storage device with an array of memory cells; Fig. 2A and Fig. 2B schematically a bit line repair according to a state of the art; Fig. 3 schematically a repair of faulty data stored in memory cells known to be defective in a storage device according to various embodiments; Fig. 4. Schematically, how different types of defects in a storage device of different designs are handled; Fig. 5A and Fig. 5B Schematic details of a repair of faulty data stored in memory elements known to be permanently dysfunctional in a storage device according to various embodiments; and Fig. 6 a flowchart of a method for operating an electronic device according to various embodiments. Description

[0013] The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments in which the invention can be practiced.

[0014] The word "exemplary" is used here to mean "serving as an example, instance, or illustration." Any embodiment or design described here as "exemplary" is not necessarily to be construed as preferable or advantageous over other embodiments or designs.

[0015] Different aspects of the disclosure are provided for devices, and different aspects of the disclosure are provided for methods. It is understood that the basic properties of the devices also apply to the methods and vice versa. Therefore, for the sake of brevity, a duplicate description of such properties may have been omitted.

[0016] The scenarios described above involve either leaving storage devices with defective bit lines unrepaired, which can result in a yield loss of approximately 6%, or using redundant bit groups to store data that would otherwise be stored in bit groups containing the defective bit lines. The latter approach can reduce the yield loss to less than about 0.1%, but the redundant bit groups can introduce an overhead in terms of the required area. A significant portion of this overhead may depend on the data transformation scheme (e.g., whether a 6 / 8 or 7 / 8 scheme is used; in other words, whether 6 or 7 bits of user data are transformed into 8 bits of stored data), but it can range from about 2% to 2.5%.

[0017] In various embodiments, a storage device is provided which has a yield loss of about 0.1%, but requires no additional space (in other words, the amount of overhead in terms of required space can be zero).

[0018] Additionally, in the prior art, the redundant bit groups BG can be used. r Bit group redundancy repair is considered "always on". In other words, during every read from storage device 200, it must be checked whether any of the data from the currently addressed memory area has been replaced by data from the redundant bit group BG. r needs to be replaced. This can impair reading performance (in general, and especially if an additional reading process is required).

[0019] In various embodiments, the redundant bit groups BG rThis eliminates the need for additional surface area. A processor used in the prior art, such as an existing digital controller, can be reused with some programming adjustments.

[0020] In various embodiments, an error correction code (ECC) can be used to repair bit groups affected by a failed bit line. The ECC can essentially be used in the prior art, but it can be adapted according to various embodiments, as described here.

[0021] Since a (final) correction of the failing bit lines is carried out together with the ECC correction according to various embodiments, there is no deterioration in read performance.

[0022] Fig. Figure 4 shows, for an exemplary PRRAM (Program Resistive Random Access Memory) device with 8 MB, why the storage device described here (and the method for operating it) achieves a high yield in combination with a low area requirement (memory and / or semiconductor).

[0023] - Tests and simulations show that approximately 1.2% of the sample 8 MB PPRAM devices may experience bit line failures after production.

[0024] For approximately 0.1% of storage devices, inverting the stored data may not solve the problem. Such devices might, for example, contain more than one failed bit per page. These devices can be discarded, causing the yield loss of approximately 0.1% (see right branch in Fig. 4).

[0025] In the remaining approximately 1.1% of devices, data inversion can resolve the failure, for example, because each page contains only a single failing memory cell.

[0026] Of these 1.1%, approximately 99% or more may not experience any degradation during their lifetime, meaning that no fault will be marked by the ECC or an EDC fault detection code (see left branch in Fig. 4).

[0027] Less than approximately 0.1% of memory devices may experience degradation during their lifetime, meaning that the ECC / EDC can detect and correct a fault. The detected fault is likely to be a single failure, meaning the ECC is unlikely to be pushed to its limits.

[0028] In various embodiments, a storage device 100 can include a processor 320, which can be designed to perform, initiate, and / or control various functions of the storage device 100. Fig. 3 is a digital controller specified as an example for a Processor 320, but any type of (e.g., micro) Processor 320 can be used that is suitable to provide the functionality specified here.

[0029] The storage device 100 can further comprise a plurality of storage elements 102, also referred to as memory cells (or simply "cells" or "elements"), some of which (at least) some may be affected by bit line failures, word line failures, and / or single element / cell failures. The storage elements 102 can be non-volatile storage elements, for example, resistive storage elements. The plurality of storage elements 102 can be part of the hardware of the storage device 100, which is also referred to as the hard macro 222. The storage device hardware can, for example, in addition to the storage elements 102, include source amplifiers SA, conductive lines, multiplexers, address decoders, etc., essentially as known in the prior art.

[0030] In various designs, failing bit lines (and also failing word lines and failing individual memory elements) can be detected after production during product testing and can therefore be considered "pre-detected".

[0031] The storage device 100 can be organized into groups of storage elements 102 for read and / or write and / or error detection and / or error correction processes. Each group of storage elements 102 can, for example, contain eight storage elements for storing one byte (eight bits) of data, or any other number of two or more storage elements 102.

[0032] The groups of memory elements 102 can typically be organized along word lines 106. This can lead to a situation in which each memory element 102 connected to a failing bit line 104 can be part of a (different) group of memory elements 102.

[0033] In the Fig. In the example shown in Figure 1, in which only a small fraction of a typical storage device 100 according to various embodiments is shown, eight storage elements 102 along a word line 106 (row) can form a group of storage elements 102, such that Fig. Figure 1 shows a total of eight groups of memory elements 102 (one per row). The failing bit line 104, indicated by "1", can cause one permanently dysfunctional memory cell 102 per group of memory elements. In other words, all in Fig. The memory groups shown in Figure 1 are affected by at least one permanently dysfunctional memory element 102. The group of memory elements in the second row is additionally affected by the word line failure indicated by "2", and the second memory element 102 of the group of memory elements in the third row is further affected by a single-cell error indicated by "3".

[0034] The pre-detected failing memory elements 102 can be stored in a suitable manner, for example as a (e.g. configuration) file or in a database.

[0035] In various embodiments, the information stored as part of the configuration regarding permanently dysfunctional memory elements 102 can be extended if 100 new permanently dysfunctional memory elements 102 are discovered during the lifetime of the storage device. In various embodiments, if 100 new permanently dysfunctional memory elements 102 are discovered during the lifetime of the storage device, the information can be stored as supplementary information, for example, in an additional file or database. In this case, the identification of the known permanently dysfunctional memory elements 102 can be retrieved from a combination of both the original information and the supplementary information.

[0036] Knowing the positions of failing memory elements 102 and the organizational structure of the memory elements 102 a priori means that the bit groups (e.g., groups of eight memory elements, each designed to store one data byte) affected by the permanently dysfunctional memory elements 102 can also be determined. Any group of memory elements 102 containing a permanently dysfunctional memory element 102 can be identified as potentially faulty.

[0037] The plurality of memory elements 102, or a predefined subset of the plurality of memory elements 102, for example a subset called a "page" (each page can have several groups of memory elements 102, the memory elements 102 being arranged as an array or matrix along several bit lines 104 and along several word lines 106), can be characterized as belonging to a group of memory elements 102 containing one or more potentially faulty memory elements 102, or to a group of memory elements 102 not containing an a priori known permanently faulty memory element 102.The identifier can be provided, for example, as a so-called erase vector, which can have a data value for each group of memory elements (of the storage device 100 or the predefined subset; in other words, the erase vector can have as many elements / values ​​as the storage device or the predefined subset has groups of memory elements 102). The data value of the erase vector can be set to a first value (e.g., "1") for a bit group that contains at least one permanently dysfunctional memory element 102, and to a second value (e.g., "0") that differs from the first value for a bit group that is free of permanently dysfunctional memory elements 102. This second erase vector is referred to as the second erase vector vec2 to distinguish it from another (first) erase vector vec1, which is described below.

[0038] The second deletion vector vec2 can be generated "in flight" as part of a read process in various implementations. Alternatively, the second deletion vector vec2 can be generated and stored in advance in various implementations, e.g., as a file or in a database.

[0039] Fig. 5A and Fig. Figure 5B schematically shows details of a repair of (potentially) faulty data stored in memory elements known to be permanently dysfunctional in a storage device according to various embodiments.

[0040] The second deletion vector vec2 can be provided to a code that performs error correction (ECC, ECC-Engine 550) in various embodiments.

[0041] With the second erase vector vec2, which is provided as input to the ECC 550, the detection capability of the ECC 550 (or rather its corresponding fault detection code EDC, which is considered part of the ECC 550) to detect groups of memory elements 102 containing previously known permanently dysfunctional memory elements 102 is not required. Thus, providing the second erase vector vec2 can save fault detection power.

[0042] Furthermore, error correction performance can be saved in various embodiments by one, some, or all of the following aspects.

[0043] In various embodiments, a correction of data 226, which is stored in a group of memory elements 102, for which the second erase vector vec2 indicates (e.g. by having the first value, e.g. 1) that the group of memory elements 102 has a permanently dysfunctional memory element 102 (“pre-detected”, as stated above), can only be carried out if all of the following conditions are true: - Data inversion during write access was not successfully applied (i.e., the data word was not corrected); - the data transformation 332 (a preprocess of ECC processing, which can use a predefined transformation pattern to transform a predefined number (e.g. 6 or 7) of data values ​​into a predefined larger number (e.g. 8) of transformed data values) has not already corrected the data, where the transformation process may in principle be known in the prior art; - written data is not already a valid / expected codeword (ECC processing may include an encoding process 534 during a write access to the memory elements 102 and a decoding process 334, which is an inverse process, during a read access to the memory elements 102; as part of the write operation, the written data can be read back and it can be verified that the data read from the group of memory elements 102 constitutes a codeword of the code, i.e., has been written without errors, possibly despite the permanently dysfunctional memory element 102, which may have been stuck on a favorable data value for the data that was written). - Permanently dysfunctional memory elements 102 caused by a defective word line can be repaired, essentially as known in the prior art, by storing redundant data in another word line, but this mechanism was either not applied or it failed.

[0044] In various embodiments, as mentioned above, an additional input can be provided to the ECC 550. This is in Fig. 5A and Fig. 5B next to the data 226 and the second deletion vector vec2, indicated by the first deletion vector vec1.

[0045] The first erase vector vec1 can be provided by the ECC, in particular by the decoder (the EDC), which, during a verification read as part of the write process, recognizes that the data read does not form a codeword of the ECC.

[0046] As outlined above, both the first erase vector vec1 and the second erase vector vec2 can have the same length as the number of groups of memory elements that have been addressed for reading from memory (the data stored in the groups of memory elements can be referred to as bit groups, for example bytes in the case of eight bits).

[0047] For the first erase vector vec1, the values ​​can follow the same scheme as described above for the second erase vector vec2: a first value (e.g. “1”) can indicate that the respective bit group has at least one error (resulting from the known permanently dysfunctional memory element 102 or another source of error), and a second value (e.g. “0”) can indicate that the respective bit group forms a codeword of the ECC and is therefore considered error-free.

[0048] In other words, each position in a delete vector (the first delete vector vec1 and the second delete vector vec2) marks whether the corresponding byte is faulty (first value, e.g. "1") or not (second value, e.g. "0").

[0049] Both deletion vectors, the first deletion vector vec1 and the second deletion vector vec2, can be taken into account in different embodiments when applying the correction.

[0050] In various implementations, the two erase vectors, the first erase vector vec1 and the second erase vector vec2, can be added together, for example, using an OR gate. Even if both vectors, the first erase vector vec1 and the second erase vector vec2, contain an error at the same position, the resulting (final) erase vector, which can serve as the basis for deciding whether the ECC should be used to correct a given group of bits, may still indicate an error at that position (and thus trigger a correction).

[0051] Nowadays, ECC can typically correct 1 byte error and 2 erases (erases are localized errors; the position is known, but not the value). And since, in various implementations, the position of the failing bit line is known, it can be treated as one erase (otherwise, there would be a risk that the ECC could interpret the failing bit line as a byte error and reach its limit). Final deletion vector = vec1 + vec2

[0052] For example, if bit groups that are specified as error-free in the first erasure vector vec1 are to be excluded from the correction, vec1 and vec2 can be taken into account in a different way than outlined above, for example individually, or the final erasure vector can be formed differently, e.g. using other suitable logic combinations.

[0053] As briefly mentioned above, compared to the prior art, these embodiments can save memory / semiconductor / chip area in the hard macro by correcting failing bit lines using the existing ECC instead of using redundant bit groups (which may even fail themselves).

[0054] Another aspect is the reuse of existing functionality: the failing bit line (or rather the respective bit group containing the potentially faulty bit that would have been stored in the failing bit line) can be provided to the ECC as a deletion, which can be corrected along with the other deletions coming from the decoder, e.g., the ECC.

[0055] Another aspect is that a correction can only be performed if it is necessary (or even if it makes sense at all). For example, a bit group containing a permanently dysfunctional memory element cannot be corrected if inversion has already taken care of the correction (this functionality is already available and rarely used).

[0056] Another reason not to attempt ECC correction is if the data word is already uncorrectable even without the "pre-detected" failing bit group.

[0057] As in Fig. As can be seen in 5B, ECC encoding is performed on user data 552 (as part of a write process). Accordingly, decoding read and processed stored data in ECC can result in user data 552 (provided it is read and / or restored correctly).

[0058] Inversion bit I and parity bit P can be added and processed in the ECC engine 550.

[0059] A transformation table 560, which defines how the coded data 554 are to be transformed to form the raw data to be written, and conversely how the raw data are to be de-transformed to restore the coded data 554, can be part of a digital interface of the storage device 100.

[0060] As mentioned above, even additional errors occurring during the lifetime of the storage device are unlikely to push the ECC 550 to its limits, since a typical ECC 550 used for a memory such as the one described here should be able to correct one erase, one (additional, subsequently occurring) byte error, or two erases. Even if another erase occurs, the ECC 550 should still be able to correct the bit group.

[0061] The probability of a byte error occurring is much smaller than the probability of a deletion, with a relative rate of about 1 in 1000.

[0062] Fig. Figure 6 shows a flowchart 600 of a method for operating a storage device according to various embodiments. The storage device can have a plurality of storage elements, each of which can be configured to store a data value.

[0063] The procedure may include: reading a plurality of stored data values ​​from the plurality of memory elements (610); processing the stored data values ​​using an error detection code to generate a first erase vector (620); mapping an address list of permanently dysfunctional memory elements generated during the initial testing of the storage device onto the plurality of memory elements to generate a second erase vector (630); and processing the plurality of stored data values ​​using an error correction code, taking into account the first erase vector and the second erase vector (640).

[0064] The following are several examples: Example 1 is a storage device. The storage device comprises a plurality of storage elements, each of the plurality of storage elements being designed to store a data value; and a controller designed to read a plurality of stored data values ​​from the plurality of storage elements; to process the stored data values ​​using an error detection code to generate a first erase vector; to map an address list of permanently dysfunctional storage elements, generated during the initial testing of the storage device, to the plurality of storage elements to generate a second erase vector; and to process the plurality of stored data values ​​using an error correction code, taking into account the first erase vector and the second erase vector. In Example 2, the subject of Example 1 may optionally include the fact that the majority of memory elements are logically divided into groups of memory elements, and that the first erase vector for each of the groups of memory elements has a first value if processing using the error detection code results in an error in the respective group, and a second value if processing using the error detection code does not result in an error in the respective group. In Example 3, the subject of Example 1 or 2 may optionally include the fact that the majority of memory elements are logically divided into groups of memory elements, and that the second deletion vector for each of the groups of memory elements has a first value if the respective group contains a permanently dysfunctional memory element, and a second value if the respective group is free of permanently dysfunctional memory elements. In Example 4, the subject of one of Examples 1 to 3 may, if necessary, include considering the first deletion vector and the second deletion vector and applying a logic OR operation to the first deletion vector and the second deletion vector. In Example 5, the subject matter of one of Examples 1 to 4 may, where appropriate, include processing the plurality of stored data values ​​using an error correction code, taking into account the first erase vector and the second erase vector, and applying error correction if the first erase vector indicates an error detected by the error detection code, and if the second erase vector additionally or exclusively indicates a permanently dysfunctional storage element. In Example 6, the subject of one of Examples 1 to 5 may optionally include the processor being designed to process user data and write the processed user data to the plurality of memory elements in order to form the plurality of stored data values, wherein the processing includes error-correcting encoding of the user data in order to form encoded data. In Example 7, the subject of Example 6 may, if necessary, include processing further transforming the coded data using a predefined transformation scheme to form transformed data. In Example 8, the subject of Example 6 or 7 may, where appropriate, include writing and analyzing whether the written data can be read without errors, and if the analysis reveals that the written data can be read with an error, rewriting the processed user data with all bits inverted and setting a dedicated inversion bit to a predefined value indicating the inversion of the data. Example 9 is a method for operating a storage device comprising a plurality of storage elements, each of the plurality being designed to store a data value. The method includes reading multiple stored data values ​​from the plurality of storage elements, processing the stored data values ​​using an error detection code, thereby generating a first erase vector, mapping an address list of permanently dysfunctional storage elements generated during the initial testing of the storage device onto the plurality of storage elements, thereby generating a second erase vector, and processing the plurality of stored data values ​​using an error correction code, taking into account the first and second erase vectors. In Example 10, the subject of Example 9 may optionally include the fact that the majority of memory elements are logically divided into groups of memory elements, and that the first erase vector for each of the groups of memory elements has a first value if processing using the error detection code results in an error in the respective group, and a second value if processing using the error detection code does not result in an error in the respective group. In Example 11, the subject of Example 9 or 10 may, if appropriate, include the fact that the majority of memory elements are logically divided into groups of memory elements and that the second deletion vector for each of the groups of memory elements has a first value if the respective group contains a permanently dysfunctional memory element, and a second value if the respective group is free of permanently dysfunctional memory elements. In Example 12, the subject matter of one of Examples 9 to 11 may, if necessary, further include the consideration of the first deletion vector and the second deletion vector involving the application of a logical OR operation to the first deletion vector and the second deletion vector. In Example 13, the subject matter of one of Examples 9 to 12 may, where appropriate, further include processing the plurality of stored data values ​​using an error correction code, taking into account the first erase vector and the second erase vector, and applying error correction if the first erase vector indicates an error detected by the error detection code, and if the second erase vector additionally or exclusively indicates a permanently dysfunctional storage element. In Example 14, the subject matter of one of Examples 9 to 13 may optionally further include the processor being designed to process user data and write the processed user data to the plurality of memory elements in order to form the plurality of stored data values, the processing including error-correcting encoding of the user data in order to form encoded data. In Example 15, the subject of Example 14 may, if necessary, further include processing and transforming the coded data using a predefined transformation scheme to form transformed data. In Example 16, the subject of Example 14 or 15 may, where appropriate, further include the writing process including analysis to determine whether the written data can be read without errors, and if the analysis reveals that the written data can be read with an error, rewriting the processed user data with all bits inverted and setting a dedicated inversion bit to a predefined value indicating the inversion of the data.

Claims

[1] Storage device comprising: a plurality of storage elements, each of the plurality of storage elements being designed to store a data value; and a controller designed for • Reading a plurality of stored data values ​​from a plurality of memory elements; • Processing the stored data values ​​using an error detection code to generate an initial deletion vector; • Mapping an address list of permanently dysfunctional memory elements, generated during the initial testing of the storage device, to the majority of memory elements in order to generate a second erase vector; • Processing the plurality of stored data values ​​using an error correction code, taking into account the first erase vector and the second erase vector, wherein the processing of a group of memory elements marked as containing a faulty memory element in the first erase vector or the second erase vector corrects the faulty memory element as an error with a known position. [2] Storage device according to claim 1, where the majority of storage elements are logically divided into groups of storage elements, wherein the first deletion vector for each of the groups of storage elements includes a first value if processing using the error detection code results in an error in the respective group, and a second value if processing using the error detection code does not result in an error in the respective group. [3] Storage device according to claim 1 or 2, where the majority of storage elements are logically divided into groups of storage elements, wherein the second deletion vector for each of the groups of memory elements includes a first value if the respective group contains a permanently dysfunctional memory element, and a second value if the respective group is free of permanently dysfunctional memory elements. [4] Storage device according to any one of claims 1 to 3, wherein taking into account the first erase vector and the second erase vector comprises applying a logic OR operation to the first erase vector and the second erase vector. [5] Storage device according to any one of claims 1 to 4, wherein the processing of the plurality of stored data values ​​using an error correction code taking into account the first erase vector and the second erase vector comprises applying an error correction when the first erase vector indicates an error detected by the error detection code, and when additionally or exclusively the second erase vector indicates a permanently dysfunctional storage element. [6] Storage device according to any one of claims 1 to 5, the processor is further designed to Processing user data; and Writing the processed user data to the majority of storage elements to form the majority of stored data values; the processing includes error correction encoding of the user data in order to form encoded data. [7] Storage device according to claim 6, wherein the processing further comprises transforming the encoded data using a predefined transformation scheme to form transformed data. [8] Storage device according to claim 6 or 7, where the writing process includes analyzing whether the written data can be read without errors; and If the analysis results in the written data being read with an error, the processed user data is rewritten with all bits inverted and a dedicated inversion bit is set to a predefined value indicating the inversion of the data. [9] Method for operating a storage device comprising a plurality of storage elements, each of the plurality of storage elements being designed to store a data value, the method comprising: • Reading a plurality of stored data values ​​from a plurality of memory elements; • Processing the stored data values ​​using an error detection code to generate an initial deletion vector; • Mapping an address list of permanently dysfunctional memory elements, generated during the initial testing of the storage device, to the majority of memory elements in order to generate a second erase vector; and • Processing the majority of stored data values ​​using an error correction code, taking into account the first and second deletion vectors, wherein the processing of a group of memory elements that is marked as containing a faulty memory element in the first erase vector or the second erase vector corrects the faulty memory element as a fault with a known position. [10] Method according to claim 9, where the majority of storage elements are logically divided into groups of storage elements, wherein the first deletion vector for each of the groups of storage elements includes a first value if processing using the error detection code results in an error in the respective group, and a second value if processing using the error detection code does not result in an error in the respective group. [11] Method according to claim 9 or 10, where the majority of storage elements are logically divided into groups of storage elements, wherein the second deletion vector for each of the groups of memory elements includes a first value if the respective group contains a permanently dysfunctional memory element, and a second value if the respective group is free of permanently dysfunctional memory elements. [12] Method according to any one of claims 9 to 11, wherein taking into account the first deletion vector and the second deletion vector comprises applying a logic OR operation to the first deletion vector and the second deletion vector. [13] Method according to any one of claims 9 to 12, wherein processing the plurality of stored data values ​​using an error correction code taking into account the first erase vector and the second erase vector comprises applying error correction when the first erase vector indicates an error detected by the error detection code, and when additionally or exclusively the second erase vector indicates a permanently dysfunctional storage element. [14] Method according to any one of claims 9 to 13, further comprising: Processing user data; and Writing the processed user data to the majority of storage elements to form the majority of stored data values; the processing includes error correction encoding of the user data in order to form encoded data. [15] Method according to claim 14, wherein the processing further comprises transforming the coded data using a predefined transformation scheme to form transformed data. [16] Method according to claim 14 or 15, where the writing process includes analyzing whether the written data can be read without errors; and If the analysis results in the written data being read with an error, the processed user data is rewritten with all bits inverted and a dedicated inversion bit is set to a predefined value indicating the inversion of the data.

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