DIGITAL PREDICTION AND LOAD OFFSET LOOP FOR CHOPPING SENSOR ADC

Abstract

An analog-to-digital converter (ADC) circuit (200) is provided, designed to process an input signal. The ADC circuit (200) includes a modulation circuit (210) designed to modulate the input signal with a modulation frequency to generate a modulated signal. The ADC circuit (200) includes a combination circuit (206) designed to receive the modulated signal and combine it with a feedback signal (208) to generate a combined signal. The ADC circuit (200) includes a conversion circuit (220) designed to convert the combined signal into a digital signal at a sampling frequency. The ADC circuit (200) includes a tracking register (230) designed to store and update the digital signal.The ADC circuit (200) includes a prediction circuit (240) designed to estimate a future value of the digital signal based on historical data from the digital signal and to load the estimated value into the tracking register (230) at a modulation transition time. The ADC circuit (200) includes a feedback circuit (250) designed to convert a digital output signal from the tracking register into the feedback signal provided to the combination circuit. The ADC circuit (200) includes a demodulation circuit (260) designed to demodulate the digital signal at the modulation frequency to produce a digital demodulated output signal.

Description

Area

[0001] The present disclosure relates to analog-to-digital converters and in particular a digital offset ripple loop for analog-to-digital converters with a chopped sensor. background

[0002] Analog-to-digital converters (ADCs) are widely used in electronic systems to convert continuous analog signals into discrete digital representations. WO 2016 / 087869 A1, for example, describes a successive approximation analog-to-digital converter (SAR-ADC) that achieves higher resolution. This is accomplished by storing the residual error remaining after each conversion cycle and adding it to the input signal of the following cycle. By accumulating these residual values ​​over several cycles, a more accurate digital representation of the analog signal can be obtained by time-averaging the outputs. This technique increases the effective resolution of the ADC, for example, from 12 to over 14 bits, without requiring significant hardware modifications or higher clock rates.

[0003] In many sensing applications, such as magnetic field detection using Hall-effect sensors, the analog signals of interest can be corrupted by offset and low-frequency noise. These unwanted signal components can significantly impair the accuracy and resolution of the ADC output.

[0004] Chopping techniques have been employed to address problems related to offset and low-frequency noise in analog circuits. By modulating the input signal to a higher frequency before amplification and demodulating it after amplification, chopping can effectively separate the signal of interest from offset and low-frequency noise. However, implementing chopping in ADC systems can introduce additional challenges, such as residual offset due to charge injection and clock pass-through in the chopper switches.

[0005] To further improve the performance of chopped ADC systems, various offset suppression techniques have been developed. These techniques often involve complex analog circuitry or digital post-processing, which can increase power consumption, chip area, and system complexity. Furthermore, many existing offset suppression methods cannot quickly adapt to changing offset conditions, potentially leading to temporary inaccuracies during transient periods.

[0006] In applications where the ADC is used intermittently or with a duty cycle to reduce power consumption, the settling time required for the offset suppression circuitry can become a significant limitation. This settling time can reduce the effective measurement time available within each active period, potentially degrading the signal-to-noise ratio of the converted signal.

[0007] Furthermore, the interaction between chopping, offset suppression, and the ADC conversion process itself can lead to complex system dynamics. These interactions can result in residual ripple or peaks in the output spectrum that are difficult to eliminate without compromising the desired signal bandwidth or increasing system complexity.

[0008] As acquisition systems continue to demand higher accuracy, lower power consumption, and faster response times, there is a continuous need for improved ADC architectures that can effectively address offset and noise problems while maintaining simplicity and efficiency. Brief description

[0009] This need is addressed by circuits and methods according to the attached claims.

[0010] According to a first aspect of the present disclosure, an ADC circuit for processing an input signal is proposed. The ADC circuit comprises a modulation circuit designed to modulate the input signal with a modulation frequency to generate a modulated signal. The ADC circuit further comprises a combination circuit designed to receive the modulated signal and combine it with a feedback signal to generate a combined signal. The ADC circuit also includes a conversion circuit designed to convert the combined signal into a digital signal at a sampling frequency. In addition, the ADC circuit includes a tracking register designed to store and update the digital signal.The ADC circuit further includes a prediction circuit designed to estimate a future value of the digital signal based on historical data from the digital signal and to load the estimated value into the tracking register at a modulation transition time. The ADC circuit also includes a feedback circuit designed to convert a digital output signal from the tracking register into the feedback signal provided to the combination circuit. Finally, the ADC circuit includes a demodulation circuit designed to demodulate the digital signal at the modulation frequency to produce a demodulated digital output signal.

[0011] The proposed ADC circuit implements a digital offset ripple loop that predicts and loads estimated signal and / or offset values ​​at modulation transition times. This approach can skip a successive approximation register (SAR) portion of the conversion circuitry when transitioning from one modulation phase to another. As a result, low 1 / f noise is achievable, while overall white noise is reduced due to an increased averaging time. This configuration can be particularly advantageous for applications requiring high precision and low noise, such as three-dimensional (3D) sensors and consumer sensors, where power consumption and noise are critical factors.

[0012] According to some embodiments, the modulation circuit of the ADC circuit can include an analog chopper circuit designed to modulate the input signal at a chopper frequency to produce an analog chopped signal as the modulated signal. This allows for an effective reduction of low-frequency noise and offset in the input signal, as well as a reduction of the ADC input offset, thereby improving the overall signal-to-noise ratio of the ADC.

[0013] According to some embodiments, the combined circuitry of the ADC circuit can be designed to determine a difference between the modulated (chopped) signal and the feedback signal. Minimizing this difference is the basis of SAR and ΣΔ analog-to-digital conversion.

[0014] According to some embodiments, the conversion circuitry of the ADC circuit can be designed to operate as a SAR-ADC in a first operating mode and as a sigma-delta (ΣΔ)-ADC in a second operating mode. Thus, the ADC conversion circuitry can be configured to operate in two distinct modes, each suited to different operating requirements. In the first mode, the circuit functions as a SAR-ADC, which is known for its speed and efficiency in quickly converting an analog signal to a digital value through a binary search operation. This mode is particularly useful for applications requiring fast conversions with moderate resolution.In the second mode, the circuit switches to operation as a ΣΔ ADC, characterized by its ability to provide high-resolution conversion and excellent noise shaping through oversampling of the input signal and the application of noise reduction techniques. This mode is ideal for scenarios where precision and low noise are critical. The ability to switch between SAR and ΣΔ modes allows flexibility in balancing conversion speed and resolution, and adaptation to varying signal conditions and application requirements.

[0015] According to some embodiments, the first operating mode can be an initial operating mode following the initial startup of the ADC circuit, and the second operating mode can be a subsequent operating mode following the initial operating mode. The first operating mode of the ADC circuit can be used immediately after power-on or initialization of the circuit and serves as the initial operating mode. During this phase, the ADC operates in a mode likely optimized for quickly stabilizing the circuit and performing necessary calibrations, which may involve the use of a SAR ADC. After the ADC has completed its initial startup procedures and the system has stabilized, the circuit transitions to the second operating mode.In this subsequent mode, the ADC can switch to a ΣΔ ADC, which offers higher resolution and improved noise performance, enabling more accurate signal processing during normal operation. This configuration allows for fast initial conversion using SAR, followed by high-resolution conversion using sigma-delta, thus optimizing both startup time and steady-state behavior.

[0016] According to some embodiments, the conversion circuit of the ADC circuit may include a signal processing circuit designed to process the combined signal and output a processed signal, a comparator circuit designed to compare the processed signal with a reference signal at the sampling frequency and generate a digital M-bit comparator output signal, and a conversion circuit designed to convert the digital M-bit comparator output signal into a digital N-bit signal. In the context of an ADC that can operate as both a SAR ADC and a ΣΔ ADC, the conversion circuit may have several key components that work together to digitize an analog input signal.First, the signal processing circuitry processes the combined signal, which may be an amplified or integrated version of the input signal, depending on the specific configuration of the ADC. If the signal processing circuitry is configured as an amplifier, it can increase the signal strength, making it more suitable for comparison. If it is configured as an integrator, it can sum the signal over time, which is particularly useful for noise reduction and for ΣΔ ADCs, where integration is a crucial part of the modulation process. After the signal has been processed, it is fed into the comparator circuitry. The comparator circuitry compares the processed signal to a reference signal with a defined sampling frequency.In SAR ADC mode, the comparator circuit performs a series of comparisons to iteratively narrow the range of the input signal, generating a digital output signal bit by bit until it forms an M-bit digital comparator output signal that represents the signal with moderate resolution. After the comparison is complete, the conversion circuit further processes this M-bit digital comparator output signal to generate a higher-resolution N-bit digital signal. When operating in ΣΔ ADC mode, the conversion circuit employs oversampling and noise-shaping techniques to improve the resolution and accuracy of the final digital output. This mode involves converting the M-bit comparator signal, which already reflects the basic characteristics of the input, into a more precise N-bit digital signal that minimizes noise and improves signal fidelity.The flexibility of the signal processing circuitry, allowing it to function as either an amplifier or an integrator, enables the ADC to be adapted to different operating requirements, making it versatile for use in both SAR and ΣΔ configurations. This architecture allows for flexible signal processing and comparison, thus enabling efficient analog-to-digital conversion.

[0017] In some embodiments, the comparator circuit of the ADC circuit may include a comparator designed to generate a 1-bit output signal at each sampling time based on the processed signal and the reference signal. The comparator may be designed to generate a 1-bit output signal at each sampling time by comparing the processed signal to a reference signal. In SAR ADC mode, the 1-bit output of the comparator is used in a successive approximation process. At each step, the comparator determines whether the input signal is above or below a midpoint value provided by a digital-to-analog converter (DAC). Based on the comparator's output, the SAR logic adjusts its approximation until the digital representation of the signal is accurately determined, with each step contributing to the formation of the final digital output.In the context of a ΣΔ ADC, the comparator can also generate a 1-bit output at each sampling time, but this output serves a slightly different purpose. In ΣΔ modulation, the comparator's 1-bit output is part of a feedback loop, continuously comparing the current state of the processed signal to a reference. This comparison is used to adjust the feedback within the ΣΔ modulator, shaping the noise and improving the signal's resolution over time. The continuous stream of 1-bit outputs from the comparator can then be averaged and processed into a high-resolution digital output.

[0018] According to some embodiments, the tracking register of the ADC circuit may include an input designed to receive the estimated value and update the contents of the tracking register with the received estimated value at the modulation transition time. A tracking register is a component in an ADC circuit that stores and updates digital values ​​as the system processes signals. In the context of the ADC, the tracking register can ensure that the digital representation of the signal accurately follows, or "tracks," the variations of the analog input signal over time. The tracking register in the ADC circuit is equipped with an input specifically designed to receive an estimated value calculated by the system based on previous data or predicted signal behavior.At each modulation transition point—when the ADC switches phases or changes how it modulates the input signal—the tracking register updates its contents with this estimated value. This update is critical because modulation transitions can introduce variations or noise into the signal that must be accounted for to maintain accuracy. By updating the tracking register with the estimated value at these critical times, the ADC ensures that its internal digital representation of the signal remains accurate, effectively compensating for any shifts or offsets that may occur during the transition. This helps the ADC maintain a stable and precise output even when the modulation process introduces changes to the input signal.

[0019] According to some embodiments, the prediction circuit of the ADC circuit may include a Kalman filter designed to estimate the future value to be loaded into the tracking register by continuously updating an offset prediction based on a model of the ADC circuit's dynamics and current and previous N-bit digital signal samples. The Kalman filter provides an optimal estimation method that improves the prediction accuracy and consequently enhances the ADC's performance.

[0020] In some embodiments, the prediction circuit of the ADC circuit may include a moving-average filter designed to estimate the future value to be loaded into the tracking register by averaging a predefined number of recent N-bit digital signal samples. This simple yet effective prediction method can yield good results with minimal computational effort.

[0021] In some embodiments, the prediction circuitry of the ADC circuit can include a machine learning model trained to predict the future value to be loaded into the tracking register based on historical data and patterns identified in the digital N-bit signal. This advanced prediction method can adapt to complex signal patterns, potentially improving the ADC's performance in demanding applications.

[0022] According to some embodiments, the ADC circuit may further include a sensor designed to generate an analog sensor signal as the input signal. The sensor can be any device that detects and measures a physical phenomenon and converts it into an analog electrical signal. For example, a temperature sensor can generate an analog voltage proportional to the temperature it detects, while a pressure sensor can generate an analog current corresponding to the pressure level. In the context of magnetic field sensors, such as Hall-effect sensors or magnetoresistive sensors, the sensor can detect changes in magnetic fields and produce a corresponding analog voltage or current. This analog sensor signal is then fed into the ADC circuit, where it is converted into a digital format that can be further processed, analyzed, or used in digital systems.By directly integrating the sensor into the ADC circuit, the system can convert real analog signals into precise digital data more effectively and accurately, enabling a wide range of applications from environmental monitoring to industrial automation and beyond.

[0023] According to some embodiments, the sensor of the ADC circuit can include a rotating Hall sensor. A rotating Hall sensor operates by rapidly rotating, or "spinning," Hall sensor elements within the sensor. This rotation helps to compensate for misalignments or errors that may arise from irregularities in the sensor elements or external influences. The concept of rotation in the Hall sensor is related to the chopping technique used in the ADC circuit. Both rotation and chopping are methods designed to reduce or eliminate misalignment errors and low-frequency noise, such as 1 / f noise. In a rotating Hall sensor, the continuous rotation of the sensing elements acts similarly to chopping by modulating the signal and its associated misalignment errors. This modulation shifts the errors to higher frequencies, where they can be more easily filtered out by the ADC.Therefore, when the rotary Hall sensor is combined with an ADC circuit that uses chopping, the two techniques work together to improve the accuracy and stability of the sensor's output, thus providing a more accurate digital representation of the measured magnetic field.

[0024] In some embodiments, the modulation frequency of the ADC circuit can be lower than the sampling frequency. The modulation frequency, or chopping frequency, of the ADC circuit refers to the rate at which the input signal is modulated to help reduce noise and offset errors. The sampling frequency, on the other hand, is the rate at which the ADC samples the input signal or its derivatives to convert it from an analog to a digital form. If the modulation frequency is lower than the sampling frequency, it means that the input signal is modulated at a slower rate than it is sampled. This configuration allows the ADC to perform multiple samples of the signal during each modulation cycle, providing a more detailed digital representation of the signal within each modulation phase.A higher sampling frequency allows the ADC to capture the dynamics of the signal more effectively and improve the accuracy of the conversion, while the lower modulation frequency continues to effectively shift low-frequency noise and offsets to a higher frequency where they can be more easily filtered out.

[0025] According to another aspect of the present disclosure, an ADC method for processing an input signal is proposed. The method comprises: modulating the input signal with a modulation frequency to generate a modulated signal; combining the modulated signal with a feedback signal to generate a combined signal; converting the combined signal into a digital signal with a sampling frequency; storing and updating the digital signal in a tracking register; estimating a future value of the digital signal based on historical data from the digital signal and loading the estimated value into the tracking register at a modulation transition time; converting a digital output signal of the tracking register into the feedback signal; and demodulating the digital signal with the modulation frequency to generate a digital demodulated output signal.

[0026] According to yet another aspect of the present disclosure, an ADC circuit for converting an analog input signal into a digital output signal is proposed. The ADC circuit comprises a forward path including an analog chopper circuit designed to shift the analog input signal from an original frequency to a chopper frequency to produce a chopped analog signal; a conversion circuit designed to convert the chopped analog signal into a chopped digital signal at a sampling frequency; and a digital chopper circuit designed to shift the chopped digital signal from the chopper frequency back to the original frequency. The ADC circuit further comprises a feedback path including a digital-to-analog converter (DAC).Furthermore, the ADC circuit features a digital offset compensation circuit designed to predict an offset or signal value of the chopped digital signal based on previous sampling cycles, to generate a digital compensation signal based on the predicted offset or signal value, and to load the digital compensation signal into the feedback path at the beginning of a new chopping phase.

[0027] The ADC circuit implements a digital offset ripple loop with prediction and loading of compensation signals at the beginning of new chopping phases. This approach enables efficient handling of offset and chopping effects and potentially improves the ADC's noise reduction and signal accuracy. The combination of analog and digital chopping techniques provides effective noise suppression over a wide frequency range.

[0028] According to some embodiments, the conversion circuitry of the ADC circuit can be designed to operate as a SAR-ADC at the beginning of a chopping phase and as a ΣΔ-ADC for the remainder of the chopping phase. Loading the digital compensation signal into the feedback path allows the conversion circuitry to skip SAR operation when transitioning from one chopping phase to another. This hybrid SAR-ΣΔ approach, combined with predictive loading of compensation signals, enables fast initial conversion and high-resolution subsequent conversion while minimizing the effects of chopping phase transitions. This can lead to improved overall ADC performance, particularly in terms of conversion speed, resolution, and noise reduction.

[0029] Embodiments of the present disclosure can offer several advantages over conventional approaches. First, the proposed design can improve the noise performance of the ADC circuit by enabling continuous operation in ΣΔ mode, effectively eliminating the need for SAR conversions during chopping phase transitions. This can lead to a significant reduction in overall noise, with simulations indicating up to a 1.4-fold improvement in the signal-to-noise ratio (SNR) compared to conventional SAR tracking ΣΔ(SAT) systems.

[0030] Furthermore, the predictive nature of the digital offset ripple loop enables superior signal tracking, especially for moderately rapidly changing signals. By estimating future signal or offset values ​​based on historical data, the system can quickly adapt to changing input conditions, maintaining high accuracy even during transient periods. This feature is particularly advantageous in applications with dynamic input signals, such as magnetic field sensing or motion detection.

[0031] Furthermore, the digital implementation of the offset ripple loop can offer improved flexibility and scalability compared to analog alternatives. The ability to utilize various prediction algorithms, such as Kalman filters, moving averages, or even machine learning models, allows for customization based on specific application requirements. This adaptability enables optimized performance across a wide range of acquisition scenarios, from high-precision industrial measurements to energy-efficient consumer devices.

[0032] Embodiments of the present disclosure also address the challenges associated with duty cycle operation in pulse output sensors. By minimizing the settling time required at the beginning of each active period, this technique maximizes the effective measurement time within each cycle. This optimization contributes to an improved signal-to-noise ratio (SNR) and enables more efficient power management in battery-powered or energy-harvesting sensor systems.

[0033] Furthermore, the digital nature of the offset ripple loop allows for easier integration with modern digital signal processing techniques and microcontroller-based systems. This compatibility can improve overall system flexibility and enables future upgrades or modifications through firmware updates, thus providing a future-proof solution for evolving acquisition applications. Brief description of the characters

[0034] Some examples of facilities and / or procedures are described below only as examples and with reference to the accompanying drawings, in which the following applies: Fig. Figure 1 shows a schematic block diagram of a sensor system that includes a chopping ADC circuit; Fig. Figure 2 shows a block diagram of an embodiment of the proposed ADC circuit; and Fig. Figure 3 shows an exemplary time sequence of measurement channels and chopping phases and the transition between SAR and ΣΔ modes for the proposed ADC circuit. Detailed description

[0035] Some examples are now described in more detail with reference to the accompanying figures. However, other possible examples are not limited to the features of these embodiments described in detail. Other examples may include modifications of the features as well as equivalents and alternatives to the features. Furthermore, the terminology used here to describe certain examples should not limit other possible examples.

[0036] In the description of the figures, the same or similar reference symbols refer to the same or similar elements and / or features, which may be identical or implemented in a modified form while providing the same or a similar function. The thickness of lines, layers, and / or surfaces in the figures may also be exaggerated for clarity.

[0037] When two elements A and B are combined using "or," this is to be understood as revealing all possible combinations, i.e., A alone, B alone, and A and B, unless explicitly defined otherwise in a particular case. As an alternative formulation for the same combinations, "at least one of A and B" or "A and / or B" can be used. This applies equally to combinations of more than two elements.

[0038] Whenever a singular form, such as "a", "an", "a", and "the", is used, and the use of a single element is neither explicitly nor implicitly defined as mandatory, subsequent examples may also use multiple elements to implement the same function. If functionality is subsequently described as being implemented using multiple elements, further examples may implement the same functionality using a single element or a single processing entity.It is further understood that the terms “have”, “having”, “include” and / or “comprehensive”, when used, describe the presence of the specified features, integers, steps, operations, processes, elements, components and / or a group thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or a group thereof.

[0039] Sensors often introduce errors into the analog signal they output due to intrinsic properties of the sensors themselves. For example, an offset error may be present in an analog signal output by a Hall sensor. However, modern rotary techniques can help distinguish between the error and the sensor signal, as described in more detail below. The rotary technique can transform the offset error component in the Hall sensor signal into a high-frequency error (referred to as offset ripple), while the sensor signal remains low-frequency or DC.

[0040] ADCs can include amplifiers and / or integrators, which can also introduce an offset error into the signals they process. The offset error of the amplifier or integrator can add to the offset error introduced by the Hall sensor. To compensate for the offset error of the sensor and / or the offset error of the amplifier, some ADCs include choppers. Choppers are circuits that modulate the sensor signal to a higher frequency, thereby shifting the sensor output signal into a higher frequency range (i.e., the chopper frequency f). chopThe signal frequency is shifted, while the offset error component remains in a lower frequency range, making it easier to distinguish the offset error component from the signal component. For the purposes of this description, the modulated sensor signal at the chopping frequency output by the chopper circuit is referred to as "chopped" or "at the chopping frequency" to distinguish it from sensor signals that have not been modulated or that have been remodulated to the original frequency of the sensor signal, referred to as "the original frequency".

[0041] Fig. Figure 1 illustrates a schematic block diagram of a sensor system comprising a (chopping) ADC circuit 100 for converting an analog input signal VIN (e.g., a sensor signal) with an original frequency into a digital output signal DOUT.

[0042] It can be assumed that the analog input signal VIN is band-limited, and it can be assumed that the signal bandwidth is far lower than a sampling frequency f. s of the ADC circuit 100. The analog input signal VIN can have a signal component and an offset error component, which can be introduced by a sensor (not shown) that measures a physical quantity (e.g., a Hall sensor for measuring a magnetic field). To account for the offset error component in the analog input signal VIN, the ADC circuit 100 includes a chopper circuit 110, which is coupled between an input terminal 102 for the analog input signal VIN and an input terminal of an A / D conversion circuit 120. The chopper circuit 110 can be considered external to the A / D conversion circuit 120 and includes a modulator circuit with a chopper frequency f. chopThe A / D conversion circuit 120 can include an internal analog or digital demodulator circuit (not shown), which is also clocked at the chopping frequency f. chop is clocked. The chopping frequency f chop can be lower than the sampling frequency f s The ADC circuit should be 100. A chopping clock signal with chopping frequency f chop can be generated by means of a timing circuit 130 from a sampling clock signal with sampling frequency f s can be derived. The timing circuit 130 can be designed to perform a frequency division of the sampling frequency f. s to perform the chopping clock signal with the chopping frequency f chopto obtain. This can be achieved, for example, via a counter that triggers a state transition (from low to high or from high to low) of the chopping clock signal after j sampling clock pulses. The chopper or modulator circuit 110 is designed to convert the analog input signal VIN from its original frequency (which can be DC) to the chopper frequency f. chop to shift in order to generate a chopped analog signal 112 at the input of the A / D conversion circuit 120.

[0043] The in Fig. The general ADC circuit 100 described in Section 1 effectively uses a chopper circuit to modulate the analog input signal and shift its frequency to attenuate offset errors introduced by the sensor and / or the ADC itself. Despite any analog or digital demodulation provided within the A / D conversion circuit 120, the digital conversion process would not be able to follow the (signal and offset) transitions caused by modulation in tracking mode and / or ΣΔ mode. Only the SAR mode could follow these transitions, but at the cost of reduced effective measurement time within each cycle. To address this problem and further reduce the remaining offset ripple, a more technically sophisticated ADC circuit is proposed that includes additional features such as tracking and prediction circuits.These improvements aim to dynamically anticipate and correct offset ripple, thereby significantly improving the overall accuracy and stability of the digital output signal.

[0044] A block diagram of an embodiment of the proposed ADC circuit 200 is shown in Fig. 2 shown. The expert, benefiting from the present disclosure, understands that alternative implementations are also conceivable.

[0045] Fig. Figure 2 shows a sensor 202 that measures a physical quantity (e.g., a Hall sensor for measuring a magnetic field). The sensor 202 provides an analog sensor signal. The analog sensor signal can include a sensor signal component as well as an offset signal component. The analog sensor signal serves as the input signal to the analog chopper circuit 210, which operates at the chopping frequency f. chopThe analog chopper circuit 210 is designed to pulse the analog sensor signal at the chopper frequency f. chop to modulate in order to generate an analog chopped sensor signal. The analog chopper circuit 210 can include a set of analog switches or transistors that are used to periodically invert or modulate the analog sensor signal. These switches are controlled by a clock signal that corresponds to the chopping frequency f. chop is operated. When the switches are in one state, the analog sensor signal from sensor 202 can be passed through normally. When the switches change to the opposite state, the signal is inverted. This periodic switching effectively modulates the sensor signal by multiplying it with a square wave, which is multiplied by f. chop oscillates.

[0046] The analog chopped sensor signal can be supplied to an input stage 204, such as an amplifier stage. Amplifiers, such as input stage 204, may exhibit an inherent offset voltage, which is a small DC voltage present at the amplifier output even when the input is zero. This offset voltage may result from mismatches in transistors or other components within the amplifier's internal circuitry. It can arise due to manufacturing variations, differences in transistor threshold voltages, and other inaccuracies in the amplifier design. The offset introduced by the amplifier adds to any offset in the chopped sensor signal, potentially resulting in a cumulative offset error.This cumulative offset can reduce the accuracy of a final digital signal output by the ADC, as it can cause a shift in the signal's baseline, leading to a misinterpretation of the sensor data. Although the chopper circuit 210 initially helps to modulate the offset to higher frequencies, the inherent offset of the input stage 204 can reintroduce a low-frequency offset component, which could manifest as offset ripple in the processed signal.

[0047] Downstream of the input stage 204, the ADC circuit 200 further comprises a conversion circuit 220, which is designed to convert the combined signal from the combination circuit 206 with the sampling frequency f sto convert into a digital signal. The conversion circuit 220, which follows the input stage 204, is responsible for converting the combined analog signal into a digital signal with the sampling frequency f. sThe conversion circuit 220 comprises a combination circuit 206, which is designed to receive the analog chopped sensor signal from the input stage 204 and combine it with a feedback signal 208 to generate a combined signal. In the illustrated example, the combination circuit 206 is designed to determine a difference between the analog chopped sensor signal from the input stage 204 and the feedback signal 208. By determining the difference between the analog chopped sensor signal and the feedback signal, the combination circuit 206 can cancel or at least reduce any remaining offset or noise that may have been introduced during various signal processing stages. The generation of the feedback signal 208 is explained in more detail below.

[0048] One possible implementation of the conversion circuit 220 is as a conventional SAR-ADC. In this setup, the SAR-ADC can operate by iteratively comparing the analog input signal with reference voltages, thereby narrowing down the value of the signal in a stepwise binary search process until a precise digital representation is obtained. Another implementation of the conversion circuit 220 could involve a ΣΔ-ADC. In this case, the circuit can oversample the combined signal at a rate much higher than the Nyquist frequency and use noise shaping to shift quantization noise to higher frequencies, which are then filtered out. This can result in a high-resolution digital signal that accurately reflects the input signal, particularly in applications requiring low noise and high precision. Another implementation, which is described in Fig. As illustrated in Figure 2, successive approximation tracking (SAT) can be incorporated, combining elements of both SAR and ΣΔ techniques. In SAT, the conversion circuit 220 initially uses a SAR approach to quickly approximate the analog input signal, providing a coarse digital output. Subsequently, a ΣΔ modulator can refine the digital signal by tracking the signal more accurately over time, further reducing noise and improving resolution. Thus, the conversion circuit 220 can be designed to operate as a SAR ADC during a first operating mode and as a ΣΔ ADC during a second operating mode. This dual-mode operation can utilize the speed of SAR for the initial approximation and the precision of ΣΔ for fine-tuning, making it particularly useful in applications where both speed and accuracy are essential.

[0049] As in the example of Fig. As shown in Figure 2, the conversion circuit 220 can include a signal processing circuit 222 designed to process the (analog) combined signal from the combination circuit 206 and output a processed signal. Downstream of the signal processing circuit 222, the conversion circuit 220 can include a comparator circuit 224 designed to compare the processed signal from the signal processing circuit 222 with a reference signal having a sampling frequency f. s to compare and generate a digital M-bit comparison output signal. Downstream of the comparison circuit 224, the conversion circuit 220 can include a conversion circuit / logic 226 designed to convert the digital M-bit comparison output signal into a digital N-bit signal, where N can be greater than M.

[0050] Depending on the implementation of the conversion circuit 220, the signal processing circuit can include an integrator and / or an amplifier. For SAT, the signal processing circuit 222 can be configured as an amplifier during the first operating mode (SAR mode) and as an integrator during the second operating mode (ΣΔ mode).

[0051] The conversion circuit 220 in the ADC circuit 200 transforms the combined analog signal from the combination circuit 206 into a digital signal. This process can begin with the signal processing circuit 222, which can be used to prepare the (analog) combined signal for digitization. Depending on the configuration, the signal processing circuit 222 can function as an integrator, an amplifier, or both. When configured as an amplifier, the signal processing circuit 222 increases the signal strength, making it more suitable for comparison. Conversely, when configured as an integrator, the signal processing circuit 222 sums the signal over time, which is particularly useful for ΣΔ ADCs where integration is crucial for accurate signal representation. Downstream of the signal processing circuit 222, the processed analog signal is fed into the comparator circuit 224.The comparator circuit 224 operates by comparing the processed signal with a reference signal at each sampling time, determined by the sampling frequency f. s This comparison yields a digital output, which in one implementation consists of an M-bit word. Specifically, M can be 1. After the comparison, the M-bit digital output is passed to another component within the conversion circuit 220, referred to as the conversion circuit or logic 226. This component further processes the M-bit signal and refines it into an N-bit digital signal. The N-bit signal represents a final, high-resolution digital output that mirrors the original analog input.

[0052] In a system employing SAT, the signal processing circuit 222 is dynamically designed to optimize the conversion process depending on the operating mode. During the first operating mode, also known as SAR mode, the signal processing circuit 222 acts as an amplifier. This mode allows the system to rapidly approximate the signal by iteratively refining the output through successive comparisons. Once this coarse approximation is complete, the system can transition to the second operating mode, also known as ΣΔ mode. In this mode, the signal processing circuit 222 switches to the function of an integrator. This change allows the circuit to more accurately accumulate and refine the signal, taking advantage of the noise-shaping benefits of ΣΔ modulation to achieve higher resolution in the final digital output.The dual functionality of the signal processing circuit, combined with the capabilities of the comparison and conversion circuits, ensures that the ADC circuit 200 can adapt to different requirements in terms of speed and precision, thus providing a versatile and accurate solution for analog-to-digital conversion.

[0053] Downstream of the conversion circuit / logic 226, the conversion circuit 220 includes a tracking register 230 designed to store and update the digital signal from the conversion circuit 220. The tracking register 230 is a digital component that can be used to store and continuously update a digital representation of the processed signal. It can act as a memory element that stores the current value of the digital signal and updates it as new data becomes available from the conversion circuit 220. The tracking register 230 can track changes in the signal over time, enabling the system to predict and correct any variations, such as offset errors or noise, that could affect the accuracy of the final output.In operation, the tracking register 230 can function by receiving the digital signal from the conversion circuit 220, which could be the result of a SAR ADC, a ΣΔ ADC, or, in the case of SAT, a combination of both. Each time the conversion circuit 220 generates a new digital value, the tracking register 230 can update its contents with this value. This continuous updating ensures that the tracking register 230 always contains the most current and accurate digital representation of the input signal.

[0054] The proposed ADC circuit 200 further includes a prediction circuit 240, which is designed to estimate a future value of the digital signal based on historical data from the digital signal and to load the estimated value into the tracking register 230 at a chopping transition time. The prediction circuit 240 in the proposed ADC circuit 200 is designed to anticipate or estimate the future value of the digital signal based on current and historical data, thereby ensuring that the ADC system remains accurate and responsive to changes in the signal. The prediction circuit 240 can help maintain signal integrity, particularly during chopping transition times, when the analog input signal might experience sudden shifts due to the modulation / chopping process.Examples of the prediction circuit 240 exhibit several types of digital signal processing techniques. One example is a Kalman filter, which uses a mathematical model of the ADC circuit 200 to predict future values ​​by continuously updating its estimates based on past and current measurements. Another example is a moving average filter, which calculates the average of recent signal values ​​to smooth out short-term fluctuations and provide a stable estimate for the next value. A further example could be a machine learning algorithm, such as a neural network, trained to recognize patterns in the signal data and predict future values ​​based on those patterns.The predictive circuit 240 can estimate the future or next value of the digital signal by analyzing historical data from the digital signal stored in the tracking register 230 or other memory components. By detecting trends or patterns in the previous values, the predictive circuit 240 can predict what the signal is likely to be at the next chopping transition. This predictive approach helps the ADC system adapt to any expected changes in the signal (at chopping transitions), thereby reducing the impact of noise or offset errors that could otherwise distort the output. The estimated value can be loaded into the tracking register 230 at a specific chopping transition time, as this is a critical time when the signal might be most susceptible to changes.During a chopping transition, the ADC circuit 200 changes the phase or modulation of the input signal, which can introduce transient effects or shifts in the signal's baseline. Loading the estimated value into the tracking register at this point ensures that the register stores the most accurate possible representation of the signal, thus compensating for sudden changes caused by the chopping process.

[0055] The estimated value loaded into the tracking register during chopping transitions is actually an estimate of the signal (and often the offset) expected during the upcoming chopping phase. As the ADC circuit 200 transitions from one chopping phase to the next, the signal characteristics may change, particularly since the chopping process modulates the signal and effectively reverses its polarity. To prepare for these changes and ensure that the tracking register 230 starts with the most accurate value possible, the system calculates an estimate of what the signal and offset will be in the next phase. Shortly before the new chopping phase begins, this calculated estimate is loaded into the tracking register 230.This allows the system to ensure that the tracking register 230 is initialized at the start of the next chopping phase with a value closely matching the expected signal. The estimation takes into account historical data from previous phases as well as any known patterns or expected changes in the signal and offset. By anticipating what the signal will look like in the next chopping phase, the conversion circuit 220 can continue to accurately track and process the signal without being distracted by the phase transition.

[0056] The conversion circuit 220 also includes a feedback circuit 250, which is designed to convert a digital output signal of the tracking register 230 into the feedback signal 208 that is provided to the combination circuit 206. As shown in Fig. As shown in Figure 2, the feedback circuit 250 can include a digital-to-analog converter (DAC) for converting the digital output signal of the tracking register 230 into the feedback signal 208. The DAC 250 can be operated at the sampling frequency f sThe feedback circuit 250 can continuously convert the digital output signal from the tracking register 230 back into an analog signal, i.e., the feedback signal 208. This (analog) feedback signal 208 is then provided to the combination circuit 206, where it is used to dynamically adjust the input to the conversion circuit 220. In particular, the feedback circuit 250 can include a DAC responsible for this conversion process. The DAC takes the digital signal stored in the tracking register 230—which represents the most recent, most accurate digital representation of the sensor signal—and transforms it into an analog signal that can be used to fine-tune the ongoing ADC process. The DAC is typically operated at the sampling frequency f sclocked, ensuring that the feedback signal is updated synchronously with the sampling rate of the ADC, thus maintaining the accuracy and responsiveness of the system.

[0057] There may be alternative implementations for the feedback circuit 250 beyond the DAC approach. For example, the feedback signal 208 could be generated using a digitally controlled variable resistor or a digitally controlled current source, which adjusts the analog signal based on the digital output without a complete conversion back to an analog form. Another alternative could involve the use of a pulse-width modulation (PWM) circuit, where the digital signal modulates the width of a series of pulses, which are then averaged to generate the feedback signal. These alternative methods may be used in certain applications where power consumption, cost, or the need for ultra-fast response times are critical factors.

[0058] Furthermore, the ADC circuit includes 200 demodulation circuitry / logic 260, which is designed to process the digital signal at the chopping frequency f. chop to demodulate in order to generate a digital demodulated output signal. The demodulation circuit / logic 260 can also include one or more digital filters, such as notch filters. The demodulation circuit or logic 260 is responsible for converting the modulated (chopped) digital signal back to its original frequency after processing the signal through the chopping process. Chopping is used to shift the signal to a higher frequency where noise and offsets can be managed more effectively. However, to obtain a usable final output, the signal must be demodulated back to its fundamental frequency, which is the role of the demodulation circuit or logic 260. This circuit operates at the chopping frequency f chopThis ensures that the digital signal is accurately reverse-shifted, eliminating modulation effects and restoring the signal to a form representing the original sensor input. In addition to demodulation, the demodulation circuitry or logic may include 260 digital filters, such as notch filters. These filters can be specifically designed to target and remove any residual noise or specific unwanted frequency components, such as offset ripple, that remain after demodulation. Notch filters, for example, can be useful for eliminating narrow frequency bands containing interference or noise, ensuring that the final digital output signal is clean and accurate.By integrating such filters, the demodulation circuit 260 can not only restore the signal to its original frequency, but also improve its quality by reducing noise and ripple, resulting in a more precise and reliable digital demodulated output signal.

[0059] The ADC 200 circuit is designed to improve the accuracy and stability of signal conversion by addressing offset ripple and reducing low-frequency noise. The ADC 200 implements a digital offset ripple loop that predicts or estimates the offset (or signal) and loads the corresponding value at the start of each new rotation or chopping phase. This predictive capability can help maintain a consistent signal output by compensating for any expected changes in offset, particularly during transitions between different operating phases. A key aspect of the proposed concept is its approach to phase transitions. The SAR portion of the conversion process can be skipped when switching from one chopping phase to another.This strategy can be used to minimize errors and disturbances that might occur during these transitions, which are times when the signal could be particularly susceptible to changes or noise. By focusing on high-frequency chopping, the system is able to retain these advantages while simultaneously reducing low 1 / f noise, a type of noise that typically affects the lowest frequencies and can degrade signal quality.

[0060] The ADC 200 circuit can only use the chopping sigma-delta (ΣΔ) mode after startup. During startup, the system can use various modes to quickly stabilize the signal, but once stabilized, it can exclusively use the chopping ΣΔ mode to maintain high accuracy and minimize noise.

[0061] Fig. Figure 3 presents an exemplary temporal sequence of different measurement channels (CH X, CH Y, CH Z, CH T), chopping phases (PH1-PH4) within each measurement channel and the transition between SAR and ΣΔ modes.

[0062] The channels CH X, CH Y, CH Z and CH T can, for example, correspond to the measurement of X, Y, Z components of a magnetic field as well as a temperature value. Fig. Figure 3 shows several operating periods, beginning with a sleep mode in which the system is inactive to conserve power, followed by a bias settling period. This bias settling period allows the system to stabilize after waking from sleep mode, ensuring that the sensor(s) and ADC are ready for accurate signal processing. After bias settling, and for each measurement channel, the system enters several initial SAR chopping phases (SAR PH1 - SAR PH4) in which the conversion circuit 220 operates in SAR ADC mode. During these initial chopping phases, the system performs successive approximation to quickly approximate the sensor signal. The SAR mode involves adaptive tracking, starting with a large step size for the most significant bit (MSB) and gradually narrowing down to the least significant bit (LSB) for fine resolution.This approach allows for a fast initial approximation of the signal, which is then further refined.

[0063] After the initial SAR chopping phases, the system transitions to subsequent ΣΔ chopping phases (SD PH1 - SD PH4). Here, the conversion circuit 220 switches to ΣΔ ADC mode and remains in this mode. During these ΣΔ chopping phases, the signal is tracked with high accuracy using ΣΔ modulation, which is known for its noise-shaping capabilities and high resolution. The ΣΔ chopping phases are used to further refine the signal, reducing any noise and offset errors that may have persisted after the initial SAR phases. Fig. Section 3 indicates that during these ΣΔ chopping phases, the system can perform several cycles, depending on the requirements for average power consumption and noise reduction, to further reduce noise. The ΣΔ ADC may be particularly effective at suppressing flicker noise (low-frequency noise).

[0064] Fig.Figure 3 also shows that estimates of the moving average of the (digital) signal and the offset can be loaded into the tracking register 230 at chopping transition times between adjacent ΣΔ chopping phases. As the system progresses from one ΣΔ chopping phase to the next, there are transition times at which the signal processing might be susceptible to sudden changes or noise, which could affect the accuracy of the output. To mitigate this, estimates of the moving average of the digital signal, which may have been calculated by the prediction circuit 240 during the preceding chopping phase, are loaded into the tracking register 230 at these transition times and fed back to the combination circuit 206.This ensures that the tracking register 230 stores a stable and accurate estimate of the signal and offset as it enters the next chopping phase. Loading these averaged estimates into the tracking register 230 at the precise moment of transition between adjacent ΣΔ chopping phases helps the system "lock" a reliable value, thus preventing the introduction of errors that could arise from abrupt changes or disturbances during the transition.

[0065] The ADC 200 circuit can effectively handle quasi-constant signals and offsets while minimizing noise and instability, particularly during chopping phase transitions. To address these challenges, two exemplary approaches are described. Each approach offers unique strategies for tracking the signal and offset, as well as for attenuating quantization noise and potential oscillations during critical transitions between chopping phases.

[0066] Assume two chopping phases in which the sensor signal and the offset are nearly constant (quasi-constant), allowing the ADC circuit 200 to efficiently predict and correct these values. The system operates in two chopping phases, with the sensor signal being modulated (chopped) between a positive and a negative chopping phase. During these chopping phases, the tracking register 230 can store a value that includes both the signal and the offset. An exemplary implementation might focus on estimating the signal using a moving average from previous phases, which can then be used to correct the tracked value. This approach might involve calculating a mirrored track value that remains positive, helping to minimize quantization noise and maintain stability, particularly during phase transitions.In another implementation, the system can instead estimate the offset by using a moving average of the offset from previous phases. The tracked value can be mirrored around a midpoint and fitted using the offset estimate, resulting in an inverted sign compared to the first method. This approach can be more effective at handling rapid signal changes, making it suitable for less stable signals; however, it can introduce more noise and potential instability during transitions between chopping phases. Both approaches aim to prevent interference with the analog integrator by minimizing the use of chopping during integration, although the second method may require additional steps to manage instabilities during phase transitions.

[0067] Embodiments of the present disclosure relate to an enhanced analog-to-digital converter (ADC) circuit that integrates a digital offset ripple loop to improve signal processing accuracy, particularly in systems that employ chopping techniques to manage offset errors and noise. The core of the circuit is a digital offset ripple loop that predicts and corrects offset during the signal conversion process, thereby improving the overall signal-to-noise ratio (SNR) and reducing low-frequency noise.

[0068] The proposed ADC circuit features several key components: a modulation circuit that modulates the input signal to a higher frequency, a combination circuit that combines the modulated signal with a feedback signal, and a conversion circuit that digitizes the combined signal. The system also includes a tracking register that stores and updates the digital signal, along with a prediction circuit that provides estimates of the digital signal based on historical data. This prediction supports dynamic correction of the signal at critical times, such as during chopping phase transitions.The feedback circuit converts the digital signal back into an analog feedback signal, which is used to further refine the input signal, and the demodulation circuit restores the signal to its original frequency, ensuring that the final digital output is accurate and noise-free.

[0069] One aspect of embodiments of the present disclosure is the ability to handle offset errors and low-frequency noise through a combination of SAR and ΣΔ-ADC techniques together with a predictive digital loop. This approach allows the ADC to skip SAR operation during phase transitions, thereby reducing noise and improving accuracy, making it particularly useful for high-precision applications such as magnetic field measurement with Hall sensors.

[0070] The aspects and features described in relation to a particular of the preceding examples can also be combined with one or more of the further examples to replace an identical or similar feature of that further example or to additionally introduce the features into the further example.

[0071] Examples may also include or refer to a (computer) program that contains program code for executing one or more of the above procedures, when the program is executed on a computer, processor, or other programmable hardware component. Thus, steps, operations, or processes of various procedures described above can also be executed by programmed computers, processors, or other programmable hardware components. Examples may also include program storage devices, such as digital data storage media that are machine-, processor-, or computer-readable and that encode and / or contain machine-executable, processor-executable, or computer-executable programs and instructions.Program storage devices can be, for example, digital storage devices, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media. Other examples include computers, processors, control units, (field)programmable logic arrays ((F)PLAs), (field)programmable gate arrays ((F)PGAs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), integrated circuits (ICs), or system-on-a-chip (SoC) systems programmed to perform the steps of the procedures described above.

[0072] It is further understood that the disclosure of several steps, processes, operations, or functions disclosed in the description or in the claims is not to be interpreted as meaning that these operations are necessarily dependent on the described sequence, unless expressly stated in a specific case or required for technical reasons. Therefore, the preceding description does not restrict the execution of several steps or functions to a specific sequence. Furthermore, in other examples, a single step, function, process, or operation may have and / or be subdivided into several substeps, functions, processes, or operations.

[0073] When certain aspects relating to a device or system are described, these aspects should also be understood as a description of the corresponding procedure. For example, a block, device, or functional aspect of the device or system may correspond to a feature, such as a process step, of the corresponding procedure. Accordingly, aspects described in relation to a procedure should also be understood as a description of a corresponding block, element, property, or functional feature of a corresponding device or system.

[0074] The following claims are hereby included in the detailed description, each claim being able to stand alone as a separate example. It should also be noted that while a dependent claim in the claims refers to a specific combination with one or more other claims, other examples may also include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby expressly suggested unless it is determined in a specific case that a particular combination is not intended. Furthermore, features of a claim should also be included for any other independent claim, even if that claim is not directly defined as dependent on that other independent claim.

Claims

[1] Analog-to-digital converter or ADC circuit (200) designed to process an input signal, wherein the ADC circuit (200) comprises: a modulation circuit (210) designed to modulate the input signal with a modulation frequency in order to produce a modulated signal; a combination circuit (206) designed to receive the modulated signal and combine it with a feedback signal (208) to produce a combined signal; a conversion circuit (220) designed to convert the combined signal into a digital signal at a sampling frequency; a tracking register (230) designed to store and update the digital signal; a prediction circuit (240) designed to estimate a future value of the digital signal based on historical data from the digital signal and to load the estimated value into the tracking register (230) at a modulation transition time; a feedback circuit (250) designed to convert a digital output signal of the tracking register into the feedback signal provided to the combination circuit; and a demodulation circuit (260) designed to demodulate the digital signal at the modulation frequency to produce a digital demodulated output signal. [2] ADC circuit (200) according to claim 1, wherein the modulation circuit (210) comprises an analog chopper circuit designed to modulate the input signal with a chopper frequency in order to generate an analog chopped signal as the modulated signal. [3] ADC circuit (200) according to one of the preceding claims, wherein the combination circuit (206) is designed to determine a difference between the modulated signal and the feedback signal. [4] ADC circuit (200) according to one of the preceding claims, wherein the conversion circuit (220) is designed to operate as a successive approximation register ADC during a first operating mode and as a sigma-delta ADC during a second operating mode. [5] ADC circuit (200) according to claim 4, wherein the first operating mode is an initial operating mode after the initial startup of the ADC circuit (200) and the second operating mode is a subsequent operating mode after the initial operating mode. [6] ADC circuit (200) according to any of the preceding claims, wherein the conversion circuit (220) comprises: a signal processing circuit (222) designed to process the combined signal and output a processed signal; a comparator circuit (224) designed to compare the processed signal with a reference signal at the sampling frequency and to generate a digital M-bit comparator output signal; and a conversion circuit (226) designed to convert the digital M-bit comparison output signal into a digital N-bit signal. [7] ADC circuit (200) according to claim 6, wherein the signal processing circuit (222) comprises an integrator and / or an amplifier. [8] ADC circuit (200) according to claim 7, wherein the signal processing circuit (222) is configured as an amplifier during a first operating mode and as an integrator during a second operating mode. [9] ADC circuit (200) according to any one of claims 6 to 8, wherein the comparator circuit (224) comprises a comparator designed to generate a 1-bit output signal based on the processed signal and the reference signal at each sampling time. [10] ADC circuit (200) according to one of the preceding claims, wherein the tracking register (230) comprises an input configured to receive the estimated value and to update the contents of the tracking register with the received estimated value at the modulation transition time. [11] ADC circuit (200) according to one of the preceding claims, wherein the prediction circuit (240) comprises: a Kalman filter designed to estimate the future value to be loaded into the tracking register by continuously updating an offset prediction based on a model of the dynamics of the ADC circuit as well as current and previous digital N-bit signal samples. [12] ADC circuit (200) according to one of the preceding claims, wherein the prediction circuit (240) comprises: a moving average filter designed to estimate the future value to be loaded into the tracking register by averaging a predefined number of recent N-bit digital signal samples. [13] ADC circuit (200) according to one of the preceding claims, wherein the prediction circuit (240) comprises: a machine learning model trained to predict the future value to be loaded into the tracking register based on historical data and patterns identified in the digital N-bit signal. [14] ADC circuit (200) according to any one of the preceding claims, further comprising: a sensor (202) designed to generate an analog sensor signal as the input signal. [15] ADC circuit (200) according to claim 13, wherein the sensor (202) comprises a rotary Hall sensor. [16] ADC circuit (200) according to one of the preceding claims, wherein the modulation frequency is lower than the sampling frequency. [17] ADC circuit (200) for converting an analog input signal into a digital output signal, wherein the ADC circuit comprises: a forward path that includes the following: an analog chopper circuit (210) designed to shift the analog input signal from an original frequency to a chopper frequency in order to produce a chopped analog signal; a conversion circuit (220) designed to convert the chopped analog signal into a chopped digital signal at a sampling frequency; and a digital chopper circuit (260) designed to shift the chopped digital signal from the chopper frequency to the original frequency; a feedback path comprising a digital-to-analog converter (250); and a digital offset compensation circuit (230; 240) designed to do the following: Predictions of an offset or signal value of the chopped digital signal based on previous sampling cycles; Generating a digital compensation signal based on the predicted offset or signal value; and Loading the digital compensation signal into the feedback path at the beginning of a new chopping phase. [18] ADC circuit (200) according to claim 17, wherein the conversion circuit (220) is designed to operate as a SAR-ADC at the beginning of a chopping phase and as a ΣΔ-ADC during the remainder of the chopping phase, wherein loading the digital compensation signal into the feedback path enables the conversion circuit to skip SAR operation when switching from one chopping phase to another. [19] ADC method for processing an input signal, wherein the method comprises: Modulating the input signal with a modulation frequency to create a modulated signal; Combining the modulated signal with a feedback signal to create a combined signal; Converting the combined signal into a digital signal using a sampling frequency; Storing and updating the digital signal in a tracking register; Estimating a future value of the digital signal based on historical data from the digital signal and loading the estimated value into the tracking register at a modulation transition time; Converting a digital output signal from the tracking register into the feedback signal; and Demodulating the digital signal with the modulation frequency to generate a digital demodulated output signal.

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