Method for manufacturing a semiconductor device and semiconductor device

Abstract

According to the present disclosure, a method for manufacturing a semiconductor device includes five steps. A first step is for forming a semiconductor device pattern. A second step is for grinding a peripheral portion partially in a thickness direction. A third step is for dividing the wafer in a direction perpendicular to the thickness direction at a position closer to a depth at which the peripheral portion of the wafer is ground, and for dividing a first divided wafer, which does not include the semiconductor device pattern, from the wafer. A fourth step is for grinding a peripheral portion of a divided surface of the first divided wafer.And a fifth step is provided for forming a semiconductor device structure on the divided surface of the first divided wafer, the peripheral part of the divided surface thereof being ground.

Description

Background of the inventionArea

[0001] The present disclosure relates to a method of manufacturing a semiconductor device and a semiconductor device. background

[0002] JP 2021-52178 A discloses a technique for reducing substrate costs by using a thin-cut wafer as a basis for epitaxial growth.

[0003] However, the method described above requires chamfering a wafer prior to dicing. Chamfering reduces a wafer diameter, which may prevent transportation and processing using the same equipment as used for a wafer prior to processing, or may require adapting the equipment to accommodate a change in wafer diameter. Summary

[0004] In view of the problems described above, it is an object of the present disclosure to provide a method for manufacturing a semiconductor device and a semiconductor device capable of performing transportation and processing using the same apparatus as for a wafer before processing by limiting a reduction in wafer diameter.

[0005] The features and advantages of the present disclosure can be summarized as follows.

[0006] A method for manufacturing a semiconductor device according to the present disclosure includes: a step of forming a semiconductor device pattern on a second main surface of a wafer having a first main surface and the second main surface opposite to each other; a step of grinding a peripheral part of the second main surface of the wafer, on which the semiconductor device pattern is formed, partially in a thickness direction from the second main surface toward the first main surface; a step of dividing the wafer in a direction perpendicular to the thickness direction at a position closer to the second main surface than a depth to which the peripheral part of the wafer is ground, and dividing a first divided wafer not including the semiconductor device pattern from the wafer;a step of grinding a peripheral part of a divided surface of the first divided wafer; and a step of forming a semiconductor device structure on the divided surface of the first divided wafer, the peripheral part of the divided surface thereof being ground.

[0007] Other and further objects, features and advantages of the disclosure will become more apparent from the following description. Short description of the characters Fig. 1 is a view showing a semiconductor device according to the first embodiment of the present disclosure. Fig. 2 is a view showing a grinding step according to the first embodiment of the present disclosure. Fig. 3 is a view showing a dividing step according to the first embodiment of the present disclosure. Fig. 4 is a view showing a joining step according to the first embodiment of the present disclosure. Fig. 5 is an enlarged view showing the connecting step according to the first embodiment of the present disclosure. Fig. 6 is a view showing a chamfering step according to the first embodiment of the present disclosure. Fig. 7 is a view showing a device forming step according to the first embodiment of the present disclosure. Fig. 8 is a view showing a semiconductor device according to a first comparative example. Fig. 9 is a view showing a dividing step according to the first comparative example. Fig. 10 is a view showing a chamfering step according to a second comparative example. Fig. 11 is a view showing a dividing step according to the second comparative example. Fig. 12 is a view showing a modification of the grinding step according to the first embodiment of the present disclosure. Fig. 13 is a view showing a first modification of the connecting step according to the first embodiment of the present disclosure. Fig. 14 is a view showing a second modification of the connecting step according to the first embodiment of the present disclosure. Fig. 15 is a view showing a modification of the chamfering step according to the first embodiment of the present disclosure. Fig. 16 is a view showing a thickening step according to a second embodiment of the present disclosure. Fig. 17 is a view showing a chamfering step according to the second embodiment of the present disclosure. Fig. 18 is a view showing a device forming step according to the second embodiment of the present disclosure. Fig. 19 is a view showing a modification of the chamfering step according to the second embodiment of the present disclosure. Fig. 20 is a view showing a chamfering step according to a third embodiment of the present disclosure. Fig. 21 is a view showing a device forming step according to the third embodiment of the present disclosure. Fig. 22 is a view showing a modification of the chamfering step according to the third embodiment of the present disclosure. Fig. 23 is a view showing a grinding step to be performed by an apparatus formed by attaching a grindstone to a rotary edge working machine. Fig. 24 is a view showing a kerf loss associated with the grinding step in Fig. 23. Description of EmbodimentsFirst Embodiment.[Method for processing a semiconductor device according to a first embodiment of the present disclosure]

[0008] A method for processing a semiconductor device according to a first embodiment of the present disclosure is described. Fig. 1 is a view showing a semiconductor device according to the first embodiment of the present disclosure. A semiconductor device 100 includes a wafer 12. The wafer 12 is, for example, a monocrystalline SiC wafer having a second main surface opposite a first main surface. Note that the first main surface is a wafer back surface, and the second main surface is a wafer front surface.

[0009] The wafer 12 may be formed of Si, or it may be formed of a wide-bandgap semiconductor having a wider bandgap than Si. The wide-bandgap semiconductor is, for example, a SiC- or GaN-based material, a gallium oxide-based material, or diamond. If a switching device or a diode device is formed using a wide-bandgap semiconductor, a withstand voltage and allowable current density can be increased. This enables size reduction.

[0010] One aspect of the present disclosure is cost-effectiveness, and is particularly advantageous with respect to a semiconductor device using a wafer that is not readily available. A concrete advantageous example is a case where the wafer 12 is formed of SiC. SiC wafers are harder to increase in diameter, they are more expensive, and they provide a lower yield than Si wafers due to crystal defects. That is, there is a problem in that SiC wafers are not cost-effective.

[0011] Monocrystalline SiC is generally manufactured using a sublimation process. In the sublimation process, the temperature difference within a crystal increases as the wafer diameter increases, so crystal defects increase. Therefore, there is a problem that SiC wafers suffer a reduction in the availability of substrates with fewer crystal defects as the wafer diameter increases.

[0012] The problems with SiC wafers described above can be solved simultaneously by reusing a SiC wafer with fewer crystal defects.

[0013] An epitaxial layer is formed on the second main surface of the wafer 12. A semiconductor device structure 14 is formed on the epitaxial layer. The semiconductor device structure 14 is, for example, a power device structure such as a MOSFET, a diode, or an IGBT. Forming the semiconductor device structure 14 includes ion implantation and forming a surface electrode. Note that the semiconductor device structure 14 is formed within the outermost peripheral portion of the wafer 12, which is tapered.

[0014] It should be noted that if the wafer 12 is formed from GaN, the semiconductor device structure 14 is, for example, a GaN radio frequency device structure. Alternatively, a GaN radio frequency device structure may be formed on the wafer 12 formed from SiC.

[0015] Fig. 2 is a view showing a grinding step according to the first embodiment of the present disclosure. In the grinding step of the present embodiment, a peripheral part of the second main surface of the wafer 12 is partially ground in a thickness direction from the second main surface toward the first main surface, thereby forming a wafer 16 having a convex structure in cross section. This results in formation of a semiconductor device 102 in which the semiconductor device structure 14 protrudes from the peripheral part.

[0016] The grinding step can be performed, for example, by an apparatus configured by attaching a grindstone to a rotary edge processing machine. The grindstone used is one adapted to grind a wafer into any desired shape by grinding a periphery of the wafer. The grinding step can be performed by partially cutting a periphery by a dicing apparatus.

[0017] Fig. Fig. 23 is a view showing a grinding step to be performed by an apparatus formed by attaching a grindstone to a rotary edge-finishing machine. A view on the left side of Fig. Figure 23 shows a wafer after grinding using a new grindstone immediately after replacement. A view on the right side of Fig. Figure 23 shows a wafer after grinding using a worn grindstone. Since a plurality of wafers are processed using the same grindstone, the grindstone wears out, and expected grinding cannot be performed. A wafer shape after processing corresponds to the right side in Fig. 23. In this case, the grinding step converts the corners 50 and 51 into a wafer with rounded corners 50a and 51a.

[0018] If the corner 50a has a radius of 500 μm or less, dust generation and chipping due to a knife edge (described later) can be reduced. If the corner 50a has a smaller radius, ie, a radius of 300 μm or less, dust generation or chipping can be reduced to a greater extent. If the corner 50a has a radius of 100 μm or less, dust generation or chipping due to an edge shape can be largely suppressed.

[0019] Fig. 24 is a view showing a sawing loss which affects the grinding step in Fig. 23. A view on the left in Fig. 24 shows a wafer before dividing, and a view on the right side in Fig. 24 shows a wafer after dividing. Fig. Figure 24 shows a sawing loss which is generated when the grinding step cuts the corner 51 in the view on the left side in Fig. 23 into a corner 51b with a large radius.

[0020] It should be noted that a saw loss is a so-called material loss, which refers to a portion that is removed as sections at the time of wafer cutting. Specifically, a portion corresponds to a boundary between the wafers after dividing in the view on the right in Fig. 24 with one saw loss.

[0021] If the corner 51b has a large radius as in the view on the left in Fig. 24, is a shape of an end part as in the view on the right in Fig. 24 sharp. Such a sharp shape is referred to as a knife edge. The knife edge causes chipping and dust generation.

[0022] Chipping and dust generation due to a knife edge are suppressed to a greater extent when a sawing loss at the time of dividing is larger. That is, even if the corner 51b has a large radius, concerns about chipping and dust generation are reduced. For example, if a sawing loss at the time of dividing is larger than 100 µm, a radius of 200 µm or less is tolerated. If the sawing loss is smaller than 100 µm to 80 µm, a radius of 150 µm or less is tolerated. If the sawing loss is much smaller and 60 µm or less, a radius of 100 µm or less is tolerated. Note that if one of the divided wafers is processed and reused to form a device again, a sawing loss and the radius of the corner 51b are preferably small.

[0023] Furthermore, if the angle of a step corresponds to 45 degrees to 135 degrees, dust generation or chipping due to a knife edge can be reduced. If the angle corresponds to 60 degrees or less than 120 degrees, dust generation or chipping can be reduced to a greater extent. If the angle corresponds to 75 degrees or less than 105 degrees, dust generation or chipping due to a knife edge can be largely suppressed.

[0024] It should be noted that a processing width during the grinding step is preferably small. This is because if a grinding width is large, a region with a small substrate thickness at a peripheral part of the wafer 16 is large, which is likely to cause chipping and cracking. It is known that chipping and cracking frequently occur if the grinding width is 10 mm or more. For this reason, the grinding width is preferably less than 10 mm. A narrower width, such as a width less than 5 mm, 3 mm, or 1 mm, is more preferable.

[0025] The grinding step is preferably performed only to a depth that leaves a substrate thickness of 100 µm or more. This allows for the prevention of cracks and chips occurring at an end portion of a wafer to be reused after the dividing step (described later).

[0026] Furthermore, the grinding step may be performed before forming the epitaxial layer, which is performed before forming the semiconductor device structure 14, or it may be performed after forming the epitaxial layer. The grinding step is performed outside the semiconductor device structure 14, so that no damage to the semiconductor device structure 14 occurs.

[0027] Fig. 3 is a view showing a dividing step according to the first embodiment of the present disclosure. In the dividing step of the present embodiment, the wafer 16 is divided in a direction perpendicular to the thickness direction at a position closer to the second main surface than a depth to which the peripheral part in the wafer 12 is ground. By this division, the semiconductor device 102 is divided into a divided wafer 18 including the semiconductor device pattern 14 and a divided wafer 20 not including the semiconductor device pattern 14. That is, the divided wafer 20 not including the semiconductor device pattern 14 is divided from the wafer 16.

[0028] At this time, a peripheral part of the divided wafer 18 does not become a knife edge. This is because an outermost peripheral part which may become a knife edge can be eliminated in advance by Fig. 2 is performed. This results in progressing a process for manufacturing a semiconductor device without dust generation or chipping in the divided wafer 18.

[0029] Moreover, a wafer diameter of the divided wafer 20 is the same as a wafer diameter of the original wafer 12. This is because the grinding step of the present embodiment does not remove an outermost peripheral part, unlike a chamfering step (which will be described later with reference to Fig. 10). That is, limiting a reduction in wafer diameter enables transportation and processing using the same equipment as for a wafer before processing.

[0030] Note that a method for dividing the wafer may be a method involving contact with a dicing saw or the like, or a non-contact method using a laser or the like. For example, a laser cutting technique may be used that forms a modification layer with a laser and performs division in a direction perpendicular to a direction from the first main surface toward a second main surface.

[0031] A substrate thickness of the divided wafer 20 is preferably 100 µm or more. This is because if the substrate thickness of the divided wafer 20 is small, breakage in subsequent steps in the Fig. 4 to 7 may occur or transport and processing may become difficult due to severe distortion.

[0032] Fig. 4 is a view showing a bonding step according to the first embodiment of the present disclosure. In the bonding step of the present embodiment, another divided wafer 20 is bonded to a first main surface of the divided wafer 20. This results in formation of a bonded wafer 21 having the same wafer diameter as the original wafer 12. By bonding a plurality of divided wafers 20 as described above to increase a substrate thickness, warpage of the wafer can be suppressed to a greater extent than in a case where the divided wafer 20 is used individually.

[0033] Fig. 5 is an enlarged view showing the bonding step according to the first embodiment of the present disclosure. The bonding step of the present embodiment can be performed, for example, using a technique based on room temperature bonding. At this time, an amorphous layer 24 is formed at bonding interfaces of the bonded wafer 21.

[0034] Room temperature bonding is a bonding method capable of obtaining a clean interface because a metal layer and the like are not included in a bonding interface. Adhesive force at the time of bonding can be increased by performing a planarization step of planarizing at least one of the bonding interfaces by polishing before the bonding step. Note that planarization may be performed by CMP or the like instead of polishing.

[0035] Fig. 6 is a view showing a chamfering step according to the first embodiment of the present disclosure. In the chamfering step of the present embodiment, a peripheral part on a second main surface side of the bonded wafer 21 is ground into a tapered shape. That is, a peripheral part of a divided surface of the divided wafer 20 on the second main surface side is ground into a tapered shape. This results in formation of a bonded wafer 23 in which a divided wafer 30 whose peripheral part on a second main surface side is processed into a tapered shape and the unprocessed divided wafer 20 are bonded to each other. Since this step can bring a shape of the bonded wafer 21 close to a shape of the original wafer 12, fine-tuning for wafer alignment is unnecessary.

[0036] Fine-tuning for wafer alignment is described in detail. In wafer alignment, a location where the light transmittance is equal to or less than a threshold value when a laser light is scanned across a wafer is detected as an end portion of the wafer. If an end portion of a wafer is machined into a tapered shape, the end portion of the wafer is easily detected because the surface roughness of the tapered portion makes it unlikely that light will pass through.

[0037] For example, if a wafer is ground so that its cross section has a convex structure, an end portion of the wafer is thinner than a middle portion of the wafer. In this case, a light transmittance level at the end portion of the wafer may not be equal to or lower than the threshold, and the end portion of the wafer may not be detected.

[0038] For the reason described above, if the wafer is processed by the same apparatus as a general wafer, it is necessary to adjust the light transmittance threshold as needed or set a new threshold that allows detection of end portions of both wafers. That is, in either case, fine-tuning is required for wafer alignment. In the chamfering step of the present embodiment, the peripheral portion on the second main surface side of the bonded wafer 21 is ground into a tapered shape. This chamfering step has the advantage that fine-tuning is unnecessary.

[0039] The bonded wafer 23 can be processed to have a desired substrate thickness as a whole, for example, by grinding, polishing, CMP, or the like. The desired substrate thickness can be, for example, the same substrate thickness as the wafer 12. By means of this configuration, at the time of reusing the bonded wafer 23 as a wafer, it is possible to perform transportation and processing using the same equipment as for a wafer before processing, without performing adjustment involved in a difference in substrate thickness.

[0040] Fig. 7 is a view showing a device formation step according to the first embodiment of the present disclosure. In the device formation step of the present embodiment, an epitaxial layer is formed on a second main surface side of the bonded wafer 23, and the semiconductor device structure 14 is formed on the epitaxial layer. That is, the semiconductor device structure 14 is formed on a divided surface of the divided wafer 30. Note that the semiconductor device structure 14 is formed within an outermost peripheral part of the divided wafer 30, which is tapered.

[0041] A semiconductor device 108 obtained in the manner described above has a similar function to the semiconductor device 100. For this reason, the semiconductor device 108 can successively Fig. 2 to 7, such as the semiconductor device 100.

[0042] As described above, the Fig. The steps described in Figures 2 to 7 allow a reduction in the wafer diameter of a semiconductor device. This enables transport and processing using the same equipment as for a wafer before processing. [Method for processing a semiconductor device according to a comparative example]

[0043] In order to describe effects of a semiconductor device according to the present disclosure, a method of processing a semiconductor device according to a comparative example will be described. Fig. 8 is a view showing a semiconductor device according to a first comparative example. A semiconductor device 500 includes a wafer 502 and a semiconductor device structure 504, and has a configuration similar to that of the semiconductor device 100.

[0044] Fig. 9 is a view showing a dividing step according to the first comparative example. In the dividing step according to the first comparative example, the wafer 502 is divided in a direction perpendicular to a thickness direction. By this division, the semiconductor device 500 is divided into a divided wafer 506 including the semiconductor device pattern 504 and a divided wafer 508 not including the semiconductor device pattern 504.

[0045] At this time, a peripheral part of the divided wafer 506 becomes a thin and sharp knife edge. If a process for manufacturing a semiconductor device using a wafer whose peripheral part is a knife edge has progressed, a carrier that supports wafers may be scraped off, causing dust or chipping. For this reason, to perform a wafer dividing step, processing that prevents a peripheral part from becoming a knife edge is necessary.

[0046] Fig. 10 is a view showing a chamfering step according to a second comparative example. In the second comparative example, the chamfering step is performed on a semiconductor device 500 having a configuration similar to that in the first comparative example before a dividing step.

[0047] In the chamfering step according to the second comparative example, a peripheral part of a wafer 502 is ground such that the peripheral part is penetrated in a thickness direction. That is, an outermost peripheral part of the wafer 502 is removed. This results in the production of a divided wafer 510 having a semiconductor device structure 504 and a peripheral part 512 of the wafer that does not include the semiconductor device structure 504.

[0048] Fig. 11 is a view showing a dividing step according to the second comparative example. In the dividing step according to the second comparative example, the divided wafer 510 is divided in a direction perpendicular to the thickness direction. By this division, the divided wafer 510 is divided into a divided wafer 514 including the semiconductor device structure 504 and a divided wafer 516 not including the semiconductor device structure 504.

[0049] At this time, a peripheral part of the divided wafer 514 does not become a knife edge. This is because an outermost peripheral part which may become a knife edge is eliminated in advance by Fig. 10 is performed. This results in progressing a process for manufacturing a semiconductor device without dust generation or chipping in the divided wafer 514.

[0050] A wafer diameter of the divided wafer 516 is smaller than a wafer diameter of the original wafer 502. This is because the outermost peripheral part is removed by performing the chamfering step, which is Fig. 10. This results in preventing transportation and processing using the same equipment as for a wafer before processing at the time of reuse of the divided wafer 516, or creates the need for an equipment adjustment so that the equipment can handle a change in wafer diameter. The present disclosure can solve this problem. [Method of processing a semiconductor device according to a modification of the first embodiment of the present disclosure]

[0051] Hereinafter, processing methods according to modifications of the present embodiment are illustrated. Fig. 12 is a view showing a modification of the grinding step according to the first embodiment of the present disclosure. A grinding step of the modification differs from the grinding step in Fig. 2 in that the grinding step further includes a step of grinding the entirety of a peripheral part of a wafer.

[0052] An upper view in Fig. 12 is a view showing the semiconductor device 100 before the grinding step. A bottom view in Fig. 12 is a view showing a semiconductor device 102a after the grinding step. The grinding step of the modification includes a process of grinding the entire outermost peripheral part of a wafer in addition to the grinding step of the first embodiment. For this reason, a wafer diameter of a wafer 16a after the grinding step is smaller than the wafer diameter of wafer 12.

[0053] Since an end portion of the back surface of the wafer 16 is chamfered, a substrate thickness decreases toward the end portion. This may result in cracking and chipping at the end portion on the back surface of the wafer 16. The grinding step of the modification has the effect of suppressing cracking and chipping at the end portion by grinding a peripheral portion on the back surface of the wafer 16a.

[0054] It should be noted that during the grinding step of modification, it is preferable that a width for grinding the entire outermost peripheral part of a wafer, that is, a reduction in terms of wafer diameter, be small. This is because if a processing width is large, a wafer diameter of a wafer to be reused in the future will be small, which may hinder transportation and processing at the time of forming a device structure.

[0055] If a reduction in wafer diameter is less than 1 mm, the reduction can be handled by an apparatus adjustment or a tool change. If the reduction in wafer diameter is less than 0.8 mm, more apparatuses can handle the reduction even without an apparatus adjustment or a tool change. If the reduction in wafer diameter is less than 0.5 mm, many more apparatuses can handle the reduction even without an apparatus adjustment or a tool change. Based on the above, a width for grinding the entirety of a peripheral part of a wafer is preferably less than 1 mm, more preferably less than 0.8 mm, and further preferably less than 0.5 mm.

[0056] The width for grinding the entire outermost peripheral part of a wafer during the grinding step of the modification is much smaller than a width for processing a peripheral part during the chamfering step according to the second comparative example. This is because an object of the chamfering step according to the second comparative example can be achieved by forming a convex structure in the grinding step of the modification. Therefore, the grinding step of the modification has the effect of limiting a reduction in a wafer diameter compared to the comparative example.

[0057] Fig. 13 is a view showing a first modification of the bonding step according to the first embodiment of the present disclosure. In a bonding step of the first modification, the divided wafer 20 and a divided wafer 22 having a smaller wafer diameter than the divided wafer 20 are bonded to each other. This results in formation of a bonded wafer 21a having a convex structure in a cross section. Forming a bonded wafer having a convex structure makes it possible to omit a chamfering step to be subsequently performed in addition to suppressing wafer warpage.

[0058] Fig. 14 is a view showing a second modification of the bonding step according to the first embodiment of the present disclosure. A bonding step of the second modification differs from the first embodiment in a planarization process performed before bonding. Specifically, polishing of a peripheral part of a bonding interface is performed to a greater extent than polishing at a central part of the bonding interface. As a result, a peripheral part of a wafer becomes thinner than a central part, and a non-bonded region 26 is formed at a peripheral part of a bonding interface of a bonded wafer 21b.

[0059] A substrate thickness of each of the divided wafers bonded to each other can be measured by measuring the unbonded region 26, for example, using a light interference wafer thickness measurement. That is, a depth of a bonding interface that the bonded wafer 21b has can be detected in advance.

[0060] For example, if a wafer that has undergone a multiple dividing step and a bonding step is used, a bonding interface may be present near the semiconductor device structure 14 comprising a completed semiconductor device. In this case, the completed semiconductor device may suffer from poor characteristics and deterioration in reliability. The present modification can detect in advance a bonding interface present near the semiconductor device structure 14. For this reason, the above-described problem can be avoided by grinding and removing an affected bonding interface.

[0061] It should be noted that moisture infiltrates into the above-described unbonded region in a subsequent wet etching step. The moisture cannot be removed by spin drying, which is to be performed as a processing following the wet etching step, and it may cause problems in subsequent manufacturing steps. If the unbonded region is 1 mm or less wide from a periphery, the amount of moisture infiltrated is negligible. For this reason, the unbonded region is preferably 1 mm or less wide from the periphery of the bonded wafer 21b.

[0062] Fig. 15 is a view showing a modification of the chamfering step according to the first embodiment of the present disclosure. A chamfering step of the modification processes the peripheral part on the second main surface side of the bonded wafer 21 such that a cross section has a convex structure. This results in formation of a bonded wafer 23a in which a divided wafer 30a whose inner diameter is reduced due to uniformly grinding a peripheral part and a divided wafer 20 whose cross section is formed to have a convex structure by uniformly grinding a peripheral part to a fixed depth are bonded to each other. That is, an inner diameter of an upper surface of the divided wafer 20a is identical to the inner diameter of the divided wafer 30a.

[0063] For example, the chamfering step of the present modification can be applied to the bonded wafer 21b according to the second modification of the bonding step. In this case, the unbonded region 26 can be removed by the chamfering step. Second Embodiment. [Method for processing a semiconductor device according to a second embodiment of the present disclosure]

[0064] Fig. 16 is a view showing a thickening step according to a second embodiment of the present disclosure. In the first embodiment, the bonding step of bonding a plurality of divided wafers 20 is performed to suppress warpage of the divided wafer 20. In the thickening process of the present embodiment, an epitaxial layer 32 is formed on a divided wafer 20. This results in formation of a thick-layer wafer 41 having the same wafer diameter as the original wafer 12. By increasing a substrate thickness as described above, warpage of the wafer can be suppressed to a greater extent than in a case where the divided wafer 20 is used individually. Note that the formation of the epitaxial layer can be performed on either a first main surface or a second main surface.

[0065] A difference in resistivity between the epitaxial layer 32 and the divided wafer 20 is preferably small. This is because if the difference in resistivity between the epitaxial layer 32 and the divided wafer 20 becomes large, electrical characteristics change, resulting in a fluctuation in electrical characteristics of the entire semiconductor device at the time of forming a semiconductor device structure 14 in a subsequent step.

[0066] If the above-described resistivity difference is 30 mΩ·m or less, variations in the electrical characteristics of the entire semiconductor device fall within a range that allows the semiconductor device to be used equivalently to an original semiconductor device. If the above-described resistivity difference is 15 mΩ·m or less, variations in the electrical characteristics of the entire semiconductor device fall within an error range. If the above-described resistivity difference is 6 mΩ·m or less, variations in the electrical characteristics of the entire semiconductor device are almost non-existent.

[0067] Based on the above, the difference in resistivity between the epitaxial layer 32 and the divided wafer 20 is preferably 30 mΩ·m or less, more preferably 15 mΩ·m or less, and further preferably 6 mΩ·m or less.

[0068] The epitaxial layer 32 is preferably thick. This is because if the epitaxial layer 32 is thin, the effect of suppressing warpage of the divided wafer 20 cannot be sufficiently achieved.

[0069] If a thickness of the epitaxial layer 32 is 50 μm or more, warpage can be sufficiently suppressed, but a defect may occur during transportation or suction in a manufacturing apparatus to be used. If the thickness of the epitaxial layer 32 is 100 μm or more, warpage can be sufficiently suppressed, and a defect during transportation or suction in the manufacturing apparatus to be used hardly occurs. If the thickness of the epitaxial layer 32 is 150 μm, a semiconductor device 114 has a thickness identical to that of a wafer before dividing, and no defect occurs during transportation or suction in the manufacturing apparatus to be used.

[0070] Based on the above, the thickness of the epitaxial layer 32 is preferably 50 µm or more, more preferably 100 µm or more, and further preferably 150 µm.

[0071] Fig. 17 is a view showing a chamfering step according to the second embodiment of the present disclosure. In the chamfering step of the present embodiment, a peripheral part of a second main surface side of the thick-film wafer is processed into a tapered shape. This results in obtaining a thick-film wafer 43 in which an epitaxial layer 34 is formed on the unprocessed wafer 20, the peripheral part of which is processed into a tapered shape on a second main surface side.

[0072] The thick-film wafer 43 can be processed to have a desired substrate thickness, for example, by grinding, polishing, CMP, or the like. The desired substrate thickness can be, for example, the same substrate thickness as the wafer 12. By means of this configuration, at the time of reusing the thick-film wafer 43 as a wafer, it is possible to perform transportation and processing using the same equipment as for a wafer before processing, without performing adjustments involving a difference in substrate thickness.

[0073] Fig. 18 is a view showing a device formation step according to the second embodiment of the present disclosure. In the device formation step of the present embodiment, an epitaxial layer is formed on a second main surface side of the thick-film wafer 43, and the semiconductor device structure 14 is formed on the epitaxial layer. Note that the semiconductor device structure 14 is formed within the outermost peripheral part of the epitaxial layer 34, which is tapered.

[0074] A semiconductor device 118 obtained in the manner described above has a similar function to the semiconductor device 100. For this reason, the semiconductor device 118 can successively Fig. 2 to 7 or the Fig. 2 and 3 and 16 to 18, like the semiconductor device 100.

[0075] As described above, the Fig. 16 to 18, a reduction in the wafer diameter of a semiconductor device is achieved. This enables transport and processing using the same equipment as for a wafer before processing. [Method of processing a semiconductor device according to a modification of a second embodiment of the present disclosure]

[0076] Fig. 19 is a view showing a modification of the chamfering step according to the second embodiment of the present disclosure. A chamfering step of the modification processes the peripheral part on the second main surface side of the thick-film wafer 41 such that a cross section has a convex structure. This results in obtaining a thick-film wafer 43a in which an epitaxial layer 34a, whose peripheral part is uniformly ground, is formed on a divided wafer 20b, whose peripheral part is uniformly ground to a fixed depth.

[0077] For example, the chamfering step of the present modification may be performed with respect to a semiconductor device having a non-connected region 26, such as a semiconductor device 104b. In this case, the non-connected region 26 may be removed by the chamfering step. Third embodiment.

[0078] Fig. 20 is a view showing a chamfering step according to a third embodiment of the present disclosure. In the first and second embodiments, a chamfering step is performed after the entire wafer is thickened to suppress warpage of the wafer 16. A substrate thickness of a divided wafer according to the present embodiment falls within a range where warpage does not affect manufacturing steps. For this reason, the divided wafer is reused without being thickened.

[0079] This results in a reduction in the number of man-hours required for wafer reuse.

[0080] In the chamfering step of the present embodiment, a peripheral part on a second main surface side of a divided wafer is processed into a chamfered shape. This results in obtaining a divided wafer 30b with a peripheral part on a second main surface side thereof processed into a chamfered shape.

[0081] Fig. 21 is a view showing a device formation step according to the third embodiment of the present disclosure. In the device formation process of the present embodiment, an epitaxial layer is formed on the second main surface side of the divided wafer 30b, and a semiconductor device structure 14 is formed on the epitaxial layer. Note that the semiconductor device structure 14 is formed within an outermost peripheral part of the divided wafer 30b, which is tapered.

[0082] A semiconductor device 128 obtained in the manner described above has a similar function to the semiconductor device 100. For this reason, the semiconductor device 128 can successively Fig. 2 to 7, such as the semiconductor device 100.

[0083] As described above, the Fig. 20 and Fig. The steps shown in Figure 21 allow a reduction in the wafer diameter of a semiconductor device. This enables transport and processing using the same equipment as for a wafer before processing.

[0084] Fig.22 is a view showing a modification of the chamfering step according to the third embodiment of the present disclosure. In the chamfering step of the modification, a peripheral part of a side of a second main surface of a divided wafer is processed such that a cross section has a convex structure. This results in obtaining a divided wafer 30c with a peripheral part uniformly ground.

[0085] It should be noted that although aspects of the present disclosure have been described that connect two sliced ​​wafers, only one connection of a plurality of sliced ​​wafers is required. That is, details of the present disclosure may be applied to an aspect that connects three or more sliced ​​wafers.

[0086] Below, different aspects of the present disclosure are described collectively as appendices. (Appendix 1)

[0087] A method for manufacturing a semiconductor device comprising: a step of forming a semiconductor device structure on a second main surface of a wafer having a first main surface and the second main surface opposite to each other; a step of grinding a peripheral part of the second main surface of the wafer, on which the semiconductor device structure is formed, partially in a thickness direction from the second main surface toward the first main surface; a step of dividing the wafer in a direction perpendicular to the thickness direction at a position closer to the second main surface than a depth to which the peripheral part of the wafer is ground, and dividing a first divided wafer not including the semiconductor device structure from the wafer; a step of grinding a peripheral part of a divided surface of the first divided wafer; and a step of forming a semiconductor device structure on the divided surface of the first divided wafer, the peripheral part of the divided surface thereof being ground. (Appendix 2)

[0088] A method for manufacturing a semiconductor device according to Annex 1, further comprising a step of bonding a second divided wafer to the first main surface of the first divided wafer. (Appendix 3)

[0089] A process for manufacturing a semiconductor device according to Annex 2, wherein an amorphous layer is formed at a connection interface between the first divided wafer and the second divided wafer. (Appendix 4)

[0090] A method for manufacturing a semiconductor device according to Annex 2 or 3, further comprising a step of polishing and planarizing a connection interface of the first divided wafer or the second divided wafer before connecting, wherein polishing is performed at a peripheral part of the connection interface to a greater extent than polishing at a central part of the connection interface. (Appendix 5)

[0091] A method of manufacturing a semiconductor device according to any one of Annexes 1 to 4, wherein a cross-section of the wafer after grinding the peripheral part of the second main surface and before dividing has a convex structure. (Appendix 6)

[0092] A method for manufacturing a semiconductor device according to Annex 5, further comprising a step of grinding an entirety of an outermost peripheral part of the wafer before dividing the wafer. (Appendix 7)

[0093] A method of manufacturing a semiconductor device according to any one of Annexes 1 to 6, wherein the peripheral part of the divided surface of the first divided wafer is ground into a beveled shape. (Appendix 8)

[0094] A method of manufacturing a semiconductor device according to any one of Annexes 1 to 6, wherein a cross section of the wafer after grinding the peripheral part of the divided surface of the first divided wafer and before forming the semiconductor device structure on the divided surface has a convex structure. (Appendix 9)

[0095] A method for manufacturing a semiconductor device according to Annex 1, further comprising a step of forming an epitaxial layer on the first divided wafer. (Appendix 10)

[0096] A method of manufacturing a semiconductor device according to any one of Annexes 1 to 9, wherein the wafer is made of a wide bandgap semiconductor. (Appendix 11)

[0097] Semiconductor device comprising: a first divided wafer having a first main surface and a second main surface opposite to each other and having a semiconductor device structure on the second main surface; and a second divided wafer connected to the first main surface of the first divided wafer, wherein a non-connected region is formed at a peripheral part of a connection interface between the first divided wafer and the second divided wafer. (Appendix 12)

[0098] Semiconductor device according to Annex 11, where an amorphous layer is formed at the connection interface. (Appendix 13)

[0099] Semiconductor device according to Annex 11 or 12, where a peripheral part of the first divided wafer is processed into a tapered shape. (Appendix 14)

[0100] A semiconductor device according to any one of Annexes 11 to 13, wherein a wafer diameter of the first divided wafer is smaller than a wafer diameter of the second divided wafer. (Appendix 15)

[0101] A semiconductor device according to any one of Annexes 11 to 14, wherein a cross section of the second divided wafer has a convex structure, and an inner diameter of an upper surface of the second divided wafer is identical to an inner diameter of the first divided wafer. (Appendix 16)

[0102] Semiconductor device comprising: a first divided wafer having a first main surface and a second main surface opposite to each other; an epitaxial layer formed on the second main surface of the first divided wafer; and a semiconductor device structure formed on the epitaxial layer, wherein a cross section of the first divided wafer has a convex structure. (Appendix 17)

[0103] Semiconductor device according to Annex 16, where the epitaxial layer has a thickness of 50 µm or more. (Appendix 18)

[0104] Semiconductor device comprising: a first divided wafer having a first main surface and a second main surface opposite each other and having a semiconductor device structure on the second main surface, wherein a cross section of the first divided wafer has a convex structure.

[0105] Obviously, numerous modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the disclosure may be practiced differently from that specifically described.

[0106] The entire disclosure of Japanese Patent Application No. 2023-213137, filed on December 18, 2023, including the specification, claims, figures, and abstract on which the priority of the application is based, is incorporated herein by reference in its entirety. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2021-52178 A

[0002] JP 2023-213137

[0106]

Claims

[1] A method for manufacturing a semiconductor device (100) comprising: • a step of forming a semiconductor device structure (14) on a second main surface of a wafer (12) having a first main surface and the second main surface opposite to each other; • a step of grinding a peripheral part of the second main surface of the wafer (12) on which the semiconductor device structure (14) is formed, partially in a thickness direction from the second main surface toward the first main surface; • a step of dividing the wafer (12) in a direction perpendicular to the thickness direction at a position closer to the second main surface than a depth to which the peripheral part of the wafer (12) is ground, and dividing a first divided wafer (18) not including the semiconductor device structure (14) from the wafer (12); • a step of grinding a peripheral part of a divided surface of the first divided wafer (18); and • a step of forming a semiconductor device structure (14) on the divided surface of the first divided wafer (18), the peripheral part of the divided surface thereof being ground. [2] A method of manufacturing a semiconductor device (100) according to claim 1, further comprising a step of bonding a second divided wafer (18) to the first main surface of the first divided wafer (18). [3] A method of manufacturing a semiconductor device (100) according to claim 2, wherein an amorphous layer (24) is formed at a connection interface between the first divided wafer (18) and the second divided wafer (18). [4] A method of manufacturing a semiconductor device (100) according to claim 2 or 3, further comprising • a step of polishing and planarizing a connection interface of the first divided wafer (18) or the second divided wafer (18) before connecting, wherein • polishing is performed at a peripheral part of the connection interface to a greater extent than polishing at a central part of the connection interface. [5] A method of manufacturing a semiconductor device (100) according to any one of claims 1 to 4, wherein a cross section of the wafer (12) after grinding the peripheral part of the second main surface and before dividing has a convex structure. [6] A method of manufacturing a semiconductor device (100) according to claim 5, further comprising a step of grinding an entirety of an outermost peripheral part of the wafer (12) before dividing the wafer (12). [7] A method of manufacturing a semiconductor device (100) according to any one of claims 1 to 6, wherein the peripheral part of the divided surface of the first divided wafer (18) is ground into a tapered shape. [8] A method of manufacturing a semiconductor device (100) according to any one of claims 1 to 6, wherein a cross section of the wafer (12) after grinding the peripheral part of the divided surface of the first divided wafer (18) and before forming the semiconductor device pattern (14) on the divided surface has a convex structure. [9] A method of manufacturing a semiconductor device (100) according to claim 1, further comprising a step of forming an epitaxial layer (32) on the first divided wafer (18). [10] A method of manufacturing a semiconductor device (100) according to any one of claims 1 to 9, wherein the wafer (12) is formed of a wide bandgap semiconductor. [11] A semiconductor device (100) comprising: • a first divided wafer (18) having a first main surface and a second main surface opposite each other and having a semiconductor device structure (14) on the second main surface; and • a second divided wafer (18) connected to the first main surface of the first divided wafer (18), wherein • a non-connected region (26) is formed at a peripheral part of a connection interface between the first divided wafer (18) and the second divided wafer (18). [12] The semiconductor device (100) of claim 11, wherein an amorphous layer (24) is formed at the connection interface. [13] The semiconductor device (100) according to claim 11 or 12, wherein a peripheral part of the first divided wafer (18) is processed into a tapered shape. [14] The semiconductor device (100) according to any one of claims 11 to 13, wherein a wafer (12) diameter of the first divided wafer (18) is smaller than a wafer (12) diameter of the second divided wafer (18). [15] Semiconductor device (100) according to one of claims 11 to 14, wherein • a cross section of the second divided wafer (18) has a convex structure, and • an inner diameter of an upper surface of the second divided wafer (18) is identical to an inner diameter of the first divided wafer (18). [16] Semiconductor device (100) comprising: • a first divided wafer (18) having a first main surface and a second main surface opposite each other; • an epitaxial layer (32) formed on the second main surface of the first divided wafer (18); and • a semiconductor device structure (14) formed on the epitaxial layer (32), wherein • a cross section of the first divided wafer (18) has a convex structure. [17] The semiconductor device (100) according to claim 16, wherein the epitaxial layer (32) has a thickness of 50 µm or more. [18] Semiconductor device (100) comprising: • a first divided wafer (18) having a first main surface and a second main surface opposite each other and having a semiconductor device structure (14) on the second main surface, wherein • a cross section of the first divided wafer (18) has a convex structure.

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