Semiconductor device

Abstract

A coupling element (50) has a connected surface (55) which is in contact with a connecting element (60). In a top view seen in a direction perpendicular to a front electrode (10), the connected surface (55) covers at least a portion of each of a plurality of diode regions (2). The plurality of diode regions (2) comprises a first diode region (21), a second diode region (22), and a third diode region (23). In the top view, the second diode region (22) is located in a first direction (101) with respect to the first diode region (21) and is spaced apart from the first diode region (21). In the top view, the third diode region (23) is located in a direction (102) which is perpendicular to the first direction (101) with respect to the first diode region (21) and it is spaced apart from the first diode region (21) and the second diode region (22).

Description

Cross-reference to related applications

[0001] This non-provisional application is based on Japanese Patent Application No. 2023-183823, filed on October 26, 2023, with the Japan Patent Office, the entire contents of which are hereby incorporated by reference. Background of the inventionField of the invention

[0002] The present disclosure relates to a semiconductor device. Description of the state of the art

[0003] An insulated-gate bipolar transistor (IGBT), a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), and other similar semiconductor devices generate heat when conducting, starting to conduct, and stopping conduction. This heat generation can shorten the lifespan of the semiconductor device on which the semiconductor device is mounted. This affects the reliability of the semiconductor device. Accordingly, there is a need for a technique for dissipating heat when a semiconductor device generates heat.

[0004] As an example of a semiconductor device, Japanese Patent Application Laid-Open No. 2022-158037 discloses a semiconductor device including an RC-IGBT chip arranged on a copper circuit structure. The semiconductor device includes a wire connected to a surface electrode (an emitter electrode) of the RC-IGBT. The wire is used as external wiring. Summary of the invention

[0005] When the RC-IGBT is short-circuited, the RC-IGBT generates heat in an IGBT region. In particular, the IGBT region generates heat at a portion located near the surface electrode. The semiconductor device described in Japanese Patent Application Laid-Open No. 2022-158037 includes the RC-IGBT with a surface that is externally electrically connected using a wire. Therefore, heat generated at a portion of the RC-IGBT chip near the surface electrode is insufficiently dissipated. The present disclosure has been made in view of the foregoing, and an object thereof is to provide a semiconductor device capable of enhancing heat dissipation at a portion near a front-side electrode.

[0006] A semiconductor device according to the present disclosure includes an insulated-gate bipolar transistor region, a plurality of diode regions, a front-side electrode, a connection element, and a coupling element. The plurality of diode regions are in contact with the insulated-gate bipolar transistor region. The front-side electrode is in contact with the insulated-gate bipolar transistor region and the plurality of diode regions. The connection element is provided on the front-side electrode. The coupling element is connected to the front-side electrode through the connection element. The insulated-gate bipolar transistor region and the plurality of diode regions form a reverse-conducting insulated-gate bipolar transistor. The coupling element has a connected surface in contact with the connection element.In a plan view viewed in a direction perpendicular to the front-side electrode, the bonded area covers at least a portion of each of the plurality of diode regions. The plurality of diode regions includes a first diode region, a second diode region, and a third diode region. In the plan view, the second diode region is located in a first direction relative to the first diode region and is spaced apart from the first diode region. In the plan view, the third diode region is located in a second direction relative to the first diode region, the second direction being perpendicular to the first direction, and is spaced apart from each of the first and second diode regions.

[0007] The above and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings. Short description of the characters Fig. 1 is a schematic plan view showing a configuration of a semiconductor device according to a first embodiment Fig. Figure 2 is a schematic cross-section taken along a line II-II of Fig. 1 is taken. Fig. 3 is a schematic plan view showing a configuration of a semiconductor device. Fig. 4 is a schematic cross-sectional view showing a configuration of the semiconductor device. Fig. 5 is a schematic plan view showing a configuration of a semiconductor device according to a first modification of the first embodiment. Fig. 6 is a schematic plan view showing a configuration of a semiconductor device according to a second modification of the first embodiment. Fig. 7 is a schematic plan view showing a configuration of a semiconductor device according to a third modification of the first embodiment. Fig. 8 is a schematic plan view showing a configuration of a semiconductor device according to a second embodiment. Fig. Figure 9 is a schematic cross-section taken along a line IX-IX in Fig. 8 is taken. Fig. 10 is a schematic plan view showing a configuration of a semiconductor device according to a third embodiment. Fig. 11 is a schematic plan view showing a configuration of a semiconductor device according to the third embodiment. Fig. Figure 12 is a schematic cross-section taken along a line XII-XII in Fig. 11 is taken. Fig. 13 is a schematic plan view showing a configuration of a semiconductor device according to a fourth embodiment. Fig. 14 is a schematic plan view showing a configuration of a semiconductor device according to a fifth embodiment. Fig. 15 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a sixth embodiment. Fig. 16 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a modification of the sixth embodiment. Fig. 17 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a seventh embodiment. Fig. 18 is a schematic plan view showing a configuration of a semiconductor device according to an eighth embodiment. Fig. 19 is a schematic cross-section taken along a line XIX-XIX in Fig. 18 is taken. Fig. 20 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a ninth embodiment. Description of the preferred embodiments

[0008] Embodiments of the present disclosure are described below with reference to the figures. In the following figures, identical or equivalent components are labeled identically and will not be described repeatedly. First embodiment<Konfiguration eines Halbleitergerätes>

[0009] Initially, a configuration of a semiconductor device 100 according to a first embodiment will be described with reference to FIGS. Fig. 1 and Fig. 2. For simplified illustration, Fig. 1 a plurality of diode regions 2, which are described below, by a dashed line.

[0010] As in Fig. 1 and Fig. As shown in Figure 2, a semiconductor device 100 according to the first embodiment mainly includes a semiconductor device 30, a connecting element 60, and a coupling element 50. The connecting element 60 connects the semiconductor device 30 and the coupling element 50 to each other. The coupling element 50 electrically connects the semiconductor device 30 and an external device (not shown).

[0011] As in the Fig. 2 and Fig. As shown in Figure 3, the semiconductor device 30 includes a front-side electrode 10, a back-side electrode 11, an insulated-gate bipolar transistor region 1, a plurality of diode regions 2, and a termination region 4. Hereinafter, the insulated-gate bipolar transistor region 1 is also referred to as an IGBT region 1.

[0012] As in Fig. As shown in Figure 2, a semiconductor device 30 has a first surface 71 and a second surface 72. The second surface 72 is opposite to the first surface 71. A direction from the first surface 71 to the second surface 72 is a third direction 103. The third direction 103 is a direction perpendicular to the front-side electrode 10. The front-side electrode 10 is provided on the first surface 71. The front-side electrode 10 is an emitter electrode. The back-side electrode 11 is provided on the second surface 72. The back-side electrode 11 is a collector electrode.

[0013] The IGBT region 1 and the plurality of diode regions 2 define the first surface 71 and the second surface 72. The IGBT region 1 is in contact with the front side electrode 10 and the back side electrode 11, respectively. The IGBT region 1 is electrically connected to the front side electrode 10 and the back side electrode 11, respectively.

[0014] As in Fig. 2, each of the plurality of diode regions 2 is in contact with the IGBT region 1. Each of the plurality of diode regions 2 is in contact with the front side electrode 10 and the back side electrode 11, respectively. Each of the plurality of diode regions 2 is electrically connected to the front side electrode 10 and the back side electrode 11, respectively.

[0015] The plurality of diode regions 2 are arranged at a distance from each other. When viewed in a direction perpendicular to the front-side electrode 10 (hereinafter also referred to as a plan view), for example, each of the plurality of diode regions 2 has a rectangular shape.

[0016] The termination region 4 is in contact with the IGBT region 1. The termination region 4 surrounds the IGBT region 1 and the plurality of diode regions 2. The termination region 4 defines a part of the second area 72. The configuration of the termination region 4 will be specifically described later.

[0017] As in Fig. As shown in Figure 2, a connecting element 60 is provided on the front-side electrode 10. The connecting element 60 is, for example, a solder. In a plan view, the connecting element 60 is surrounded by the termination region 4. The connecting element 60 transfers heat from the front-side electrode 10 to the coupling element 50.

[0018] The coupling element 50 is mechanically connected to the front-side electrode 10 by the connecting element 60. Specifically, the coupling element 50 is electrically connected to the front-side electrode 10 by the connecting element 60. The coupling element 50 is made of metal.

[0019] As in the Fig. 1 and Fig. 2, the coupling element 50 includes a flat plate portion 49 and a conductive plate portion 51. The coupling element 50 is a DLB (Direct Lead Bonding) electrode. In a plan view, the flat plate portion 49 has a rectangular shape. The flat plate portion 49 is in contact with the connecting element 60. In the third direction 103, the connecting element 60 is provided between the flat plate portion 49 and the front-side electrode 10. The flat plate portion 49 may be spaced apart from the front-side electrode 10. In a plan view, the flat plate portion 49 is surrounded by the termination region 4.

[0020] As in the Fig. 1 and Fig. 2, the flat plate part 49 has a first end 81 and a second end 82. The first end 81 extends, for example, in a direction in which a longer side of the plurality of diode regions 2 extends. The flat plate part 49 has an end 82 provided on a side opposite the first end 81. The second end 82 may extend, for example, in a direction substantially parallel to that in which the first end 81 extends.

[0021] As in Fig. 2, the flat plate part 49 has a joined surface 55 and a front surface 56. The joined surface 55 is a surface of the flat plate part 49 that is in contact with the connecting element 60. In other words, the flat plate part 49 is in contact with the connecting element 60 at a joined surface 55. The joined surface 55 is, for example, flat. The front surface 56 is opposite to the joined surface 55. Viewed from another angle, the front surface 56 is provided in a direction opposite to the third direction 103 with respect to the joined surface 55.

[0022] As in Fig. 1, the flat plate part 49 covers at least a part of each of the plurality of diode regions 2 in plan view. Viewed from another angle, the connected area 55 (see Fig. 2) in plan view at least a part of each of the plurality of diode regions 2.

[0023] As in the Fig. 1 and Fig. 2, the conductive plate part 51 is adjacent to the flat plate part 49. Specifically, the conductive plate part 51 is adjacent to the flat plate part 49, for example, at the first end 81. The conductive plate part 51 is provided, for example, in a direction opposite to the third direction 103 with respect to the flat plate part 49. The conductive plate part 51 is spaced from the connecting member 60. An interface between the conductive plate part 51 and the flat plate part 49 is a connecting part 59. In other words, the conductive plate part 51 and the flat plate part 49 are adjacent to each other at the connecting part 59. The conductive plate part 51 forms a path for a current flowing between the front-side electrode 10 and an external device (not shown).

[0024] The conductive plate portion 51 extends in a direction substantially parallel to the direction in which the longer side of the plurality of diode regions 2 extends. Viewed from another angle, the connecting portion 59 extends in the direction in which the longer side of each of the plurality of diode regions 2 extends. <Konfiguration eines Halbleitergerätes>

[0025] A configuration of a semiconductor device 30 will now be described with reference to the Fig. 3 and Fig. 4. For simplified illustration, the front electrode 10 is shown in Fig. 3 not shown. The Fig. The cross section shown in Figure 4 is a cross section perpendicular to the front side electrode 10.

[0026] As in Fig. As shown in Figure 3, the semiconductor device 30 is an island-type RC-IGBT. Specifically, the plurality of diode regions 2 are provided in the shape of islands. Viewed from another angle, two or more diode regions 2 are aligned in the first direction 101 and the second direction 102, respectively, in a region that overlaps a single front-side electrode 10 in plan view.

[0027] The plurality of diode regions 2 includes a first diode region 21, a second diode region 22, and a third diode region 23. The first diode region 21 is, for example, a diode region 2 located at a corner of the plurality of diode regions 2. The second diode region 22 is spaced apart from the first diode region 21. In a plan view, a direction from the first diode region 21 to the second diode region 22 is a first direction 101. Viewed from another angle, the second diode region 22 is located in the first direction 101 relative to the first diode region 21.

[0028] The third diode region 23 is spaced apart from each of the first diode region 21 and the second diode region 22. In plan view, a direction from the first diode region 21 toward the third diode region 23 is a second direction 102. Viewed from another angle, the third diode region 23 is located in the second direction 102 with respect to the first diode region 21. The second direction 102 is a direction perpendicular to the first direction 101. For example, the plurality of diode regions 2 may each have a longer side parallel to the second direction 102.

[0029] As in Fig. 3, the plurality of diode regions 2 comprise a plurality of rows 20. Each of the plurality of rows 20 is composed of a plurality of diode regions 2 aligned in the second direction 102. While the number of diode regions 2 included in a row 20 is not specifically limited, the row comprises, for example, four diode regions. In the row 20, for example, four diode regions 2 may be aligned substantially equidistantly in the second direction 102. The plurality of rows 20 are aligned in the first direction 101. The plurality of rows 20 may, for example, be aligned substantially equidistantly in the first direction 101. While the number of rows 20 is not specifically limited, for example, eight rows are provided.

[0030] Each of the plurality of diode regions 2 is surrounded by the IGBT region 1. Viewed from another angle, the IGBT region 1 has a portion sandwiched between two diode regions 2 in the first direction 101. The IGBT region 1 has a portion sandwiched between two diode regions 2 in the second direction 102.

[0031] In plan view, the semiconductor device 30 has, for example, a rectangular shape. In plan view, the semiconductor device 30 has a longer side extending in the first direction 101. In plan view, the semiconductor device 30 has a shorter side extending in the second direction 102.

[0032] As in Fig. As shown in FIG. 4, the semiconductor device 30 includes a semiconductor substrate 70. A configuration of the diode region 2 will now be described. The semiconductor substrate 70 includes, for example, an n-type drift layer 43, an n+-type carrier storage layer 32, a p-type base layer 35, a p-type anode layer 28, an n-type buffer layer 37, and an n+-type cathode layer 29.

[0033] The n+-type carrier storage layer 32 is provided on the n--type drift layer 43. The n+-type carrier storage layer 32 has a higher impurity concentration than the n--type drift layer 43. The p-type base layer 35 is provided on the n+-type carrier storage layer 32.

[0034] The p-type anode layer 28 is provided on the p-type base layer 35. The p-type anode layer 28 is provided in the diode region 2. The p-type anode layer 28 has a higher impurity concentration than the p-type base layer 35. The p-type anode layer 28 defines a part of the first area 71 (see Fig. 2).

[0035] The n-type buffer layer 37 is in the third direction 103 with respect to the n - -type drift layer 43 is provided. The n-type buffer layer 37 is in contact with the n - -type drift layer 43. The n-type buffer layer 37 has a higher impurity concentration than the n - -Type drift layer 43.

[0036] The n+-type cathode layer 29 is provided in the third direction 103 with respect to the n-type buffer layer 37. The n+-type cathode layer 29 is in contact with the n-type buffer layer 37. The n+-type cathode layer 29 is provided in the diode region 2. The n+-type cathode layer 29 is electrically connected to the backside electrode 11. The n+-type cathode layer 29 defines a part of the second surface 72 (see Fig. 2).

[0037] A first trench gate 31a is provided in the semiconductor substrate 70 at the diode region 2. The first trench gate 31a extends from the first surface 71 in the third direction 103. The first trench gate 31a reaches the n--type drift layer 43. The first trench gate 31a is electrically connected to the front-side electrode 10.

[0038] A configuration of the IGBT region 1 will now be described. The semiconductor substrate 70 has an n+-type source layer 33, a p+-type contact layer 38, and a p-type collector layer 36. The n+-type source layer 33 is provided on the p-type base layer 35. The n+-type source layer 33 is provided in the IGBT region 1. The n+-type source layer 33 defines a part of the first area 71 (see Fig. 2).

[0039] The p+-type contact layer 38 is provided on the p-type base layer 35. The p+-type contact layer 38 is provided in the IGBT region 1 and the termination region 4. The p+-type contact layer 38 is spaced apart from the n+-type source layer 33. The p+-type contact layer 38 has a higher p-type impurity concentration than the p-type base layer 35. The p+-type contact layer 38 may have a p-type impurity concentration equal to that of the p-type anode layer 28.

[0040] The p-type collector layer 36 is provided in the third direction 103 with respect to the n-type buffer layer 37. The p-type collector layer 36 is in contact with the n-type buffer layer 37. The p-type collector layer 36 is provided in the IGBT region 1. The p-type collector layer 36 defines a part of the second surface 72 (see Fig. 2). The p-type collector layer 36 is electrically connected to the backside electrode 11. The p-type collector layer 36 is in contact with the n+-type cathode layer 29. An interface between the p-type collector layer 36 and the n+-type cathode layer 29 serves as a boundary between the diode region 2 and the IGBT region 1.

[0041] A second trench gate 31b and a third trench gate 31c are provided in the semiconductor substrate 70 at the IGBT region 1. The second trench gate 31b extends from the first surface 71 in the third direction 103. The second trench gate 31b reaches the n--type drift layer 43. The second trench gate 31b is in contact with the n+-type source layer 33. An interlayer insulating layer 34 is provided on the second trench gate 31b. The second trench gate 31b and the front-side electrode 10 are electrically insulated from each other by the interlayer insulating layer 34.

[0042] The third trench gate 31c extends from the first surface 71 in the third direction 103. The third trench gate 31c reaches the n--type drift layer 43. The third trench gate 31c is in contact with the p+-type contact layer 38. The third trench gate 31c is electrically connected to the front side electrode 10.

[0043] A configuration of the termination region 4 will now be described. The semiconductor substrate 70 includes a p-type termination well layer 41, an n+-type channel stopper layer 42, and a p-type termination collector layer 36a.

[0044] The p-type termination well layer 41 is provided in the termination region 4. The p-type termination well layer 41 is in contact with the n-type drift layer 43. The p-type termination well layer 41 defines a part of the first area 71 (see Fig. 2). The semiconductor substrate 70 has, for example, three p-type termination well layers 41. The three p-type termination well layers 41 are spaced apart from each other. In plan view, each of the three p-type termination well layers 41 has an annular shape. Each of the three p-type termination well layers 41 surrounds the IGBT region 1 and the plurality of diode regions 2.

[0045] The n+-type channel stopper layer 42 is provided in the termination region 4. The n+-type channel stopper layer 42 defines a part of the first area 71 (see Fig. 2). In plan view, the n+-type channel stopper layer 42 has a ring-like shape. The n+-type channel stopper layer 42 surrounds the p-type termination well layer 41.

[0046] A termination electrode 10a is provided on the p-type termination well layer 41 and the n+-type channel stopper layer 42. The termination electrode 10a is electrically connected to the p-type termination well layer 41 and the n+-type channel stopper layer 42.

[0047] A termination protection layer 5 is provided in the termination region 4. The termination protection layer 5 covers the front-side electrode 10, the termination electrode 10a, and the interlayer insulating layer 34. The termination protection layer 5 is formed of, for example, polyimide. An end surface of the termination protection layer 5, which is closer to the IGBT region 1, serves as a boundary between the termination region 4 and the IGBT region 1.

[0048] The p-type termination collector layer 36a is provided in the third direction 103 with respect to the n-type buffer layer 37. The p-type termination collector layer 36a is in contact with the n-type buffer layer 37. The p-type termination collector layer 36a is provided in the termination region 4. The p-type termination collector layer 36a defines a part of the second area 72 (see Fig. 2). The p-type termination collector layer 36a is substantially identical in configuration to the p-type collector layer 36.

[0049] A function and an effect of the semiconductor device 100 according to the first embodiment will now be described.

[0050] The RC-IGBT generates heat when it conducts, starts conducting, and stops conducting. Specifically, the IGBT region 1 generates heat when the IGBT region 1 conducts. A copper circuit structure may be connected to the back electrode 11 of the RC-IGBT. In this case, a part of the RC-IGBT near the back electrode 11 dissipates heat using the copper circuit structure. However, if a short circuit is caused in the RC-IGBT, particularly high heat generation occurs in a part of the IGBT region 1 near the front electrode 10. In this case, the RC-IGBT may be damaged immediately due to the heat generation.

[0051] For the semiconductor device 100 according to the first embodiment, the bonded area 55 of the coupling element 50 covers at least a portion of each of the plurality of diode regions 2 in plan view. In the plan view, the second diode region 22 is located in the first direction 101 with respect to the first diode region 21. The second diode region 22 is spaced apart from the first diode region 21. In the plan view, the third diode region 23 is located in the second direction 102 with respect to the first diode region 21. The third diode region 23 is spaced apart from each of the first diode region 21 and the second diode region 22. This allows the plurality of diode regions 2 to contact the IGBT region 1 in an enlarged area. This, in turn, allows heat generated by the IGBT region 1 to be efficiently transferred from the IGBT region 1 to the plurality of diode regions 2.Furthermore, the bonded area 55, which covers at least a portion of each of the plurality of diode regions 2, enables heat to be efficiently transferred from each of the plurality of diode regions 2 to the coupling element 50. As a result, enhanced heat dissipation can be provided in a portion of the semiconductor device 100 near the front-side electrode 10.

[0052] The semiconductor device 100 according to the first embodiment enables heat dissipation in a part of the semiconductor device 100 near the front-side electrode 10. This can prevent the semiconductor device 100 from locally having an excessively high temperature when a short circuit is caused in the RC-IGBT. As a result, the semiconductor device 100 can have an increased short-circuit withstand time.

[0053] The semiconductor device 100 according to the first embodiment has the first diode region 21 in a rectangular shape in plan view. The coupling member 50 includes a flat plate part 49 and a conductive plate part 51. The connection part 59 between the flat plate part 49 and the conductive plate part 51 extends in a direction in which the longer side of the first diode region 21 extends. When compared with the connection part 59 extending in a direction in which the shorter side of the first diode region 21 extends, the former can improve uniformity of a current flowing between the first diode region 21 and the connection part 59. This, in turn, can reduce an increase in the amount of heat generated because a current is concentrated locally.As a result, the semiconductor device 100 can provide enhanced heat dissipation while the plurality of diode regions 2 are conducting. (First modification of the first embodiment)

[0054] A configuration of the semiconductor device 100 according to the first modification of the first embodiment will now be described with reference to Fig. 5. For simplified illustration, the front electrode 10 is shown in Fig. 5 not shown.

[0055] While the above description describes a configuration in which each of the plurality of diode regions 2 has a rectangular shape in plan view, the configuration of the semiconductor device 100 according to the present disclosure is not limited to the above-described configuration. Specifically, each of the plurality of diode regions 2 may be Fig. 5, have a square shape in plan view. Viewed from another angle, a length of the diode region 2 in the first direction 101 and a length of the diode region 2 in the second direction 102 may be substantially equal. Each of the plurality of diode regions 2 has a side that is substantially parallel to the first direction 101.

[0056] This can reduce a difference in uniformity between a current flowing between the plurality of diode regions 2 and the connection part 59 of the coupling element 50 when the connection part 59 extends in the first direction 101 and a current flowing between the plurality of diode regions 2 and the connection part 59 when the connection part 59 extends in the second direction 102. From another perspective, the semiconductor device 100 can provide sufficiently enhanced heat dissipation both when the connection part 59 extends in the first direction 101 and when the connection part 59 extends in the second direction 102.This allows the arrangement of the conductive plate part 51 to be determined while considering the connection between the conductive plate part 51 and an external device while maintaining heat dissipation of the plurality of diode regions 2. As a result, an increased degree of freedom for mutual connection can be achieved. (Second modification of the first embodiment)

[0057] A configuration of a semiconductor device 100 according to a second modification of the first embodiment will be described below with reference to Fig. 6. The front electrode 10 is in Fig. 6 not shown.

[0058] As in Fig. As shown in Figure 6, the plurality of diode regions 2 may have a low density at a center of a region in which the plurality of diode regions 2 are arranged. Specifically, in the plan view, a minimum rectangular region surrounding all of the plurality of diode regions 2 is represented as a virtual region 91. A virtual line located between a peripheral edge of the virtual region 91 (or a first peripheral edge 92) and a center of a virtual region 91 (or a first center 93) serves as a boundary line 95.

[0059] The virtual region 91 has an outer peripheral region 96 and a central region 97. The outer peripheral region 96 is located between the first peripheral edge 92 and the boundary line 95. The central region 97 is located within the boundary line 95. The central region 97 borders the outer peripheral region 96. The central region 97 is surrounded by an outer peripheral region 96.

[0060] In plan view, the plurality of diode regions 2 have a lower density in the central region 97 than in the outer peripheral region 96. The diode region 2 in the central region 97 may have a smaller size than the diode region 2 in the outer peripheral region 96. Specifically, for example, the diode region 2 in the central region 97 has a shorter length in the second direction 102 than the diode region 2 in the outer peripheral region 96.

[0061] The diode region 2 in the central region 97 may have a substantially identical length in the first direction 101 to the diode region 2 in the outer peripheral region 96. In plan view, the plurality of diode regions 2 may include one diode region 2 having a square shape and one diode region 2 having a rectangular shape.

[0062] When the plurality of diode regions 2 are conducting, the central region 97 tends to have a higher temperature than the outer peripheral region 96. For the semiconductor device 100 according to the second modification of the first embodiment, the plurality of diode regions 2 have a lower density in the central region 97 than in the peripheral region 96 in plan view. This can prevent the central region 97 from having an excessively higher temperature than the outer peripheral region 96 when the plurality of diode regions 2 are conducting. This enables increased heat dissipation in a part of the semiconductor device 100 near the front-side electrode 10 when the plurality of diode regions 2 are conducting. (Third modification of the first embodiment)

[0063] A configuration of the semiconductor device 100 according to a third modification of the first embodiment will now be described with reference to Fig. 7. As described in Fig. 7, the coupling element 50 may completely cover the plurality of diode regions 2. Specifically, the connected area 55 (see Fig. 2) completely cover the plurality of diode regions 2 in plan view. In plan view, the connecting element 60 (see Fig. 2) completely cover the plurality of diode regions 2. Viewed from another angle, the plurality of diode regions 2 are surrounded by the peripheral edge of the flat plate part 49 in plan view.

[0064] This can further increase thermal energy transferred from the plurality of diode regions 2 to the coupling element 50 via the front-side electrode 10 and the connecting element 60. This enables further enhanced heat dissipation in a portion of the semiconductor device 100 near the front-side electrode 10.

[0065] While the above description described a configuration in which the first diode region 21 is located at a corner of the plurality of diode regions 2, it is possible for the first diode region 21 not to be located at the corner of the plurality of diode regions 2. The diode region 2 may be provided in a direction opposite to the first direction 101 and in a direction opposite to the second direction 102 with respect to the first diode region 21. Second embodiment

[0066] A configuration of the semiconductor device 100 according to a second embodiment will now be described with reference to FIGS. Fig. 8 and Fig. 9. The semiconductor device 100 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment mainly in that the former has a protective layer 6, and the semiconductor device according to the present embodiment has a remainder substantially identical to that of the semiconductor device 100 according to the first embodiment. The following mainly discusses how the semiconductor device according to the present embodiment differs from the semiconductor device 100 according to the first embodiment.

[0067] As in the Fig. 8 and Fig. As shown in Figure 9, the semiconductor device 100 may include the protective layer 6. The protective layer 6 is provided on the termination region 4. The protective layer 6 covers the termination region 4. The protective layer 6 is in contact with the front-side electrode 10. The protective layer 6 covers a part of the front-side electrode 10. In plan view, the protective layer 6 surrounds the plurality of diode regions 2. The protective layer 6 is formed, for example, from polyimide, a silicon nitride (SiN) layer, a semi-insulating silicon nitride (SInSiN) layer or a similar nitride layer, or a SIPOS (semi-insulating polycrystalline silicon) or a similar oxide layer. The protective layer 6 provided on the termination region 4 can relax an electric field concentration in the termination region 4. Third embodiment

[0068] A configuration of a semiconductor device 100 according to a third embodiment will now be described with reference to FIGS. Fig. 10 to 12. The semiconductor device 100 according to the third embodiment differs from the semiconductor device 100 according to the first embodiment mainly in that a sufficiently large distance is provided between each of the peripheral edge of the bonded area 55 and the termination region 4 and the plurality of diode regions 2 in plan view, and the semiconductor device according to the present embodiment has a remainder substantially identical to that of the semiconductor device 100 according to the first embodiment. The following mainly discusses how the semiconductor device according to the present embodiment differs from the semiconductor device 100 according to the first embodiment.

[0069] As in Fig. As shown in Figure 10, a shortest distance between the termination region 4 and the plurality of diode regions 2 in plan view is represented as a first distance L1. Specifically, the first distance L1 is a shortest distance in plan view between the termination protection layer 5 of the termination region 4 (see Fig. 4) and the n+-type cathode layer 29 (see Fig. 4). The first distance L1 is, for example, a shortest distance between the termination region 4 and the plurality of diode regions 2 in the first direction 101.

[0070] As in the Fig. 11 and Fig. 12, a shortest distance between the peripheral edge of the connected surface 55 (see Fig. 12) (or a second peripheral edge 98) and the plurality of diode regions 2 is represented in plan view by a second distance L2. Specifically, a second distance L2 is a shortest distance between a peripheral edge 98 and an n+-type cathode layer 29 (see Fig. 4) in plan view. The second distance L2 is, for example, a shortest distance between the second peripheral edge 98 and the plurality of diode regions 2 in the first direction 101. In plan view, the second peripheral edge 98 may substantially overlap the peripheral edge of the flat plate part 49.

[0071] As in Fig. 12, a distance between the first surface 71 and the second surface 72 in the third direction 103 is represented as a thickness H of the IGBT region 1 in the third direction 103. The thickness H is a thickness of the semiconductor substrate 70 (see Fig. 4) in the third direction 103. The thickness H is substantially equal to a thickness of the diode region 2 in the third direction 103.

[0072] As in the Fig. 10 to 12, the first distance L1 is equal to or greater than the thickness H. The second distance L2 is equal to or greater than the thickness H. The second distance L2 is shorter than the first distance L1.

[0073] The semiconductor device 100 according to the third embodiment has the first distance L1, which is equal to or greater than the thickness H. Thus, a sufficiently large distance exists between the termination region 4 and the plurality of diode regions 2. This can prevent the flow of holes from the termination region 4 into the plurality of diode regions 2. This can suppress power loss when the plurality of diode regions 2 are conducting.

[0074] When the plurality of diode regions 2 conduct, charge carriers diffuse from the diode regions 2 in a direction inclined by 45° with respect to the third direction 103. Heat is generated in a region into which charge carriers diffuse. The semiconductor device 100 according to the third embodiment has a second distance L2 equal to or greater than the thickness H. Therefore, the bonded surface 55 can cover, in plan view, a region into which charge carriers diffuse while the plurality of diode regions 2 conduct. The semiconductor device 100 can thus provide further enhanced heat dissipation. Fourth embodiment

[0075] A configuration of the semiconductor device 100 according to a fourth embodiment will now be described with reference to Fig. 13. The semiconductor device 100 according to the fourth embodiment differs from the semiconductor device 100 according to the first embodiment mainly in that the diode region 2 is provided so as to sandwich the gate pad 7, and the semiconductor device according to the present embodiment has a remainder substantially identical to that of the semiconductor device 100 according to the first embodiment. The following mainly discusses how the semiconductor device according to the present embodiment differs from the semiconductor device 100 according to the first embodiment.

[0076] As in Fig. 13, the semiconductor device 100 includes the gate pad 7. In the plan view, the gate pad 7 is provided, for example, in the first direction 101 with respect to a center of the front-side electrode 10 (or a second center 94). The gate pad 7 is located, for example, adjacent to the termination region 4. In the plan view, an imaginary line passing through the second center 94 and parallel to the first direction 101 is represented as a center line A. In the plan view, the center line A passes, for example, through the gate pad 7. The gate pad 7 is configured to receive a signal for controlling a conduction of the IGBT region 1 (see Fig. 2) to receive.

[0077] The semiconductor device 100 has a gate pad 7 on a side opposite the backside electrode 11. Viewed from another angle, the gate pad 7 is provided in a direction opposite to the third direction 103 with respect to the IGBT region 1.

[0078] The plurality of diode regions 2 include two sets of pad-enclosure diode regions. Specifically, the plurality of diode regions 2 includes a fourth diode region 24, a fifth diode region 25, a sixth diode region 26, and a seventh diode region 27. The fourth diode region 24, the fifth diode region 25, the sixth diode region 26, and the seventh diode region 27 are spaced apart from each other.

[0079] The fifth diode region 25 is provided in the second direction 102 relative to the fourth diode region 24. In the second direction 102, the fourth diode region 24 and the fifth diode region 25 are provided such that they sandwich the gate pad 7. Viewed from a different angle, in the top view, the gate pad 7 is provided between the fourth diode region 24 and the fifth diode region 25.

[0080] The seventh diode region 27 is provided in the second direction 102 relative to the sixth diode region 26. In the second direction 102, the sixth diode region 26 and the seventh diode region 27 are arranged to sandwich the gate pad 7. Viewed from another angle, the gate pad 7 is provided between the sixth diode region 26 and the seventh diode region 27 in plan view.

[0081] The flat plate part 49 does not cover the gate pad 7. Viewed from a different angle, the connected surface 55 (see Fig. 2) spaced from the gate pad 7. In plan view, a portion of the flat plate portion 49 forks near the gate pad 7. Specifically, the flat plate portion 49 includes a main body 80, and a first portion 61 and a second portion 62. The first portion 61 is adjacent to the main body 80. The first portion 61 is provided in the first direction 101 relative to the main body 80. In plan view, the first portion 61 overlaps the fourth diode region 24 and the sixth diode region 26, respectively.

[0082] The second part 62 is adjacent to the main body 80. The second part 62 is provided in the first direction 101 with respect to the main body 80. The second part 62 is spaced apart from the first part 61. The second part 62 is provided in the second direction 102 with respect to the first part 61. The second part 62 overlaps the fifth diode region 25 and the seventh diode region 27, respectively, in plan view. In the plan view, the gate pad 7 is provided between the first part 61 and the second part 62.

[0083] In plan view, the conductive plate portion 51 is provided, for example, in a direction opposite to the gate pad 7 with respect to the second center 94. Viewed from another angle, the conductive plate portion 51 is provided, for example, in a direction opposite to the first direction 101 with respect to the second center 94. In plan view, the second center 94 is located, for example, between the conductive plate portion 51 and the gate pad 7.

[0084] For the semiconductor device 100 of the fourth embodiment, the plurality of diode regions 2 includes the fourth diode region 24 and the fifth diode region 25. The gate pad 7 is provided between the fourth diode region 24 and the fifth region 25. Compared with the absence of the fourth diode region 24 and the fifth diode region 25, the former can reduce the density of the plurality of diode regions 2 for a given total area of ​​the plurality of diode regions 2 in plan view. This enables enhanced heat dissipation in a part of the semiconductor device 100 near the front-side electrode 10 when the plurality of diode regions 2 are conducting.

[0085] For the semiconductor device 100 according to the fourth embodiment, the flat plate part 49 includes the first part 61 and the second part 62. In plan view, the first part 61 overlaps the fourth diode region 24. In plan view, the second part 62 overlaps the fifth diode region 25. This can increase the heat energy transferred from the fourth diode region 24 and the fifth diode region 25 to the coupling element 50, respectively. This enables enhanced heat dissipation in the fourth diode region 24 and the fifth diode region 25.

[0086] For the semiconductor device 100 according to the fourth embodiment, the conductive plate portion 51 is provided in a direction opposite to the gate pad 7 in plan view with respect to the second center 94. This can prevent interference between the gate terminal connected to the gate pad 7 and the conductive plate portion 51. Thus, an increased degree of freedom for mutual connection can be achieved.

[0087] The plurality of diode regions 2 may include a pair of pad-enclosed diode regions. In other words, the plurality of diode regions 2 may not include the sixth diode region 26 and the seventh diode region 27. Fifth embodiment

[0088] A configuration of the semiconductor device 100 according to a fifth embodiment will now be described with reference to Fig. 14. The semiconductor device 100 according to the fifth embodiment differs from the semiconductor device 100 according to the fourth embodiment mainly in that the bonded area 55 covers a temperature measuring diode 8, and the semiconductor device according to the present embodiment has a remainder substantially identical to that of the semiconductor device 100 according to the fourth embodiment. The following mainly discusses how the semiconductor device according to the present embodiment differs from the semiconductor device 100 according to the fourth embodiment.

[0089] As in Fig. 14, the semiconductor device 100 includes the temperature measuring diode 8, and an anode pad 12 and a cathode pad 13. In plan view, the temperature measuring diode 8 is provided between any two of the plurality of diode regions 2. The temperature measuring diode 8 is provided, for example, near the center of the semiconductor device 100. Specifically, the second center 94 in plan view may overlap the temperature measuring diode 8. In plan view, the center line A may pass through the temperature measuring diode 8. In plan view, the flat plate part 49 covers the temperature measuring diode 8. Viewed from another angle, the connected surface 55 (see Fig. 2) the temperature measuring diode 8.

[0090] The anode pad 12 is electrically connected to the temperature measuring diode 8. The cathode pad 13 is electrically connected to the temperature measuring diode 8. In the plan view, the flat plate part 49 does not cover the anode pad 12 and the cathode pad 13. In other words, in the plan view, the connected surface 55 (see Fig. 2) spaced from the anode pad 12 and the cathode pad 13, respectively.

[0091] In plan view, the conductive plate portion 51 may be provided in the first direction 101 relative to the second center 94. In plan view, the conductive plate portion 51 may be provided between the second center 94 and the gate pad 7. When the semiconductor device 100 has a plurality of top surface electrodes 10, the second center 94 is a center of the smallest rectangular region surrounding all of the plurality of surface electrodes 10 in plan view.

[0092] The semiconductor device 100 according to the fifth embodiment includes a bonded surface 55 covering the temperature measuring diode 8. This can help transfer heat from the temperature measuring diode 8 to the coupling element 50. This can enhance heat dissipation of the temperature measuring diode 8.

[0093] The temperature measuring diode 8 may be provided along the gate pad 7. The temperature measuring diode 8 may be provided in the first direction 101 with respect to the second center 94. Sixth embodiment

[0094] A configuration of the semiconductor device 100 according to a sixth embodiment will now be described with reference to Fig. 15. The semiconductor device 100 according to the sixth embodiment differs from the semiconductor device 100 according to the first embodiment mainly in that the coupling element 50 has a raised portion 52, and the semiconductor device according to the present embodiment has a remainder that is substantially identical to that of the semiconductor device 100 according to the first embodiment. The following mainly discusses how the semiconductor device according to the present embodiment differs from the semiconductor device 100 according to the first embodiment. Fig. 15 corresponds to the cross section shown in Fig. 2 shown cross section.

[0095] As in Fig. 15, the coupling element 50 has a raised portion 52. The raised portion 52 is adjacent to the flat plate portion 49. The raised portion 52 is spaced apart from the conductive plate portion 51. At the second end 82, the raised portion 52 is adjacent to the flat plate portion 49. The raised portion 52 is spaced apart from the conductive plate portion 51. The raised portion 52 is inclined with respect to the flat plate portion 49 in a direction from the front-side electrode 10 to the flat plate portion 49. An inclination angle of the raised portion 52 with respect to the flat plate portion 49 is not specifically limited.

[0096] For the semiconductor device 100 of the sixth embodiment, the coupling element 50 includes the raised portion 52. Compared to the coupling element 50 without the raised portion 52, the former allows the coupling element 50 to have an increased surface area. This enables enhanced heat dissipation from the coupling element 50 to the outside of the semiconductor device 100. (Modification of the sixth embodiment)

[0097] As in Fig. 16, a first uneven part 53 may be provided on the front surface 56 of the flat plate part 49. Specifically, a plurality of first recesses 75 and a plurality of first protrusions 76 may be provided on the front surface 56. The plurality of first protrusions 76 are spaced apart from each other. In the first direction 101, the plurality of first protrusions 76 are provided between the conductive plate part 51 and the raised part 52. The first recess 75 is provided between two adjacent first protrusions 76. Each of the plurality of first protrusions 76 extends, for example, in the second direction 102. The plurality of first recesses 75 and the plurality of first protrusions 76 are not specifically limited in size.

[0098] For the semiconductor device 100 according to the modification of the sixth embodiment, the first uneven portion 53 is provided on the front surface 56 of the flat plate portion 49. This can provide the coupling element 50 with a further increased surface area. As a result, the semiconductor device 100 can provide further enhanced heat dissipation. Seventh embodiment

[0099] A configuration of a semiconductor device 100 according to a seventh embodiment will now be described. The semiconductor device 100 according to the seventh embodiment differs from the semiconductor device 100 according to the sixth embodiment mainly in that the flat plate part 49 has a third protrusion 79, and the semiconductor device according to the present embodiment has a remainder substantially identical to that of the semiconductor device 100 according to the sixth embodiment. The following mainly discusses how the semiconductor device according to the present embodiment differs from the semiconductor device 100 according to the sixth embodiment.

[0100] As in Fig. 17, the flat plate part 49 includes a plate-shaped part 48 and a third protrusion 79. The plate-shaped part 48 is a part that defines the front surface 56, the first end 81, and the second end 82. The third protrusion 79 is provided in the third direction 103 with respect to the plate-shaped part 48. The third protrusion 79 protrudes in the third direction 103. The plate-shaped part 48 and the third protrusion 79 define the connected surface 55. The protrusion 79 is in contact with the connecting element 60. The third protrusion 79 may have a lower surface that, for example, lies in a plane or protrudes in the third direction 103. The protrusion 79 may be spaced from the front-side electrode 10. In plan view, the third protrusion 79 is surrounded, for example, by the connecting element 60. In plan view, the third projection 79 may, for example, completely cover the plurality of diode regions 2.

[0101] For the semiconductor device 100 according to the seventh embodiment, the flat plate portion 49 has the third protrusion 79. Therefore, in a process for manufacturing the semiconductor device 100, the third protrusion 79 extrudes the connecting element 60 outward in a direction in a plane perpendicular to the third direction 103 before the connecting element solidifies. This makes it possible to effectively bring the flat plate portion 49 and the connecting element 60 into close contact with each other. This, in turn, prevents the formation of voids at a boundary between the flat plate portion 49 and the connecting element 60. Eighth embodiment

[0102] A configuration of a semiconductor device 100 according to an eighth embodiment will now be described with reference to FIGS. Fig. 18 and Fig. 19. The semiconductor device 100 according to the eighth embodiment differs from the semiconductor device 100 according to the sixth embodiment mainly in that the flat plate part 49 is provided with a through-hole 99, and the semiconductor device according to the present embodiment has a remainder substantially identical to that of the semiconductor device 100 according to the sixth embodiment. The following mainly discusses how the semiconductor device according to the present embodiment differs from the semiconductor device 100 according to the sixth embodiment.

[0103] As in the Fig. 18 and Fig. As shown in Figure 19, the flat plate portion 49 is provided with at least one or more through-holes 99. Specifically, one through-hole 99 may be provided, or two or more through-holes may be provided. The through-hole 99 extends in the third direction 103. The through-hole 99 penetrates the front side 56 and the connected surface 55. A portion of the connecting element 60 is located in the through-hole 99.

[0104] In the process of manufacturing the semiconductor device 100, when the front electrode 10 and the coupling member 50 are connected to each other using the connecting member 60, the connecting member 60 is heated. As the connecting member 60 thermally expands, the connecting member 60 exerts pressure on the semiconductor device 30. The semiconductor device 100 according to the eighth embodiment includes the flat plate part 49 provided with at least one or more through holes 99. Accordingly, when the front electrode 10 and the coupling member 50 are connected to each other using the connecting member 60, the connecting member 60 wets and spreads within the through hole 99. This can reduce the pressure exerted by the connecting member 60 on the semiconductor device 30 when the front electrode 10 and the coupling member 50 are connected to each other.As a result, cracking of the semiconductor device 30 can be prevented. Ninth embodiment

[0105] A configuration of the semiconductor device 100 according to a ninth embodiment will be described with reference to Fig. 20. The semiconductor device 100 according to the ninth embodiment differs from the semiconductor device 100 according to the sixth embodiment mainly in that the bonded surface 55 is provided with a second uneven part 54, and the semiconductor device according to the present embodiment has a remainder substantially identical to that of the semiconductor device 100 according to the sixth embodiment. The following mainly discusses how the semiconductor device according to the present embodiment differs from the semiconductor device 100 according to the sixth embodiment.

[0106] As in Fig.20, the joined surface 55 is provided with the second uneven part 54. Specifically, the joined surface 55 is provided with a plurality of second recesses 77 and a plurality of second protrusions 78. The plurality of protrusions 78 are spaced apart from each other. In the first direction 101, the plurality of second protrusions 78 are provided between the conductive plate part 51 and the raised part 52. The second recess 77 is provided between two adjacent second protrusions 78. Each of the plurality of second protrusions 78 extends, for example, in the second direction 102. The second uneven part 54 is in contact with the connecting element 60. The plurality of second recesses 77 and the plurality of second protrusions 78 are not specifically limited in size.

[0107] The semiconductor device 100 according to the ninth embodiment has the bonded surface 55 provided with the second uneven portion 54. This can provide an anchoring effect, enabling increased bonding strength between the front-side electrode 10 and the coupling member 50 using the bonding member 60. Specifically, when the front-side electrode 10 and the coupling member 50 are bonded using the bonding member 60, the molten bonding member 60 enters the second uneven portion 54. This can effectively bring the coupling member 50 and the bonding member 60 into close contact with each other. As a result, increased bonding strength between the front-side electrode 10 and the coupling member 50 can be achieved.

[0108] While a configuration of the coupling member 50 having the raised portion 52 in the modification of the sixth embodiment and the seventh to ninth embodiments has been described, the configuration of the coupling member 50 is not limited to the above configuration. Specifically, the coupling member 50 may not have the raised portion 52.

[0109] It should be understood that the embodiments disclosed herein have been described purely for illustrative purposes and in all respects in a non-limiting manner. The scope of the present disclosure is defined by the terms of the claims rather than the above description, and it is intended to include any modifications within the meaning and scope equivalent to the terms of the claims.

[0110] Aspects of the present disclosure are summarized below as appendices. (Appendix 1)

[0111] Semiconductor device comprising: a region of an insulated gate bipolar transistor; a plurality of diode regions in contact with the insulated gate bipolar transistor region; a front side electrode in contact with the insulated gate bipolar transistor region and the plurality of diode regions; a connecting element provided on the front side electrode; and a coupling element connected to the front side electrode through the connecting element, wherein the insulated gate bipolar transistor region and the plurality of diode regions form a reverse conducting insulated gate bipolar transistor, the coupling element has a connected surface which is in contact with the connecting element, in a plan view viewed in a direction perpendicular to the front electrode, the bonded area covers at least a portion of each of the plurality of diode regions, in plan view have the multitude of diode regions a first diode region a second diode region located in a first direction with respect to the first diode region and spaced from the first diode region, and a third diode region located in a second direction relative to the first diode region, the second direction being perpendicular to the first direction, and spaced from each of the first and second diode regions. (Appendix 2)

[0112] Semiconductor device according to Appendix 1, wherein the coupling element comprises: a flat plate portion defining the connected surface; and a conductive plate portion adjacent to the flat plate portion and spaced from the connecting element. (Appendix 3)

[0113] Semiconductor device according to Appendix 2, wherein the first diode region has a rectangular shape in plan view, and a connecting part between the flat plate part and the conductive plate part extends in a direction in which a longer side of the first diode region extends. (Appendix 4)

[0114] A semiconductor device according to appendix 2 or 3, further comprising a gate pad provided in a direction from the insulated gate bipolar transistor region to the front side electrode with respect to the insulated gate bipolar transistor region and receiving a signal for controlling conduction of the insulated gate bipolar transistor region, wherein the plurality of diode regions comprise a fourth diode region and a fifth diode region spaced from the fourth diode region, The gate pad is provided in the plan view between the fourth diode region and the fifth diode region, The connected surface is spaced from the gate pad in plan view, the flat plate part has a first part overlapping the fourth diode region in plan view and a second part overlapping the fifth diode region in plan view, the second part being spaced from the first part. (Appendix 5)

[0115] Semiconductor device according to Appendix 4, wherein in plan view, the gate pad is provided in the first direction relative to a center of the front side electrode, and in plan view, the conductive plate part is provided in a direction opposite to the gate pad with respect to the center of the front side electrode. (Appendix 6)

[0116] Semiconductor device according to one of Appendices 2 to 5, wherein the coupling element has a raised part which is adjacent to the flat plate part and deviates from the conductive plate part, and the raised part is inclined with respect to the flat plate part in a direction from the front side electrode to the flat plate part. (Appendix 7)

[0117] Semiconductor device according to one of the appendices 2 to 6, wherein the flat plate part has a front surface which is opposite to the connected surface, and the front surface is provided with a first uneven part. (Appendix 8)

[0118] Semiconductor device according to one of Appendices 2 to 7, wherein the flat plate part has a projection which projects in a direction from the flat plate part to the front electrode, and the overhang defines part of the connected area. (Appendix 9)

[0119] A semiconductor device according to any one of appendices 2 to 8, wherein the flat plate part is provided with at least one through hole. (Appendix 10)

[0120] Semiconductor device according to one of the appendices 2 to 9, wherein the connected surface is provided with a second uneven part, and the second uneven part is in contact with the connecting element. (Appendix 11)

[0121] A semiconductor device according to Appendix 1 or 2, wherein each of the plurality of diode regions has a square shape in plan view. (Appendix 12)

[0122] Semiconductor device according to one of the appendices 1 to 11, wherein wherein, in the plan view, a minimum rectangular region surrounding all of the plurality of diode regions is represented as a virtual region, and wherein a virtual line between a peripheral edge of the virtual region and a center of the virtual region is defined as a boundary line, the virtual region consists of an outer peripheral region located between the peripheral edge of the virtual region and the boundary line and a middle region located within the borderline and bordering the outer peripheral region, and in plan view, the plurality of diode regions in the central region has a lower density than the plurality of diode regions in the outer peripheral region. (Appendix 13)

[0123] A semiconductor device according to any one of appendices 1 to 12, wherein in plan view the bonded area completely covers the plurality of diode regions. (Appendix 14)

[0124] Semiconductor device according to one of the appendices 1 to 13, further comprising: a termination region in contact with the insulated gate bipolar transistor region and surrounding the insulated gate bipolar transistor region and the plurality of diode regions; and a protective layer provided on the termination region. (Appendix 15)

[0125] A semiconductor device according to any one of Appendices 1 to 13, further comprising a termination region which is in contact with the insulated gate bipolar transistor region and surrounds the insulated gate bipolar transistor region and the plurality of diode regions, wherein a shortest distance between the termination region and the plurality of diode regions in plan view is equal to or greater than a thickness of the region of the insulated gate bipolar transistor in the direction perpendicular to the front side electrode. (Appendix 16)

[0126] A semiconductor device according to any one of appendices 1 to 15, wherein a shortest distance between a peripheral edge of the bonded area and the plurality of diode regions in plan view is equal to or greater than a thickness of the region of the insulated gate bipolar transistor in the direction perpendicular to the front side electrode. (Appendix 17)

[0127] A semiconductor device according to any one of Appendices 1 to 16, further comprising a temperature measuring diode provided between any two of the plurality of diode regions in plan view, wherein the connected surface covers the temperature measuring diode in the top view. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023–183823

[0001]

Claims

[1] A semiconductor device (100) comprising: • a region (1) of an insulated gate bipolar transistor; • a plurality of diode regions (2) in contact with the region (1) of the insulated gate bipolar transistor; • a front side electrode (10) in contact with the insulated gate bipolar transistor region (1) and the plurality of diode regions (2); • a connecting element (60) provided on the front electrode (10); and • a coupling element (50) which is connected to the front electrode (10) by the connecting element (60), wherein • the insulated gate bipolar transistor region (1) and the plurality of diode regions (2) form a reverse conducting insulated gate bipolar transistor, • the coupling element (50) has a connected surface (55) which is in contact with the connecting element (60), • in a plan view viewed in a direction perpendicular to the front electrode (10), the bonded surface (55) covers at least a part of each of the plurality of diode regions (2), • in plan view have the plurality of diode regions (2) ◯ a first diode region (21), ◯ a second diode region (22) which is located in a first direction (101) with respect to the first diode region (21) and is spaced from the first diode region (21), and ◯ a third diode region (23) which is located in a second direction (102) with respect to the first diode region (21), the second direction (102) being perpendicular to the first direction (101), and which is spaced from each of the first diode region (21) and the second diode region (22). [2] The semiconductor device (100) according to claim 1, wherein the coupling element (50) comprises: • a flat plate portion (49) defining the connected surface (55); and • a conductive plate part (51) which is adjacent to the flat plate part (49) and is spaced from the connecting element (60). [3] A semiconductor device (100) according to claim 2, wherein • the first diode region (21) has a rectangular shape in plan view, and • a connecting part (59) between the flat plate part (49) and the conductive plate part (51) extends in a direction in which a longer side of the first diode region (21) extends. [4] A semiconductor device (100) according to claim 2 or 3, further comprising • a gate pad (7) provided in a direction from the insulated gate bipolar transistor region (1) to the front side electrode (10) with respect to the insulated gate bipolar transistor region (1) and receiving a signal for controlling conduction of the insulated gate bipolar transistor region (1), wherein • the plurality of diode regions (2) include a fourth diode region (24) and a fifth diode region (25) spaced from the fourth diode region (24), • in plan view, the gate pad (7) is provided between the fourth diode region (24) and the fifth diode region (25), • in plan view, the connected surface (55) is spaced from the gate pad (7), • the flat plate part (49) has: ◯ a first part (61) which overlaps the fourth diode region (24) in plan view, and ◯ a second part (62) which overlaps the fifth diode region (25) in plan view, and the second part (62) is spaced from the first part (61). [5] A semiconductor device (100) according to claim 4, wherein • the gate pad (7) is provided in the first direction (101) in plan view relative to a center (94) of the front side electrode (10), and • the conductive plate part (51) is provided in a direction opposite to the gate pad (7) with respect to the center (94) of the front side electrode (10) in plan view. [6] Semiconductor device (100) according to one of claims 2 to 5, wherein • the coupling element (50) has a raised part (52) which adjoins the flat plate part (49) and deviates from the conductive plate part (51), and • the raised part (52) is inclined with respect to the flat plate part (49) in a direction from the front side electrode (10) to the flat plate part (49). [7] Semiconductor device (100) according to one of claims 2 to 6, wherein • the flat plate part (49) has a front surface (56) which is opposite to the connected surface (55), and • the front surface (56) is provided with a first uneven part (53). [8] Semiconductor device (100) according to one of claims 2 to 7, wherein • the flat plate part (49) has a projection (79) which projects in a direction from the flat plate part (49) towards the front side electrode (10), and • the projection (79) defines part of the connected surface (55). [9] A semiconductor device (100) according to any one of claims 2 to 8, wherein the flat plate part (49) is provided with at least one or more through holes (99). [10] A semiconductor device (100) according to any one of claims 2 to 9, wherein • the connected surface (55) is provided with a second uneven part (54), and • the second uneven part (54) is in contact with the connecting element (60). [11] A semiconductor device according to claim 1 or 2, wherein each of said plurality of diode regions (2) has a square shape in plan view. [12] A semiconductor device (100) according to any one of claims 1 to 11, wherein, • when in the plan view, a minimum rectangular region surrounding all of the plurality of diode regions (2) is represented as a virtual region (91) and a virtual line located between a peripheral edge (92) of the virtual region (91) and a center (93) of the virtual region (91) is defined as a boundary line (95), • the virtual region (91) is composed of ◯ an outer peripheral region (96) located between the peripheral edge (92) of the virtual region (91) and the boundary line (95) and ◯ a central region (97) located within the border line (95) and bordering the outer peripheral region (96), and • in plan view, the plurality of diode regions (2) in the central region (97) have a lower density than the plurality of diode regions (2) in the outer peripheral region (96). [13] The semiconductor device (100) according to any one of claims 1 to 12, wherein, in plan view, the bonded area (55) completely covers the plurality of diode regions (2). [14] Semiconductor device (100) according to one of claims 1 to 13, further comprising: • a termination region (4) which is in contact with the insulated gate bipolar transistor region (1) and surrounds the insulated gate bipolar transistor region (1) and the plurality of diode regions (2); and • a protective layer (6) provided on the termination region (4). [15] Semiconductor device (100) according to one of claims 1 to 13, further comprising • a termination region (4) which is in contact with the insulated gate bipolar transistor region (1) and surrounds the insulated gate bipolar transistor region (1) and the plurality of diode regions (2), wherein • a shortest distance (L1) between the termination region (4) and the plurality of diode regions (2) in plan view is equal to or greater than a thickness (H) of the region (1) of the insulated gate bipolar transistor in the direction perpendicular to the front side electrode (10). [16] The semiconductor device (100) according to any one of claims 1 to 15, wherein a shortest distance (L2) between a peripheral edge (98) of the bonded area (55) and the plurality of diode regions (2) in plan view is equal to or greater than a thickness (H) of the insulated gate bipolar transistor region (1) in the direction perpendicular to the front side electrode (10). [17] Semiconductor device (100) according to one of claims 1 to 16, further comprising • a temperature measuring diode (8) which is provided in plan view between any two of the plurality of diode regions (2), wherein • the connected surface (55) covers the temperature measuring diode (8) in the top view.

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