METHOD AND DEVICES FOR CONTROLLING TRANSISTOR SWITCHING

Abstract

An exemplary arrangement comprises: a driver circuit arrangement with one terminal; a capacitor with one terminal; a diode circuit arrangement with a first terminal and a second terminal; a transistor with a first terminal, a second terminal and a control terminal, wherein the first terminal of the transistor is coupled to the first terminal of the diode circuit arrangement, the control terminal of the transistor is coupled to the terminal of the capacitor and the second terminal of the diode circuit arrangement; and a current mirror circuit arrangement with a first terminal and a second terminal, wherein the first terminal of the current mirror circuit arrangement is coupled to the terminal of the driver circuit arrangement, the second terminal of the current mirror circuit arrangement is coupled to the second terminal of the transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims priority to U.S. Patent Application No. 63 / 595,046, provisionally filed on November 1, 2023, and priority to U.S. Patent Application No. 18 / 755,318, filed on June 26, 2024, which are hereby incorporated by reference in their entirety. TECHNICAL FIELD

[0002] This description relates generally to switching and, more particularly, to methods and apparatus for controlling transistor switching. BACKGROUND

[0003] With advances in electronics, systems are capable of operating reliably under increasingly complex operating conditions, such as higher power and higher speeds. Increasingly complex circuitry, driver circuitry implements advanced techniques for regulating the power supply to a load. Such circuitry enables the driver circuitry to precisely control and regulate transistor switching despite complex operating conditions. SUMMARY

[0004] For methods and apparatus for regulating transistor switching, an example apparatus comprises driver circuitry having a terminal; a capacitor having a terminal; diode circuitry having a first terminal and a second terminal; a transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor is coupled to the first terminal of the diode circuitry, wherein the control terminal of the transistor is coupled to the terminal of the capacitor and the second terminal of the diode circuitry; and current mirror circuitry having a first terminal and a second terminal, wherein the first terminal of the current mirror circuitry is coupled to the terminal of the driver circuitry, wherein the second terminal of the current mirror circuitry is coupled to the second terminal of the transistor.Other examples are described.

[0005] For methods and devices for regulating transistor switching, an exemplary device comprises a supply terminal; driver circuitry having a terminal; diode circuitry having a first terminal and a second terminal; current mirror circuitry having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the current mirror circuitry is coupled to the supply terminal and the first terminal of the diode circuitry, wherein the second terminal of the current mirror circuitry is coupled to the second terminal of the diode circuitry;and current scaling circuitry having a first terminal and a second terminal, wherein the first terminal of the current scaling circuitry is coupled to the terminal of the driver circuitry, wherein the second terminal of the current scaling circuitry is coupled to the third terminal of the current mirror circuitry. Other examples are described.

[0006] For methods and devices for regulating transistor switching, an exemplary device comprises a first transistor having a first terminal and a control terminal; a capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is coupled to the first terminal of the first transistor; a second transistor having a first terminal and a control terminal; a current mirror circuit having a first terminal and a second terminal, wherein the first terminal of the current mirror circuit is coupled to the second terminal of the capacitor, the first terminal of the second transistor, and the control terminal of the second transistor;and current scaling circuitry having a first terminal and a second terminal, wherein the first terminal of the current scaling circuitry is coupled to the second terminal of the current mirror circuitry, wherein the second terminal of the current scaling circuitry is coupled to the control terminal of the first transistor. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of an exemplary drive system including gate driver circuitry that uses exemplary current multiplication circuitry and a boost current source for adjusting a drive current to reduce the load on a motor during switching. Fig. 2 is a circuit diagram of the exemplary control system of Fig. 1. Fig. 3 is a circuit diagram of a first configuration of the exemplary control system of Fig. 1 and Fig. 2. Fig. 4 is a circuit diagram of a second configuration of the exemplary control system of Fig. 1, Fig. 2 and Fig. 3. Fig. 5 is a circuit diagram of an example of the current multiplication circuit arrangement of Fig. 1, Fig. 2, Fig. 3 and Fig. 4. Fig. 6 is a flowchart illustrating exemplary operations that may be executed and / or instantiated and / or performed to implement the current multiplication circuitry of Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5 to control a slew rate of a voltage on a transistor. Fig. 7 is a flowchart illustrating exemplary operations that may be executed and / or instantiated and / or performed to control the gate driver circuitry of Fig. 1, Fig. 2, Fig. 3 and Fig. 4 to dynamically adjust a slew rate of a voltage on a transistor. Fig. Figure 8 is a timing diagram of exemplary operations of the gate driver circuitry of Fig. 1, Fig. 2, Fig. 3 and Fig. 4 for controlling the slew rate of a voltage across a transistor.

[0007] The drawings are not necessarily to scale. In general, like reference numerals in the drawing(s) and in this description refer to the same or similar features and / or parts (in terms of function and / or structure). Although the drawings show areas with clear lines and boundaries, some or all of these lines and boundaries may be idealized. In practice, the boundaries or lines may be imperceptible, interlaced, or irregular. DETAILED DESCRIPTION

[0008] With advances in electronics, systems are capable of operating reliably under increasingly complex operating conditions, such as higher power and higher speeds. Increasingly complex circuitry, driver circuitry implements advanced techniques for regulating the power supply to a load. Such circuitry enables the driver circuitry to precisely control and regulate transistor switching despite complex operating conditions.

[0009] When driving direct current (DC) motors, driver circuitry connected to one terminal of the DC motor regulates the power supply to the motor by controlling transistors, while the remaining terminal of the DC motor is connected to ground. A first transistor (called the high-side transistor) controls the power supply from a supply terminal to the motor, and a second transistor (called the low-side transistor) controls the power supply from the motor to a common potential. During operations to drive (e.g., power, move) the motor, the driver circuitry turns the transistors on and off to regulate the power supply to the motor. During a first operation, the driver circuitry turns the first transistor on (e.g., activates it, causes it to conduct current) and turns the second transistor off (e.g.,deactivates it, causing it to conduct no current). In a second operation, the driver circuitry turns off the first transistor and turns on the second transistor.

[0010] By switching between the first and second operations of the transistors, the driver circuitry can regulate the power supply to the motor. In some systems, modifying the ratio of time in the first operation versus time in the second operation allows the driver circuitry to control the motor's operations, such as speed, torque, etc. In such systems, the driver circuitry receives one or more control signals that use pulse-width modulation (PWM) to control the timing of switching between configurations. The one or more control signals control the timing of switching using duty cycles, which represent a ratio between the time the driver circuitry is on (e.g., supplying power) and the time the driver circuitry is off (e.g., not supplying power).Increasing the duty cycle of a control signal increases the power delivered to the motor, thereby increasing the motor's speed or torque. Decreasing the duty cycle of the control signal decreases the power delivered to the motor, thereby decreasing the motor's speed or torque.

[0011] As transistor technologies continue to advance, the speeds at which transistors can switch continue to increase. As transistor switching speeds increase, the time it takes for a transistor to transition between on and off decreases. Such transitions are characterized by a slew rate, which is a rate (e.g., volts per second) that characterizes the change in voltage across the transistor. For example, when switching between a common potential (e.g., 0 volts, ground) and a 400-volt supply, the slew rate characterizes the rate at which the drain-to-source voltage across a transistor either increases or decreases.

[0012] In some systems, the driver circuitry adjusts the transistor's slew rate by controlling a current at a gate terminal of the transistor (called the gate drive current). The transistor's slew rate increases as the gate drive current increases. However, in some systems, such as motor control, increasing the transistors' slew rate increases the stress placed on motor components during switching. To regulate the gate drive current, which regulates the slew rate, some driver circuitry includes a capacitor (called a high-voltage capacitor) with a relatively large capacitance between the transistor's gate and drain terminals. To support switching at increasingly higher voltages, the capacitor's capacitance continues to increase.The capacitor uses portions of the gate drive current to compensate for changes in the transistor's voltage, thereby reducing the gate drive current. However, as switching voltages and currents continue to increase, the capacitor's capacitance continues to increase, increasing the size of the system-on-chip (SoC) driver circuitry.

[0013] Examples described herein include methods and apparatus for regulating transistor switching. In some described examples, gate driver circuitry generates and controls a gate drive current to regulate a slew rate of a voltage change across a transistor during a switching operation. The gate driver circuitry includes current multiplication circuitry coupled to the transistor through a relatively small capacitor. When switching begins, the gate driver circuitry supplies a first gate drive current to the gate of the transistor using first and second current source circuitry. Once the gate drive current activates the transistor (e.g., turns it on, causes it to conduct), the capacitor begins to source current from the current multiplication circuitry in response to a change in the voltage across the transistor.The current multiplication circuitry mirrors and scales the current supplied to the capacitor. The current multiplication circuitry derives the scaled current from the gate drive current, thereby mimicking a relatively large capacitance coupled between the gate and drain of the transistor. Advantageously, the current multiplication circuitry uses a capacitor with a relatively small capacitance to mimic a relatively large capacitance coupled between the gate and drain of the transistor. Advantageously, the current multiplication circuitry prevents excessively high slew rates of the transistor from stressing a load by limiting the slew rate.

[0014] Also described herein are examples in which the gate drive circuitry includes first and second current source circuitry, charging circuitry, capacitor circuitry, and comparator circuitry. The first and second current source circuitry generate the gate drive current in response to a control signal from external circuitry. The charging circuitry charges capacitors of the capacitor circuitry. In some examples, the capacitor circuitry includes a set of first capacitors and a set of second capacitors, with the charging circuitry structured to charge them. When charging, the set of capacitors generates a switching voltage. When not charged, the capacitors provide a reference voltage.In example operations, the charging circuitry is structured to charge one of the set of capacitors and use the other of the sets of capacitors to provide the reference voltage. For example, the charging circuitry may charge the set of first capacitors to generate the switching voltage and use the set of second capacitors to provide the reference voltage. The comparator circuitry compares the switching voltage to the reference voltage. The comparator circuitry controls the second current source circuitry in response to the comparison of the switching voltage to the reference voltage. In some examples, once the switching voltage becomes greater than the reference voltage, the comparator circuitry disables the second current source circuitry, thereby reducing the gate drive current and the slew rate of the transistor.

[0015] Advantageously, the gate driver circuitry described herein comprises circuitry for adjusting the slew rate of the transistor during switching operations. Advantageously, the use of a relatively high slew rate increases power efficiency, and the use of a relatively low slew rate reduces the stress on a load. Advantageously, the gate driver circuitry initially sets the transistor to a relatively high slew rate before reducing the gate drive current to reduce the slew rate. Advantageously, switching between different slew rates increases power efficiency without excessively stressing the load.

[0016] Fig. 1 is a block diagram of an exemplary control system 100. In the example of Fig. 1, the control system 100 includes an exemplary driver circuitry 105 and an exemplary motor 110. The driver circuitry 105 of Fig. 1 includes an exemplary power stage circuitry 115, an exemplary high-side gate driver circuitry 120, and an exemplary low-side gate driver circuitry 125. The low-side gate driver circuitry 125 of Fig. 1 includes a first example current source circuitry 130, a second example current source circuitry 135, an example capacitor 140, an example current multiplication circuitry 145, an example charging circuitry 150, an example capacitor circuitry 155, an example multiplexer circuitry 160, an example control circuitry 165, and an example comparator circuitry 170.

[0017] The driver circuitry 105 is coupled to the motor 110. In some examples, the driver circuitry 105 is coupled to an external signal source, e.g., programmable circuitry structured to provide one or more control signals. Examples of the driver circuitry 105 are described below in connection with Fig. 2, Fig. 3, Fig. 4 and Fig. 5 further illustrated and described. Although in the example of Fig. 1, the driver circuitry 105 includes the gate driver circuitry 120, 125 and the power stage circuitry 115, in other examples the power stage circuitry 115 may be external to the driver circuitry 105.

[0018] The motor 110 has a first terminal and a second terminal. The first terminal of the motor 110 is coupled to the driver circuitry 105. The second terminal of the motor 110 is coupled to a common terminal that provides a common potential (e.g., ground). In some examples, the motor 110 is physically coupled to an external system. For example, in automotive systems, the motor 110 is mechanically coupled to a wheel. In industrial systems, the motor 110 is mechanically coupled to one or more components to drive operations such as manufacturing. In the example of Fig. 1, the motor 110 is a direct current (DC) motor. Alternatively, the control system 100 can be Fig. 1 to replace the motor 110 with a stepper motor or another type of motor. Although in the example of Fig. 1 the driver circuitry 105 is structured to supply power to the motor 110, the driver circuitry 105 may be coupled to any type of load.

[0019] The power stage circuitry 115 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first and second terminals of the power stage circuitry 115 are coupled to the gate driver circuitry 120. The third and fourth terminals of the power stage circuitry 115 are coupled to the gate driver circuitry 125. The fifth terminal of the power stage circuitry 115 is coupled to the motor 110. Examples of the power stage circuitry 115 are described below in connection with Fig. 2, Fig. 3, Fig. 4 and Fig. 5 shown and described.

[0020] The gate driver circuitry 120 has a first terminal, a second terminal, and a third terminal. The first and second terminals of the gate driver circuitry 120 are coupled to the power stage circuitry 115. The third terminal of the gate driver circuitry 120 may be coupled to external circuitry structured to generate a high-side control signal (PWM HI ). The low-side control signal is a PWM signal that controls the switching of the power stage circuitry 115.

[0021] The gate driver circuitry 125 has a first terminal, a second terminal, and a third terminal. The first and second terminals of the gate driver circuitry 125 are coupled to the power stage circuitry 115. The third terminal of the gate driver circuitry 125 may be coupled to external circuitry structured to generate a low-side control signal (PWM LOW ). The low-side control signal is a PWM signal that controls the switching of the power stage circuitry 115. Examples of the gate driver circuitry 125 are described below in connection with Fig. 2, Fig. 3, Fig. 4 and Fig. 5 shown and described.

[0022] The current source circuitry 130 has a first terminal and a second terminal. The first terminal of the current source circuitry 130 is coupled to the current source circuitry 135, the control circuitry 165, and may be coupled to external circuitry structured to provide the low-side control signal. The second terminal of the current source circuitry 130 is coupled to the power stage circuitry 115, the current source circuitry 135, and the current multiplication circuitry 145. Examples of the current source circuitry 130 are described below in connection with Fig. 2, Fig. 3, Fig. 4 and Fig. 5 shown and described.

[0023] The current source circuitry 135 has a first terminal, a second terminal, and a control terminal. The first terminal of the current source circuitry 135 is coupled to the current source circuitry 130, the control circuitry 165, and may be coupled to external circuitry structured to provide the low-side control signal. The second terminal of the current source circuitry 135 is coupled to the power stage circuitry 115, the current source circuitry 130, and the current multiplication circuitry 145. The control terminal of the current source circuitry 135 is coupled to the comparator circuitry 170. An example of the current source circuitry 135 is described below in connection with Fig. 2, Fig. 3 and Fig. 4 shown and described.

[0024] The capacitor 140 has a first terminal and a second terminal. The first terminal of the capacitor 140 is coupled to the power stage circuitry 115. The second terminal of the capacitor 140 is coupled to the current multiplication circuitry 145 and the charging circuitry 150. Examples of the capacitor 140 are described below in connection with Fig. 2, Fig. 3, Fig. 4 and Fig. 5 shown and described.

[0025] The current multiplication circuitry 145 has a first terminal, a second terminal, and a third terminal. The first terminal of the current multiplication circuitry 145 is coupled to the power stage circuitry 115 and the current source circuitry 130, 135. The second terminal of the current multiplication circuitry 145 is coupled to the charging circuitry 150. The third terminal of the current multiplication circuitry 145 is coupled to the capacitor 140 and the charging circuitry 150. Examples of the current multiplication circuitry 145 are described below in connection with Fig. 2, Fig. 3, Fig. 4 and Fig. 5 shown and described.

[0026] The charging circuitry 150 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of the charging circuitry is coupled to the capacitor 140 and the current multiplication circuitry 145. The second terminal of the charging circuitry 150 is coupled to the current multiplication circuitry 145. The third and fourth terminals of the charging circuitry 150 are coupled to the capacitor circuitry 155. The fifth and sixth terminals of the charging circuitry 150 are coupled to the multiplexer circuitry 160 and the control circuitry 165. An example of the charging circuitry is described below in connection with Fig. 2, Fig. 3 and Fig. 4 shown and described.

[0027] The capacitor circuit arrangement 155 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first and second terminals of the capacitor circuit arrangement 155 are coupled to the charging circuit arrangement 150. The third, fourth, fifth, and sixth terminals of the capacitor circuit arrangement 155 are coupled to the multiplexer circuit arrangement 160. An example of the capacitor circuit arrangement 155 is described below in connection with Fig. 2, Fig. 3 and Fig. 4 shown and described.

[0028] The multiplexer circuitry 160 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, and an eighth terminal. The first, second, third, and fourth terminals of the multiplexer circuitry 160 are coupled to the capacitor circuitry 155. The fifth and sixth terminals of the multiplexer circuitry 160 are coupled to the charging circuitry 150 and the control circuitry 165. The seventh and eighth terminals of the multiplexer circuitry 160 are coupled to the comparator circuitry 170. An example of the multiplexer circuitry 160 and configurations of the multiplexer circuitry 160 is described below in connection with Fig. 2, Fig. 3 and Fig. 4 shown and described.

[0029] The control circuitry 165 has a first terminal, a second terminal, and a third terminal. The first terminal of the control circuitry 165 is coupled to the current source circuitry 130, 135 and may be coupled to external circuitry structured to provide the low-side control signal. The second and third terminals of the control circuitry 165 are coupled to the charging circuitry 150 and the multiplexer circuitry 160, respectively. An example of the control circuitry 165 is described below in connection with Fig. 2 shown and described.

[0030] The comparator circuitry 170 has a first terminal, a second terminal, and an output terminal. The first and second terminals of the comparator circuitry 170 are coupled to the multiplexer circuitry 160. The output terminal of the comparator circuitry 170 is coupled to the current source circuitry 135. An example of the comparator circuitry 170 is described below in connection with Fig. 2, Fig. 3 and Fig. 4 shown and described.

[0031] In exemplary operations of drive system 100, driver circuitry 105 receives the high-side and low-side control signals from external circuitry structured to control driver circuitry 105. In some examples, the external circuitry controls the operations of motor 110 in response to adjusting the control signals. For example, increasing the duty cycle of the high-side control signal and decreasing the duty cycle of the low-side control signals increases the amount of power supplied to motor 110. In such an example, motor 110 provides additional mechanical energy in response to the increase in power from driver circuitry 105.

[0032] In example operations of driver circuitry 105, gate driver circuitry 120, 125 independently controls the switching of power stage circuitry 115. In some examples, power stage circuitry 115 supplies power to motor 110 in response to current from high-side gate driver circuitry 120. In such examples, power stage circuitry 115 discharges energy from motor 110 in response to low-side gate driver circuitry 125 sinking current from motor 110. In response to the transition of gate driver circuitry 125 from supplying current to sinking current from motor 110, currents through motor 110 quickly change direction, stressing the electrical components of motor 110. In the example of Fig. 1, gate driver circuitry 125 reduces the amount of stress applied to motor 110 during switching operations by using current multiplication circuitry 145 and current source circuitry 135 to control the gate drive current that controls switching. Exemplary operations of gate driver circuitry 125 to reduce the stress on motor 110 and increase power efficiency are described in conjunction with the night vision Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, and Fig. 7 described.

[0033] Fig. 2 is a circuit diagram of an exemplary drive system 200, which is an example of the drive system 100 of Fig. 1. In the example of Fig. 2, the control system 200 includes an exemplary driver circuitry 202 and an exemplary load 204. The exemplary driver circuitry 202 of Fig. 2 includes an exemplary power stage circuitry 206, an exemplary high-side gate driver circuitry 208, and an exemplary low-side gate driver circuitry 210. The exemplary power stage circuitry 206 of Fig. 2 includes a first exemplary transistor 214 and a second exemplary transistor 216. The exemplary low-side gate driver circuitry 210 of Fig. 2 includes a first example current source circuitry 218, a second example current source circuitry 220, a first example capacitor 222, an example current multiplication circuitry 224, an example charging circuitry 226, an example capacitor circuitry 228, an example multiplexer circuitry 230, an example control circuitry 232, and an example comparator circuitry 233.

[0034] The exemplary current multiplication circuitry 224 of Fig. 2 includes a third exemplary transistor 234, a fourth exemplary transistor 236, a fifth exemplary transistor 238, and a sixth exemplary transistor 240. The exemplary charging circuitry 226 of Fig. 2 includes a seventh exemplary transistor 242, a first exemplary switch 244, an eighth exemplary transistor 246, and a second exemplary switch 248. The exemplary capacitor circuit arrangement 228 of Fig. 2 includes a second exemplary capacitor 250, a third exemplary capacitor 252, a fourth exemplary capacitor 254, and a fifth exemplary capacitor 256. The exemplary multiplexer circuitry 230 of Fig. 2 includes a third exemplary switch 258, a fourth exemplary switch 260, a fifth exemplary switch 262, and a sixth exemplary switch 264. The exemplary control circuitry 232 of Fig. 2 includes a first exemplary inverter 266, an exemplary buffer 268, an exemplary flip-flop 270, and a second exemplary inverter 272.

[0035] Driver circuitry 202 is coupled to load 204. Driver circuitry 202 may be coupled to external circuitry structured to provide the high-side control signals and the low-side control signals. Driver circuitry 202 is an example of driver circuitry 105 of Fig. 1. The load 204 is coupled to the driver circuitry 202. In some examples, the load 204 may be mechanically or electrically coupled to one or more components. In some examples, the load 204 represents the motor 110 of Fig. 1.

[0036] The power stage circuitry 206 is coupled to the load 204 and the gate driver circuitry 208, 210. The power stage circuitry 206 is an example of the power stage circuitry 115 of Fig. 1. Gate driver circuitry 208 is coupled to power stage circuitry 206 and may be coupled to external circuitry structured to provide the high-side supply signal. Gate driver circuitry 208 is an example of gate driver circuitry 120 of Fig. 1. Gate driver circuitry 210 is coupled to power stage circuitry 206 and may be coupled to external circuitry structured to provide the low-side control signal. Gate driver circuitry 210 is an example of gate driver circuitry 125 of Fig. 1.

[0037] Transistor 214 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 214 is coupled to a first supply terminal that supplies a first supply voltage (V SUP_1). The second and third terminals of transistor 214 are coupled to load 204, gate driver circuitry 210, and transistor 216. In some examples, the third terminal of transistor 214 is referred to as a bulk terminal. The control terminal of transistor 214 is coupled to gate driver circuitry 208. In some examples, transistor 214 is referred to as a high-side transistor, which supplies the first supply voltage to load 204 based on a high-side drive current from gate driver circuitry 208.

[0038] Transistor 216 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of transistor 216 is coupled to load 204, gate driver circuitry 210, and transistor 214. The second and third terminals of transistor 216 are coupled to a common terminal that provides a common potential (e.g., ground, AVSS, etc.). In some examples, the third terminal of transistor 214 is referred to as the bulk terminal. The control terminal of transistor 216 is coupled to gate driver circuitry 210. In some examples, transistor 216 is referred to as a low-side transistor, providing a current path to the common potential based on a low-side drive current from gate driver circuitry 210.

[0039] Current source circuitry 218 is coupled to power stage circuitry 206, current source circuitry 220, current multiplication circuitry 224, and control switching circuitry 232, and may be coupled to external circuitry structured to provide the low-side control signal. Current source circuitry 218 is an example of current source circuitry 130 of Fig. 1. Current source circuitry 220 is coupled to power stage circuitry 206, current source circuitry 218, current multiplication circuitry 224, control switching circuitry 232, comparator circuitry 233, and may be coupled to external circuitry structured to provide the low-side control signal. Current source circuitry 220 is an example of current source circuitry 135 of Fig. 1.

[0040] Capacitor 222 has a first terminal and a second terminal. A first terminal of capacitor 222 is coupled to load 204 and transistors 214, 216. The second terminal of capacitor 222 is coupled to current multiplication circuitry 224 and charging circuitry 226. Capacitor 222 is an example of capacitor 140 of Fig. 1. The current multiplication circuitry 224 is coupled to the power stage circuitry 206, the current source circuitry 218, 220, the capacitor 222, and the charging circuitry 226. The current multiplication circuitry 224 is an example of the current multiplication circuitry 145 of Fig. 1. Another example of the current multiplication circuitry 145, 224 is described below in connection with Fig. 5 shown and described.

[0041] In some examples, capacitor 222 has a capacitance proportional to a gate-to-drain capacitance (Cgd) of transistor 216. In such examples, current multiplication circuitry 224 uses capacitor 222 to compensate for transistor 216 having a relatively low gate-to-drain capacitance, such as when transistor 216 is a gallium nitride (GaN) substrate transistor. Advantageously, current multiplication circuitry 224 compensates for a relatively low gate-to-drain capacitance of transistor 216 using capacitor 222.

[0042] The charging circuitry 226 is coupled to the capacitor 222, the current multiplication circuitry 224, the capacitor circuitry 228, the multiplexer circuitry 230, and the control circuitry 232. The charging circuitry 226 is an example of the charging circuitry 150 of Fig. 1. Capacitor 228 is coupled to charging circuitry 226 and multiplexer circuitry 230. Capacitor circuitry 228 is an example of capacitor circuitry 155 of Fig. 1. The multiplexer circuitry 230 is coupled to the charging circuitry 226, the capacitor circuitry 228, the control circuitry 232, and the comparator circuitry 233. The multiplexer circuitry 230 is an example of the multiplexer circuitry 160 of Fig. 1. The control circuitry 232 is coupled to the current source circuitry 130, 135, the charging circuitry 150, the multiplexer circuitry 160, and may be coupled to external circuitry structured to provide the low-side control signal. The control circuitry 232 is an example of the control circuitry 165 of Fig. 1. The comparator circuitry 233 is coupled to the current source circuitry 220 and the multiplexer circuitry 230. The comparator circuitry 233 is an example of the comparator circuitry 170 of Fig. 1.

[0043] Transistor 234 has a first terminal, a second terminal, a third terminal, and a control terminal. The first and second terminals of transistor 234 are coupled to a second supply terminal that supplies a second supply voltage (V SUP_2). In some examples, the second supply voltage is less than the first supply voltage. In such examples, the second supply voltage enables the gate driver circuitry 210 to use relatively lower voltage transistors that can switch at higher speeds. In some examples, the second terminal of transistor 234 is referred to as the bulk terminal. The third terminal and the control terminal of transistor 234 are coupled to capacitor 222, charging circuitry 226, and transistor 236. In the example of Fig. 2, transistor 234 is structured as a diode circuit that regulates the direction of the current supplied to capacitor 222. In some examples, transistor 234 is illustrated and described as a diode circuit. Alternatively, current multiplication circuitry 224 may be modified to replace or represent transistor 234 using a diode circuit.

[0044] Transistor 236 has a first terminal, a second terminal, a third terminal, and a control terminal. The first and second terminals of transistor 236 are coupled to the second supply terminal, which provides the second supply voltage. In some examples, the second terminal of transistor 236 is referred to as the bulk terminal. The third terminal of transistor 236 is coupled to transistors 238, 240. The control terminal of transistor 236 is coupled to capacitor 222, charging circuitry 226, and transistor 234. In the example of Fig. 2, transistor 236 is structured as a current mirror circuit. In some examples, transistor 236 mirrors the current flowing through transistor 234. Alternatively, current multiplication circuitry 224 may be modified to replace or represent one or both transistors 234, 236 as a current mirror circuit.

[0045] Transistor 238 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal and the control terminal of transistor 238 are coupled to transistors 236, 240. The second and third terminals of transistor 238 are coupled to the common terminal, which provides the common potential. In some examples, the third terminal of transistor 238 is referred to as the bulk terminal. In the example of Fig. 2, transistor 238 is structured as a current mirror circuit. In some examples, transistor 238 mirrors the current flowing through transistor 236. Alternatively, current multiplication circuitry 224 may be modified to replace or represent transistor 238 as a current mirror circuit.

[0046] Transistor 240 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 240 is coupled to transistor 216 and current source circuitry 218, 220. The second and third terminals of transistor 240 are coupled to the common terminal, which provides the common potential. In some examples, the third terminal of transistor 240 is referred to as the bulk terminal. The control terminal of transistor 240 is coupled to transistors 236, 238. In the example of Fig. 2, transistor 240 is structured as current scaling circuitry. In some examples, transistor 240 scales the current flowing through transistor 238. Alternatively, current multiplication circuitry 224 may be modified to replace or represent one or both of transistors 238, 240 as current scaling circuitry.

[0047] Transistor 242 has a first terminal, a second terminal, a third terminal, and a control terminal. The first and second terminals of transistor 242 are coupled to the second supply terminal, which provides the second supply voltage. In some examples, the second terminal of transistor 242 is referred to as the bulk terminal. The third terminal of transistor 242 is coupled to switch 244. The control terminal of transistor 242 is coupled to capacitor 222, current multiplication circuitry 224, and transistor 246. In the example of Fig. 2, transistor 242 is structured as control circuitry that, when enabled, supplies current to switch 244. Alternatively, current multiplication circuitry 224 may be modified to replace or represent transistor 242 as control circuitry.

[0048] Switch 244 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 244 is coupled to transistor 242. The second terminal of switch 244 is coupled to capacitor circuitry 228. The control terminal of switch 244 is coupled to multiplexer circuitry 230 and control circuitry 232.

[0049] Transistor 246 has a first terminal, a second terminal, a third terminal, and a control terminal. The first and second terminals of transistor 246 are coupled to the second supply terminal, which provides the second supply voltage. In some examples, the second terminal of transistor 246 is referred to as a bulk terminal. The third terminal of transistor 246 is coupled to capacitor circuitry 228. The control terminal of transistor 246 is coupled to capacitor 222, current multiplication circuitry 224, and transistor 242. In the example of Fig. 2, transistor 246 is structured as control circuitry that, when enabled, supplies current to switch 248. Alternatively, current multiplication circuitry 224 may be modified to replace or represent transistor 246 as control circuitry.

[0050] The switch 248 has a first terminal, a second terminal, and a control terminal. The first terminal of the switch 248 is coupled to the transistor 246. The second terminal of the switch 248 is coupled to the capacitor circuitry 228. The control terminal of the switch 248 is coupled to the multiplexer circuitry 230 and the control circuitry 232. In some examples, the switches 244, 248 are implemented using transistors. In other examples, the charging circuitry 226 can be modified to implement the switches 244, 248 as switching circuitry or in combination with the transistors 242, 246.

[0051] Capacitor 250 has a first terminal and a second terminal. The first terminal of capacitor 250 is coupled to charging circuitry 226 and multiplexer circuitry 230. The second terminal of capacitor 250 is coupled to charging circuitry 226, multiplexer circuitry 230, and capacitor 254. Capacitor 252 has a first terminal and a second terminal. The first terminal of capacitor 252 is coupled to charging circuitry 226 and multiplexer circuitry 230. The second terminal of capacitor 252 is coupled to charging circuitry 226, multiplexer circuitry 230, and capacitor 256.

[0052] Capacitor 254 has a first terminal and a second terminal. The first terminal of capacitor 254 is coupled to multiplexer circuitry 230 and capacitor 250. The second terminal of capacitor 254 is coupled to the common terminal, which provides the common potential. Capacitor 256 has a first terminal and a second terminal. The first terminal of capacitor 256 is coupled to multiplexer circuitry 230 and capacitor 252. The second terminal of capacitor 256 is coupled to the common terminal, which provides the common potential.

[0053] In the example of Fig. 2, the capacitors 250, 254 are referred to as a set of first capacitors 250, 254, and the capacitors 252, 256 are referred to as a set of second capacitors 252, 256. When the charging circuitry 226 is structured to charge the set of first capacitors 250, 254 (as described in more detail below), the set of first capacitors 250, 254 generates a switching voltage at the first terminal of the capacitor 250. When the charging circuitry 226 is not structured to charge the set of first capacitors 250, 254 (as described in more detail below), the set of first capacitors 250, 254 provides a reference voltage at the second terminal of the capacitor 250 and the first terminal of the capacitor 254.

[0054] Likewise, when the charging circuitry 226 is structured to charge the set of second capacitors 252, 256, the set of second capacitors 252, 256 generates the switching voltage at the first terminal of the capacitor 252. Furthermore, when the charging circuitry 226 is structured to discharge the set of second capacitors 252, 256, the set of second capacitors 252, 256 generates the reference voltage at the second terminal of the capacitor 252 and at the first terminal of the capacitor 256. Advantageously, the charging circuitry 226 can cause either the set of first capacitors 250, 254 or the set of second capacitors 252, 256 to generate either the reference voltage or the switching voltage. Advantageously, the reference voltage represents a discharge of the capacitor circuitry 228, and the switching voltage represents a charging of the capacitor circuitry 228.

[0055] The switch 258 has a first terminal, a second terminal, and a control terminal. The first terminal of the switch 258 is coupled to the charging circuitry 226 and the capacitor circuitry 228. The second terminal of the switch 258 is coupled to the switch 260 and the comparator circuitry 233. The control terminal of the switch 258 is coupled to the charging circuitry 226, the control circuitry 232, and the switch 262. The switch 258 is structured to receive the switching voltage from the set of second capacitors 252, 256.

[0056] Switch 260 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 260 is coupled to charging circuitry 226 and capacitor circuitry 228. The second terminal of switch 260 is coupled to switch 258 and comparator circuitry 233. The control terminal of switch 260 is coupled to charging circuitry 226, control circuitry 232, and switch 264. Switch 260 is structured to receive the switching voltage from the set of first capacitors 250, 254.

[0057] Switch 262 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 262 is coupled to capacitor circuitry 228. The second terminal of switch 262 is coupled to switch 264 and comparator circuitry 233. The control terminal of switch 262 is coupled to charging circuitry 226, control circuitry 232, and switch 258. Switch 262 is structured to receive the reference voltage from the set of first capacitors 250, 254.

[0058] Switch 264 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 264 is coupled to capacitor circuitry 228. The second terminal of switch 264 is coupled to switch 262 and comparator circuitry 233. The control terminal of switch 264 is coupled to charging circuitry 226, control circuitry 232, and switch 260. Switch 264 is structured to receive the reference voltage from the set of second capacitors 252, 256.

[0059] The inverter 266 has a first terminal and a second terminal. The first terminal of the inverter 266 is coupled to the current source circuitry 218, 220 and may be coupled to the external circuitry structured to provide the low-side control signal. A second terminal of the inverter 266 is coupled to the flip-flop 270. In the example of Fig. 2, inverter 266 is structured to invert the low-side control signal. Alternatively, control circuitry 232 may be modified to receive an inverted replica of the low-side control signal. In such an example, control circuitry 232 may be modified to remove inverter 266. Buffer 268 has a first terminal and a second terminal. The first terminal of buffer 268 is coupled to a reset terminal that provides a reset signal. A second terminal of buffer 268 is coupled to flip-flop 270. In the example of Fig. 2, the buffer 268 is structured to have a propagation delay approximately equal to a propagation delay of the inverter 266.

[0060] Flip-flop 270 has a clock terminal (CLK), a clear terminal (CLR), a data terminal (D), an output terminal (Q), and an inverted output terminal (QZ). The clock terminal of flip-flop 270 is coupled to inverter 266. The clear terminal of flip-flop 270 is coupled to buffer 268. The data terminal of flip-flop 270 is coupled to the inverted output terminal of flip-flop 270. The output terminal of flip-flop 270 is coupled to load circuitry 226, multiplexer circuitry 230, and inverter 272. In the example of Fig. 2, flip-flop 270 is a data (D) flip-flop. Alternatively, control circuitry 232 can be modified to use an alternative type of flip-flop. Flip-flop 270 is structured as a divider circuit that generates a first switching signal by dividing the frequency of the low-side control signal. Flip-flop 270 uses the first switching signal to control switches 248, 258, and 262.

[0061] Inverter 272 has a first terminal and a second terminal. The first terminal of inverter 272 is coupled to charging circuitry 226, multiplexer circuitry 230, and flip-flop 270. The second terminal of inverter 272 is coupled to charging circuitry 226 and multiplexer circuitry 230. Inverter 272 is structured to generate a second switching signal by inverting the first switching signal from flip-flop 270. Inverter 272 uses the second switching signal to control switches 244, 260, 264.

[0062] During example operations of drive system 200, gate driver circuitry 210 controls transistor 216 in response to receiving the low-side control signal. During example operations to turn on transistor 216 (e.g., enable, conduct, etc.), control circuitry 232 uses the first and second switching signals to structure charging circuitry 226 and multiplexer circuitry 230 to support multiple-slew turn-on of transistor 216. In some such operations, gate driver circuitry 210 uses a first current to drive transistor 216 for a first period of time.However, in response to comparator circuitry 233 determining that the switching voltage from capacitor circuitry 228 is greater than or equal to the reference voltage from capacitor circuitry 228, comparator circuitry 233 deactivates current source circuitry 220. Following such a determination, gate driver circuitry 210 uses a second current that is less than the first current to drive transistor 216. Advantageously, during the first time period, the current through transistor 216 has a relatively high slew rate, thereby increasing power efficiency, and after the first time period, the current through transistor 216 has a relatively low slew rate, thereby reducing the stress on components of load 204. Advantageously, the initial use of a relatively high slew rate improves power efficiency during switching operations.

[0063] Fig. 3 is a circuit diagram of a first configuration of the exemplary control system 200 of Fig. 2, which is an example of the control system 100 of Fig. 1. In the example of Fig. 3, the drive system 200 is structured to generate a reference voltage using the set of first capacitors 250, 254 of Fig. 2 and a switching voltage by charging the set of second capacitors 252, 256 of Fig. 2. In such exemplary operations, the control circuitry 232 of Fig. 2 the switches 244, 260, 264 of Fig. 2 and closes the switches 248, 258, 262 of Fig. 2. In the first configuration of Fig. 3 controls the comparator circuit arrangement 233 of Fig. 2 the current source circuit arrangement 220 of Fig. 2 in response to a comparison of the reference voltage from the set of first capacitors 250, 254 with the switching voltage from the set of second capacitors 252, 256.

[0064] Fig. 4 is a circuit diagram of a second configuration of the exemplary control system 200 of Fig. 2, which is an example of the control system 100 of Fig. 1. In the example of Fig. 4, the drive system 200 is structured to generate a switching voltage by charging the set of first capacitors 250, 254 from Fig. 2 and to generate a reference voltage using the set of second capacitors 252, 256 of Fig. 2. In such exemplary operations, the control circuitry 232 of Fig. 2 the switches 244, 260, 264 of Fig. 2 and opens switches 248, 258, 262 of Fig. 2. In the second configuration of Fig. 4 controls the comparator circuit arrangement 233 of Fig. 2 the current source circuit arrangement 220 of Fig. 2 in response to a comparison of the switching voltage from the set of first capacitors 250, 254 with the reference voltage from the set of second capacitors 252, 256.

[0065] In the example of Fig. 2, Fig. 3 and Fig. 4, transistors 214, 216, 238, and 240 are n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, transistors 214, 216, 238, and 240 may be n-channel field-effect transistors (FETs), n-channel insulated-gate bipolar transistors (IGBTs), n-channel junction field-effect transistors (JFETs), NPN bipolar transistors (BJTs), or, with minor modifications, equivalent p-type devices. In the example of Fig. 2, Fig. 3 and Fig. 4, transistors 234, 236, 242, and 246 are p-channel MOSFETs. Alternatively, transistors 234, 236, 242, and 246 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, NPN BJTs, or, with minor modifications, equivalent n-type devices. Transistors 214, 216, 234, 236, 238, 240, 242, and 246 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the transistors 214, 216, 234, 236, 238, 240, 242, 246 may be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0066] Fig. 5 is a circuit diagram of an exemplary drive system 500, which is another example of the drive systems 100, 200 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4, which is another example of the current multiplication circuitry 145, 224 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4. In the example of Fig. 5, the control system 500 includes an exemplary driver circuitry 502 and an exemplary load 504. The driver circuitry 502 of Fig. 5 includes an exemplary power stage circuitry 506, an exemplary high-side gate driver circuitry 508, and an exemplary low-side gate driver circuitry 510. The power stage circuitry 506 of Fig. 5 includes a first exemplary transistor 514 and a second exemplary transistor 516.

[0067] The exemplary low-side gate driver circuitry 510 of Fig. 5 includes an exemplary current source circuitry 518, an exemplary capacitor 522, and an exemplary current multiplication circuitry 524. The current multiplication circuitry 524 of Fig. 5 includes a first exemplary resistor 532, a third exemplary transistor 534, a fourth exemplary transistor 536, a fifth exemplary transistor 538, a sixth exemplary transistor 540, a seventh exemplary transistor 542, a second exemplary resistor 543, an eighth exemplary transistor 544, a first exemplary diode 546, a third exemplary transistor 548, a ninth exemplary transistor 550, a first exemplary inverter 552, a second exemplary inverter 554, a tenth exemplary transistor 556, a fourth exemplary resistor 557, an eleventh exemplary transistor 558, a fifth exemplary resistor 560, a twelfth exemplary transistor 562, a second exemplary diode 564, a thirteenth exemplary transistor 566, and a fourteenth exemplary transistor 568. In the example of Fig. 5, the gate driver circuitry 510 implements single slew rate switching using the current source circuitry 518. Alternatively, the gate driver circuitry 510 may be modified to implement multiple slew rate switching, as shown in Fig. 2, Fig. 3 and Fig. 4 shown.

[0068] Driver circuitry 502 is coupled to load 504. Driver circuitry 502 may be coupled to external circuitry structured to provide the high-side control signals and the low-side control signals. Driver circuitry 502 is an alternative example of the driver circuitry 105, 202 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4. In the example of Fig. 5, driver circuitry 502 includes current multiplication circuitry 524, which further includes circuitry for reducing a quiescent current during times when transistor 516 is off. Load 504 is coupled to driver circuitry 502. In some examples, load 504 may be mechanically or electrically coupled to one or more components. Load 504 is another example of motor 110 of Fig. 1 and the load 204 of Fig. 2, Fig. 3 and Fig. 4.

[0069] The power stage circuitry 506 is coupled to the load 504 and the gate driver circuitry 508, 510. The power stage circuitry 506 is another example of the power stage circuitry 115, 206 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4. Gate driver circuitry 508 is coupled to power stage circuitry 506 and may be coupled to external circuitry structured to provide the high-side supply signal. Gate driver circuitry 508 is another example of gate driver circuitry 120, 208 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4. Gate driver circuitry 510 is coupled to power stage circuitry 506 and may be coupled to external circuitry structured to provide the low-side control signal. Gate driver circuitry 510 is an example of gate driver circuitry 125, 210 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4.

[0070] Transistor 514 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 514 is coupled to the first supply terminal, which supplies the first supply voltage (V SUP_1 ). The second and third terminals of transistor 514 are coupled to load 504, gate driver circuitry 510, and transistor 516. In some examples, the third terminal of transistor 514 is referred to as a bulk terminal. The control terminal of transistor 514 is coupled to gate driver circuitry 508. In some examples, transistor 514 is referred to as a high-side transistor, which provides the supply voltage to load 504 based on a high-side drive current from gate driver circuitry 508. Transistor 514 is an example of transistor 214 of Fig. 2, Fig. 3 and Fig. 4.

[0071] Transistor 516 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 516 is coupled to load 504, gate driver circuitry 510, and transistor 514. The second and third terminals of transistor 516 are coupled to the common terminal, which provides the common potential. In some examples, the third terminal of transistor 514 is referred to as the bulk terminal. The control terminal of transistor 516 is coupled to gate driver circuitry 510. In some examples, transistor 516 is referred to as a low-side transistor, which provides a current path to the common potential based on a low-side drive current from gate driver circuitry 510. Transistor 516 is an example of transistor 216 of Fig. 2, Fig. 3 and Fig. 4.

[0072] Current source circuitry 518 is coupled to power stage circuitry 506, current multiplication circuitry 524, and may be coupled to external circuitry structured to provide the low-side control signal. Current source circuitry 518 is another example of the current source circuitry 130, 218 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4. Capacitor 522 has a first terminal and a second terminal. A first terminal of capacitor 522 is coupled to load 504 and transistors 514, 516. The second terminal of capacitor 522 is coupled to current multiplication circuitry 524. Capacitor 522 is another example of capacitors 140, 222 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4.

[0073] Current multiplication circuitry 524 is coupled to power stage circuitry 506, current source circuitry 518, capacitor 522, and external circuitry structured to provide the low-side control signal. Current multiplication circuitry 524 is another example of the current multiplication circuitry 145, 224 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4. In the example of Fig. 5, the current multiplication circuitry 524 includes additional circuitry that reduces the quiescent current by disabling components when the transistor 516 is off.

[0074] In some examples, capacitor 522 has a capacitance proportional to a non-ideal gate-drain capacitance of transistor 516. In such examples, current multiplication circuitry 524 is structured to use capacitor 522 to compensate for transistor 516 having a relatively low gate-drain capacitance, such as when transistor 516 is a gallium nitride (GaN) substrate transistor. Advantageously, current multiplication circuitry 524 is structured to compensate for a relatively low gate-drain capacitance of transistor 516 using a relatively small capacitance.

[0075] The resistor 532 has a first terminal and a second terminal. The first terminal of the resistor 532 is coupled to the second supply terminal, which supplies the second supply voltage (V SUP_2). A second terminal of resistor 532 is coupled to capacitor 522 and transistors 534, 536. In some examples, resistor 532 is structured as discharge circuitry, preventing the control terminals of transistors 534, 536 from floating when no signal is present (also referred to as dead time). Alternatively, current multiplication circuitry 524 may be modified to exclude resistor 532 or implement another method for discharging the control terminals of transistors 534, 536.

[0076] Transistor 534 has a first terminal, a second terminal, a third terminal, and a control terminal. The first and second terminals of transistor 534 are coupled to the second supply terminal, which provides the second supply voltage. In some examples, the second terminal of transistor 534 is referred to as a bulk terminal. The third terminal and the control terminal of transistor 534 are coupled to capacitor 522, resistor 532, and transistor 536. In the example of Fig. 5, transistor 534 is structured as a diode circuit that regulates the direction of the current supplied to capacitor 522. In some examples, transistor 534 is illustrated and described as a diode circuit. Alternatively, current multiplication circuitry 524 may be modified to replace or represent transistor 534 using a diode circuit.

[0077] Transistor 536 has a first terminal, a second terminal, a third terminal, and a control terminal. The first and second terminals of transistor 536 are coupled to the second supply terminal, which provides the second supply voltage. In some examples, the second terminal of transistor 536 is referred to as the bulk terminal. The third terminal of transistor 536 is coupled to transistors 538, 540, 542, and resistor 543. The control terminal of transistor 536 is coupled to capacitor 522, resistor 532, and transistor 534. In the example of Fig. 5, transistor 536 is structured as a current mirror circuit. In some examples, transistor 536 mirrors the current flowing through transistor 534. Alternatively, current multiplication circuitry 524 may be modified to replace or represent one or both transistors 534, 536 using a current mirror circuit.

[0078] Transistor 538 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal and the control terminal of transistor 538 are coupled to transistors 536, 540, 542, and resistor 543. The second and third terminals of transistor 538 are coupled to the common terminal, which provides the common potential. In some examples, the third terminal of transistor 538 is referred to as the bulk terminal. In the example of Fig. 5, transistor 538 is structured as a current mirror circuit. In some examples, transistor 538 mirrors the current flowing through transistor 536. Alternatively, current multiplication circuitry 524 may be modified to replace or represent transistor 538 using a current mirror circuit.

[0079] Transistor 540 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 540 is coupled to transistor 516 and current source circuitry 518. The second and third terminals of transistor 540 are coupled to the common terminal, which provides the common potential. In some examples, the third terminal of transistor 540 is referred to as the bulk terminal. The control terminal of transistor 540 is coupled to transistors 536, 538, 542, and resistor 543. In the example of Fig. 5, transistor 540 is structured as current scaling circuitry. In some examples, transistor 540 scales the current flowing through transistor 538. Alternatively, current multiplication circuitry 524 may be modified to replace or represent one or both of transistors 538, 540 using alternative current scaling circuitry.

[0080] Transistor 542 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 542 is coupled to transistors 536, 538, 540, and resistor 543. The second and third terminals of transistor 542 are coupled to the common terminal, which provides the common potential. In some examples, the third terminal of transistor 542 is referred to as the bulk terminal. The control terminal of transistor 542 is coupled to transistors 544, 566, and inverters 552, 554. In the example of Fig. 5, transistor 542 is structured as control circuitry that, when activated, prevents transistors 538 and 540 from turning on. Alternatively, current multiplication circuitry 524 may be modified to replace or represent transistor 542 as control circuitry.

[0081] Resistor 543 has a first terminal and a second terminal. The first terminal of resistor 543 is coupled to transistors 536, 538, 540, 542. The second terminal of resistor 543 is coupled to the common terminal, which provides the common potential. In some examples, resistor 543 is structured as discharge circuitry, preventing the control terminals of transistors 538, 540 from floating when no signal is present (also referred to as dead time). Alternatively, current multiplication circuitry 524 may be modified to exclude resistor 543 or implement another method for discharging the control terminals of transistors 538, 540.

[0082] Transistor 544 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 544 is coupled to the second supply terminal, which provides the second supply voltage. The second and third terminals of transistor 544 are coupled to the common terminal, which provides the common potential. In some examples, the third terminal of transistor 544 is referred to as the bulk terminal. The control terminal of transistor 544 is coupled to transistors 542, 566 and inverters 552, 554. In the example of Fig. 5, transistor 544 is structured as control circuitry that, when activated, prevents transistors 534 and 536 from turning on. Alternatively, current multiplication circuitry 524 may be modified to replace or represent transistor 544 with alternative control circuitry. In such examples, transistor 544 may be represented as switching circuitry.

[0083] Diode 546 has a first terminal and a second terminal. The first terminal of diode 546 is coupled to the secondary supply terminal, which provides the second supply voltage. The second terminal of diode 546 is coupled to resistor 548 and transistor 550. In the example of Fig. 5, diode 546 is a Zener diode structured to break down (e.g., conduct current) in response to a voltage difference greater than a threshold voltage. Resistor 548 has a first terminal and a second terminal. The first terminal of resistor 548 is coupled to diode 546 and transistor 550. The second terminal of resistor 548 is coupled to the common terminal, which provides the common potential. Transistor 550 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 550 is coupled to the second supply terminal, which provides the second supply voltage. The second and third terminals of transistor 550 are coupled to the common terminal, which provides the common potential. In some examples, the third terminal of transistor 550 is referred to as the bulk terminal.The control terminal of transistor 550 is coupled to diode 546 and resistor 548.

[0084] In the example of Fig. 5, diode 546, resistor 548, and transistor 550 are structured as clamping circuitry. In some examples, diode 546, resistor 548, and transistor 550 prevent the second supply voltage from rising above a maximum voltage by clamping the second supply voltage. For example, when the second supply voltage exceeds a breakdown voltage of diode 546, resistor 548 uses current from diode 546 to turn on transistor 550, thereby clamping the second supply voltage. Alternatively, current multiplication circuitry 524 may be modified to replace or represent diode 546, resistor 548, and / or transistor 550 as clamping circuitry. In such examples, one or more of diode 546, resistor 548, and / or transistor 550 may be represented as clamping circuitry.

[0085] Inverter 552 has a first terminal and a second terminal. The first terminal of inverter 552 may be coupled to external circuitry structured to provide the low-side control signal. The second terminal of inverter 552 is coupled to transistors 542, 544, 566 and inverter 554. Inverter 554 has a first terminal and a second terminal. The first terminal of inverter 554 is coupled to transistors 542, 544, 566 and inverter 552. The second terminal of inverter 554 is coupled to transistor 556.

[0086] Transistor 556 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 556 is coupled to transistors 558, 562, and resistor 560. The second terminal of transistor 556 is coupled to resistor 557. The control terminal of transistor 556 is coupled to inverter 554. Resistor 557 has a first terminal and a second terminal. The first terminal of resistor 557 is coupled to transistor 556. The second terminal of resistor 557 is coupled to the common terminal, which provides the common potential. In some examples, resistor 557 is a current-limiting resistor that prevents excessive currents from flowing through transistors 556, 558. Alternatively, current multiplication circuitry 524 may be modified to exclude resistor 557 or to implement a different method of current regulation.

[0087] Transistor 558 has a first terminal, a second terminal, a third terminal, and a control terminal. The first and second terminals of transistor 558 are coupled to current source circuitry 518, resistor 560, transistors 562, 568, and external circuitry structured to provide the low-side control signal. In some examples, the second terminal of transistor 558 is referred to as a bulk terminal. The third terminal and the control terminal of transistor 558 are coupled to transistors 556, 562, and resistor 560. Resistor 560 has a first terminal and a second terminal. The first terminal of resistor 560 is coupled to current source circuitry 518, transistors 558, 562, 568, and external circuitry structured to provide the low-side control signal.The second terminal of resistor 560 is coupled to transistors 556, 558, 562. Transistor 562 has a first terminal, a second terminal, a third terminal, and a control terminal. The first and second terminals of transistor 562 are coupled to current source circuitry 518, transistors 558, 568, resistor 560, and external circuitry structured to provide the secondary supply voltage.

[0088] In the example of Fig. 5, transistors 558, 562 are structured as current mirror circuitry. In some examples, transistor 562 mirrors the current flowing through transistor 558. Alternatively, current multiplication circuitry 524 may be modified to replace or represent one or both transistors 558, 562 using current mirror circuitry. In such examples, transistors 558, 562 may be represented as current mirror circuitry.

[0089] Diode 564 has a first terminal and a second terminal. The first terminal of diode 564 is coupled to transistors 562, 566, and 568. The second terminal of diode 564 is coupled to the common terminal, which provides the common potential. In the example of Fig. 5, diode 564 is a Zener diode structured to break down (e.g., conduct current) in response to a voltage difference greater than a threshold voltage.

[0090] Transistor 566 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 566 is coupled to transistors 562, 568, and diode 564. The second and third terminals of transistor 566 are coupled to the common terminal, which provides the common potential. The control terminal of transistor 566 is coupled to transistors 542, 544, and inverters 552, 554. In the example of Fig. 5, transistor 566 is structured as control circuitry that, when activated, prevents transistor 568 from turning on. Alternatively, current multiplication circuitry 524 may be modified to replace or represent transistor 566 as control circuitry. In such examples, transistor 566 may be represented as switching circuitry.

[0091] Transistor 568 has a first terminal, a second terminal, a third terminal, and a control terminal. The first terminal of transistor 568 is coupled to the auxiliary supply terminal, which supplies the second auxiliary supply voltage. The second and third terminals of transistor 568 are coupled to the second supply terminal, which supplies the second supply voltage. The control terminal of transistor 568 is coupled to transistors 562, 566, and diode 564. In the example of Fig. 5, transistor 568 is structured as regulator circuitry. In some examples, transistor 568 regulates the auxiliary supply voltage to adjust the second supply voltage. Alternatively, current multiplication circuitry 524 may be modified to replace or represent transistor 568 as regulator circuitry. In such examples, transistor 568 may be represented as supply circuitry.

[0092] In the example of Fig. 5, transistors 514, 516, 538, 540, 542, 544, 550, 556, 566, 568 are n-channel MOSFETs. Alternatively, transistors 514, 516, 538, 540, 542, 544, 550, 556, 566, 568 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, or NPN BJTs. In the example of Fig. 5, transistors 534, 536, 558, 562 are p-channel MOSFETs. Alternatively, transistors 534, 536, 558, 562 may be p-channel FETs, p-channel IGBTs, p-channel JFETs, or NPN BJTs. One or more of transistors 514, 516, 534, 536, 538, 540, 542, 544, 550, 556, 566, 558, 562 may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the transistors 514, 516, 534, 536, 538, 540, 542, 544, 550, 556, 566, 558, 562 may be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0093] Fig. 6 is a flowchart illustrating exemplary operations 600 that may be executed and / or instantiated and / or performed to implement the current multiplication circuitry 145, 224, 524 of Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5 for regulating a slew rate of a voltage across a transistor (e.g. transistors 216, 516 of Fig. 2, Fig. 3, Fig. 4 and Fig. 5). The exemplary operations 600 of Fig. 6 begin at block 610, where the gate driver circuitry 125, 210, 510 of Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5 receives a switching signal to turn on a transistor. (Block 610). In some examples, the external circuitry provides a low-side control signal to the gate driver circuitry 125, 210. In such examples, the low-side control signal is a pulse width modulation (PWM) signal having a duty cycle that determines an on and off time of the transistors 216, 516. The on time corresponds to periods of time during which the gate driver circuitry 125, 210, 510 provides a drive current that causes the transistors 216, 516 to conduct current. The off time corresponds to periods of time during which the gate driver circuitry 125, 210, 510 does not generate a drive current that can cause the transistors 216, 516 to conduct current. In such exemplary operations, adjusting the duty cycle of the low-side control signal allows the external circuitry to supply power to the motor 110 from Fig. 1 modified.

[0094] The current source circuit arrangements 130, 135, 218, 220, 518 of Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5 generate a gate drive current using the switching signal. (Block 620). In some examples, the current source circuitry 130, 135, 218, 220, 518 provides current in response to receiving the low-side control signal corresponding to the turn-on time. For example, the current source circuitry 130, 135, 218, 220, 518 provides current in response to receiving a low-side control signal that is logic high (e.g., a logic one). In such examples, currents from the current source circuitry 130, 135, 218, 220, 518 are combined to generate the gate drive current. However, as described below in Fig. As described in Figure 7, by deactivating current source circuitry 135, 220, the gate drive current is set equal to the current from current source circuitry 130, 218. Advantageously, gate driver circuitry 125, 210 can modify the gate drive current using current source circuitry 135, 220.

[0095] Current source circuitry 130, 135, 218, 220, 518 adjusts a slew rate of voltage changes across the transistor. (Block 630) In some examples, current source circuitry 130, 135, 218, 220, 518 adjusts the slew rate of transistors 216, 516 in response to the magnitude of the gate drive current. For example, transistors 216, 516 have a higher slew rate when the gate drive current is increased and have a lower slew rate when the gate drive current is decreased. In such examples, current source circuitry 130, 135, 218, 220, 518 are structured to provide currents that adjust the slew rate of transistors 216, 516 to a predetermined value. Advantageously, the slew rate of the transistors 216, 516 is adjusted by adjusting the gate drive current.Advantageously, the current source circuit arrangements 130, 135, 218, 220 may be structured to adjust the slew rate of the transistors 216, 516.

[0096] The current multiplication circuitry 145, 224, 524 provides a reference current to a capacitor in response to changes in the voltage of a drain of the transistor. (Block 640). In some examples, the transistors 234, 534 are Fig. 2, Fig. 3, Fig. 4 and Fig. 5 structured as diode circuit arrangements which connect the capacitors 222, 522 of Fig. 2, Fig. 3, Fig. 4 and Fig. 5 with power. In an exemplary operation, once the current source circuitry 130, 135, 218, 220, 518 supplies a gate drive current to the transistors 216, 516, the voltage across the capacitors 222, 522 begins to change. The capacitors 222, 522 source current from the transistors 234, 534 in response to changes in the voltage across the transistors 216, 516. Advantageously, the operations of the capacitors 222, 522 using the transistors 234, 534 are proportional to a capacitor coupled between the drain and gate terminals of the transistors 216, 516.

[0097] The current multiplication circuitry 145, 224, 524 mirrors the reference current. (Block 650). In some examples, the transistors 236, 536 are Fig. 2, Fig. 3, Fig. 4 and Fig. 5 are structured as current mirror circuits that mirror the current through transistors 234, 534. In such examples, transistors 236, 536 provide the replica of the reference current to transistors 238, 240, 538, 540 of Fig. 2, Fig. 3, Fig. 4 and Fig. 5. Advantageously, transistors 234, 534 mirror the current supplied to capacitors 222, 522.

[0098] Current multiplication circuitry 145, 224, 524 scales the reference current (block 660). In some examples, transistors 238, 538 are structured as current mirror circuitry that derives a current approximately equal to the replica of the reference current from transistors 236, 536. Additionally, transistors 238, 538 control transistors 240, 540 in response to deriving the replica of the reference current. In some examples, transistors 240, 540 are structured as scaling circuitry that scales the current flowing through transistors 238, 538. In such examples, transistors 240, 540 are sized with respect to (e.g., have scaling characteristics with respect to) transistors 238, 538. In example operations, transistors 240, 540 sink a current approximately equal to the ratio of the size of transistors 240, 540 to transistors 238, 538.For example, transistors 240, 540 may sink a current approximately sixteen times the current flowing through transistors 238, 538.

[0099] Current multiplication circuitry 145, 224, 524 derives the scaled reference current from the gate drive current to regulate the slew rate of voltage changes across the transistor (block 670). In some examples, transistors 240, 540 are structured as current sink circuitry that sinks the scaled current from the control terminal of transistor 216. In such examples, transistors 240, 540 reduce the gate drive current in response to sinking the scaled current.

[0100] Advantageously, the current multiplication circuitry 145, 224, 524 uses the scaled current to mimic a relatively large capacitance coupled between the gate and drain terminals of the transistors 216, 516. Advantageously, the current multiplication circuitry 145, 224, 524 reduces the size of a capacitance required to regulate the slew rate of the transistors 216, 516. For example, if a capacitance of eight picofarads is required between the gate and drain terminals of the transistors 216, 516 and the current multiplication circuitry 145, 224, 524 scales the reference current by sixteen, the capacitors 140, 222, 522 may have a capacitance of half a picofarad (pF). In such examples, the capacitors 140, 222, 522 and the current multiplying circuitry 145, 224, 524 mimic the capacitance of eight picofarads using a capacitance that is one-sixteenth the size.Advantageously, reducing the capacitance of capacitors 140, 222, 522 reduces the size of the system-on-chip (SoC) of gate driver circuitry 125, 210, 510. Advantageously, in GaN designs, reducing the capacitance of capacitors 140, 222, 522 reduces the integration complexity of gate driver circuitry 210, 510.

[0101] In some examples, the gate driver circuitry 125, 210, 510 dynamically adjusts the slew rate. (Blocks 710, 720, 730, 740, 750, 760, 770, 780, 790 of Fig. 7). Exemplary operations of blocks 710, 720, 730, 740, 750, 760, 770, 780, 790 are described below in connection with Fig. 7. Advantageously, dynamically adjusting the slew rate of transistors 216, 516 allows gate driver circuitry 125, 210, 510 to increase power efficiency by first using a relatively high slew rate and then using a relatively low slew rate. Advantageously, dynamically adjusting the slew rate of transistors 216, 516 increases power efficiency and reduces the load on motor 110.

[0102] Although exemplary methods are described with reference to the flowchart in Fig. 6, many other methods for implementing the current multiplication circuitry 145, 224, 524 of Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5. For example, the execution order of the blocks may be changed, or some of the described blocks may be modified, removed, or combined. Similarly, additional operations in the manufacturing process may be included before, between, or after the blocks shown in the illustrated examples.

[0103] Fig. 7 is a flowchart illustrating exemplary operations 700 that may be executed and / or instantiated and / or performed to control the gate driver circuitry 125, 210 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4 for dynamically adjusting a slew rate of a voltage on a transistor (e.g., transistor 216 of Fig. 2, Fig. 3 and Fig. 4). The exemplary operations 700 of Fig. 7 start with blocks 610, 620, 630, 640, 650, 660, 670 of Fig. 6, in which the gate driver circuitry 125, 210 adjusts a slew rate of a voltage change across a transistor using a drive current (blocks 610, 620, 630, 640, 650, 660, 670). Example operations of blocks 610, 620, 630, 640, 650, 660, 670 are described above in connection with Fig. 6 shown and described.

[0104] The control circuit arrangement 165, 232 of Fig. 1 and Fig. 2 determines whether this is a first switching cycle. (Block 710). In some examples, the first switching cycle is a first pulse of the low-side control signal after a power-up and / or a reset. In such examples, the set of first capacitors 250, 254 of Fig. 2, Fig. 3 and Fig. 4 or the set of second capacitors 252, 256 of Fig. 2, Fig. 3 and Fig. 4 of the capacitor circuit arrangement 155, 228 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4. The control circuitry 165, 232 may include additional circuitry to determine whether the switching cycle is a first switching cycle. For example, the control circuitry 165, 232 may include an additional flip-flop that is set in the first cycle after a power-on or a reset. During the first switching cycle, the comparator circuitry 170, 233 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4, a switching voltage from one of the set of first capacitors 250, 254 or the set of second capacitors 252, 256. One of the set of first capacitors 250, 254 or the set of second capacitors 252, 256 generates the switching voltage in response to being charged. However, prior to the first switching cycle, the capacitors 250, 252, 254, 256 were not charged.

[0105] If the control circuitry 165, 232 determines that it is a first switching cycle (e.g., block 710 results in YES), the charging circuitry 150, 226 charges from Fig. 1, Fig. 2, Fig. 3 and Fig. 4 first capacitors. (Block 720). In some examples, the control circuitry 165, 232 of Fig. 1 and Fig. 2 during the first switching cycle, switch 244 from Fig. 2, Fig. 3 and Fig. 4 to charge the first capacitors 250, 254. In addition, during the first switching cycle, the control circuitry 165, 232 opens the switch 248 of Fig. 2, Fig. 3 and Fig. 4 to leave the set of second capacitors 252, 256 discharged. In such examples, the charging circuitry 226 may be referred to as being structured to charge the set of first capacitors 250, 254, and the charging circuitry 226 may be referred to as being structured not to charge the set of second capacitors 252, 256. Control then returns to block 610.

[0106] If the control circuitry 165, 232 determines that this is not a first switching cycle (e.g., block 710 results in a NO result), the control circuitry 165, 232 determines whether the switching cycle is an even switching cycle (block 730). In some examples, the control circuitry 165, 232 generates first and second switching signals for controlling the switches 244, 248, 258, 260, 262, 264 of Fig. 2, Fig. 3 and Fig. 4. In such examples, the flip-flop 270 generates Fig. 2 the first switching signal by dividing the frequency of the low-side control signal, and the inverter 272 of Fig. 2 generates the second switching signal by inverting the first switching signal. The control circuitry 165, 232 uses the first switching signal to control the switch 244, which is structured to charge the set of first capacitors 250, 254 when closed. In the exemplary operation, the flip-flop 270 switches the states of the first and second switching signals after each pulse of the low-side control signal. For example, during even-numbered pulses (e.g., every other pulse), the first switching signal is in a first state and the second switching signal is in a second state. In such examples, during odd-numbered pulses (e.g., every other pulse), the first switching signal is in the second state and the second switching signal is in the first state.

[0107] If the control circuitry 165, 232 determines that the switching cycle is an even switching cycle (e.g., block 730 results in YES), the charging circuitry 150, 220 charges second capacitors to generate a switching voltage (block 740). In some examples, in response to the second switching signal closing the switch 248, the control circuitry 165, 232 causes the charging circuitry 150, 226 to charge the set of second capacitors 252, 256. In such an example, the transistor 246 of Fig. 2, Fig. 3 and Fig. 4 the set of second capacitors 252, 256 using a current proportional to the current through the transistor 234 of Fig. 2, Fig. 3 and Fig. 4. In exemplary operations, the second switching signal closes the switches 260, 264 to set the switching voltage as the voltage between the capacitor 250 and the switch 244. For example, during the operations of block 740, the control circuitry 165, 232 structures the gate driver circuitry 210 to the first configuration shown in Fig. 3 is shown.

[0108] The charging circuitry 150, 226 determines a reference voltage using the first capacitors (Block 750). In some examples, the control circuitry 165, 232 disconnects the charging circuitry 150, 226 from the set of first capacitors 250, 254 in response to the first switching signal opening the switch 244. In such an example, the switch 244 prevents the transistor 242 from Fig. 2, Fig. 3 and Fig. 4 charges the set of first capacitors 250, 254. In an exemplary operation, the first switching signal opens the switches 258, 262 to set the reference voltage as the voltage between the capacitors 252, 256. For example, during the operations of block 750, the control circuitry 165, 232 structures the gate driver circuitry 210 to the first configuration shown in Fig. 3. Control transfers to block 780.

[0109] Although in the example of Fig. 7 If the operations of block 740 occur before the operations of block 750, the operations of blocks 740, 750 may occur approximately simultaneously. For example, the charging circuitry 150, 226 discharges the first capacitors and charges the second capacitors of the capacitor circuitry 155, 228 approximately simultaneously.

[0110] If the control circuitry 165, 232 determines the switching cycle is not an even switching cycle (e.g., block 730 results in NO), the charging circuitry 150, 220 charges the first capacitors to generate the switching voltage (block 760). In some examples, in response to the first switching signal closing switch 244, the control circuitry 165, 232 causes the charging circuitry 150, 226 to charge the set of first capacitors 250, 254. In such an example, transistor 242 charges the set of first capacitors 250, 254 using a current proportional to the current through transistor 234. In one example operation, the first switching signal also closes switches 258, 262 to set the switching voltage as the voltage between capacitor 252 and switch 248.For example, during the operations of block 760, the control circuitry 165, 232 patterns the gate driver circuitry 210 to the second configuration shown in FIG. Fig. 4 is shown.

[0111] The charging circuitry 150, 226 determines the reference voltage using the first capacitors (Block 770). In some examples, the control circuitry 165, 232 disconnects the charging circuitry 150, 226 from the set of second capacitors 252, 256 in response to the second switching signal opening the switch 248. In such an example, the switch 248 prevents the transistor 246 from charging the set of second capacitors 252, 256. In one example operation, the second switching signal opens the switches 260, 264 to set the reference voltage as the voltage between the capacitors 250, 254. For example, during the operations of Block 770, the control circuitry 165, 232 structures the gate driver circuitry 210 to the second configuration shown in Fig. 4. Control transfers to block 780.

[0112] Although in the example of Fig. 7 If the operations of block 760 occur before the operations of block 770, the operations of blocks 760, 770 may occur approximately simultaneously. For example, the charging circuitry 150, 220 charges the first capacitors and discharges the second capacitors of the capacitor circuitry 155, 228 approximately, preferably exactly, simultaneously.

[0113] The comparator circuitry 170, 233 determines whether the switching voltage is greater than the reference voltage. (Block 780). In some examples, the multiplexer circuitry 160, 230 of Fig. 1 and Fig. 2 the reference voltage and the switching voltage to the comparator circuitry 170, 233. In such examples, the comparator circuitry 170, 233 compares the switching voltage and the reference voltage to control the current source circuitry 135, 220.

[0114] If the comparator circuitry 170, 233 determines that the switching voltage is not greater than the reference voltage (e.g., block 780 returns a NO result), control returns to block 780. In some examples, the comparator circuitry 170, 233 keeps the current source circuitry 135, 220 enabled (e.g., sourcing current) until the switching voltage is greater than the reference voltage. In such example operations, an output of the comparator circuitry 170, 233 changes once the switching voltage is greater than or equal to the reference voltage.

[0115] If the comparator circuitry 170, 233 determines that the switching voltage is greater than the reference voltage (e.g., block 780 yields a YES result), the comparator circuitry 170, 233 reduces the gate drive current (block 790). In some examples, the comparator circuitry 170, 233 disables the current source circuitry 135, 220 in response to a determination that the switching voltage is greater than the reference voltage. Advantageously, the comparator circuitry 170, 233 reduces the gate drive current by disabling the current source circuitry 135, 220. Advantageously, the comparator circuitry 170, 233 reduces the slew rate of the transistor 216 by reducing the gate drive current.Advantageously, during a first period of time, transistor 216 has a relatively high slew rate with relatively high power efficiency, and during a second period of time, transistor 216 has a lower slew rate that prevents excessive loading of motor 110. Advantageously, gate driver circuitry 125, 210 increases power efficiency by using multiple slew rates to control transistor 216.

[0116] Although exemplary methods are described with reference to the flowchart in Fig. 7, many other methods for implementing the gate driver circuitry 125, 210 of Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5. For example, the execution order of the blocks may be changed, or some of the described blocks may be modified, removed, or combined. Similarly, additional operations in the manufacturing process may be included before, between, or after the blocks shown in the illustrated examples.

[0117] Fig. 8 is a timing diagram 800 of an exemplary switching operation of the gate driver circuitry 125, 210 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4. In the example of Fig. 8, the timing diagram 800 illustrates exemplary drain voltages 810. The drain voltages 810 represent voltages at the transistor 216 of Fig. 2, Fig. 3 and Fig. 4 across switching events. During the switching event of Fig. 8, the gate driver circuitry 125, 210 turns on the transistor 216, causing the motor 110 to Fig. 1 or the load 204 of Fig. 2, Fig. 3 and Fig. 4 is coupled to the common terminal. At a first time 820, external circuitry provides a low-side control signal to the gate driver circuitry 125, 210 to turn on the transistor 216. At the first time 820, the voltage at the drain of the transistor 216 is a first voltage 830, which is approximately four hundred volts (V). In the example of Fig. 8, the first voltage 830 represents the first supply voltage provided at the first supply terminal.

[0118] Between the first time 820 and a second time 840, the current source circuit arrangements 130, 135, 218, 220 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4 both current to generate the gate drive current. Between the first time 820 and the second time 840, the gate drive current has a first magnitude and sets the slew rate of transistor 216 to a relatively high value. Advantageously, the transistor 216 has a relatively high power efficiency between the first time 820 and the second time 840 in response to the relatively high slew rate.

[0119] Between the second time 840 and the third time 850, the drain voltages 810 are approximately equal to a second voltage 860, which is approximately two hundred volts. The second voltage 860 is approximately equal to half of the first voltage 830. Between the second time 840 and the third time 850, the comparator circuitry 170, 233 of Fig. 1, Fig. 2, Fig. 3 and Fig. 4, that the switching voltage is greater than the reference voltage, and deactivates the current source circuitry 135, 220. Between the second time 840 and the third time 850, the comparator circuitry 170, 233 reduces the gate drive current and the slew rate by deactivating the current source circuitry 135, 220. Advantageously, a reduction in the slew rate of the transistor 216 reduces the stress exerted on the motor 110 or the load 204 during the switching operations. Advantageously, the gate driver circuitry 125, 210 increases the power efficiency of switching operations by using the relatively high slew rate for at least a portion of the switching operations of Fig. 8.

[0120] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, when a claim uses any form of "include" or "comprise" (e.g., includes, comprises, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, additional elements, terms, etc. may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as the transitional term in, for example, a preamble to a claim, this is an open-ended term in the same way that the terms "comprehensive" and "including" are open-ended terms.The term "and / or", when used, for example, in a form such as A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects, and things, the term "at least one of A and B" refers to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and things, the term "at least one of A or B" refers to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.As used herein in the context of describing the performance or execution of processes, instructions, acts, activities, etc., the phrase “at least one of A and B” refers to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, acts, activities, and / or etc., the phrase “at least one of A or B” refers to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0121] As used herein, singular references (e.g., "a," "an," "one," "first," "second," etc.) do not preclude plurals. The term "a," "an," or "another," object, as used herein, refers to one or more of these objects. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Moreover, multiple means, elements, or acts, although recited individually, may, for example, be implemented by the same entity or object. Furthermore, although individual features may be included in different examples or claims, they may be combined, and inclusion in different examples or claims does not imply that combining features is not possible and / or advantageous.

[0122] As used herein, unless otherwise specified, the term "above" describes the relationship of two parts relative to the Earth. A first part is above a second part if the second part has at least one part between the Earth and the first part. Likewise, as used herein, a first part is "below" a second part if the first part is closer to the Earth than the second part. As noted above, a first part may be above or below a second part with other parts therebetween and / or without other parts therebetween and / or with the first and second parts touching and / or without the first and second parts in direct contact.

[0123] As used in this patent, stating that any part (e.g., a layer, film, region, area, or plate) is in any way on another part (e.g., positioned on, overlies, disposed on, formed on, etc.) indicates that said part is either in contact with the other part or that said part is overlying the other part with one or more intervening parts located therebetween.

[0124] As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate links between the elements referenced by the connection reference and / or relative motion between those elements, unless otherwise noted. Therefore, connection references do not necessarily imply that two elements are directly connected or in a fixed relationship. As used herein, stating that any part is in "contact" with another part is defined to mean that there is no intermediate part between the two parts.

[0125] Unless expressly stated otherwise, descriptors such as "first," "second," "third," etc., are used herein without implying or otherwise indicating any meaning of priority, physical order, arrangement in a list, or sequence in any way, but are used merely as labels and / or arbitrary names to distinguish elements for easier understanding of the described examples. In some examples, the use of the descriptor "first" may refer to an element in the detailed description, while in a claim, a different descriptor such as "second" or "third" may refer to the same element. In such cases, such descriptors are used merely to uniquely identify those elements in the context of discussion (e.g., in a claim) where the elements might otherwise share a common name.

[0126] As used herein, "approximately" and "about" modify their subject / values ​​to acknowledge the potential existence of variations that occur in practical applications. For example, "approximately" and "about" may modify dimensions that may not be exact due to manufacturing tolerances or other real-world imperfections. For example, "approximately" and "about" may indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise noted herein.

[0127] As used herein, "substantially real-time" refers to near-instantaneous occurrence, recognizing that real-world delays may occur for computation time, transmission, etc. Therefore, unless otherwise noted, "substantially real-time" refers to real-time + 1 second.

[0128] As used herein, the term "in communication," including variations thereof, includes one or a combination of direct communication or indirect communication through one or more intermediate components and does not require direct physical (e.g., wired) communication or constant communication, but rather also includes selective communication at periodic intervals and / or scheduled intervals and / or aperiodic intervals and / or one-time events.

[0129] As used herein, the term "programmable circuitry" is defined to include at least one of the following: (i) one or more special-purpose electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform specific operation(s) and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more semiconductor-based general-purpose electrical circuits programmable with instructions to perform one or more specific function(s) or operation(s) and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors, such as central processing units (CPUs), capable of executing first instructions,to perform one or more operations and / or functions, field-programmable gate arrays (FPGAs) that can be programmed with second instructions to effect configuration or structuring of the FPGAs to instantiate one or more operations and / or functions according to the first instructions, graphics processing units (GPUs) that can execute first instructions to perform one or more operations or functions, digital signal processors (DSPs) that can execute first instructions to perform one or more operations or functions, XPUs, network processing units (NPUs), one or more microcontrollers that can execute first instructions to perform one or more operations or functions, or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system,which comprises multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and orchestration technology (e.g., application programming interface(s) (API(s))) that can assign computational task(s) to the one(s) of the various types of programmable circuitry that is / are suitable and available to perform the computational task(s).

[0130] As used herein, integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. An integrated circuit may be implemented, for example, as an ASIC and / or FPGA and / or chip and / or microchip and / or programmable circuitry and / or semiconductor substrate coupling multiple circuit elements and / or system-on-chip (SoC), etc.

[0131] In this description, the term "couple" can cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intervening component C, where the intervening component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0132] A device "configured" to perform a task or function may be configured (e.g., programmed and / or hard-wired) at the time of manufacture by a manufacturer to perform the function, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function or other additional or alternative functions. Configuring may be accomplished through firmware and / or software programming of the device, through a design and / or configuration of hardware components and interconnections of the device, or a combination thereof.

[0133] As used herein, the terms "terminal," "node," "connection," "pin," and "lead" are used interchangeably. Unless otherwise noted, the use of these terms generally means a connection between a device element, a circuit element, an integrated circuit, a device or other electronics, or another semiconductor component, or a termination thereof.

[0134] In the description and claims, the described "circuitry" may comprise one or more circuits. A circuit or device that is described herein to include certain components may instead be configured to be coupled to those components to form the described circuitry or device. For example, a structure that is described to include one or more semiconductor elements (such as transistors), one or more passive elements (such as one or a combination of resistors, capacitors, or inductors), or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g.,a semiconductor die and / or an integrated circuit (IC) package) and may be configured to be coupled, either during manufacture or after manufacture, for example by an end user and / or a third party, to at least some of the passive elements or the sources to form the described structure.

[0135] Circuits described herein are reconfigurable to include the replaced components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise noted, components shown as resistors generally represent one or more elements connected in series and / or parallel to provide an amount of impedance represented by the shown resistance. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes.Capacitors connected in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other embodiments, additional or fewer features may be integrated into the integrated circuit. Furthermore, some or all of the features depicted as external to the integrated circuit may be included in the integrated circuit, and some features depicted as internal to the integrated circuit may be integrated outside the integrated circuit.The term “integrated circuit,” as used herein, means one or more circuits that are: (i) integrated in / over a semiconductor substrate; and / or (ii) integrated in a single semiconductor package; and / or (iii) integrated in the same module; and / or (iv) integrated in / on the same printed circuit board.

[0136] Uses of the term "ground" in the foregoing description include a chassis ground and / or an earth ground and / or a floating ground and / or a virtual ground and / or a digital ground and / or a common ground and / or any other form of ground connection applicable or suitable to the teachings of this description.

[0137] Modifications of the described embodiments as well as other embodiments are possible within the scope of the claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 595,046

[0001] US 18 / 755,318

[0001]

Claims

[1] Facility comprising: a driver circuit arrangement having a terminal; a capacitor with one terminal; a diode circuit arrangement having a first terminal and a second terminal; a transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor is coupled to the first terminal of the diode circuit arrangement, wherein the control terminal of the transistor is coupled to the terminal of the capacitor and the second terminal of the diode circuit arrangement; and a current mirror circuit arrangement having a first terminal and a second terminal, wherein the first terminal of the current mirror circuit arrangement is coupled to the terminal of the driver circuit arrangement, wherein the second terminal of the current mirror circuit arrangement is coupled to the second terminal of the transistor. [2] The device of claim 1, wherein the terminal of the capacitor is a first terminal, the capacitor further having a second terminal, the transistor being a first transistor, and the device further comprising a second transistor having a first terminal and a control terminal, the first terminal of the transistor being coupled to the second terminal of the capacitor, the control terminal of the second transistor being coupled to the terminal of the driver circuitry and the second terminal of the current mirror circuitry. [3] The device of claim 1, wherein the transistor is a first transistor and the diode circuit arrangement is a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the first terminal of the first transistor, the second terminal and the control terminals of the second transistor are coupled to the terminal of the capacitor and the control terminal of the first transistor. [4] The device of claim 1, wherein the transistor is a first transistor and the current mirror circuitry comprises: a second transistor having a first terminal and a control terminal; and a current scaling circuitry having a first terminal and a second terminal, wherein the first terminal of the current scaling circuitry is coupled to the terminal of the driver circuitry, the second terminal of the current scaling circuitry is coupled to the second terminal of the first transistor, the first terminal of the second transistor, and the control terminal of the second transistor. [5] The device of claim 4, wherein the current scaling circuitry comprises a third transistor having a first terminal and a control terminal, the first terminal of the third transistor being coupled to the terminal of the driver circuitry, the control terminal of the third transistor being coupled to the second terminal of the first transistor, the first terminal of the second transistor, and the control terminal of the second transistor. [6] The device of claim 1, wherein the transistor is a first transistor, the current mirror circuitry further comprises a third terminal, and the device further comprises a second transistor having a first terminal and a second terminal, the first terminal of the second transistor being coupled to the first terminal of the diode circuitry and the first terminal of the first transistor, the second terminal of the second transistor being coupled to the third terminal of the current mirror circuitry. [7] The device of claim 6, wherein the second transistor further comprises a control terminal and the device further comprises a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the first transistor and the second terminal of the current mirror circuitry, the second terminal of the third transistor is coupled to the third terminal of the current mirror circuitry and the second terminal of the second transistor, the control terminal of the third transistor is coupled to the control terminal of the second transistor. [8] Facility comprising: a utility connection; a driver circuit arrangement having a terminal; a diode circuit arrangement having a first terminal and a second terminal; a current mirror circuit arrangement having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the current mirror circuit arrangement is coupled to the supply terminal and the first terminal of the diode circuit arrangement, wherein the second terminal of the current mirror circuit arrangement is coupled to the second terminal of the diode circuit arrangement; and a current scaling circuitry having a first terminal and a second terminal, wherein the first terminal of the current scaling circuitry is coupled to the terminal of the driver circuitry, wherein the second terminal of the current scaling circuitry is coupled to the third terminal of the current mirror circuitry. [9] The device of claim 8, further comprising: a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the second terminal of the diode circuit arrangement and the second terminal of the current mirror circuit arrangement; and a transistor having a first terminal and a control terminal, wherein the first terminal of the transistor is coupled to the second terminal of the capacitor, wherein the control terminal of the transistor is coupled to the terminal of the driver circuitry and the first terminal of the current scaling circuitry. [10] The device of claim 8, wherein the diode circuit arrangement is a transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the transistor is coupled to the supply terminal and the first terminal of the current mirror circuit arrangement, wherein the second terminal and the control terminals of the transistor are coupled to the terminal of the second terminal of the current mirror circuit arrangement. [11] The device of claim 8, wherein the current mirror circuitry is a transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the transistor being coupled to the supply terminal and the first terminal of the diode circuitry, the second terminal of the transistor being coupled to the second terminal of the current scaling circuitry, the control terminal of the transistor being coupled to the second terminal of the diode circuitry. [12] The device of claim 8, wherein the current mirror circuitry is a first current mirror circuitry and the current scaling circuitry comprises: a first transistor having a first terminal and a control terminal; and a second transistor having a first terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the terminal of the driver circuitry and the control terminal of the second transistor is coupled to the third terminal of the first current mirror circuitry, the first terminal of the first transistor and the control terminal of the first transistor. [13] The device of claim 8, wherein the current scaling circuitry further comprises a third terminal, and the device further comprises a transistor having a first terminal and a second terminal, the first terminal of the transistor being coupled to the supply terminal, the first terminal of the diode circuitry, and the first terminal of the current mirror circuitry, the second terminal of the transistor being coupled to the third terminal of the current scaling circuitry. [14] The device of claim 13, wherein the transistor is a first transistor, the first transistor further comprises a control terminal, and the device further comprises a second transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the current mirror circuitry and the second terminal of the current scaling circuitry, the second terminal of the second transistor is coupled to the third terminal of the current scaling circuitry and the second terminal of the first transistor, the control terminal of the second transistor is coupled to the control terminal of the first transistor. [15] Facility comprising: a first transistor having a first terminal and a control terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being coupled to the first terminal of the first transistor; a second transistor having a first terminal and a control terminal; a current mirror circuit arrangement having a first terminal and a second terminal, wherein the first terminal of the current mirror circuit arrangement is coupled to the second terminal of the capacitor, the first terminal of the second transistor, and the control terminal of the second transistor; and a current scaling circuitry having a first terminal and a second terminal, wherein the first terminal of the current scaling circuitry is coupled to the second terminal of the current mirror circuitry, wherein the second terminal of the current scaling circuitry is coupled to the control terminal of the first transistor. [16] The device of claim 15, wherein the second transistor further comprises a second terminal and the current mirror circuitry is a third transistor having a first terminal, a second terminal and a control terminal, the first terminal of the third transistor being coupled to the second terminal of the second transistor, the second terminal of the third transistor being coupled to the first terminal of the current scaling circuitry, and the control terminal of the third transistor being coupled to the second terminal of the capacitor, the first terminal of the second transistor and the control terminal of the second transistor. [17] The device of claim 15, wherein the current mirror circuitry is a first current mirror circuitry and the current scaling circuitry comprises: a second current mirror circuit arrangement having a first terminal and a second terminal; and a third transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the first transistor, the second terminal of the third transistor is coupled to the second terminal of the current mirror circuit arrangement, and the control terminal of the third transistor is coupled to the second terminal of the first current mirror circuit arrangement and the second terminal of the second current mirror circuit arrangement. [18] The device of claim 17, wherein the second current mirror circuitry is a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal and the control terminal of the fourth transistor being coupled to the second terminal of the first current mirror circuitry, the second terminal of the second current mirror circuitry, and the control terminal of the third transistor, and the second terminal of the fourth transistor being coupled to the second terminal of the third transistor. [19] The device of claim 15, wherein the second transistor further comprises a second terminal, wherein the current mirror circuitry further comprises a third terminal, wherein the current scaling circuitry further comprises a third terminal, and the device further comprises a third transistor having a first terminal and a second terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the second transistor and the third terminal of the current mirror circuitry, wherein the second terminal of the third transistor is coupled to the third terminal of the current scaling circuitry. [20] The device of claim 19, wherein the third transistor further comprises a control terminal, and the device further comprises a fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth transistor is coupled to the second terminal of the current mirror circuitry and the first terminal of the current scaling circuitry, the second terminal of the fourth transistor is coupled to the third terminal of the current scaling circuitry and the second terminal of the third transistor, the control terminal of the fourth transistor is coupled to the control terminal of the third transistor.

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