MULTI-PHASE INVERTER

Abstract

According to one embodiment, a circuit includes: a battery monitoring circuit configured to monitor a positive supply voltage and a negative supply voltage with respect to a neutral node; an inverter configured to provide multiple modulated phase voltages representing a reference voltage vector; and a space vector modulator configured to generate modulated drive signals for the inverter based on the reference voltage vector, wherein duty cycles of the modulated drive signals depend on the monitored positive supply voltage and the monitored negative supply voltage.

Description

[0001] This disclosure relates to the field of electronic circuits, in particular to a multiphase inverter.

[0002] Multiphase inverters are typically used to drive synchronous or asynchronous motors. Such motors are also called inverter-fed synchronous / asynchronous motors. Brushless DC motors (which are actually synchronous motors in which the excitation field is generated by permanent magnets) can also be driven using inverters. Multiphase inverters often have three phases, but can also have two, four, or more phases.

[0003] A common type of inverter is the so-called active neutral point clamped (ANPC) inverter. ANPC inverters are multi-level inverters that can generate modulated phase voltages that can assume three or more different voltage levels. For example, in a three-level inverter, each phase voltage can assume either the voltage level of the positive supply voltage, zero (voltage level of the neutral point), or the voltage level of the negative supply voltage. In battery-supplied inverters, the neutral point is usually created by dividing the battery voltage U DC (often referred to as DC bus voltage) into two equal voltages using a capacitive voltage divider. In this way, a symmetrical bipolar supply is provided, where the positive supply voltage U DC / 2, the voltage of the neutral point is - by definition - zero volts and the negative supply voltage is -U DC / 2.

[0004] In some applications, two batteries (or battery modules) are connected in series, and the common circuit node where the batteries are connected is used as the neutral point. In such a situation, the bipolar supply can become asymmetric if the states of charge (SoC) of the two batteries are different. At the same time, the DC bus voltage U DC the sum of the battery voltages of the two batteries.

[0005] Inverters are typically controlled by multiple pulse-width modulated (PWM) signals, which are used to enable (turn on) and disable (turn off) the inverter's transistors. Various suitable PWM schemes are known. However, in the case of an asymmetric supply consisting of two batteries (or battery modules) connected at the neutral point, known PWM switching schemes can cause the battery with the lower SoC to discharge more than the battery with the higher SoC, thus exacerbating the asymmetry of the bipolar supply.

[0006] In addition, known algorithms used to generate the PWM signals assume that the power supply is symmetrical, and operation with an asymmetrical supply will result in a systematic error.

[0007] Described herein is a circuit that, according to one embodiment, includes a battery monitoring circuit configured to monitor a positive supply voltage and a negative supply voltage with respect to a neutral node, an inverter configured to provide a plurality of modulated phase voltages representing a reference voltage vector, and a space vector modulator configured to generate modulated drive signals for the inverter based on the reference voltage vector. The drive signals have duty cycles that depend on the monitored positive supply voltage and the monitored negative supply voltage.

[0008] Furthermore, a corresponding method is described herein. According to one embodiment, the method includes monitoring a positive and a negative supply voltage of an inverter with respect to a neutral node and generating modulated drive signals for the inverter based on a reference voltage vector using a space vector modulator. The duty cycles of the modulated drive signals are controlled depending on the monitored positive supply voltage and the monitored negative supply voltage. The modulated drive signals are supplied to the inverter, causing the inverter to provide a plurality of modulated phase voltages representing the reference voltage vector.

[0009] Furthermore, a three-level inverter system is described here. According to one embodiment, the system comprises a first power supply and a second power supply connected at a neutral node and providing a positive and a negative supply voltage. The system further comprises a battery monitoring circuit configured to monitor the positive supply voltage and the negative supply voltage, and an inverter powered by the positive supply voltage and the negative supply voltage. A space vector modulator is configured to generate modulated drive signals for the inverter such that the positive supply voltage and the negative supply voltage are brought back into balance or remain substantially in balance.

[0010] The invention will be better understood with reference to the following drawings and descriptions. The components in the figures are not necessarily to scale; instead, the emphasis is placed upon illustrating the principles of the invention. Furthermore, like reference numerals designate corresponding parts throughout the figures. Regarding the drawings: Fig. 1 is a block diagram illustrating an example of a control loop for controlling a three-phase synchronous motor using space vector modulation; Fig. Figure 2 is an example block diagram illustrating a PWM modulator and an ANPC inverter that can be used for space vector modulation. Fig. 3 shows an example of a three-phase ANPC inverter with three phases. Fig. 4 visualizes in diagrams (a) to (d) the four different switching states of each inverter phase. Fig. Figure 5 shows a table containing several sequences of inverter states that can be used to generate any voltage vector. Fig. 6 visualizes the different stress vectors (space vectors) generated by the values ​​given in the table of Fig. 5 listed inverter states can be achieved for a symmetrical power supply of the inverter. Fig. 7 visualizes a specific modulation sequence. Fig. Figure 8 visualizes the modulation sequence of Fig. 7. Fig. 9 visualizes how the diagram of Fig. 6 for an inverter powered by an asymmetric power supply. The Fig. 10-12 illustrate the decomposition of the hexagon of the diagram of Fig. 6 for the purpose of determining a modulation sequence and the times associated with the inverter states of the determined sequence. Fig. 13 visualizes a modulation sequence that corresponds to the voltage vector in Fig. 11 corresponds.

[0011] Some embodiments of the present invention are directed to a method of operating an inverter in a manner suitable for operation on asymmetric power supplies.

[0012] Before discussing examples of PWM modulator and ANPC inverter in more detail, an exemplary application of space vector modulation is presented with reference to Fig. 1, which is a block diagram illustrating an example of a control loop for controlling a three-phase synchronous motor 100 used as an illustrative example of a load supplied with a multi-phase voltage.

[0013] The motor 100 is driven using an inverter controlled using a space vector modulator. The functional block containing the modulator and the inverter is shown in Fig. 1 labeled 200. In the present example, the space vector modulator receives a reference space vector defined by the amplitude V REF and the angle θ (polar coordinates of the reference space vector V REF *). The inverter generates the modulated phase voltages V U , V V , V W which are supplied to the motor 100. To control the angular velocity of the motor 100, the three resulting phase currents i U , i V , i W In some applications, the angular position θs of the rotor is measured, e.g., using a rotary encoder or the like.

[0014] In this example, the measured values ​​of the phase currents i U , i V , i W Subject to a coordinate transformation, commonly referred to as the Clarke-Park transformation (Clark transformation and subsequent Park transformation). The Clark and Park transformations can be combined into one transformation step, and the corresponding function block is Fig. 1 labeled 220. The Clarke-Park transform 220 generates the orthogonal current signals id and i q . The axes of the corresponding Cartesian coordinate system are often denoted by d and q, and therefore the Park transformation is also called the d / q transformation. The current signals i d and iq are sent to the controller 230, which determines the corresponding setpoints V d,SET and V q,SET receives, supplied.

[0015] The controller 230 generates the output signals V dand Vq based on the current signals i d and i q and the setpoints V d,SET and V q,SET . The controller output signals V d and V q are subjected to an inverse Park transformation, which leads to corresponding voltage signals V α and V β (in Fig. 1 not shown), where the indices α and β represent the axes of a Cartesian coordinate system in the rotating reference frame. The voltage signals V α and V β , which contains the mentioned reference space vector V REF * in the Cartesian coordinate system α / β, are subsequently transformed into polar coordinates to determine the amplitude V REF and the angle θ, which are the input parameters for the space vector modulator. The function block containing the inverse Park transform and the coordinate transformation into polar coordinates is shown in Fig. 1 labeled 210. In some implementations, the function blocks 210 and 220 can measure the angular position θ S of the rotor as input parameter.

[0016] The control loop in Fig. The concept illustrated in Figure 1 is commonly known as vector control or field-oriented control (FOC) and will therefore not be discussed in detail here. However, for the purposes of the following discussion, it is important that the function block 200, and in particular the inverter, is powered by a bipolar voltage supply, e.g., the positive supply voltage +U P and the negative supply voltage -U Nwith respect to the reference voltage of a so-called neutral node n0 (neutral point), which can be defined as zero volts without loss of generality. The bipolar voltage supply is provided by two batteries (or two battery modules, each containing several batteries) connected in series at the neutral node n. Since the state of charge (SoC) of the two batteries (in Fig. 1 labelled “Battery 1” and “Battery 2”) is not necessarily identical, the bipolar voltage supply may be asymmetric with respect to the electrical potential of the neutral node n0 (i.e. U P ≠U N ).

[0017] Fig. Figure 2 illustrates the functional block 200 in more detail. Accordingly, the functional block 200 includes the inverter 202 and the space vector modulator 201, which typically uses a PWM circuit scheme to control the inverter operation. As shown in Fig. 2, the inverter 202 receives from the space vector modulator 201 a plurality of gate signals which are applied to the control electrodes of the transistors included in the inverter 202, and the inverter 202 generates the corresponding modulated phase voltages V U , V V , V W for the 3-phase motor 100. It is noted that in some applications, more than three phases may be used. As previously mentioned, the inverter 202 is powered by a bipolar supply (voltages +U P and -U N with respect to the neutral point voltage, which can be defined as 0 V) ​​and the supply voltages +U P and -U N may be asymmetrical with respect to the neutral point due to different battery charge levels. The parameter ρ can be used to quantify the degree of asymmetry of the bipolar supply. In this example, the parameter ρ is defined as the ratio U N / U DC defined, where U DC the sum of the supply voltages U P +U N Accordingly, the supply voltages can also be referred to as U N = ρ·U DC and U P = (1-ρ)·U DC where the parameter ρ can (theoretically) vary between 0 and 1 (p=0 shows U N =0, ρ=1 shows U P =0). Accordingly, ρ is referred to as the symmetry parameter, which quantitatively describes the symmetry (or lack of symmetry / asymmetry) of the power supply.

[0018] The Fig. The circuit shown in Figure 2 further includes a battery monitoring circuit 203 which is designed to measure the positive supply voltage U P and the negative supply voltage U Nwith respect to a neutral node n0 of a battery. The battery monitoring circuit 203 can monitor any signal or parameter that affects the battery voltages U P and U N represent, provide, for example a measured U DC , which is the sum U P +U N and the parameter ρ described above. Other signals or parameters may be used depending on the actual implementation. The parameters U DC and ρ can be communicated to the space vector modulator 201 in any known manner, for example, using a digital bus such as CAN (Controller Area Network) or other suitable communication link. In another example, analog voltage signals representing U P and U N represent, are fed to the space vector modulator 201.

[0019] In addition, the circuit contains Fig. 2 the inverter 202, which is designed to generate a plurality of modulated phase voltages comprising a reference voltage vector V REF * (Amplitude V REF and angle θ in polar coordinates). The space vector modulator 201 is designed to provide modulated drive signals for the inverter 202 based on the reference voltage vector V REF to generate. In the examples described here, PMW circuit schemes are used. If the inverter 202 consists of metal-on-semiconductor field-effect transistors (MOSFETs), the mentioned drive signals are the gate voltages supplied to the gates of the MOSFETs. Each drive signal (gate signal) is modulated according to a duty cycle. In the examples described here, the duty cycles of the modulated drive signals depend on the monitored positive supply voltage U P and the monitored negative supply voltage -U N In the Fig. In the example shown in Figure 2, the duty cycles of the modulated control signals depend on the total DC voltage U DC and the parameter ρ (which together uniquely U P and -U N and thus provide the same information as the voltages U P and -U N convey).

[0020] Fig. 3 shows an exemplary embodiment of the inverter 202. According to Fig. 3, the inverter is composed of three phases, with each phase implemented by a corresponding branch of the inverter. As mentioned, in other embodiments, the inverter may have more than three phases. The batteries labeled "Battery 1" and "Battery 2" are represented by voltage sources in the illustrated example, with the voltage sources electrically connected at neutral point n0.

[0021] Each of the three branches of the inverter of Fig. 3 has six with Qip MOSFETs, where the superscript p (p=0, 1, 2) indicates the phase / branch and the subscript i (i=0, ... 5) indicates a specific transistor of a specific phase / branch. In each branch p, the transistors form Q2p, Q0p, Q1p and Q5p a chain (series connection) between the positive supply node n1 (where the voltage U P provided) and the negative supply node n4 (at which the voltage -U N In this context, a "chain of transistors" or a series connection of two or more transistors means that the main current paths (drain-source current paths) of the transistors are electrically connected in series. This means that for the first branch p=0, the transistor Q20 between the positive supply node n1 and the circuit nodes n20 switched, the transistor Q00 is between the circuit nodes n20 and the phase output node nx0 switched, the transistor Q10 is between the phase output nodes nx0 and the circuit node n30 switched, the transistor Q50 is between the circuit nodes n30 and the negative supply node n4. Between the circuit nodes n20 and n30 is a series connection of the two other transistors Q30 and Q40 parallel to the series connection of the transistors Q00 and Q10 switched, whereby the common circuit node between the transistors Q30 and Q40 connected to the neutral node n0. The other branches of the inverter (p=1 and p=2) are constructed analogously to the first branch (p=0).

[0022] In the examples described here, each phase p of the inverter can assume one of four states, referred to as the P-type state, the U-type state, the L-type state, and the N-type state. These four states are shown in Fig. 4, diagrams (a) to (d), where in each state shown, the transistors shown in gray are inactive (off) while the other transistors are active (on).

[0023] In the P-type state, the transistors are Q2p, Q0p and Q4p switched on, while the other transistors Q1p, Q3p and Q5p are switched off. As a result, the phase voltage at the output node nxp equal to the positive supply voltage U P, if the voltage drop across the conducting transistors is neglected. This situation is illustrated by diagram (a) of Fig. 4 shown.

[0024] In the U-type state, the transistors are Q0p, Q3p and Q5p switched on, while the other transistors Q1p, Q2p and Q4p are switched off. As a result, the phase voltage unp(t) at the exit node nxp equal to the neutral point voltage (0 V). This situation is shown by diagram (b) of Fig. 4, which shows that the output node nxp about the transistors Q3p and Q0p actively connected to the neutral node n0.

[0025] In the L-type state, the transistors are Q1p, Q2p and Q4p switched on, while the other transistors Q0p, Q3p and Q5p are switched off. Accordingly, the L-type state is complementary to the U-type state. Here, too, the phase voltage unp(t) at the exit node nxp equal to the neutral point voltage (0 V). This situation is shown by diagram (c) in Fig. 4, which shows that the output node nxp about the transistors Q4p and Q1p actively connected to the neutral node n0.

[0026] In the N-type state, the transistors are Q1p, Q3p and Q5p switched on, while the other transistors Q2p, Q0p and Q4p are off. Accordingly, the N-type state is complementary to the P-type state. As a result, the phase voltage at the output node nxp equal to the negative supply voltage -U N This situation is illustrated by diagram (d) of Fig. 4 shown.

[0027] In the above discussion, it is assumed that the voltage drops across active transistors are negligible. The states P, U, L and N of a particular branch p of the inverter were determined with reference to Fig. 4. Similarly, the state of a three-phase inverter can be expressed by triples such as LNN, LUN, PUN, PUU, PUN, etc. In the examples described here, the only allowed state transitions in a given branch p of an inverter are P↔L, N↔U, and L↔U, while transitions between a P-type state and a U-type state are avoided, as are transitions between an N-type state and an L-type state. Accordingly, state LUN means that phase p=0 has an L-type state, phase p=1 has a U-type state, and phase p=2 has an N-type state, to give just one example. For a 4-phase inverter, the state would be expressed by a quadruple such as LUNP, and in the case of an n-phase inverter (with an integer n > 1), by an n-tuple.

[0028] To generate a specific output, the space vector modulator 201 (see Fig. 2) repeats a specific sequence of states called the “modulation sequence,” with each state being active for a specific time. Fig. Figure 5 shows a table with 72 different modulation sequences, where each row of the table represents a specific sequence of switching states of the inverter. In this description, a modulation sequence with o N , µ N , v N , o P , µ P , v P where each of the switching states o N , µ N etc. represents a triple such as LNN, LUN, etc. The variables Σ, σ, and ζ, which characterize a particular sequence contained in the table, are discussed later.

[0029] The output of inverter 202 (cf. Fig. 2) is determined by the reference voltage V REFand the associated angle θ. The space vector modulator 201 is designed to generate the modulated control signals (e.g., gate signals) for the signals in the inverter 202 (see Fig. 3) transistors in such a way that the inverter 202 is within a range of T PWM designated cycle period a desired sequence of inverter states (switching states of the inverter, see table of Fig. 5). The desired modulation sequence is based on the reference voltage vector (magnitude V REF and angle θ) received by the space vector modulator 201.

[0030] The aforementioned "selection" of the modulation sequence and the associated temporal division of the inverter states are controlled by the space vector modulator 201. Accordingly, the space vector modulator 201 is configured to generate the modulated control signals such that—within a cycle period—each inverter state of the selected modulation sequence is active for a specific on-time. In the embodiments described herein, the on-times of the individual inverter states (in Fig. 5 with o N , µ N , v N , o P , µ P , and v P designated) by the duty cycles of the drive signals output by the space vector modulator 201 and supplied to the transistors contained in the individual phases / branches of the inverter 202.

[0031] Fig. 6 visualizes the different stress vectors (spatial vectors in Cartesian coordinates) generated by the values ​​given in the table of Fig. 5 listed inverter states can be generated. Fig. 6 can also be considered as a visualization of the Clarke transformation, which converts the three voltages output by the inverter (i.e. each inverter state) VU=un0(t),VV=un1(t) and VW=un1(t) to a corresponding space vector in Cartesian coordinates. At this point in the discussion, it is important to understand that the diagram of Fig. 6 represents a situation in which the power supply of the inverter is symmetrical. That is, the supply voltages U P and U N are equal and the symmetry parameter ρ is equal to 0.5.

[0032] Any triple of inverter output voltages (phase voltages) (V U , V V , V W) can be considered as a 3 × 1 vector, which can be converted into the Cartesian coordinate system according to the following transformation (Clarke transformation): (VxVy)=(1−12−12032−32)(VUVVVW).

[0033] However, it is noted that the x and y coordinates, as in Fig. 6, are normalized and the x and y axes are therefore not in volts but dimensionless.

[0034] In Cartesian coordinates, the states are those created by a three-level three-phase inverter as in Fig. 3 can be generated, all either on the vertices of an inner (smaller) hexagon, on the vertices of an outer (larger) hexagon, or on the midpoints of the edges of the outer hexagon (i.e., in the middle between two adjacent vertices). A total of 19 different stress vectors can be generated, namely the zero vector in the center, six vectors with endpoints on the vertices of the inner hexagon, six with endpoints on the vertices of the outer hexagon, and six with endpoints on the edges of the outer hexagon. Fig. 6, it is obvious that different inverter states can lead to the same vector in Cartesian coordinates. For example, the inverter states PPP, NNN, UUU, LLL, LUU, ULU, UUL, ULL, LUL, and LLU all lead to the zero vector. Similarly, the inverter states LNN, UNN, PLL, PUL, PLU, and PUU all lead to the vector that denotes the rightmost vertex of the inner hexagon. Only the six states PPN, NPN, NPP, NNP, PNP, and PNN uniquely represent the six vectors that denote the six vertices of the Fig. 6. It is noted that the scaling of the x- and y-axes of the diagram in Fig. 6 and is not important for the present discussion. Every state (and thus every vertex) that is in Fig. 6 represents a voltage (expressed in Cartesian coordinates or as magnitude and angle) that can be generated by the inverter at its output.

[0035] Fig. 6 also contains an example reference voltage vector (magnitude V REF , angle θ). This reference voltage can be represented by a modulation sequence that contains inverter states associated with the adjacent vertices of the triangle enclosing the endpoint of the reference vector. In the example of Fig. 6, the reference vector can be represented by the modulation sequence PUU, LUU, LUN, LNN, LUN, LUU. This sequence is shown in the table of Fig. 5 is not included, which shows that the table of Fig. 5 is an example and not the only option for selecting the modulation sequences. In the present example, the space vector modulator 201 determines the times T A , T B and T C , where the time T A the states PUU and LNN (which are equivalent in the sense that both are mapped to the same space vector / vertex), the time T Bis associated with the state LUU (which occurs twice in the mentioned modulation sequence) and the time Tc is associated with the state LUN (which also occurs twice).

[0036] The time division of the above mentioned modulation sequence is shown in the diagram of Fig. 7. The two occurrences of the state LUU each have a duration of T B / 2, the two occurrences of the state LUN each have a duration of T B / 2, the state LNN has a duration of T A / 2 and the equivalent state PUU is (temporally) divided into two parts. The first part is located at the beginning of the sequence and the second part at the end of the sequence, with each part having a length of T A / 4. The sum T A +T B +T C is equal to the PWM cycle time T PWM . The Times T A , T Band Tc uniquely determine the duty cycles of the drive signals that control the switching operation of the transistors contained in the inverter.

[0037] As from Fig. 6, the specific modulation sequence PUU, LUU, LUN, LNN, LUN, LUU, (PUU) can be purely based on the reference voltage vector V REF * To select a suitable sequence of inverter states, the space vector modulator only needs to select the three adjacent vertices of the triangles that form the hexagons of Fig. 6. The times T associated with the states A , T B , Tc are also purely based on the reference voltage vector V REF * and the inverter states contained in the selected sequence. Algorithms for calculating the times T A , T B, Tc are known as such and are therefore not discussed in detail here. In principle, the times can be determined by calculating barycentric coordinates for the reference vector V REF * obtained using the voltages represented by the three vertices represented by the selected sequence. As mentioned, PUU and LNN represent the same (first) vertex, and LUU and LUN represent the second and third vertices relevant to the currently considered modulation sequence.

[0038] The reference vector V REF * is the only (non-constant) input parameter that influences the selection of the modulation sequence and the calculation of the times associated with the inverter states of the selected sequence. As mentioned, Fig. 6 and the above explanation are based on the assumption of a symmetrical power supply to the inverter, which is typically the case in conventional systems where the DC voltage is divided by a capacitive voltage divider in a 1:1 ratio to obtain the neutral point voltage. However, the situation is somewhat more complicated when the power supply to the inverter 202 is asymmetric (i.e., ρ≠0.5).

[0039] In a first approach, the modulation sequence is selected as explained above (as if the power supply were symmetrical). The times T A , T B and T C can be determined as explained above (e.g., using the barycentric method). The time T A , which in the example of Fig. 7 for the states PUU and LNN, is now dependent on the supply voltages U P and U N, for example, depending on the symmetry parameter ρ. An example is given in Fig. 8 shown.

[0040] In Fig. Figure 8 is a diagram illustrating the modified timing of the above-mentioned modulation sequence depending on the actually measured power supply asymmetry. Fig. 8 is almost identical to Fig. 7, except that the time T A for the state PUU in T AP and for the state LNN in T AN was changed, where T AN =T A +ΔT and T AP =T A -ΔT, so that the total PWM cycle time remains unchanged. This modification has no effect on the inverter's output voltage when averaged over a cycle, since the PUU and LNN states represent the same voltage vector (see Fig. 6, PUU and LNN are assigned to the same vertex). As can be seen from the Fig. 3 and Fig. 4, the PUU state will connect the load to the first battery (the U P provides), while the LNN state couples the load to the second battery (which -U N provides), with both states representing the same vertex. Accordingly, a positive ΔT increases the time for the LNN state and decreases the time for the PUU state, while the total time for the respective vertex remains unchanged.

[0041] Therefore, in a situation where the SoC of the first battery is lower than the SoC of the second battery (i.e., ρ>0.5, U N >U P ), ΔT can be set to positive time values ​​to couple the first battery to the load for a shorter time (and the second battery for a longer time). Conversely, in a situation where the SoC of the first battery is higher than the SoC of the second battery (i.e., ρ<0.5, U N P ​), ΔT can be set to negative time values ​​to couple the first battery to the load for a longer time (and the second battery for a shorter time). The time difference ΔT can be increased to larger positive or negative values ​​if the deviation of ρ from its ideal value of 0.5 increases or decreases, respectively. If the SoC of both batteries is approximately the same (e.g., ρ ∈ [0.5-ε, 0.5+ε], where ε is a small positive value), ΔT can be set to zero.

[0042] The concept discussed above was explained with reference to the exemplary modulation sequence of the Fig. 7 and Fig. 8, which for a reference vector V REF * whose endpoint lies in the first triangle / segment (between θ=0° and θ=60°) of the inner hexagon. As in Fig. However, as can be seen in Figure 6, this concept can be applied to all triangles / segments that form the hexagons of Fig. 6. It is noted that this concept helps stabilize the symmetry of the power supply, as it allows more power to be drawn from the battery with the higher SoC than from the battery with the lower SoC. In a system where one or more single-phase loads draw power from only one of the batteries, the bipolar power supply provided jointly by the two batteries will always be asymmetric. Driving a three-phase load as described above helps to rebalance the supply or at least reduce its asymmetry. Furthermore, a runaway condition, which causes the battery with the lower SoC to discharge even more than the other battery, can be avoided.

[0043] In other words, the space vector modulator 201 is designed to generate the modulated control signals for the inverter 202 such that within one cycle period T PWM each switching state (see Fig. 5, Conditions o N , µ N , v N , o P , µ P , v P ) of the desired modulation sequence for a specific on-time (see also Fig. 13, One-times TN0,TN1,TN2,TP0,TP1) is active. The actual on-times of the switching states are determined by the duty cycles of the control signals, and the control signals are generated based on the on-times determined by the space vector modulator 201. In the Fig. 7 and Fig. In the example shown in Figure 8, the desired modulation contains the first states (see Fig. 5, Conditions o N , µ N , v N ) and second states (see Fig. 5, Conditions o P , µP , v P ), where the first states cause the inverter to switch on during a cycle T PWM to generate a positive average load current (which makes the load - on average - more coupled to the first battery), and the second states cause the inverter to PWM to generate a negative average load current (thus coupling the load—on average—more closely to the second battery). Using the present approach, the space vector modulator 201 controls the duty cycles of the modulated drive signals such that the cumulative on-times of the first states are greater than the cumulative on-times of the second states when the positive supply voltage U P a higher value than the negative supply voltage -U N has, and vice versa.

[0044] In the example above, the selection of the modulation sequence was based on the reference vector V REF * assuming a symmetrical power supply. This means that the space vector modulator is essentially operated as if the power supply were symmetrical, and only the timing of the sequence is adjusted as described above with reference to the Fig. 7 and Fig. 8. This approach helps to keep the power supply in an approximately balanced state and can even be used to rebalance an asymmetric power supply. However, the above-mentioned approach does not take into account the fact that the actual average voltage vector generated by the inverter (averaged over one cycle) does not exactly correspond to the reference vector V REF* Suitable when the power supply is asymmetrical. As a result, the DC component may deviate from zero and higher harmonics may be generated. The approach described below enables precise three-phase operation of the inverter with asymmetrical bipolar power supplies, even when the asymmetry is significant.

[0045] As mentioned, Fig. 6 a situation where the power supply of the inverter is symmetrical (ie U P =U N , ρ=0.5). If the symmetry parameter ρ for any reason increases to values ​​above 0.5 or decreases to values ​​below 0.5, the inner hexagon of Fig. 6 distorted. Fig. 9 shows the situation for ρ=0.6, which means that the voltage U N the second battery 1.5 times the voltage U P of the first battery. The inner hexagon of Fig. 6 are in fact two congruent hexagons, whose congruence is also destroyed for ρ≠0.5. Accordingly, inverter states (e.g. PLL and LNN) that are Fig. 6 generate the same stress vector, no longer to the same stress vector. Furthermore, for ρ>0.5 or ρ<0.5, the stress vectors whose endpoints are located on the edges of the outer hexagon (which is not distorted) move from the midpoint between two vertices toward one of the neighboring vertices.

[0046] The Fig. 10-12 illustrate for the purpose of selecting a suitable modulation sequence for a particular reference vector V REF * and calculating the times associated with the inverter states of the selected sequence, the decomposition of the hexagon of the diagram of Fig. 6 into sectors Σ, sections σ and segments ζ. To keep the representation simple, Fig. 10-12 illustrates the situation for ρ=0.5 (undistorted inner hexagon). However, the following approach is generic and can also be applied to situations where the symmetry parameter ρ is greater or less than 0.5.

[0047] Fig. 10 corresponds to the diagram of Fig. 6. The outer hexagon is regularly divided into six triangles, called sectors ∑. The stress vectors whose endpoints lie on the vertices of the outer hexagon (which is not distorted for ρ≠0.5) have angles of 0°, 60°, 120°, 180°, 240°, and 300°. Each reference vector V REF * lies in sector ∑, if the angle θ of the vector V REF * lies in the interval [∑·π / 3, (∑+1)-π / 3]. In other words, the sector ∑=0 extends from 0 to π / 3 rad (60°), the sector ∑=1 extends from π / 3 to 2π / 3 rad (120°), etc.

[0048] As in Fig. 10, each sector ∑ can be divided into two sections σ, where the section σ=0 is located at lower angles and the section σ=1 is located at higher angles. Although in Fig. 10 the sections σ=0 and σ=1 have the same size, this is not necessarily the case in a general situation where ρ≠0.5. In the Fig. In the asymmetric case shown in Figure 9, the section σ=0 is larger than the section σ=1 in the sector ∑=0, while the opposite is true for the sector ∑=1. The angle at which a sector is divided into the two sections σ=0 and σ=1 is Fig. 10 is denoted by φ, where φ is different in each sector ∑ and depends on the supply voltages U P , U N depends.

[0049] Each section σ of a sector ∑ is divided into six segments ζ (ie ζ=0, 1, ..., 5) which are Fig. 11 and Fig. 12 are shown. In Fig. 11, the shaded area of ​​the diagram indicates the section σ=0 of the sector ∑=0. The segments associated with the section σ=0 are the triangles shown in Fig. 11 are labeled ζ=0.1, ζ=2.3, and ζ=4.5, respectively. As mentioned above, in the symmetric case, some inverter states lead to the same voltage vectors. Accordingly, the segments ζ=0 and ζ=1, as well as the segments ζ=2 and ζ=3, and the segments ζ=4 and ζ=5 are congruent. However, in the asymmetric case (ρ≠0.5), the congruence is destroyed, as in Fig. 9. Nevertheless, segments that are congruent in the symmetric case may partially overlap in the asymmetric case.

[0050] In Fig. 12, the shaded area of ​​the diagram indicates the section σ=1 of the sector ∑=0. The segments associated with the section σ=1 are the triangles shown in Fig. 12 are labeled ζ=0,1, ζ=2,3 and ζ=4,5 respectively. Here too, the segments ζ=0 and ζ=1 as well as the segments ζ=2 and ζ=3 and the segments ζ=4 and ζ=5 are congruent. The segments in the Fig. 11 and Fig. 12 are essentially the four triangles that form a sector ∑. Each vertex is the endpoint of a voltage vector (V x , V y ), which corresponds to one or more inverter states (V U , V V , V W ) corresponds.

[0051] To select a particular modulation sequence, the space vector modulator 201 must determine in which segment (denoted by ∑, σ, and ζ) the end point of the reference voltage vector V REF *. Geometrically, this determination is obvious. The space vector modulator 201 can make this determination by calculating the barycentric coordinates for the reference vector V REF* using the voltage vectors represented by the three vertices of each segment ζ (barycentric method). If the correct segment is found, this method also yields the times corresponding to the inverter states corresponding to the respective vertices. The mathematics behind the problem of determining whether a point lies within a triangle is well known and therefore will not be discussed in detail here.

[0052] A result of the decomposition of the outer hexagon into the Fig. 10-12 in sectors ∑, sections σ and segments ζ is in the table of Fig. 5, which has already been discussed above. Six sectors with two sections each, each of which is assigned to six segments, result in 72 possible combinations, which are shown in the table of Fig. 5. However, as discussed above, the segments ζ=0 and ζ=1, as well as the segments ζ=2 and ζ=3 and the segments ζ=4 and ζ=5, overlap. Therefore, a modulation sequence consists of the subsequences assigned to two overlapping segments. In Fig. 5, each row contains one of 36 modulation sequences, with the first subsequence (of three inverter states) of each sequence being assigned to the segments ζ=0, 2, or 4, and the second subsequence (of three inverter states) of each sequence being assigned to the segments ζ=1, 3, or 5. Together, the two subsequences contain six inverter states that form a modulation sequence.

[0053] Fig. 11 shows an example where the reference vector V REF * has an end point in the segments ζ=4 and ζ=5 in the lower section σ=0 of the first sector ∑=0. These parameters ∑, σ, ζ characterize the modulation sequence LNN, PNN, PUN, PUU, PUN, PNN in the third row of the table in Fig. 5. During the modulation sequence, the inverter output jumps between the vertices of the triangles represented by the segments ζ=4 and ζ=5 (which are shown in Fig. 11 are congruent, but in a general case only partially overlap, as in Fig. 9). The resulting switching pattern is shown by the timing diagrams in Fig. 13, in which the first state LNN as in the previous examples of the Fig. 7 and Fig. 8 has been divided into two halves again, further illustrated.

[0054] Since all vertices in Fig. 11 with the exception of those of the outer hexagon from the supply voltages U P and U N depend, it is obvious that the Fig. 13 shown one-times TN0,TN1,TN2,TP0,TP1,TP2, which results from the barycentric method, also from the supply voltages U P and U N(and thus on the parameter ρ). Consequently, the duty cycles of the control signals generated by the space vector modulator 201 for the transistors of the inverter 202 also depend on the supply voltages U P and U N away.

[0055] Although the invention has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the components or structures (units, assemblies, devices, circuits, systems, etc.) described above, the terms used to describe such components (including any reference to a "means") are intended, unless otherwise specified, to correspond to any component or structure that performs the stated function of the described component (i.e., that is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention illustrated herein.

Claims

[1] Circuit that has: a battery monitoring circuit configured to provide a positive supply voltage (U P ) and a negative supply voltage (U N ) with respect to a neutral node(s); an inverter (202) configured to generate a plurality of modulated phase voltages (V u , V v , V w ) representing a reference voltage vector; and a space vector modulator (201) configured to generate modulated drive signals for the inverter (202) based on the reference voltage vector, wherein duty cycles of the modulated drive signals are determined by the monitored positive supply voltage and the monitored negative supply voltage (U N ) depend. [2] The circuit of claim 1, further comprising: a first battery and a second battery connected to the neutral node (n) and configured to supply the positive supply voltage (U P ) and the negative supply voltage (U N ). [3] The circuit of claim 1 or 2, wherein the inverter (202) is an active neutral point clamped (ANPC) multi-level converter. [4] A circuit according to claim 3, wherein: the ANPC multi-level converter comprises three phases, each of the three phases being coupled between a first supply node (n1) and a second supply node (n4) and being designed to supply a DC supply voltage corresponding to a difference between the positive supply voltage (U P ) and the negative supply voltage (U N ) corresponds to, and each phase of the three phases is designed to supply a respective one of the three phase voltages (V u , V v , V w) by outputting either the positive supply voltage (U P ), the negative supply voltage (U N ) or a neutral point voltage depending on a switching state of the ANPC multi-level converter. [5] Circuit according to one of claims 1 to 4, wherein the space vector modulator (201) is adapted to generate the modulated drive signals such that the inverter (202) passes through a selectable modulation sequence of switching states within a cycle period, and the selectable modulation sequence is adapted to be selected based on the reference voltage vector. [6] A circuit according to claim 5, wherein: the space vector modulator (201) is designed to generate the modulated control signals such that within a cycle period each switching state of the selectable modulation sequence is active for a specific on-time; the on-times of the switching states are designed to be determined based on the duty cycles of the control signals; and the duty cycles of the control signals are designed to be dependent on the monitored positive supply voltage and the monitored negative supply voltage (U N ) to hang out. [7] A circuit according to claim 5, wherein: the selectable modulation sequence contains first states and second states; the first states are configured to cause the inverter (202) to generate a positive average load current during a cycle in which the first states are active; and the second states are configured to cause the inverter (202) to generate a negative average load current during a cycle in which the second states are active. [8] A circuit according to claim 7, wherein: the space vector modulator (201) is designed to, in response to the positive supply voltage (U P ) a higher value than the negative supply voltage (U N ) to control the duty cycles of the modulated control signals such that cumulative on-times of the first states are greater than cumulative on-times of the second states; and the space vector modulator (201) is designed to, in response to the positive supply voltage (U P ) a smaller amount than the negative supply voltage (U N ) to control the duty cycles of the modulated control signals such that the cumulative on-times of the second states are greater than the cumulative on-times of the first states. [9] Method comprising: Monitoring a positive supply voltage (U P ) and a negative supply voltage (U N) an inverter (202) with respect to a neutral node (n); Generating modulated drive signals for the inverter (202) based on a reference voltage vector by a space vector modulator (201), wherein duty cycles of the modulated drive signals are determined by the monitored positive supply voltage and the monitored negative supply voltage (U N ) depend; and Providing the modulated drive signals to the inverter (202), wherein the inverter (202) is configured to provide a plurality of modulated phase voltages representing the reference voltage vector in response to the modulated drive signals. [10] The method of claim 9, wherein the inverter (202) is an active neutral point clamped (ANPC) multi-level converter. [11] A method according to claim 9 or 10, further comprising: Providing the positive supply voltage (U P) by a first battery connected to the neutral node (n); and Providing the negative supply voltage (U N ) by a second battery connected to the neutral node (n). [12] Three-level inverter system comprising: a first power supply connected to a neutral node (n) and configured to provide a positive supply voltage (U P ) to deliver; a second power supply connected to the neutral node (n) and configured to provide a negative supply voltage (U N ) to deliver; a battery monitoring circuit (203) which is designed to monitor the positive supply voltage (U P ) and the negative supply voltage (U N ) to monitor; an inverter (202) which is driven by the positive supply voltage (U P ) and the negative supply voltage (U N) is supplied; and a space vector modulator (201) configured to generate modulated drive signals for the inverter (202) based on the monitored positive supply voltage and the negative supply voltage (U N ), wherein the generated modulated control signals are designed to cause the positive supply voltage (U P ) and the negative supply voltage (U N ) remain essentially balanced. [13] A three-level inverter system according to claim 12, wherein the inverter (202) is configured to provide a plurality of modulated phase voltages representing a reference voltage vector; the space vector modulator (201) is designed to generate the modulated drive signals for the inverter (202) based on the reference voltage vector; and Duty cycles of the modulated control signals from the monitored positive supply voltage and the monitored negative supply voltage (U N ) depend. [14] A three-level inverter system according to claim 12 or 13, wherein the inverter (202) is an active neutral point clamped (ANPC) three-level converter. [15] A three-level inverter system according to claim 14, wherein the ANPC three-level converter includes three phases, each of the three phases being coupled between a first and a second supply node and being configured to provide a DC supply voltage corresponding to a difference of the positive supply voltage (U P ) and the negative supply voltage (U N ) corresponds to; and each phase of the three phases is adapted to generate a respective one of three phase voltages (V u , V v , V w) by outputting either the positive supply voltage (U P ), the negative supply voltage (U N ) or a neutral point voltage. [16] Three-level inverter system according to one of claims 12 to 15, wherein the space vector modulator (201) is designed to generate the modulated control signals such that the inverter (202) passes through a selectable modulation sequence of switching states within one cycle period; and the selectable modulation sequence is configured to be selected based on a reference voltage vector. [17] Three-level inverter system according to one of claims 12 to 15, wherein the space vector modulator (201) is designed to generate the modulated control signals such that the inverter (202) passes through a selected modulation sequence of switching states within one cycle period; and the selectable modulation sequence is designed to be determined based on a reference voltage vector such that the positive supply voltage (U P ) and the negative supply voltage (U N ) remain essentially balanced. [18] Three-level inverter system according to one of claims 12 to 15, wherein the space vector modulator (201) is designed to generate the modulated control signals such that within a cycle period each switching state of a selectable modulation sequence is active for a specific on-time; the on-times of the switching states are designed to be determined based on the duty cycles of the control signals; and the duty cycles of the control signals from the monitored positive supply voltage and the monitored negative supply voltage (U N ) depend.

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