Semiconductor Device and Writing Method

Abstract

The access time from a CPU to a register can be reduced while preventing software complication. A semiconductor device includes: a decoder circuit that determines a write source process; a write enable setting memory circuit that stores a write enable setting specifying a processor authorized to perform writes to each bit of a write destination register; a masking / union circuit that generates a value to be written back to the write destination register based on the write enable setting and the write source processor; and a write-back circuit that writes the value back to the write destination register.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to Japanese Patent Application No. 2023-184433, filed on October 27, 2023, the disclosure of which is incorporated herein by reference. BACKGROUND

[0002] The present invention relates to a semiconductor device that performs data writing and a writing method.

[0003] In recent years, there has been a demand to mount a plurality of CPUs (Central Processing Units) on a semiconductor device such as an in-vehicle microcomputer to sequentially execute a safety-related function even when a fault occurs. The safety-related function includes a function for preventing a series of faults when the plurality of CPUs access a shared resource register. In the shared resource register mounted on the in-vehicle microcomputer, a register may include a bit section accessible by the plurality of CPUs.

[0004] A technique is disclosed which is listed below.

[0005] [Patent Document 1] International Patent Publication No. 2010 / 029682

[0006] In a related art, only the enabled bit portion can be rewritten by a read-modify-write process. For example, Patent Document 1 discloses a technique related to an information processor that executes the read-modify-write process.

[0007] However, executing the read-modify-write method requires arbitration processing to stop access from a CPU different from the CPU accessing the register, as well as a variety of access processing and arithmetic processing based on the read-modify-write method. Therefore, this method has problems such as software complication and an increase in the CPU's access time to the register.

[0008] The complexity of software and the increase in CPU access time are causing increased software development time and reduced performance of the in-vehicle microcomputer. Therefore, the requirements for a hardware-based function and system for avoiding a variety of faults have increased. Such a function and system are called FFI (Freedom From Interface) and are required by IS026262. SUMMARY

[0009] As described above, it is desirable to reduce the access time from the CPU to the register while avoiding the complication of the software.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0011] A semiconductor device according to an embodiment includes: a decoder circuit that designates a write source processor; a write enable setting storage circuit that stores a write enable setting indicating a processor enabled to perform writing to each bit of a write destination register; a mask / merge circuit that generates a value to be written back to the write destination register based on the write enable setting and the write source processor; and a write-back circuit that writes back the value to be written back to the write destination register.

[0012] A writing method according to an embodiment includes: a step of determining a write source processor; a step of generating a value to be written back to a write destination register based on the write source processor and a write enable setting indicating a processor enabled to perform writing to each bit of the write destination register; and a step of writing back the value to be written back to the write destination register.

[0013] According to the embodiment, the access time from the CPU to the register can be reduced while preventing the complication of the software. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing a configuration of a semiconductor device according to a first embodiment. Fig. 2 is a schematic diagram showing a configuration of a decoder circuit according to the first embodiment. Fig. 3 is a schematic diagram showing a write enable setting circuit according to the first embodiment. Fig. 4 is a schematic diagram showing a configuration of a masking / combining circuit according to the first embodiment. Fig. 5 is a timing chart showing an operation of the decoder circuit according to the first embodiment. Fig. 6 is a timing chart showing an operation of the masking / combining circuit according to the first embodiment. Fig. 7 is a timing chart showing an operation of the write-back circuit according to the first embodiment. Fig. 8 is a diagram for explaining a configuration of a semiconductor device according to a second embodiment. Fig. 9 is a schematic diagram showing a configuration of a write-back circuit according to the second embodiment. Fig. 10 is a timing chart for explaining an operation of the write-back circuit according to the second embodiment. DETAILED DESCRIPTION

[0014] For clarity of explanation, the following description and drawings are conveniently omitted and simplified. Each of the elements, each illustrated in the drawings as functional blocks that perform various types of processing, may be configured from a CPU, memory, or other circuit in a hardware manner, or may be achieved by executing a program or the like loaded into the memory in a software manner. Therefore, those skilled in the art would understand that the functional blocks can be achieved in various forms by hardware, software operating on the hardware, or their combination, and are not limited to any one of the forms. In each drawing, the same elements are designated by the same reference numerals, and their description will not be repeated if necessary.

[0015] The program includes a set of instructions (or software code) to cause a computer to perform one or more functions explained in embodiments when loaded into the computer. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. The computer-readable media or tangible storage media may include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD), other storage technologies, CD-ROM, Digital Versatile Disc (DVD), Blu-ray Disc (registered trademark), other optical disk storage, magnetic cartridge, magnetic tape, magnetic disk storage, and other magnetic storage devices. The program may be transmitted on a transient computer-readable medium or communications medium.The transient computer-readable media or communication media include, for example, but are not limited to, electrical, optical, acoustic and propagation signals of other forms. FIRST EMBODIMENT

[0016] Fig. 1 is a schematic diagram showing a configuration of a semiconductor device 100 according to a first embodiment. PWDATA[31:0], bus slave selection signals PSEL0 to PSEL7, and PADDR[31:0] are input to the semiconductor device 100 from a write source processor 200 via an APB (Advanced Peripheral Bus) bus interface IF. PWDATA[31:0] is also referred to as write data. PADDR[31:0] is also referred to as a bus address. Bus slave selection signals PSEL0 to PSEL7 correspond to ID0 to ID7 of the write source processors. Note that the number of IDs may be two or more, six or fewer, or eight or more. Then, the semiconductor device 100 executes writing to a write destination register 310 of a write destination module 300 via the APB bus interface IF.

[0017] The semiconductor device 100 includes a decoder circuit 110, a write enable setting storage circuit 120, a mask / merge circuit 130, and a write-back circuit 140.

[0018] Decoder circuit 110 receives as input the bus slave select signals PSEL0 through PSEL7 and PADDR[31:0]. The bus slave select signal PSEL specifies a write source processor 200. Decoder circuit 110 identifies the write source processor 200.

[0019] Decoder circuit 110 stores information (also referred to as MASK_CON) about whether a masking process is to be performed on each bit of write destination register 310. For example, if the masking process is not performed on a bit, all processors may be enabled to write data to that bit. If the masking process is performed on a bit, a specific processor may be enabled to write data to that bit.

[0020] The decoder circuit 110 generates a decode ID (also referred to as a decode signal) based on the MASK_CON and the bus slave selection signals PSEL0 to PSEL7 and outputs the decode ID to the mask / combine circuit 130.

[0021] In addition, the decoder circuit 110 outputs PSEL_OUT based on PSEL0 to PSEL7 to the write-back circuit 140. Note that a more detailed configuration of the decoder circuit 110 will be described later.

[0022] The write enable setting storage circuit 120 stores a write enable setting indicating a processor enabled to execute writing to each bit of the write destination register 310. The write enable setting storage circuit 120 may include, for example, three flip-flops corresponding to each bit. As a result, ID0 to ID7 of the processors 200 can be expressed. The write enable setting of each bit is also referred to as SFR_ID[2:0]. Note that a detailed configuration of the write enable setting storage circuit 120 will be described later.

[0023] The masking / merging circuit 130 generates a value to be written back to the write destination register 310 based on the write enable setting and the write source processor 200. Specifically, the masking / merging circuit 130 may generate the value to be written back to the write destination register 310 for each bit based on the write enable setting and the decode ID. The masking / merging circuit 130 includes, for example, a masking circuit 131, a masking circuit 132, an OR circuit 133, and a comparator circuit 134. Each of the masking circuits 131 and 132 is composed of, for example, an AND circuit or the like. The masking circuit 131 outputs the data to be written (such as PWDATA

[31] ) to the OR circuit 133 based on an instruction from the comparator circuit 134.The masking circuit 132 outputs the data already written to a bit (such as bit 31) of the write destination register 310 based on the instruction of the comparator circuit 134. The comparator circuit 134 operates the masking circuits 131 and 132 based on the decode ID and the SFR_ID. Note that a detailed configuration of the masking / merging circuit 130 will be described later.

[0024] Write-back circuit 140 writes the value to be written back for each bit input from mask / combine circuit 130 to write-destination register 310. Note that write-back circuit 140 may include a selector for selecting PWDATA[31:0] and the value to be written back based on PSEL_OUT. Write-back circuit 140 also outputs PWDATA[31:0], PSEL, and PADDR[31:0] to write-destination module 300.

[0025] With reference to Fig. Figure 2 describes the detailed configuration of the decoder circuit 110. The decoder circuit 110 includes a comparator circuit 111, a selector 112, a signal generator 113, and a selector 114.

[0026] Comparator circuit 111 compares PADDR[18:16] contained in address bus PADDR[19:0] with PSEL_ID[2:0], which is the binarized data of bus slave select signals PSEL0 to PSEL7. PADDR[18:16] is a bit indicating write source processor 200. Comparator circuit 111 outputs a comparison result to selector 112 and selector 114.

[0027] As input, selector 112 receives MASK_CON[31:0] for each PADDR[15:0], which indicates whether the masking process should be performed on each bit. Note that "H" below may be added to a hexadecimal trailing end, while "B" may be added to a binary trailing end.

[0028] If the PADDR[15:0] is "0000 H “, the MASK_CON[31:0] is, for example, set to “01···01 B The numeric value "1" indicates that the masking process is valid, and the numeric value "0" indicates an always writable state. If the PADDR[15:0] is "0001 H “, the MASK_CON[31:0] is displayed as “00···11 B '. If the PADDR[15:0] is '1FFF H “, the MASK_CON[31:0] is displayed as “00··· 000 B ". If the signals compared by the comparator circuit 111 are equal, the selector 112 outputs the MASK_CON[31:0] corresponding to the PADDR[15:0] to the signal generator 113.

[0029] The signal generator 113 generates a decode ID[3:0][31:0] using the MASK_CON[31:0] and the PSEL_ID[2:0]. If each bit of the MASK_CON[31:0] is 0, the signal generator 113 sets the decode ID[3:0][] corresponding to this bit to 8. H". If each bit of MASK_CON[31:0] is 1, the signal generator 113 sets the decoding ID[3:0][] corresponding to this bit = {0 B + PSEL_ID[2:0]}". For example, if the PADDR is "0001 H “, the MASK_CON[31:0] is “00···11 B “ and the PSEL_ID[2:0] is “1 H In this case, the decoding ID[3:0][31:0] is “88···11 H “.

[0030] If each bit of MASK_CON[31:0] is 0, it can also be said that the signal generator 113 replaces this bit with a predetermined bit (such as 8). If each bit of MASK_CON[31:0] is 1, it can also be said that the signal generator 113 replaces this bit with the PSEL_ID.

[0031] The selector 114 receives as inputs PSEL0 to PSEL7 and the signal whose output is set to 1. If the signals compared by the comparator circuit 111 are not equal, the selector 114 outputs 1 as PSEL_OUT. If the signals compared by the comparator circuit 111 are equal, the selector 114 outputs the PSEL_OUT corresponding to PSEL0 to PSEL7. For example, if PSEL_ID[2][1][0] is "001", the selector 114 outputs PSEL0. If PSEL_ID[2][1][0] is "010", the selector 114 outputs PSEL1. If PSEL_ID[2][1][0] is "111", the selector 114 outputs PSEL7.

[0032] The decoder circuit 110 has a function of outputting {0000 H + PADDR[15:0]} based on PADDR[15:0].

[0033] The decoder circuit 110 can reduce a probability of occurrence of error writing by using the comparator circuit 111 to compare PSEL_ID[2:0] and PADDR[18:16].

[0034] With reference to Fig. 3 explains the detailed configuration of the write enable setting storage circuit 120. The write enable setting storage circuit 120 includes an APB bus decoder 121 and a memory 122.

[0035] The APB bus decoder 121 receives PSEL, PADDR[31:0], PWDATA[31:0], and PWRITE as inputs via the APB bus interface IF. PWRITE is a signal indicating whether writing should be performed. The APB bus decoder 121 outputs PRDATA[31:0] via the APB bus interface IF.

[0036] Memory 122 contains three FF flip-flops for each bit. The three FF flip-flops store the write enable setting (also referred to as SRF_ID[2:0]), which indicates the ID of the processor authorized to write to that bit. Memory 122 outputs the SRF_ID[2:0] of each bit from bit0 to bit31. The write enable setting can be set via APB bus decoder 121.

[0037] With reference to Fig. 4, the detailed configuration of the masking / combining circuit 130 is explained. The masking / combining circuit 130 includes a masking / combining circuit 130_0 for bit0, ..., a masking / combining circuit 130_30 for bit30, and a masking / combining circuit 130_31 for bit31. The masking / combining circuit 130_31 will be specifically explained, and the detailed explanation for the masking / combining circuits 130_0 to 130_30 will be omitted.

[0038] The masking / combining circuit 130_31 includes an AND circuit 131, an AND circuit 132, an OR circuit 133, and a comparator circuit 134. The AND circuit 131 receives as input PWDATA

[31] and AB_OUT, which is an output of the comparator circuit 134. The AND circuit 132 receives as input a register value

[31] of the write-destination register 310 and negates AB_OUT, which is the output of the comparator circuit 134. The OR circuit 133 generates a write-back register value

[31] of the write-destination register 310 by performing an OR operation between an output of the AND circuit 131 and an output of the AND circuit 132.

[0039] As an input, the comparator circuit 134 receives “A = Decode ID[3:0]

[31] ” and “B = {0 B + SFR_ID[2:0]}" and then outputs "AB_OUT = 1" if a condition in which "A = B" or "A = 8 H" is met. If the condition is not met, especially if "A ≠ B" is specified, the comparator circuit 134 outputs "AB_OUT = 0".

[0040] For example, in a case of “MASK_CON

[31] = 0” because the masking process is not executed, “Decode-ID[3:0]

[31] = 8 H ", and therefore "AB_OUT = 1" is set, and PWDATA

[31] is written back. Alternatively, even in a case of "MASK_CON

[31] = 1", when PSEL_ID[2:0]

[31] and SFR_ID[2:0]

[31] are the same, "AB_OUT = 1" is set, and PWDATA

[31] is written back. If the conditions described above are not met, "AB_OUT = 0" is set, and therefore the register value

[31] of the write destination register 310 is written back.

[0041] The same processing is also performed in the masking / combining circuits 130_0, ..., and 130_30. As a result, the write-back register value [0], ..., the write-back register value

[30] , and the write-back register value

[31] are output.

[0042] Next, with reference to Fig. 5 to Fig. 7 an operation of the semiconductor device 100 is explained.

[0043] Fig. Figure 5 is a timing diagram illustrating the operation of decoder circuit 110. Decoder circuit 110 determines whether PADDR[19:16] extracted from PADDR[19:0], which is an address accessed by a user, is equal to PSEL_ID[2:0], which indicates PSEL0 to PSEL7. For example, if PADDR[19:16] is "0001s" while PSEL_ID[2:0] is 1, H, it can be determined that PADDR[19:16] is equal to PSEL_ID[2:0]. Based on this, decoder circuit 110 determines whether this access is the user's intended access.

[0044] The decoder circuit 110 selects information about whether the masking process is to be performed on each bit of the write destination register 310 based on PADDR[15:0], which indicates the address of the write destination register 310, and outputs the information as MASK_CON[31:0]. As shown by a dashed arrow 21, the decoder circuit 110 replaces "1" contained in MASK_CON[31:0] with PSEL_ID[2:0] and replaces "0" contained in MASK_CON[31:0] with "8," and outputs the resulting data as the decode ID[3:0][31:0]. As shown by a dashed arrow 22, the decoder circuit 110 outputs PSERL_OUT corresponding to PSEL0 to PSEL7. Further, as shown by a dashed arrow 23, the decoder circuit 110 outputs "0000" B+ PADDR[15:0]" as PADDR_OUT[19:0].

[0045] Fig. 6 is a timing diagram illustrating the operation of the masking / merging circuit 130. The masking / merging circuit 130 determines for each bit whether a condition is met where the decode ID[3:0] is 8 or where the decode ID[3:0] is equal to SFR_ID[2:0]. The masking / merging circuit 130 writes PWDATA of that bit to the write-back register value of the bit that meets this condition.

[0046] For example, the first to fourth bits from the left of the decoding ID[3:0][31:0] are “8888 H ” and therefore the PWDATA and the write-back register value are equal to each other, as shown by arrow 31. For the same reason, the PWDATA “0011 B “ equal to the write-back register value “0011 B “, as shown by arrow 32.

[0047] In addition, the ninth to twelfth bits from the left of the decoding ID[3:0][31:0] are “1111H “ and the corresponding bits of the SFR_ID[2:0][31:0] are also “1111 H Therefore, as shown by a dashed arrow 33, the PWDATA “0110 B “ equal to the write-back register value “0110 B ". Similarly, the second to fourth bits from the right of the decoding ID[3:0][31:0] are "111 H “ and second to fourth bits from the right of the SFR_ID[2:0][31:0] are also “111 H '. Therefore, as shown by a dashed arrow 34, the PWDATA '110 B “ equal to the write-back register value “100 B “.

[0048] The masking / merging circuit 130 writes the write-destination register value of that bit to the write-back register value of the bit that does not satisfy the condition. For example, the fifth through eighth bits from the left of the decode ID[3:0][31:0] are "1111." H “ and the corresponding bits of the SFR_ID[2:0][31:0] are “2222 H” and therefore they are not equal to each other. Therefore, as shown by a dashed arrow 35, the write destination register value “0000 B ” and the write-back register value “0000 B " are equal to each other. Similarly, the first bit from the right of the decoding ID[3:0][31:0] is "0 H “ and the first bit from the right of the SFR_ID[2:0][31:0] is “1 H " and therefore they are not equal to each other. Therefore, as shown by a dashed arrow 36, the write destination register value "0" and the write-back register value "0" are equal to each other.

[0049] Fig. 7 is a timing diagram illustrating the operation of the write-back circuit 140. The decoder circuit 110 has already generated PADDR_OUT[15:0], from which the bit related to the write source processor 200 has been removed. As indicated by a dashed arrow 41, the write-back circuit 140 generates PADDR[31:0], which is a combination of PADDR_OUT[19:0] based on PADDR_OUT[15:0] and PADDR[31:20], and outputs PADDR[31:0] to the write destination module 300. Furthermore, as indicated by a dashed arrow 42, the write-back circuit 140 outputs the write-back register value [31:0] to the write destination module 300 as PWDATA[31:0]. In addition, as shown by a dashed arrow 43, the write-back circuit 140 generates PSEL based on the PSEL_OUT and outputs the PSEL to the write target module 300.

[0050] The semiconductor device 100 according to the first embodiment can control writing from the plurality of processors to the write target module 300 by identifying the write source processor 200 and using the write enable setting. This case does not require exclusive control using software and register reading for write-back.

[0051] In the semiconductor device 100, the CPU access time can be reduced while preventing software complications. And even if the software is modified, the function of preventing a variety of errors can be maintained. SECOND EMBODIMENT

[0052] A second embodiment is a modification example of the first embodiment. Referring to Fig. 8, a configuration of a semiconductor device 100a according to the second embodiment is explained. In comparison between Fig. 1 and Fig. 8, PSEL (Privilege), indicating that the write source processor 200 is privileged, is output to the write-back circuit 140. If the write source processor 200 is privileged, the semiconductor device 100a outputs PADDR[31:0] and PWDATA[31:0] to the write target module 300 without passing through the mask / merge circuit 130.

[0053] With reference to Fig. Figure 9 explains the detailed configuration of the write-back circuit 140 according to the second embodiment. The write-back circuit 140 includes selectors 141 to 143.

[0054] When the PSEL (privilege) is active, selector 141 selects the PSEL (privilege) and outputs the privilege to the write target module 300. When the PSEL (privilege) is active, selector 142 selects PWDATA[31:0] and outputs PWDATA[31:0] to the write target module 300. When the PSEL (privilege) is active, selector 143 selects PADDR[31:0] and outputs PADDR[31:0] to the write target module 300.

[0055] Fig. 10 is a timing chart showing an operation of the write-back circuit 140 according to the second embodiment. When the PSEL (privilege) is active, as indicated by a dashed arrow 51, not the write-back register value [31:0] but PWDATA[31:0] is output to the write-destination module 300. Furthermore, as indicated by a dashed arrow 52, ​​PADDR[31:0] is output to the write-destination module 300. Furthermore, as indicated by a dashed arrow 53, the PSEL (privilege) is output to the write-destination module 300.

[0056] The semiconductor device 100a according to the second embodiment can give the write-source CPU the privilege mode of not executing the masking process and can therefore systematically control the access authority to the register.

[0057] In the foregoing, the invention made by the inventors of the present application has been concretely described based on the embodiments. However, it goes without saying that the present invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the present invention. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-184433

[0001]

Claims

[1] A semiconductor device comprising: a decoder circuit that determines a write source processor; a write enable setting storage circuit that stores a write enable setting indicating a processor enabled to perform writing to each bit of a write destination register; a mask / merge circuit that generates a value to be written back to the write destination register based on the write enable setting and the write source processor; and a write-back circuit that writes back the value to be written back to the write-destination register. [2] A semiconductor device according to claim 1, wherein the decoder circuit receives a bus address and a bus slave selection signal corresponding to the write source processor as an input, the bus address contains a bit that specifies the write source processor, and the decoder circuit determines whether the bit contained in the bus address and the bus slave selection signal are equal to each other. [3] A semiconductor device according to claim 1, wherein, when a masking process on each bit of the write destination register is invalid, the decoder circuit replaces the bit with a predetermined bit to generate a decode signal, or if the masking process on the bit is valid, the decoder circuit replaces the bit with a bit indicating the write source processor to generate the decode signal. [4] A semiconductor device according to claim 3, wherein, when a condition is met in which the bit is equal to the predetermined bit or in which the bit indicating the write source processor is equal to the write enable setting, the masking / merging circuit generates the value to be written back on the basis of write data supplied by the write source processor, or if the condition is not met, the mask / merge circuit generates the value to be written back based on data written to the write destination register. [5] A semiconductor device according to claim 1, where, if the write source processor is privileged, a bus address and write data are output without passing through the mask / merge circuit. [6] Writing procedure comprising the steps: Determining a write source processor; Generating a value to be written back to a write destination register based on the write source processor and a write enable setting that indicates a processor enabled to perform writing to each bit of the write destination register; and Write the value to be written back to the write destination register. [7] The write method of claim 6, wherein, when the write source processor is privileged, a bus address and write data are output without passing through the step of generating the value to be written back.

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