NON-VOID SEMICONDUCTOR DEVICE

Abstract

A non-volatile semiconductor memory device or the like is provided, capable of reducing a cell voltage distribution range while simultaneously suppressing write delay. The non-volatile semiconductor memory device comprises: a plurality of gate lines; a plurality of bit lines intersecting the plurality of gate lines; and a plurality of memory cells connected at respective intersection points between the gate lines and the bit lines. Each plurality of memory cells is connected via the various bit lines to a gate line selected from the plurality of gate lines, and the non-volatile semiconductor memory device further comprises a plurality of write bit line current or voltage control circuits, each controlling the bit line currents to perform write operations to the plurality of memory cells simultaneously.

Description

REFERENCE TO RELATED REGISTRATION

[0001] The disclosure of Japanese patent application No. 2023-190734, filed on November 8, 2023, including the specification, drawings and abstract, is hereby incorporated by reference in its entirety. BACKGROUND

[0002] This disclosure relates to a non-volatile semiconductor storage device.

[0003] Flash memory is a non-volatile memory that performs data recording by storing electrons in a floating gate, using a semiconductor element known as a floating-gate MOSFET (metal oxide semiconductor field effect transistor).

[0004] Reference is made to a "multi-bit (value) technique" to achieve an increase in flash memory capacity. In general multi-bit writing, writing is performed simultaneously to a large number of cells in the same row. Since each memory cell has a physical variation, its cell voltage can have a write distribution range. In a multi-level cell (MLC) or similar, it is also important to control the write distribution range for reasons of reliability or other factors.

[0005] A major trend is a method for controlling write speed by gradually increasing a gate voltage. This is because, for example, the method allows Vtm to increase along the gate voltage if the other condition is the same, the control is easier to implement due to the lower load current compared to SL / BL, and the control is easier to implement due to its large voltage range.

[0006] The disclosed technology is listed below.

[0007] [Patent document 1] Japanese unexamined patent application, publication number 2023-92938 SUMMARY

[0008] In related technology, however, reducing the rise range of a pulse voltage, for example, to reduce the distribution range of a mean write level of the multi-level cell (MLC) or the like, leads to a problem, i.e., a delay in write time due to insufficient operating margin (i.e., write / erase window).

[0009] The present disclosure was made to solve such a problem and its objective is to provide a non-volatile semiconductor memory device or the like which is capable of reducing a cell voltage distribution range while suppressing write delay.

[0010] Other objectives and new features will become apparent from the description of this specification and the accompanying drawings.

[0011] In a non-volatile semiconductor memory device according to an embodiment comprising: a plurality of gate lines; a plurality of bit lines, each crossing the plurality of gate lines; and a plurality of memory cells connected via respective intersections between the gate lines and the bit lines, the plurality of memory cells is connected via the various bit lines to a gate line selected from the plurality of gate lines, and the non-volatile semiconductor memory device further comprising a plurality of write bit line current or voltage control circuits, each controlling bit line currents to perform writing to the plurality of memory cells simultaneously.

[0012] According to one embodiment, a non-volatile semiconductor memory device or the like can be provided which is able to reduce a cell voltage distribution range and simultaneously suppress a write delay. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a distribution diagram of a cell stream to illustrate a data write operation based on a reference stream type of flash memory; Fig. Figure 2 is a diagram showing a cell cross-sectional structure of a typical memory chip; Fig. Figure 3 is a diagram to illustrate a general multi-bit write operation; Fig. Figure 4 is a circuit diagram to illustrate general multi-bit writing; Fig. Figure 5 is a diagram to illustrate general multi-bit writing; Fig. Figure 6 is a diagram to illustrate general multi-bit writing; Fig. Figure 7 is a circuit diagram illustrating multi-bit writing according to an exemplary implementation; Fig. Figure 8 is a diagram illustrating multi-bit writing according to the exemplary implementation; Fig. 9 is a diagram illustrating an electronic device with a non-volatile semiconductor storage device according to the present embodiment; Fig. Figure 10 is a circuit diagram comprising a write bit line current control circuit according to the present embodiment; Fig. Figure 11 is a circuit diagram showing details of the write bit line current control circuit according to the present embodiment; Fig. Figure 12 is a diagram to illustrate a writing process in an initial phase of writing; Fig. Figure 13 is a circuit diagram to illustrate the writing process in the initial phase of writing; Fig. 14 is a diagram to illustrate a writing process in a middle phase of writing; Fig. Figure 15 is a circuit diagram to illustrate the writing process in the middle phase of writing; Fig. Figure 16 is a diagram illustrating a writing process in a final stage of writing; Fig. Figure 17 is a circuit diagram to illustrate the writing process in the final stage of writing; Fig. 18 is a flowchart of a distribution-reduced writing process according to the present embodiment; Fig. Figure 19 is a diagram illustrating a general multi-bit write operation according to another embodiment; Fig. 20 is a diagram illustrating a writing process according to another embodiment; Fig. Figure 21 is a circuit diagram to illustrate the writing process according to another embodiment; Fig. Figure 22 is a circuit diagram illustrating a writing process according to another embodiment; and Fig. Figure 23 is a circuit diagram comprising a write bit line voltage control circuit according to another embodiment. DETAILED DESCRIPTION

[0013] To simplify the explanation, the following description and drawings are accordingly omitted and simplified. In the drawings, the same elements are labelled with the same reference symbols, and their repeated explanation is omitted where necessary.

[0014] First, an overview of flash memory is provided. Flash memory is a storage medium in which data can be read and written, and it comes in various types, from built-in to portable. Examples of flash memory types include USB flash drives, SD cards, memory cards, USB flash drives, and solid-state drives (SSDs). Flash memory types are classified into NAND and NOR types based on their different electrical circuit structures. Flash memory comprises several billion cells or more, and each of these cells stores data "0" or "1". The smaller the cell size and the more cells a memory chip contains, the greater the storage capacity of the medium.

[0015] If the threshold voltage (Vt) in an erase state, where charges are discharged from its floating gate, is negative, the data stored in the memory cell in the flash memory is "1". Conversely, if a write operation is performed in the erase state to provide charges to the floating gate, the memory cell switches to a write state. If the threshold voltage (Vt) in the write state is positive, the data stored in the memory cell is "0". That is, the threshold voltage (Vt) in the erase state of the memory cell, which consists of a field-effect transistor, is lower than the threshold voltage in its write state.

[0016] The memory cell, acting as the read target, generates a cell current (also known as source-drain current) that depends on the threshold voltage when a read voltage (positive voltage) is applied to its gate. In the same memory cell, the cell current in the erase state is greater than the cell current in the write state; that is, the rise in the threshold voltage due to the supply of charges (see Fig. 1) A reading amplifier compares a reference current with the cell current to read the data “1” or “0”.

[0017] Fig. Figure 1 is a cell current distribution diagram to illustrate a data write operation based on a reference current type of flash memory. Fig. Figure 1 shows a cell current distribution curve in a case where the total stored data across a multitude of memory cells that configure the non-volatile storage device is "0", and a cell current distribution curve in a case where the stored data is "1". The cell current distribution curve in the case where the stored data is "1" is also called the erase cell distribution curve, and the cell current distribution curve in the case where the stored data is "0" is also called the write cell distribution curve. For the reference current read type, a reference current must be set within a current range where the erase cell distribution curve and the write cell distribution curve do not overlap.This is because the stored data may be falsely verified by the occurrence of a current region where the erase cell distribution curve and the write cell distribution curve overlap.

[0018] Fig. Figure 2 is a diagram showing a cell cross-sectional structure of a typical memory chip. Fig. Figure 2 is a diagram illustrating the respective normal potential arrangements at the time of a read, write, and erase operation. A cell comprises a transistor structure consisting of an n-type semiconductor and a p-type semiconductor, a gate structure, and a tunnel oxide film sandwiched between the transistor structure and the gate structure. The gate structure includes a control gate (CG), a floating gate (FG), and a memory gate (MG).

[0019] During normal writing, for example when an SSI (Source Side Injection) write is performed in an FMONOS (Flash Metal Oxide Nitride Oxide Semiconductor) cell, the write is performed in a potential arrangement, as shown in a middle diagram of Fig. Figure 2 illustrates this. That is, the magnetoresistance (MG) voltage is set to a high voltage (such as 10.5V), and the gravitational gate (CG) voltage is set to 1.0V. The source voltage is set to 4.5V, and the drain voltage is set to 0.7V. Due to this potential arrangement, electrons flowing from the source (S) are stored in the floating gate (FG) after passing through the tunnel oxide film. Since the threshold voltage (Vt) is positive in the write state, the stored data is therefore "0". In a multiple-level cell (MLC) or similar device, it may be desirable to control the write process more precisely (by gradually changing the MG voltage) due to reliability requirements.

[0020] On the other hand, at the time of data erasure, the drain voltage is set to OV and the source voltage is set to 7V. The MG voltage is set to -7V. Holes are generated near the source by the high voltage applied to the source due to the band-to-band tunneling effect, and the holes are pulled into the floating-gate FG by the negative voltage of the MG to cancel out the electrons in the floating-gate FG.

[0021] At the time of reading, the MG voltage is set to OV and the CG voltage is set to a low voltage (1.5V). The drain voltage is also set to 1.5V. As a result, a current flowing from the source to the drain is detected. If electrons are stored in the floating-gate FG, the current can only flow with difficulty. Accordingly, the stored data is recognized as "0". Conversely, if there are no electrons in the floating-gate FG, the current flows easily. Accordingly, the stored data is recognized as "1".

[0022] Fig. Figure 3 is a diagram illustrating general multi-bit writing. A vertical axis represents a drain current, or "ion," flowing between the source and the drain, as shown in Figure 3. Fig. 2 shown. A left diagram of Fig. Figure 3 shows a cell distribution in a single-level cell (SLC) and a right-hand diagram of Fig. Figure 3 shows a cell distribution in the multi-level cell (MLC - multiple level cell).

[0023] The single-level cell (SLC) is one of the NAND-type flash memory systems and is a system for storing 1-bit data from binary values ​​in a single memory element (memory cell). In the case of a "1" erase cell, no electrons are stored in the floating gate (FG). Consequently, a relatively high current flows. In the case of a "0" write cell, electrons are stored in the floating gate (FG). Consequently, a relatively low current flows. In the SLC, the respective write and erase ranges are determined by the relationship between a minimum cell current value in the erase cell distribution curve and a maximum cell current value in the write cell distribution curve. This also determines the reliability of the number of write operations, etc. Even in the SLC, the memory cell is significantly affected by excessively low write cell values.Accordingly, it may be desirable to reduce the write distribution area to prevent cell degradation.

[0024] On the other hand, a multi-level cell (MLC) is a system for storing multi-bit data consisting of ternary values ​​in a single memory element (memory cell). A Fig. The example shown in Figure 3 includes four distributions. The MLC can store four states, "00", "01", "10", and "11" (i.e., two bits). In particular, in an "OO" erase cell, no electrons are stored in the floating-gate FG. Accordingly, a relatively high current flows. On the other hand, in a write cell "10", a write cell "01", and a write cell "00", the electrons stored in the floating-gate FG are gradual in that order. Accordingly, a relatively low current flows. In the MLC, the cell's write and erase window is increased by raising the cell voltage distribution between the write cell "00" and the erase cell "11". Therefore, reliability and operational problems increase. Some embodiments can use a quad-level cell (QLC) and a triple-level cell (TLC) for multi-bit writing, and the present disclosure is applicable.

[0025] Fig. Figure 4 is a circuit diagram illustrating general multi-bit writing. The terms "Vcg" and "Vsl" represent fixed potentials. In this example, Vcg is 1.0 V and Vsl is 4.5 V. A potential "Vmg" is variable and can be gradually increased from 4.0 V to 10.5 V by a voltage source. Each Vbl is approximately 0.7 V and Ibl is 1.66 µA.

[0026] For example, in the SLC, the data in the write cell is set to "0", and the data not to be written (and which remains deleted) is set to "1". The control for writing the data "0" or "1" is carried out by a bitline write stream. If the write operation is to all cells (cells A, B, and C), the bitline stream is caused to flow through all cells, as shown in Fig. Figure 4 illustrates this. In this case, the bit line voltage is approximately 0.7V. Conversely, if writing does not occur to the individual cell, the bit line current in the individual cell is stopped.

[0027] Fig. Figure 5 is a diagram illustrating general multi-bit writing. As in Fig. As shown in Figure 4, the write operation to the multitude of cells (cells A, B, and C) is performed by applying a predetermined Vmg pulse voltage and a predetermined write bit line current Ibl to the target memory cell. The larger the amount of electrons stored in the floating gate FG, the higher the cell voltage Vt gradually becomes. It should be noted that the cell voltage Vt is a lower limit of the voltage of a gate through which a drain current flows and is also referred to as the "threshold voltage." When the Vmg voltage (or a reference current) is then applied to each of the cells (cells A, B, and C) to perform a read operation, it can be verified whether the write operation has completed for each cell or not, depending on whether the drain current corresponding to a Vt verification level of the cell is flowing. This system is called verification.Therefore, it can be verified for each cell whether the cell voltage exceeds a target cell voltage Vt verification level or not. Fig. Figure 5 represents a verification period between Vmg pulse voltages, referred to as (verification). If the cell voltage Vt does not reach the verification level, the Vmg pulse voltage is increased by a predetermined amount and applied. A verification process is then performed to check if the cell voltage Vt reaches a verification level, which signals the end of the write operation. Thus, the multi-bit write operation is performed by gradually increasing the Vmg pulse voltage and then repeating the verification process as described above.

[0028] It should be noted that in the MLC, the same write level (such as "10") can be written to all cells (cells A, B, and C). In this case, as in Fig. As shown in Figure 5, the verification level, which represents the end of the write operation, is the same for all cells (cells A, B, and C). However, different write levels can be assigned to the cells (cells A, B, and C) (for example, "10", "01", and "00" can be written to cells A, B, and C, respectively). In this case, the verification level, which represents the end of the write operation, can differ between the cells (cells A, B, and C).

[0029] As in Fig. As shown in Figure 6, a rise time range of the Vmg pulse voltage must be reduced to decrease the cell Vt distribution. However, this increases the respective number of rewrite and retry attempts, and it takes a while for the cell voltage Vt (of cell A) to return to normal. Fig. 6), into which the write was finally performed) reaches the verification level, and the multi-bit write is delayed.

[0030] In general, multi-bit writing involves simultaneously writing to a large number of cells on the same word line. Since the write speed and initial position of each cell vary, their cell voltage, Vt, has a predetermined distribution range. Writing is stopped sequentially from a cell whose cell voltage, Vt, reaches the verification level among the large number of cells being written to simultaneously. Specifically, to reduce the cell Vt distribution when the rise time of the Vmg pulse voltage is reduced, cell A (cell A in the word line) is called the first cell to be written to. Fig. 6), into which the writing process is eventually carried out under the large number of cells being written to simultaneously, is significantly delayed.

[0031] The deterioration of the memory cell can be suppressed by reducing the distribution range of the cell voltage Vt, and the amount of information can be increased by storing a large number of bits in a memory.

[0032] As described above, in the related technology, the operating margin (write and erase window) is insufficient, and therefore the problem is that the write time is delayed by the reduced distribution range of the mean write level of the MLC.

[0033] Fig. Figure 7 is a circuit diagram illustrating multi-bit writing according to an exemplary embodiment. In this embodiment, the current flowing through each of the bit lines bl is controlled at a plurality of levels (two levels, which in this example are 1.66 µA or 0.83 µA). The voltage Vmg is the same for word lines w1 in the row direction. Accordingly, it is not possible to access each of the cells (cells A, B, and C in Fig. 7) a different voltage is applied. Accordingly, in the present embodiment, adjusting the current flowing through each of the bit lines bl at the multitude of levels allows the different voltages to be applied to the cells (cells A, B, and C in Fig. 7) Thus, in the MLC, the current Ibl in a cell other than the one whose cell voltage Vt exceeds the verification level (which marks the end of the write operation) is reduced, and the write speed in that cell is decreased. As a result, the write distribution range of the cell voltage can be reduced.

[0034] Fig. Figure 8 is a diagram illustrating multi-bit writing according to the exemplary embodiment. In the present embodiment, a different verification level (i.e., a verification level B in Fig. 8) prepared lower than the verification level of the cell voltage Vt (i.e., the verification level A in Fig. 8), which represents the end of the write operation. Verification level B is used to control the current Ibl flowing through each bit line bl. Specifically, the Vmg voltage (or reference current) corresponding to verification level A or B of the cell voltage Vt is predetermined. When the predetermined Vmg voltage (or reference current) is applied to perform the read, it can be verified whether the cell voltage Vt exceeds a target cell level Vt. That is, if current value data corresponding to verification level A or B can be read by applying the cell voltage corresponding to verification level A or B, it can be verified that the cell voltage Vt exceeds the target cell voltage level Vt.If, on the other hand, the current value data corresponding to verification level A or B cannot be read by applying the cell voltage corresponding to verification level A or B, it can be verified that the cell voltage Vt does not exceed the target cell voltage level Vt.

[0035] After the Vmg pulse voltage is gradually increased to reach a level where the cell voltage Vt reaches the verification level B, the cell voltage is applied to the corresponding cell to perform the data read. If the desired current value data can be read, the current Ibl is reduced (from 1.66 µA to 0.83 µA). This reduces the write speed and the cell voltage distribution range. For example, if the distribution range is to be halved, the write speed is halved, and the number of write attempts is increased by a maximum of one. However, the total number of retries is several dozen (20 or more in this design). Accordingly, this increment makes no significant difference. That is, the write delay in the MLC can be suppressed while reducing the distribution range.The write speed is changed at this point by the bit line current Ibl. Level matching is not achieved at so many levels in the bit lines. However, the current can be roughly controlled in the case of a resolution of approximately a low single-digit level order. The current can be controlled for each of the bit lines. Accordingly, the write operation does not have to be restarted from the beginning.

[0036] Fig. Figure 9 shows an electronic device 3 comprising a non-volatile semiconductor storage device 1. The electronic device 3 includes at least one control circuit 5 that controls the operation of the entire circuit. A processing circuit in the control circuit 5 may be based on one or more microprocessors, application processors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, integrated circuits for specific use, or the like. In particular, the processing circuit may control a Y-selector described later, instruct a gate driver circuit in a write bit line current or voltage control circuit (via a write flag 1 or 2), control a voltage source, or the like. The control circuit may be used to execute software, such as an operating system or an application, on the device.

[0037] Fig. Figure 10 is a circuit diagram showing the storage device according to the exemplary embodiment. The non-volatile semiconductor storage device 1, i.e., a flash memory, comprises a memory cell array 10, a plurality of Y selectors 50, a plurality of write bit line current control circuits 100, and a gate driver circuit 30. The write bit line current control circuits 100 are each provided to correspond to the Y selectors 50.

[0038] The Y-selector 50 receives (from the control circuit 5) an externally input bit line address signal and selects a write or read bit line from a plurality of write and read bit lines. The write bit line current control circuit 100 controls the write bit line current to be supplied to the bit line selected by the Y-selector 50. The gate driver circuit 30 is configured to turn on write flag 1 or write flag 2 in each of the transistors in the write bit line current control circuit 100.

[0039] Fig. Figure 11 is an enlarged diagram of the write bit line current control circuit 100. The bit line bl coupled to the Y-selector 50 is connected to transistors Tr3 and Tr4, which are used for a current during normal writing (“Inor” in Fig. 11) The bit line bl coupled to the Y-selector 50 is connected to transistors Tr5 and Tr6 for a normal write current. Transistors Tr3 and Tr4 and transistors Tr5 and Tr6 are connected in parallel. One gate electrode of transistor Tr3 and one gate electrode of transistor Tr5 are connected together. When the gate voltage exceeding the threshold voltage is applied as write flag 1 at the normal write time, the "normal write" current Inor (Ibl = 1.66 µA) flows through transistors Tr3 and Tr4 and transistors Tr5 and Tr6.

[0040] On the other hand, the bit line bl coupled to the Y selector 50 is connected to transistors Tr1 and Tr2, which are responsible for a current ("low" in) at the time of slow writing. Fig. 11) can be used. If the gate voltage exceeding the threshold voltage is applied as write flag 2 at the time of slow writing, a “slow write” current Ilow (Ibl = 0.83 µA) flows through transistors Tr1 and Tr2. The “slow write” current Ilow (Ibl = 0.83 µA) can be half the size of the “normal write” current Inor (Ibl = 1.66 µA).

[0041] Although in Fig. Not shown in Figure 10, a voltage source is provided for gradually increasing and applying the Vmg voltage. The gate driver circuit 30 can be provided as part of the integrated circuit. Each Vbl is approximately 0.7V and the Ibl is 1.66 µA. The gate line of each of transistors Tr2 and Tr6 in each of the write bit line current control circuits 100 is connected to a transistor Tr7.

[0042] Fig. Figure 12 is a diagram to illustrate a writing process in an initial stage of writing, and Fig. Figure 13 is a circuit diagram illustrating the writing process in the initial writing phase. During this initial phase (i.e., until the cell voltage Vt exceeds the verification level B), while the Vmg voltage is gradually increased, cell writing is performed using the Ibl current (i.e., 1.66 µA) and the current source used during normal writing. As shown in the circuit diagram of Fig. As shown in Figure 13, for all cells A, B and C, each of the write bit line current control circuits 100 performs a control to allow the “normal write” current Inor (Ibl = 1.66 µA) to flow through transistors Tr3 and Tr4 and transistors Tr5 and Tr6 when the gate voltage exceeding the threshold voltage is applied as write flag 1 at the time of normal writing.

[0043] Fig. Figure 14 is a diagram illustrating a writing process in a middle stage of writing, and Fig. Figure 15 is a circuit diagram illustrating the writing process in the middle phase of the writing process. In the middle phase, the Vmg voltage continues to gradually increase, and the cell (i.e., cell B in Fig. 14), whose cell voltage Vt exceeds verification level B, appears. It should be noted that the cell voltage Vt of cell C exceeds verification level A, and therefore the writing is terminated. As shown in the circuit diagram of Fig. As shown in Figure 15, for cell A, the write bit line current control circuit 100 performs control to allow the "normal write" current Inor (Ibl = 1.66 µA) to flow through transistors Tr3 and Tr4 and transistors Tr5 and Tr6 when the gate voltage exceeding the threshold voltage is applied as write flag 1 at the time of normal writing. For cell B, the write bit line current control circuit 100 performs control to allow the "slow write" current Ilow (Ibl = 0.83 µA) to flow through transistors Tr1 and Tr2 when the gate voltage exceeding the threshold voltage is applied as write flag 2 at the time of slow writing. The write operation for cell C has ended, and therefore the write bit line current control circuit 100 does not allow the "normal write" current Inor (Ibl = 1.66 µA) and the "slow write" current Ilow (Ibl = 0.83 µA) to flow through it.

[0044] Fig. Figure 16 is a diagram illustrating a writing process in a final stage of the writing process, and Fig. Figure 17 is a circuit diagram illustrating the writing process in the final stage of the writing process. In the final stage of the writing process, the voltage Vmg is gradually increased, and the respective cell voltages Vt of almost all cells exceed the verification level B ( Fig. 16). As in Fig. As shown in Figure 17, for cell A, the write bit line current control circuit 100 performs control to allow the "slow write" current Ilow (Ibl = 0.83 µA) to flow through transistors Tr1 and Tr2 when the gate voltage exceeding the threshold voltage is applied as write flag 2 at the time of the slow write. For cells B and C, the respective cell voltages Vt of cells B and C exceed the verification level A, and the write has been terminated; therefore, neither of the write bit line current control circuits 100 allows the "normal write" current Inor (Ibl = 1.66 µA) nor the "slow write" current Ilow (Ibl = 0.83 µA) to flow through them.

[0045] For all cells (cells A, B and C), when the respective cell voltages exceed the verification level A, all write bit line current control circuits 100 each stop the current, and the write is terminated.

[0046] Fig. Figure 18 is a flowchart of a distribution-reduced writing process. The flowchart can be generated by at least one of the control circuits 5 ( Fig. 9) are carried out, which control the operation of the entire circuit. The control circuit 5 receives data from an external source, which is to be written to each of the memory cells (step S101). For each of the memory cells, the control circuit 5 checks whether the write flag 1 is "H" (at the time of writing) or "L" (at the time of not writing), while the write flag 2 is "H" (at the time of writing) or "L" (at the time of not writing) (step S102). If the write flag 1 is "H" (at the time of writing) while the write flag 2 is "H" (at the time of writing) ("NO" in step S102), the control circuit 5 checks, based on the read result of each of the memory cells, whether their cell voltage exceeds the verification level A or not (step S104).If the cell voltage does not exceed verification level A (“NO” in step S105), control circuit 5 checks, based on the read result of each cell, whether the cell voltage exceeds verification level B (step S106). If, on the other hand, the cell voltage does exceed verification level A (“YES” in step S105), control circuit 5 sets both write flag 1 and write flag 2 to “L” (at the time of no writing) (step S1051). This stops writing to the cell.

[0047] If the cell voltage exceeds level B (“YES” in step S107), write flag 2 is “H” (at the time of writing), while write flag 1 is “L” (at the time of no writing). Control circuit 5 causes write bit line current control circuit 100 to allow the “slow write” current to flow through the bit line to the corresponding cell to perform the slow write (step S108). Conversely, if the cell voltage does not exceed level B (“NO” in step S107), write flag 1 is “H” (at the time of writing). Control circuit 5 causes write bit line current control circuit 100 to allow the “normal write” current to flow through the bit line to the corresponding cell to perform the normal write (step S109). If the write data is 2 or 1 in all IOs “L” (at the time of non-writing) (“YES” in step S110), processing ends.On the other hand, if the write data 2 or 1 in all IOs is not “L” (at the time of not writing) (i.e., if one of them is “H” (at the time of writing) (“NO” in step S110), the write operation is performed (step S111), and the processing from step S102 to step S110 is repeated.

[0048] In the embodiment described above, the cell voltage distribution Vt can be reduced. Furthermore, this disclosure is also applicable to fast and high-speed writing, as described below. The plurality of memory cells can include at least one multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC). OTHER EXAMPLES OF EXECUTION

[0049] Fig. Figure 19 is a diagram illustrating general multi-bit writing according to another embodiment. In a general MLC case, to write a multitude of cell voltage levels simultaneously, a write start voltage is initiated that corresponds to a distribution "B" corresponding to verification level B, which is lower than verification level A, representing the end of the write. This must be started from the relatively low Vmg voltage. Consequently, it takes a long time to complete writing a distribution "A" corresponding to verification level A, which represents the end of the write.

[0050] Accordingly, in the present embodiment, the write current Ibl for each of the target distributions corresponding to the memory cells is made controllable by the write bit line current control circuit 100, which is the same as that of the embodiment described above, in order to achieve the fast write operation.

[0051] Fig. Figure 20 is a diagram illustrating the writing process according to another embodiment. For the cell (such as cell A or cell C) corresponding to distribution A, the "normal write" current Inor (Ibl = 1.66 µA) is set to achieve the normal write speed. Conversely, for the cell (such as cell B) corresponding to distribution B and having a lower cell voltage level than distribution A, the "slow write" current Inor (Ibl = 0.83 µA) is set to achieve the slow write speed. It should be noted that, for example, distribution A corresponds to the cell in [Figure 20]. Fig. The 3 depicted writing cell “01” can correspond to the distribution B of the in Fig. This can correspond to the letter cell “10” shown in the 3.

[0052] As a result, the Vmg voltage at the start of the write operation can be set relatively higher than the voltage specified in the Fig. 19 case shown, and the number of write repetitions can be reduced to increase the speed of the writing process.

[0053] Fig. Figure 21 is a circuit diagram illustrating the writing process according to the present embodiment. The circuit diagram of Fig. 21 is similar to the circuit diagram of Fig. 10 or the like. However, in the embodiment described above, either the "normal write" current or the "slow write" current can be selected depending on a target distribution that is different for each of the memory cells, without changing the write speed during processing, as described in the present embodiment.

[0054] Fig. Figure 22 is a circuit diagram illustrating the writing process according to the present embodiment. For cell A or cell C, corresponding to distribution A, the "normal write" current Inor (Ibl = 1.66 µA) is set to achieve the normal write speed. Conversely, for cell B, corresponding to distribution B and having a lower cell voltage level than distribution A, the "slow write" current Inor (Ibl = 0.83 µA) is set to achieve the slow write speed.

[0055] As in Fig. As shown in Figure 22, for cell A, the write bit line current control circuit 100 performs control to allow the "normal write" current Inor (Ibl = 1.66 µA) to flow through transistors Tr3 and Tr4 and transistors Tr5 and Tr6 when the gate voltage exceeding the threshold voltage is applied as a normal write according to distribution A. Similarly, for cell C, the write bit line current control circuit 100 performs control to allow the "normal write" current Inor (Ibl = 1.66 µA) to flow through transistors Tr3 and Tr4 and transistors Tr5 and Tr6 when the gate voltage exceeding the threshold voltage is applied at the time of normal writing according to distribution A.

[0056] On the other hand, for cell B, the write bit line current control circuit 100 performs a control to allow the “slow write” current Ilow (Ibl = 0.83 µA) to flow through transistors Tr1 and Tr2 when the gate voltage exceeding the threshold voltage is applied as a slow write according to distribution B.

[0057] For cells A, B, and C, the same Vmg voltage is gradually increased and applied, as in Fig. 20 is shown. In this case, the Vmg voltage can be set higher at the beginning than in the one shown. Fig. 19 shown in the comparative example, and therefore the writing process can be completed in a short time.

[0058] In some embodiments, it should be noted that a "normal write" current can flow according to a target distribution A for cell A, a "medium write" current can flow according to a target distribution B for cell B, and a "slow write" current can flow according to a target distribution C for cell C. In this case, a circuit for the "normal write" current, a circuit for the "medium write" current, and a circuit for the "slow write" current can be arranged in parallel in the write bit line current control circuit. In this case, at least three transistors can be arranged in parallel in the circuit for the "normal write" current. At least two transistors can be arranged in parallel in the circuit for the "medium write" current. At least one transistor can be arranged in parallel in the circuit for the "slow write" current.Thus, the present disclosure is also applicable to an n-bit MLC cell (“n” is an optional integer) such as a TLC or a QLC, as experts can see.

[0059] Fig. 23 is a circuit diagram comprising a write bit line voltage control circuit according to another embodiment. The in Fig. The write bit line current control circuit 100 described in 10 or similar can also be achieved by a circuit described in Fig. The write bit line voltage control circuit 100b shown in section 23 can be replaced. A basic operating principle is similar to that in Fig. 10 or the similar embodiment described.

[0060] The bit line bl coupled to the Y-selector 50 is connected to the one for the current ("Inor" in Fig. 11) Transistor Tr2 is connected at the time of normal writing. A write voltage V1 is applied to a source electrode of transistor Tr2. When the gate voltage exceeding the threshold voltage is applied as write flag 1 at the time of normal writing, the "normal write" current Inor flows through transistor Tr2.

[0061] On the other hand, the bit line bl coupled to the Y-selector 50 is connected to the one for the current ("ilow" in Fig. 11) Transistor Tr1 is connected at the time of slow writing. A write voltage V2 is applied to a source electrode of transistor Tr1. In the write bit line current control circuit 100b, the write voltage V1 used for normal writing is controlled to be lower than the write voltage V2 used for slow writing. When the gate voltage exceeding the threshold voltage is applied as write flag 2 at the time of slow writing, the "slow write" current Ilow flows through transistor Tr2.

[0062] According to some embodiments, a non-volatile semiconductor memory device can be provided. In the non-volatile semiconductor memory device, which comprises: a plurality of gate lines; a plurality of bit lines, each of which crosses the plurality of gate lines; and a plurality of memory cells connected at respective intersection points between the gate lines and the bit lines, the plurality of memory cells are each connected via the various bit lines to a gate line selected from the plurality of gate lines, and the non-volatile semiconductor memory device further comprises a plurality of write bit line current or voltage control circuits, each of which controls bit line currents to perform the writing to the plurality of memory cells simultaneously.In another embodiment, the non-volatile semiconductor memory device can be configured to provide a plurality of cell voltage verification levels for checking cell states, each for a plurality of target cell voltage distributions, and such that the write bit line current or voltage control circuits each control write speeds by using the plurality of bit line currents selected based on a plurality of gate voltages and read results corresponding to the verification levels.The non-volatile semiconductor memory device can be configured such that a first cell voltage verification level, representing the end of the cell write, and a second cell voltage verification level, which is lower than the first cell voltage verification level, are each provided for target cell voltage distributions, and such that, if it is verified from a read result of a memory cell that the cell voltage exceeds the second cell voltage verification level, the write bit line current or voltage control circuit controls a write bit line current of the memory cell to a current that is lower than the normal current.

[0063] In another embodiment, the write bit line current control circuit 100 can comprise: a first transistor Tr4 and a second transistor Tr6, each having a gate that receives a reference potential and connected in parallel to each other to pass a first write bit line current; and a third transistor Tr2, having a gate that receives a reference potential and passing a second write bit line current that is smaller than the first write bit line current (see Fig. 11) The write bit line current control circuit 100 may further comprise: a fourth transistor Tr3 and a fifth transistor Tr5, each having a gate that receives a write flag signal and connected in series with the first transistor Tr4 and the second transistor Tr6 respectively; and a sixth transistor Tr1, having a gate that receives a write flag signal and connected directly to the third transistor Tr2 (see Fig. 11).

[0064] The write bit line voltage control circuit 100b can comprise: a first transistor Tr1, which has a gate that receives a first write flag signal, and a source that receives a write voltage and passes a first write bit line current; and a second transistor Tr2, which has a gate that receives a second write flag signal, and a source that receives a write voltage and passes a second write bit line current that is smaller than the first write bit line current, and a source potential V1 of the first transistor Tr1 can be controlled to be lower than a source potential V2 of the second transistor Tr2 (see Fig. 23).

[0065] In a further embodiment, the non-volatile semiconductor memory device may comprise: a first Y-selector that selects a gate line from a plurality of gate lines; a second Y-selector that selects a gate line from the plurality of gate lines; and a third Y-selector that selects a gate line from the plurality of gate lines, and may include a first write bit line current or voltage control circuit, a second write bit line current or voltage control circuit, and a third write bit line current or voltage control circuit, each corresponding to the first Y-selector, the second Y-selector, and the third Y-selector, respectively.

[0066] A pulse voltage can be applied multiple times to the respective gate electrodes of the plurality of memory cells via gate lines. The pulse voltage can be applied multiple times while gradually increasing, and verification periods can be provided between each application of the pulse voltage, during which verification is performed. The plurality of memory cells can include at least one multi-level cell (MLC), one triple-level cell (TLC), and one quad-level cell (QLC).

[0067] The invention of the inventors of the present application has been described in detail above, based on exemplary embodiments. However, the present invention is not limited to the above exemplary embodiments, and various modifications can be made within the scope of the present invention. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-190734

[0001] JP 2023-92938

[0007]

Claims

[1] A non-volatile semiconductor memory device comprising: a plurality of gate lines; a plurality of bit lines each crossing the plurality of gate lines; and a plurality of memory cells connected to respective intersections between the gate lines and the bit lines, wherein the plurality of memory cells are connected to a gate line selected from the plurality of gate lines via the different bit lines, respectively, and the non-volatile semiconductor memory device further comprises a plurality of write bit line current or voltage control circuits each controlling bit line currents to perform simultaneous writing to the plurality of memory cells. [2] The non-volatile semiconductor memory device according to claim 1, wherein a plurality of cell voltage verification levels are provided for checking cell states respectively for a plurality of target cell voltage distributions, and the write bit line current or voltage control circuits each control write speeds by using the plurality of bit line currents selected based on a plurality of gate voltages and read results corresponding to the verification levels. [3] The non-volatile semiconductor memory device according to claim 2, wherein a first cell voltage verification level representing the end of a line write and a second cell voltage verification level lower than the first cell voltage verification level are provided for the target cell voltage distributions, and when it is verified from a read result of a memory cell that the cell voltage exceeds the second cell voltage verification level, the write bit line current or voltage control circuit controls a write bit line current of the memory cell to a current lower than a normal current. [4] The non-volatile semiconductor memory device according to claim 2, wherein the write bit line current control circuit comprises: a first transistor and a second transistor, each having a gate receiving a reference potential and connected in parallel to each other to pass a first write bit line current; and a third transistor having a gate receiving a reference potential, and passes a second write bit line current that is smaller than the first write bit line current. [5] The non-volatile semiconductor memory device according to claim 4, wherein the write bit line current control circuit comprises: a fourth transistor and a fifth transistor, each having a gate that receives a write flag signal and connected in series with the first transistor and the second transistor, respectively; and a sixth transistor having a gate receiving a write flag signal and directly connected to the third transistor. [6] The non-volatile semiconductor memory device according to claim 2, wherein the write bit line voltage control circuit comprises: a first transistor having a gate receiving a first write flag signal and a source receiving a write voltage and passing a first write bit line current; and a second transistor having a gate receiving a second write flag signal and a source receiving a write voltage and passing a second write bit line current that is less than the first write bit line current, and a source potential of the first transistor is controlled to be lower than a source potential of the second transistor. [7] The non-volatile semiconductor memory device according to claim 1, wherein a pulse voltage is applied multiple times to the respective gate electrodes of the plurality of memory cells via the gate lines, the pulse voltage is applied multiple times while gradually increasing, and verification periods during which verification is carried out are provided between each of the multiple application times of the pulse voltage. [8] The non-volatile semiconductor memory device according to claim 1, wherein the plurality of memory cells comprises an n-bit (n is an optional integer) multi-level cell (MLC), that is, at least one of a triple-level cell (TLC) and a quad-level cell (QLC).

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