COMMUNICATION INTERFACE CONTROL WITH OUTPUT MONITORING

Abstract

In the described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides an instruction to the transceiver and the bus monitor specifying a commanded destination address, a read / write flag, and a memory address. The transceiver provides a clock signal to the first pin and the bus monitor and sends a message to the second pin and the bus monitor such that the message includes a transmitted destination address, the read / write flag, and the memory address. The bus monitor compares the commanded destination address with the transmitted destination address and provides a signal to the processor in response to the comparison.

Description

TECHNICAL FIELD

[0001] This application relates generally to controller-to-target communication interfaces and, more particularly, to the detection of an output error of a controller. BACKGROUND

[0002] Inter-Integrated Circuit (I 2 C, pronounced I-Squared-C and alternatively referred to as I2C or IIC) is a synchronous, asymmetric, multi-controller / multi-destination serial communication bus. In some examples, I 2 C is used to communicatively connect integrated circuits (ICs), such as lower-speed peripheral ICs, with processors or microcontrollers. In some examples, I 2 C short-distance communication between ICs interconnected on a printed circuit board (PCB). In some examples, I 2 C is used to connect ICs for industrial or automotive applications. SUMMARY

[0003] In the described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides an instruction to the transceiver and the bus monitor specifying a commanded destination address, a read / write flag, and a memory address. The transceiver provides a clock signal to the first pin and the bus monitor and sends a message to the second pin and the bus monitor such that the message includes a transmitted destination address, the read / write flag, and the memory address. The bus monitor compares the commanded destination address with the transmitted destination address and provides a signal to the processor in response to the comparison. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a functional block diagram of an example I2C system. Fig. Figure 2 is a functional block diagram and circuit diagram of a second example I2C system. Fig. 3A is a bitwise structure of an exemplary I2C communication between the control microcontroller unit and a target of Fig. 1 to implement a write command. Fig. Figure 3B is a bitwise structure of an exemplary I2C communication between the control microcontroller unit and a target of Fig. 1 to implement a read command. Fig. Figure 4 is a timing diagram showing the timing of a serial clock signal and a serial data signal to provide a START condition signal and a STOP condition signal. Fig. Figure 5 is a functional block diagram of a third example I2C system. Fig. 6 is a process 600 for operating the control MCU of Fig. 1. DETAILED DESCRIPTION

[0004] In some examples, an I2C system 100 includes at least one control MCU 102 with a transceiver 118 coupled to one or more targets 104a, 104b, ... 104N via a serial data bus (SDA bus) 108. The transceiver 118 receives instructions from a CPU 114, from which the transceiver 118 communicates a serial data stream to the serial data bus (SDA bus) 108. The serial data stream includes various information, including an address for identifying one of the targets so that the addressed target can respond in an appropriate manner. To reduce the possibility of inaccuracies in destination addressing by the MCU 102, the control MCU 102 also includes a bus monitor 120 that verifies the correct addressing of a destination by comparing the destination address identified by the CPU 114 instruction with the corresponding destination address identified by the CPU-instructed transceiver 118.Error mitigation is implemented when a destination address mismatch is detected.

[0005] Here, some structures or signals that are different but related have reference numerals that use a [number][letter] format, such as targets 104a, 104b, ... 104N and controllers 202a, 202b, ... 202M. In some examples, these structures or signals are generally referred to in the singular or as a group using the [number] and without the [letter], such as targets 104 and controllers 202. Additionally, the same reference numerals or other reference numerals are used in the drawings to indicate structurally and / or functionally related features.

[0006] Fig. 1 is a functional block diagram of an exemplary I2C system 100. The I2C system 100 includes a control microcontroller unit (control MCU) 102, which acts as a controller 202 (see Fig. 2) of the I2C system 100, a plurality of target ICs (targets) 104 used as targets of the I2C system 100, a serial clock bus (SCL bus) 106, and an SDA bus 108. There are a number N of targets 104, including a first target (target 1) 104a, a second target (target 2) 104b, and an Nth target (target N) 104N. Communication occurs between the control MCU 102 and one of the targets 104 via the SDA bus 108. As will be explained later, Fig. 3A, such communications are provided by groupings of serial data on the SDA bus 108, where different serial data groups may provide, for example, single control bits (such as read, write, start, stop, acknowledge) or multiple data bits (such as destination addresses).

[0007] The control MCU 102 includes an I2C unit 110, a clock 112 that provides a clock signal with a fundamental frequency, a central processing unit (CPU) 114, and an event handler 116. The I2C unit 110 includes an I2C transceiver 118 and a bus monitor 120. The I2C transceiver 118 includes a processor 122 and a first memory 124. The bus monitor 120 includes a comparator 126 and a second memory 128.

[0008] An output of the clock 112 is connected to a clock input of the I2C transceiver 118. A data port of the CPU 114 is connected via a CPU bus to a data port of the I2C transceiver 118 and a first data input of the bus monitor 120. An ignore condition output of the I2C transceiver 118 is connected to an ignore condition input of the bus monitor 120. An SCL port of the I2C transceiver 118 is connected to an SCL pin 130 of the control MCU 102 and to a clock input of the bus monitor 120. An SDA port of the I2C transceiver 118 is connected to an SDA pin 132 of the control MCU 102 and to a second data input of the bus monitor 120. An error interrupt output of the bus monitor 120, from which the bus monitor 120 provides an active or inactive error interrupt signal, is connected to an input of the event handler 116.An active error interrupt signal corresponds to an I2C addressing error detected by the bus monitor 120.

[0009] The SCL pin 130 is connected to the SCL bus 106. The SDA pin 132 is connected to the SDA bus 108. The targets 104 each include a clock input and a data input. The respective clock inputs of the targets 104 are connected to the SCL bus 106, and the respective data inputs of the targets 104 are connected to the SDA bus 108. An exemplary structure and functionality of the control MCU 102 for applying signals to and monitoring signals on the SDA bus 108 are described with reference to Fig. 2 described.

[0010] Fig. 2 is a functional block diagram and circuit diagram of a second example I2C system 200 having multiple controllers 202 and multiple targets 104, i.e., a topology having multiple controllers 202 and multiple targets 104. Fig. Figure 2 also shows an exemplary circuit arrangement for determining logical values ​​of bits in SDA signals. The individual controllers 202 and targets 104 are connected to the SCL bus 106 and the SDA bus 108, respectively. The SDA bus 108 includes a voltage source 204, which provides a source voltage, and a resistor 206. The I2C system 200 also includes a ground 208.

[0011] There are a number M of controllers 202. The controllers 202 include a first controller (controller 1) 202a, a second controller (controller 2) 202b, and up to an Mth controller (controller M) 202M. In some examples, each controller 202 may correspond to a controller MCU 102. The controllers 202 are each connected to the SCL bus 106 and the SDA bus 108.

[0012] The first controller 202a is shown and described as representative of the controllers 202. In some examples, the first controller 202a corresponds to the controller MCU 102. The first controller 202a includes a buffer 210, an n-channel metal-oxide-semiconductor field-effect transistor (an NMOS) 212, and a ground pin 214.

[0013] The SDA pin 132 of the first controller 202a is connected to an input of the buffer 210 and a drain of the NMOS 212. An output of the buffer 210 is connected to a data input of the I2C transceiver 118, and a gate of the NMOS 212 is connected to a data output of the transceiver 118. This data input and data output of the I2C transceiver 118 correspond to the SDA terminal of the Fig. 1 described I2C transceiver 118. The source of the NMOS 212 is connected to ground 208 via the ground pin 214.

[0014] The SDA bus 108 is connected as a serial interface to provide two distinct logic states. In this regard, the SDA bus 108 is connected to the voltage source 204 via resistor 206, so that the SDA bus 108 is pulled high (to the source voltage) by default, where high represents a first of the two distinct logic states (e.g., a logic zero). The I2C transceiver 118 can connect the SDA bus 108 to ground 208 by supplying a gate voltage to the NMOS 212 to turn on the NMOS 212. Accordingly, turning on the NMOS 212 pulls the SDA bus 108 to a low voltage (ground voltage), where low represents a second of the two distinct logic states (e.g., a logic one). The I2C transceiver 118 can monitor an SDA signal and thus the represented logic value on the SDA bus 108 via the SDA pin 132 and the buffer 210 by turning off the NMOS 212.This is referred to as enabling the SDA bus 108 by the first controller 202a.

[0015] Each of the controllers 202 can send an SDA signal representing a read or write command to the SDA bus 108. SDA signals are interpreted with respect to Fig. 3A, Fig. 3B and Fig. 4. The read or write command is to be executed by a target 104 corresponding to a destination address contained in the SDA signal stream. If multiple controllers 202 send an SDA signal simultaneously, the one whose read or write command is executed first is determined using an arbitration process described below. In some examples, controllers 202 may also be used as targets 104.

[0016] In some examples, CPU 114 knows the destination addresses of targets 104 connected to SCL and SDA buses 106 and 108. In some examples, a processor external to I2C system 200 that uses control MCU 102 to communicate with targets 104 (e.g., by sending instructions to control MCU 102 to be translated into messages to be sent by I2C transceiver 118 to a corresponding target 104) knows the destination addresses of targets 104 connected to SCL and SDA buses 106 and 108. Destination addresses are determined by system-level configuration.

[0017] With further reference to Fig. 1, the CPU 114 controls the I2C transceiver 118 to control specific targets 104 to execute read commands and write commands. Accordingly, each target 104 may monitor the SDA bus 108 to detect commands issued by an I2C transceiver 118 and, in response, execute such a command if addressed to the specific target 104. For read commands and for write commands, the CPU 114 provides an instruction including an indication of whether a read or write operation is to be performed, a target address specifying a corresponding one of the targets 104, a target memory address within the specified target 104, and data to be written to the target memory address within the specified target 104. The target addresses provided by the CPU 114 are written to the first memory 124 and the second memory 128.Accordingly, the same target address from the instruction provided by the CPU 114 is written to both the first memory 124 and the second memory 128.

[0018] Because the CPU 114 is connected to both the I2C transceiver 118 and the bus monitor 120 via the CPU bus, the destination address provided by the CPU 114 can be written to the first memory 124 and the second memory 128 in parallel and without software mediation. Accordingly, the first memory 124 and the second memory 128 can both be written as hardware processes without additional software overhead. This enables faster processing of I2C messages and easier development of control software. After the I2C transceiver 118 receives the instruction from the CPU 114, it generates the message (the SDA signal) and sends it to the SDA bus 108. The destination address provided by the message sent by the I2C transceiver 118 to the SDA bus 108 is then written to the second memory 128.Accordingly, both the destination address provided by the CPU 114 and the destination address provided by the I2C transceiver 118 are written to the second memory 128.

[0019] Clock 112 provides the clock signal at the fundamental frequency to I2C transceiver 118. I2C transceiver 118 generates an SCL signal in response to the clock signal at a frequency corresponding to I2C data rates. In some examples, I2C messages (SDA signals) have data rates between 100 kilohertz (kHz) and 400 kHz. I2C transceiver 118 generates an SDA signal with data switches clocked in response to clock edges of the SCL signal. The data switches are high-to-low or low-to-high transitions of the SDA signal. Data switch timing and sampling of the SDA signal using the SCL signal are described with respect to Fig. 4 described in more detail.

[0020] The I2C transceiver 118 provides the SCL signal to the SCL bus 106 via the SCL pin 130 and provides the SDA signal to the SDA bus 108 via the SDA pin 132, as described in more detail below. The I2C transceiver 118 also provides the SCL signal, the SDA signal, and an ignore condition signal to the bus monitor 120. In response to an ignore condition signal, the bus monitor 120 stops comparing the two destination addresses stored in the second memory 128. This corresponds to the bus monitor 120 not determining whether to generate an error interrupt signal. Recall that the destination address is stored in the instruction provided by the CPU 114 in the second memory 128. In addition, the destination address in the SDA signal supplied by the I2C transceiver 118 to the SDA bus 108 is stored in the second memory 128.

[0021] In some examples, additional actions taken by bus monitor 120 or I2C transceiver 118 following an ignore condition signal depend on the type of ignore condition signal. An arbitration lost signal or an illegal stop signal may be asserted by I2C transceiver 118 as an ignore condition signal. The arbitration lost signal and the illegal stop signal are described (in more detail) below. In some examples, ignore conditions occur during normal operation of I2C system 200.

[0022] Bus monitor 120 samples the SDA signal received over the feedback connection from I2C transceiver 118. Bus monitor 120 samples the SDA signal using the SCL signal (also received over the feedback connection) to determine the destination address specified by the SDA signal. The destination address specified by the SDA signal is stored in second memory 128. Comparator 126 compares the destination address provided by CPU 114 with the destination address specified by the SDA signal. If the destination addresses are equal, bus monitor 120 provides a disabled error interrupt signal to event handler 116. The disabled error interrupt signal indicates that the destination address contained in the SDA signal matches the destination address provided by CPU 114.

[0023] If the destination addresses are different, bus monitor 120 provides an asserted error interrupt signal to event handler 116. The asserted error interrupt signal indicates a destination addressing error. In some examples, bus monitor 120 provides the error interrupt signal to event handler 116 immediately after detecting the destination addressing error, without waiting to determine whether an ignore condition signal is received.

[0024] In some examples, a target addressing error may be caused by a fault in the controlling MCU 102 (with a controller 202) or by a fault on the SDA bus 108. In some examples, a target addressing error is caused by a random hardware failure, and therefore a reliability issue, in the I2C transceiver 118 or the SDA bus 108 (or 204). A random hardware failure in the I2C transceiver 118 may occur in the processor 122 or the first memory 124. The event handler 116 may be implemented using hardware, software (such as software instructions stored in memory and executed by the CPU 114), or a combination of both.

[0025] In some examples, in response to an asserted fault interrupt signal (destination addressing error), CPU 114 initiates a STOP condition on SDA bus 108 using I2C transceiver 118. In some examples, initiating a STOP condition corresponds to transmitting a STOP condition signal 408 ( Fig. 4). In some examples, in response to an asserted fault interrupt signal, the event handler 116 may initiate a power-on reset (POR) of the control MCU 102. In some examples, in response to an asserted fault interrupt signal, the event handler 116 may send a message to an IC controlling the I2C system 100 indicating improper operation of the control MCU 102 and causing the control MCU 102 to enter a safe state in which the control MCU 102 does not send signals to the SCL and SDA buses 106 and 108.

[0026] As described above, I2C transceiver 118 also provides the SCL signal to SCL bus 106 via SCL pin 130 and provides the SDA signal to SDA bus 108 via SDA pin 132. All of the targets 104 connected to SCL and SDA buses 106 and 108 receive the SCL and SDA signals. The target 104 corresponding to the destination address contained in the SDA signal executes the read and / or write instruction contained in the SDA signal.

[0027] In response to an SDA signal corresponding to a write command, a target 104 specified by the SDA signal writes data contained in an SDA signal to a memory address contained in the SDA signal. In response to an SDA signal corresponding to a read command, a target 104 specified by the SDA signal writes a memory address specified by the SDA signal to a memory of the target 104, reads data from the memory specified by the address, and provides the read data to the I2C transceiver 118. In some examples, the transceiver 118 provides read data and acknowledgment signals received from the target 104 to the CPU 114. The structure and process of the I2C read and write signals are described with respect to Fig. 3A and Fig. 3B is described in more detail.

[0028] The following is a description of ignore condition signals. A STOP condition signal 408, which Fig. 4, terminates an I2C communication (a message) between a controller 202 and a target 104. An illegal stop is a STOP condition signal 408 that occurs at a position in an I2C communication that does not correspond to a normal I2C read or write message. The STOP condition signal 408 and the illegal stop signal are described with respect to Fig. 4 described in more detail.

[0029] Two controllers 202 that simultaneously attempt to transmit an SDA signal are said to be in arbitration. An asserted arbitration lost signal may be generated when two controllers 202 (see Fig. 2) Attempt to simultaneously transmit an SDA signal. As described above, the I2C transceiver 118 sends a logic one as the ground voltage and accordingly connects the SDA bus 108 to ground 208 to send the logic one. The I2C transceiver 118 sends a logic zero as the source voltage and accordingly releases the SDA bus 108 from the connection to ground 208 so that the SDA bus 108 can be pulled high by the voltage source 204 to send the logic zero.

[0030] The controller 202 that first attempts to send a logic zero (enabling the SDA bus 108 to go high), while the other controller 202 attempts to send a logic one (connecting the SDA bus 108 to ground 208 to pull the SDA bus 108 low), will not be able to send the logic zero due to the connection to ground 208. The unsuccessful controller 202 is referred to as the loser of the arbitration. The unsuccessful controller 202 knows that it has failed because it receives the SDA signal via buffer 210 on the SDA bus 108. A lost arbitration corresponds to the fact that the SDA bus 108 carries an SDA signal with a voltage lower than logic zero (high), specifically, a voltage corresponding to the ground connection established by the controller 202 that won the arbitration.

[0031] The I2C transceiver 118 that unsuccessfully attempted to transmit the logic one provides the asserted Arbitration Lost signal to its corresponding bus monitor 120 and stops transmitting the SDA signal. The controller 202 that won the arbitration is allowed to transmit its SDA signal without interference, and the controller 202 that lost the arbitration waits until the arbitration winner's SDA signal has finished. In some examples, the termination of the SDA signal corresponds to a STOP condition signal 408, as described with respect to Fig. 4 described.

[0032] Following the STOP condition signal 408, the controller 202 that lost arbitration attempts to retransmit its SDA signal. When the bus monitor 120 receives the asserted Arbitration Lost signal, the bus monitor 120 terminates operation with respect to the interrupted SDA signal. When the interrupted SDA signal is retransmitted, the retransmitted message is treated by the bus monitor 120 as if the initial transmission attempt had not occurred.

[0033] Fig. 3A is a bit-by-bit structure of an exemplary I2C communication 300 between the control MCU 102 and a target 104 of Fig. 1 to implement a write command.

[0034] The I2C transceiver 118 of the control MCU 102 sends a START condition (S) signal 302 on the SDA bus 108, a destination address 304 specifying a p-th destination (e.g., destination 104a in one example) to perform the write command, and a read / write bit (an R / W bit) 306 set to zero. The START condition signal 302 is referenced to Fig. 4. The seven bits of destination address 304 are numbered from A6, which corresponds to a most significant bit (MSB), to A0, which corresponds to a least significant bit (LSB). The seven-bit destination address allows the addressing of 2 7 =128 targets 104. The overbar over the W and not over the R in R / W indicates that the write meaning is asserted when the R / W bit 306 is equal to zero and the read meaning is asserted when the R / W bit 306 is equal to one.

[0035] After receiving the START condition signal 302, the destination address 304, and the R / W bit 306, the destination 104a corresponding to the destination address 304 sends a first acknowledgement bit (ACK or A bit) 308 to the SDA bus 108 to confirm receipt. The controlling MCU 102 then sends a register address 310 to the SDA bus 108, which specifies the memory address in the destination 104a of a register to be written to. In some examples, the register address 310 is a one-byte (eight-bit) address numbered from B7 for an MSB to B0 for an LSB. The destination 104a writes the register address 310 to a memory of the destination 104a and references the written register address 310 to perform the requested memory write operation.

[0036] After the target 104a sends a second ACK bit 312, which confirms receipt of the register address 310 and the ready status to the SDA bus 108, the control MCU 102 sends register data 314 to the target 104a to be written to the register address 310. In some examples, the register data 314 is one-byte (eight-bit) data, numbered from D7 for an MSB to D0 for an LSB. After the target 104a receives and writes the register data 314, the target 104a sends a third ACK bit 316 to the control MCU 102.

[0037] After the third ACK bit 316, the controller MCU 102 may either send additional bytes of register data 314 or (as shown) send a STOP condition signal 318 to the target 104a to terminate the I2C communication 300. The STOP condition signal 318 also indicates to other controllers 202 that the SCL bus 106 and the SDA bus 108 are available for message transmission.

[0038] Fig. 3B is a bit-by-bit structure of an exemplary I2C communication 320 between the control MCU 102 and a target 104 of Fig. 1 for implementing a read command. An initial portion of the I2C communication 320 corresponds to an initial portion of the I2C communication via the second ACK bit 312. The I2C communication 320 for implementing a read command begins by providing a destination address 304 of a specified destination 104a, setting an R / W bit 306 equal to zero so that a register address 310 is written, and providing a register address 310 at which the read operation begins. Accordingly, the destination memory address at which the read access begins is written first, and the data is read from the memory at that address (and, in some examples, from the memory at successive addresses).

[0039] Upon receiving the second ACK bit 312 from the target 104a, indicating that the register address 310 has been written, the control MCU 102 sends a Repeated START Condition (SR) signal 322, which enables the sending of an R / W bit 306 corresponding to a read action. In some examples, the Repeated START Condition signal 322 has similar or identical SCL and SDA signal timing (see Fig. 4) such as a START condition signal 302 that initiates an I2C communication 300 or 320 (see Fig. 4). After sending the Repeat START Condition signal 322, the control MCU 102 again sends the destination address 324 and then an R / W bit 306 equal to one, indicating the read action.

[0040] In response to the R / W bit 306, the target 104a sends a third ACK bit 328 and then sends a byte of read register data 330 retrieved from a memory of the target 104 starting at register address 310. After the controlling MCU 102 receives the read register data 330, it may send an ACK bit to the target 104a, causing the target 104a to read another byte of data from a memory address sequentially following the end of the read register data 330. Alternatively, as in the illustrated example, the controlling MCU 102 may send an inverted acknowledge bit (NACK or NA) 332 to the target 104a. The NACK bit 332 commands the target 104a to stop communication and release the SDA bus 108. The MCU controller 102 follows the NACK bit with a STOP condition signal 334. In some examples, an ACK bit is active low and a NACK bit is active high.

[0041] Fig. 4 is a timing diagram 400 illustrating the timing of an SCL signal 402 and an SDA signal 404 to provide a START condition signal 406 and a STOP condition signal 408. Data transfer 410 from a controller 202 to a target 104 and / or from the target 104 to the controller 202 occurs between the START condition signal 406 and the STOP condition signal 408.

[0042] A START condition signal 406 corresponds to a falling edge of the SDA signal 404 while the SCL signal 402 is high. A STOP condition signal 408 corresponds to a rising edge of the SDA signal 404 while the SCL signal 402 is high. An illegal STOP that triggers an illegal stop signal (as described above) corresponds to a STOP condition signal 408 generated at a portion of an SDA signal 404 that does not correspond to one of the Fig. 3A and Fig. 3B described expected positions of the STOP condition signal 408.

[0043] When the I2C transceiver 118 detects an illegal stop condition, it sends an illegal stop signal to the bus monitor 120, and a state machine of the I2C transceiver 118 is reset. A state machine of the I2C transceiver 118 tracks which bit (or other signal) in an I2C communication (such as an I2C communication 300 for implementing a write command or an I2C communication 320 for implementing a read command) the I2C transceiver 118 is currently transmitting. Accordingly, the state machine of the I2C transceiver 118 tracks which bit (or other signal) in which field (such as register address 310 or destination address 324) is currently being generated by the I2C transceiver 118 and transmitted to the SDA bus 108.In response to the illegal stop signal, the bus monitor 120 aborts the comparison between the destination address provided by the CPU 114 and the destination address transmitted by the I2C transceiver 118 and avoids providing an indication of a false alarm to the event handler 116.

[0044] Accordingly, the transmission of I2C data bits (in Fig. 4 not shown) the SDA signal 404 does not change during a high period (half a clock cycle) of the SCL signal 402. In other words, the SDA signal 404 toggles to provide data while the SCL signal 402 is low and remains constant while the SCL signal 402 is high. This corresponds to the SDA signal 404 having a constant low value (a logical one) or high value (a logical zero) while the SCL signal 402 provides a rising edge and then a falling edge. Accordingly, the frequency and phase of the SCL signal 402 can be described as being synchronized with the data of the SDA signal 404.

[0045] Fig. 5 is a functional block diagram of a third exemplary I2C system 500. In the I2C system 500, the bus monitor 120 includes a finite state machine (EA) 502, a first multiplexer (MUX 1) 504, a second multiplexer (MUX 2) 506, and a logic inverter 508. The memory 128 includes an input destination address memory 510 and an output destination address memory 512. The input destination address memory 510 refers to the input of the I2C transceiver 118 received by the CPU 114, and the output destination address memory 512 refers to the output of the I2C transceiver 118 as an SDA signal sent to a destination 104. The input and output destination address memories 510 and 512 correspond to the second memory 128 of Fig. 1.

[0046] The data port of CPU 114 is connected via the CPU bus to the data port of I2C transceiver 118, a first input of MUX 1 504, and an input of logic inverter 508. An output of logic inverter 508 is connected to a second input of MUX 1 504. A diagnostic test output of CPU 114 provides a diagnostic test signal to a control input of MUX 1 504. An output of MUX 1 504 is connected to an input of input destination address latch 510. An enable output of CPU 114 provides an enable signal to a control input of MUX 2 506.

[0047] The SCL pin of I2C transceiver 118 is connected to SCL pin 130 and a clock input of EA 502. The SDA pin of I2C transceiver 118 is connected to SDA pin 132 and a data input of EA 502. An output of EA 502 is connected to an input of output destination address latch 512. An output of input destination address latch 510 is connected to a first data input of comparator 126, and an output of output destination address latch 512 is connected to a second data input of comparator 126.

[0048] A first ignore output of the I2C transceiver 118 is connected to a first ignore input of the comparator 126 and provides an arbitration lost signal. A second ignore output of the I2C transceiver 118 is connected to a second ignore input of the comparator 126 and provides an illegal stop signal.

[0049] The output of comparator 126 is connected to a first input of MUX 2 506. A second input of MUX 2 506 receives a signal with a logic zero value corresponding to the deactivated error interrupt signal. An output of MUX 2 506 provides the error interrupt signal to event handler 116.

[0050] The EA 502 extracts the destination address from the SDA signal (the message sent by the transceiver 118) in response to the SCL signal. Extracting data from an SDA signal (parsing the SDA signal in response to the SCL signal) is described above with respect to Fig. 4. In some examples, the EA 502 is programmed and / or includes hardware to extract a configured number of bits following a START condition signal 406 in the SDA signal. Accordingly, in examples that follow the example described above with respect to Fig. 3A and Fig. 3B, the destination address is a set of bits that sequentially follow a START condition signal 406. The configured number of bits is the number of bits in destination addresses corresponding to the destinations 104 connected to the SCL and SDA buses 106 and 108. In some examples, the configured number of bits is seven or ten (or another number).

[0051] In some examples, the EA 502 detects an ignored condition, such as an arbitration lost condition or an invalid stop condition. In some examples, the EA 502 does this in response to an ignored condition signal provided by the I2C transceiver 118. In some examples, the EA 502 independently detects an ignored condition by parsing the SDA signal in response to the SCL signal, as described with respect to Fig. 4 described.

[0052] Comparator 126 compares the destination address stored in input destination address memory 512 with the destination address stored in output destination address memory 512 and provides an output in response to the comparison. In some examples, comparator 126 provides a logic one output when the two destination addresses are different, corresponding to an addressing error, and a logic zero output when the two destination addresses are the same, corresponding to normal addressing operation. When the enable signal is asserted, MUX 2 506 provides the output of comparator 126 to event handler 116. When the enable signal is asserted, MUX 2 506 provides a logic zero, indicating normal operation or a do-not-care condition, to event handler 116.

[0053] When the diagnostic test signal is deactivated, MUX 1 504 provides a signal received at its non-inverted input to the input destination address memory 510. When the diagnostic test signal is activated, MUX 1 504 provides a signal received at its inverted input to the input destination address memory 510. Accordingly, the CPU 114 can activate the diagnostic test signal to test the valid function of the comparator 126 by intentionally injecting an error using the inverted signal. When the diagnostic test signal is activated, a valid function of the comparator 126 corresponds to an error interrupt signal indicating an addressing error. When the diagnostic test signal is deactivated, a valid function of the comparator 126 is assumed (or previously verified by diagnostics), and the output of the comparator 126 depends on a valid function of the I2C transceiver 118.

[0054] Fig. 6 is a process 600 for operating the control MCU 102 of Fig. 1. In step 602, send an instruction from a processor of a control IC to a transceiver of the control IC. The instruction specifies an address of a specified target IC, a read or write command, and a memory address of the specified target IC. In some examples, the control IC is the control MCU 102, the processor is the CPU 114, the instruction is the data provided by the CPU 114 to the I2C transceiver 118, and the command is a read command or a write command.

[0055] In step 604, attempt to send a message including the destination address, the command, and the memory address from the control IC to a bus using the transceiver. In some examples, the bus is the SDA bus 108. In step 606, send the message from the transceiver to a bus monitor of the control IC. In some examples, steps 604 and 606 correspond to the signal paths for an SDA signal transmitted by the I2C transceiver 118, specifically via the SDA pin 132, to the SDA bus 108 and to the bus monitor 120.

[0056] In step 608, determine whether the destination address contained in the instruction and the destination address contained in the message are equal using the bus monitor. If the destination addresses are equal, in step 610, receive a response message from the destination IC specified by the destination address in the message using the transceiver. If the destination addresses are not equal, in step 612, send an error interrupt signal to an event handler.

[0057] In some examples, systems and methods described herein, including bus monitor 120, enable compliance of an I2C controller 202 with requirements, such as safety requirements, of a safety or other standard such as International Electrotechnical Commission (IEC) 61784. For example, IEC 61784 requires addressing authentication. In some examples, compliance with this requirement is enabled by bus monitor 120 detecting addressing errors and providing the error interrupt signal.

[0058] Modifications of the described examples and other examples are possible within the scope of the claims.

[0059] In some examples, the event handler 116 is part of the CPU 114.

[0060] In some examples, circuits described herein, such as a target 104, the processor 122, the comparator 126, the CPU 114, or the MCU 102, may be implemented using a processor such as a CPU, a digital signal processor (DSP), or an MCU.

[0061] In some examples, disclosed processes and structures are used to enable data integrity verification for a communication protocol other than I2C, such as Serial Peripheral Interface (SPI) or Universal Asynchronous Receiver / Transmitter (UART).

[0062] In some examples, a destination address within an I2C communication (or other) includes a different number of bits than described above, such as ten bits, which is 2 10 =1024 addressable targets.

[0063] In some examples, CPU 114 provides the read / write command as a read / write flag. In some examples, CPU 114 provides the instruction in a form that specifies the destination address, the read / write flag, and the memory address. In some examples, I2C transceiver 118 (such as processor 122 of I2C transceiver 118) interprets the instruction to generate a corresponding I2C communication. Accordingly, in some examples, the formats, such as bitwise formats, of the instruction and the I2C communication differ.

[0064] In some disclosed processes and structures, signal fields other than the destination address are used to compare to confirm that portions of a message transmitted by a transceiver of a controller to a destination match corresponding portions of an instruction from a processor of the controller directing the transceiver to generate and transmit the message.

[0065] In some examples, the bus monitor 120 compares fields in messages transmitted by the I2C transceiver 118 to the SDA bus 108 with a corresponding field in an instruction by the CPU 114 to the I2C transceiver 118 in addition to or other than the destination address field.

[0066] In some examples, a processor external to the controller 202 provides the instruction that the I2C transceiver 118 uses to generate the message (I2C communication).

[0067] In some examples, processors described herein are implemented using a CPU, a digital signal processor (DSP), or an MCU.

[0068] The term "couple" is used throughout the specification. The term can cover connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if a device A provides a signal to control a device B to perform an action, in a first example, device A is coupled to device B, or in a second example, device A is coupled to device B via an intervening component C, if the intervening component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal provided by device A.

[0069] In this specification, the term "and / or" (when used in a form such as A, B, and / or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A with B and with C. Additionally, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to implementations that include any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0070] A device "configured" to perform a task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform the function, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuring may be accomplished through firmware and / or software programming of the device, through an assembly and / or layout of hardware components and interconnections of the device, or a combination thereof.

[0071] As used herein, the terms "terminal," "node," "interconnect," "pin," "ball," and "lead" are used interchangeably. Unless otherwise indicated, the use of these terms generally means a connection between, or termination of, a device element, circuit element, integrated circuit, device, or other electronics or semiconductor component.

[0072] A circuit or device that is described herein as including certain components may instead be configured to be coupled to those components to form the described circuit arrangement or device. For example, a structure that is described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g.,a semiconductor die and / or an integrated circuit (IC) package) and may be configured to be coupled, either during manufacture or after manufacture, for example by an end user and / or a third party, to at least some of the passive elements and / or the sources to form the described structure.

[0073] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a metal-oxide-silicon FET ("MOSFET") (such as an n-channel MOSFET, nMOSFET, or a p-channel MOSFET, pMOSFET), a bipolar transistor (BJT - e.g., NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or a field-effect transistor (JFET) may be used instead of or in conjunction with the devices described herein. The transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device structure transistors.Furthermore, the devices may be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0074] Circuits described herein are reconfigurable to include the replaced components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise noted, components shown as resistors generally represent one or more elements connected in series and / or parallel to provide an amount of impedance represented by the shown resistance. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes.Capacitors connected in series between the same two nodes as the single resistor or capacitor.

[0075] While certain elements of the described examples may be included in an integrated circuit and other elements may be external to the integrated circuit, in other embodiments, additional or fewer features may be integrated into the integrated circuit. Furthermore, some or all of the features depicted as external to the integrated circuit may be included in the integrated circuit, and / or some features depicted as internal to the integrated circuit may be integrated external to the integrated circuit. The term "integrated circuit," as used herein, refers to one or more circuits that are: (i) integrated in / over a semiconductor substrate; (ii) integrated in a single semiconductor package; (iii) integrated into the same module; and / or (iv) integrated in / on the same printed circuit board. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited non-patent literature

[0000] International Electrotechnical Commission (IEC) 61784. IEC 61784

[0057]

Claims

[1] Integrated circuit (IC) comprising: a first pin; a second pin; a bus monitor having a first input, a second input, a third input and an output; and a transceiver having an input, a first output, and a second output, wherein the input of the transceiver and the first input of the bus monitor are each configured to receive an instruction specifying a commanded destination address, a read / write flag, and a memory address, the first output of the transceiver being coupled to the first pin and to the second input of the bus monitor, the second output of the transceiver being coupled to the second pin and the third input of the bus monitor, and the transceiver being configured to generate a message in response to the instruction, the message including a message destination address, the read / write flag, and the memory address; wherein the bus monitor is configured to compare a signal received at its first input with a signal received at its second input, the comparison being made in response to a signal received at its third input, and to provide a signal in response to the comparison. [2] The IC of claim 1, wherein the IC is an inter-integrated circuit controller. [3] IC according to claim 1, wherein the bus monitor includes a first memory and a second memory; and wherein the bus monitor is configured to write the commanded destination address into the first memory and is configured to write the message destination address into the second memory. [4] The IC of claim 1, wherein the bus monitor is configured to compare the commanded destination address with the message destination address. [5] IC according to claim 1, further including a clock circuit having an output configured to provide a first clock signal having a first clock frequency; wherein the transmitter has a clock input coupled to the clock output of the clock circuit and for generating a second clock signal in response to the first clock signal, the second clock signal having a second clock frequency; and wherein the transmitter is configured to generate the message in response to the second clock signal and to provide the second clock signal at the second output of the transmitter. [6] IC according to claim 1, Wherein the bus monitor includes a finite state machine configured to determine the message destination address in response to the signal received at the first input of the bus monitor and the signal received at the third input of the bus monitor; wherein the bus monitor is configured to determine the commanded destination address in response to the signal received at the second input of the bus monitor; and where the comparison action compares the message destination address with the specified destination address. [7] The IC of claim 1, wherein the transceiver includes a control output, the IC further comprising: a ground pin; and a transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor is coupled to the first pin, the second terminal of the transistor is coupled to the ground pin, and the control terminal of the transistor is coupled to the control output of the transceiver. [8] IC according to claim 1, wherein the bus monitor includes a multiplexer and a logic inverter, the multiplexer having a first and a second input, a control input and an output, and the logic inverter including an input and an output; and wherein the first input of the multiplexer is configured to receive the instruction, the input of the logic inverter is configured to receive the instruction, the second input of the multiplexer is coupled to the output of the logic inverter, the control input of the multiplexer is configured to receive a diagnostic test control signal, and the output of the multiplexer is coupled to the second input of the bus monitor. [9] The IC of claim 1, wherein the bus monitor includes a multiplexer, the multiplexer having first and second inputs, a control input, and an output, and the first input of the multiplexer is coupled to the output of the bus monitor. [10] Integrated circuit (IC) comprising: a first pin; a second pin; a processor having an input and an output, the processor configured to provide, via the output, an instruction specifying a commanded target address, a read / write flag, and a memory address; a bus monitor having a first input, a second input, a third input, and an output, the output of the bus monitor being coupled to the input of the processor; and a transceiver having an input, a first output, and a second output, wherein the output of the processor is coupled to the input of the transceiver and the first input of the bus monitor, the first output of the transceiver is coupled to the first pin and to the second input of the bus monitor, the second output of the transceiver is coupled to the second pin and the third input of the bus monitor, and the transceiver is configured to generate a message in response to the instruction, such that the message includes a message destination address, the read / write flag, and the memory address; wherein the bus monitor is configured to compare a signal received at its first input with a signal received at its second input, the comparison being made in response to a signal received at its third input, and to provide a signal to the processor in response to the comparison. [11] The IC of claim 10, wherein the IC is an inter-integrated circuit controller. [12] IC according to claim 10, wherein the bus monitor includes a first memory and a second memory; and wherein the bus monitor is configured to write the commanded destination address into the first memory and is configured to write the message destination address into the second memory. [13] The IC of claim 10, wherein the bus monitor is configured to compare the commanded destination address with the message destination address. [14] IC according to claim 10, wherein the clock circuit is configured to provide a clock signal having a clock frequency; wherein the transmitter has a clock input and the output of the clock circuit is coupled to the clock input of the transmitter; and wherein the transmitter is adapted to generate the message in response to the clock signal. [15] IC according to claim 10, wherein the bus monitor includes a finite state machine configured to determine the message destination address in response to the signal received at the first input of the bus monitor and the signal received at the third input of the bus monitor; wherein the bus monitor is configured to determine the commanded destination address in response to the signal received at the second input of the bus monitor; and where the comparison action compares the message destination address with the specified destination address. [16] The IC of claim 10, wherein the transceiver includes a control output, the IC further comprising: a ground pin; and a transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor is coupled to the second pin, the second terminal of the transistor is coupled to the ground pin, and the control terminal of the transistor is coupled to the control output of the transceiver. [17] IC according to claim 10, wherein the processor has a control output; wherein the bus monitor includes a multiplexer and a logic inverter, the multiplexer having a first and a second input, a control input and an output, and the logic inverter including an input and an output; and wherein the first input of the multiplexer and the input of the logic inverter are each coupled to the output of the processor, the second input of the multiplexer is coupled to the output of the logic inverter, the control input of the multiplexer is coupled to the control output of the processor, and the output of the multiplexer is coupled to the second input of the bus monitor. [18] IC according to claim 10, wherein the processor includes a control output; and wherein the bus monitor includes a multiplexer, the multiplexer having a first and a second input, a control input and an output, the first input of the multiplexer being coupled to the output of the bus monitor, the control output of the multiplexer being coupled to the control output of the processor, and the output of the multiplexer being coupled to the input of the processor. [19] A method of operating an integrated circuit (IC), the method comprising: Sending an instruction by a processor to a transceiver, the instruction specifying a commanded address of a specified target IC, a read or write command, and a memory address of the specified target IC; Transmitting, from the IC by the transceiver, a message including a message address corresponding to the instructed address, the command, and the memory address; Determining, using a bus monitor, whether the commanded address and the message address are equal; and Determine whether an error interrupt signal should be delivered by the bus monitor to an event handler based on whether the instructed address and the message address are equal. [20] The method of claim 19, further comprising: Generating a clock signal having a clock frequency, wherein transmitting includes transmitting, from the IC by the transceiver, the clock signal; and before determining, parsing the message using a finite state machine of the bus monitor, in response to the clock signal, to recover the message address from the message.

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