Semiconductor packages and associated methods for producing wettable edges

Abstract

Implementations of a substrate can include a first set of connecting rods; a second set of connecting rods; and a plurality of conduits coupled between the first set of connecting rods and the second set of connecting rods. The first set of connecting rods can intersect with the second set of connecting rods. Each intersection of the first set of connecting rods and the second set of connecting rods can be recessed by the plurality of conduits.

Description

BACKGROUND 1. TECHNICAL AREA

[0001] The aspects addressed in this document relate generally to semiconductor packages, such as packages for a semiconductor die. 2. BACKGROUND

[0002] Semiconductor packages have been developed to provide electrical connections between a semiconductor die and a mainboard or printed circuit board to which the semiconductor package is attached. Various semiconductor packages provide protection from moisture or mechanical support for a semiconductor die. Other semiconductor packages serve to protect the semiconductor die from shocks or vibrations. SUMMARY

[0003] Implementations of a substrate may include a set of intersecting connecting rods forming a grid pattern, where each intersection point in the set of intersecting connecting rods may be down-coupled by a plurality of conduits coupled within the grid pattern of the set of intersecting connecting rods.

[0004] Implementations of a substrate can include one, all, or any of the following: The first group of the set of intersecting connecting rods can be oriented essentially perpendicular to a second group of the set of intersecting connecting rods.

[0005] The thickness of the set of intersecting connecting rods and the number of conductors can be less than 0.2 mm.

[0006] The downward reduction can be 0.08 mm or greater.

[0007] Implementations of a substrate can include a first set of connecting rods; a second set of connecting rods; and a plurality of conduits coupled between the first set of connecting rods and the second set of connecting rods. The first set of connecting rods can intersect with the second set of connecting rods. Each intersection of the first set of connecting rods and the second set of connecting rods can be recessed by the plurality of conduits.

[0008] Implementations of a substrate can include one, all, or any of the following: The first set of connecting rods and the second set of connecting rods intersect essentially perpendicularly.

[0009] The thickness of the first set of connecting bars and the second set of connecting bars can be less than 0.2 mm.

[0010] The thickness of the multiple conductors can be less than 0.2 mm.

[0011] The downward reduction can be 0.08 mm or greater.

[0012] Implementations of a method for forming a semiconductor package may include providing a substrate that includes a first set of connecting rods; a second set of connecting rods; and a plurality of leads coupled between the first and second sets of connecting rods. The first and second sets of connecting rods may be countersunk at a plurality of intersection points. The method may include coupling a semiconductor die to the plurality of leads; depositing an electrically insulating material over the substrate; forming a channel in the electrically insulating material; and forming a flank in each of the plurality of leads.The process may include electroplating the flank of each of the plurality of leads and singulating a semiconductor package by cutting the first set of connecting rods and the second set of connecting rods.

[0013] Implementations of a method for forming a semiconductor package may include one, all, or any of the following: The electroplating of the flank of each of the multitude of conduits may further include electroplating using the first set of connecting rods and the second set of connecting rods.

[0014] Forming the flank in each of the multitude of lines can further include completely cutting through a thickness of each of the multitude of lines.

[0015] The formation of the channel in the electrically insulating material may also include partial cutting into the material of the electrically insulating material.

[0016] The formation of the channel in the electrically insulating material can further include the non-cutting of reducing the multitude of intersection points.

[0017] The singulation of the semiconductor package may also include cutting the channel in the electrically insulating material.

[0018] The substrate can be a leadframe.

[0019] The leadframe can be a plate.

[0020] The semiconductor package can be a wireless semiconductor package.

[0021] After electroplating, the flank of each of the multitude of conductors can be a solderable flank.

[0022] The electroplating of the flank of each of the multitude of conductors may further include the electroplating of the entire flank.

[0023] The foregoing and other aspects, features and advantages will be obvious to professionals from the DESCRIPTION and DRAWINGS as well as from the CLAIMS. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following describes implementations in conjunction with the accompanying drawings, where identical reference symbols denote similar elements and where: Fig. 1 is a top view of an implementation of a substrate; Fig. 2 a perspective view of the substrate implementation of Fig. 1 is; Fig. 3 is a partial see-through view of a substrate implementation after the application of an electrically insulating material to it and the cutting of channels in it; Fig. 4 a perspective view of the substrate implementation of Fig. 3 after an electroplating process; Fig. 5 is a perspective view of a large number of semiconductor packages after singulation; Fig. 6 is a cross-sectional view of a semiconductor package implementation coupled to a mainboard using solder fillets; Fig. 7 is a perspective view of an implementation of a substrate with a semiconductor die coupled to it; Fig. 8 a perspective view of the substrate implementation of Fig. 7 after the formation of electrical connections between the substrate and the semiconductor die; Fig. 9 a perspective view of the substrate of Fig. 8 after applying an electrically insulating material to it; Fig. 10 a perspective view of a soil / pipe side surface of the substrate implementation of Fig. 9 is; Fig. 11 a perspective view of the substrate implementation of Fig. 10 after the formation of channels in one direction therein is; Fig. 12 a perspective view of the substrate implementation of Fig. 11 after an electroplating process; and Fig. Figure 13 shows a perspective view of a large number of semiconductor packages after a singulation process. DESCRIPTION

[0025] This disclosure, its aspects, and implementations are not limited to the specific components, assembly procedures, or process elements disclosed herein. Many other components, assembly methods, and / or process elements known in the prior art that are compatible with the intended semiconductor package are disclosed in this disclosure for use with specific implementations. Accordingly, for example, although specific implementations are disclosed, these implementations and implementing components may include any shapes, sizes, designs, types, models, versions, dimensions, concentrations, materials, quantities, process elements, process steps, and / or the like from the prior art for these semiconductor packages, as well as implementing components and processes, that are compatible with the intended mode of operation and the intended processes.

[0026] Various semiconductor package designs utilize leads to establish electrical connections between a semiconductor die and a mainboard / printed circuit board (PCB) to which the semiconductor package is attached. In package implementations where solder is used to bond the leads to the mainboard / PCB, the solder's ability to wet the leads' sides / flanks during the bonding process affects the bond strength and quality. Wettable flanks improve the formation of solder fillets, which contribute to bond strength and are more easily detected with optical inspection tools to determine bond quality. If there is little or no wetting of the leads' sides, reliability issues can arise, and the ability to accurately inspect the bonds optically is significantly reduced.Thus, the ability to have wettable flanks for the conductors of a semiconductor package can improve package performance after bonding and support quality control during assembly.

[0027] The various semiconductor package implementations disclosed herein may be leadless or leaded. The term "leadless" in this document includes leaded designs in which the semiconductor package leads do not extend substantially beyond a surface of an electrically insulating material surrounding the leads. The term "leaded" in this document includes leaded designs in which the leads extend away from a surface of an electrically insulating material surrounding the leads. While the semiconductor package examples in this document include various leadless designs such as UDFN (Ultra Dual Flat No-Lead Packages) or DFN (Dual Flat No-Lead Packages) packages, the principles disclosed herein may also apply to the flanks of leaded packages or other types of packages.The principles disclosed herein can be used in particular for chip-on-lead package designs.

[0028] Various semiconductor dies can be included in the implementations disclosed herein. These semiconductor dies can include various substrate materials, including, but not limited to, silicon, silicon carbide, silicon-on-insulator, glass, sapphire, ruby, gallium arsenide, gallium nitride, or any other type of semiconductor material. The semiconductor dies can also include various types of semiconductor devices, including, but not limited to, metal oxide field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), diodes, power semiconductor devices, rectifiers, thyristors, or any other type of semiconductor device. One semiconductor die can be included in the various semiconductor package implementations, or multiple semiconductor dies can be included.

[0029] This document discusses the use of substrates as part of semiconductor package design to facilitate the transmission of electrical signals from the semiconductor die to the mainboard / printed circuit board and to provide mechanical support for the semiconductor die. Although the substrate types illustrated in the figures of this document reflect that the substrate is a leadframe, a strip of leadframes, or a sheet of leadframes, the principles illustrated herein can also be applied to leadframe types such as, but not limited to, printed circuit boards, laminated substrates, insulated metal substrates, or other substrate types.

[0030] Referring to Fig. 1 and Fig. Figure 2 illustrates an implementation of a substrate 2. In this implementation, the substrate 2 is a leadframe made of an electrically conductive material such as a metal or metal alloy. As illustrated, a set of first connecting rods 4 and second connecting rods 6 form part of the leadframe at a distance that forms a grid with spaces where the leads 8 are coupled to the connecting rods 4 and 5. As illustrated, the first set of connecting rods 4 and the second set of connecting rods in this implementation intersect essentially at right angles to each other to form a set of intersection points 10.

[0031] With reference to Fig. Figure 2 shows this perspective view of the leadframe 2, where at each of the plurality of intersection points 10 the intersection point is lowered or at a lower level than the rest of the material of each connecting rod of the first set of connecting rods 4 and the second set of connecting rods 6. The intersection points 10 are also lowered relative to a level of the plurality of conduits 8 of the leadframe 2. As shown in Fig. As illustrated in Figure 2, the multitude of lines and the uninterrupted sections of the connecting rods form a plane from which the multitude of intersection points 10 is lowered.

[0032] While in the leadframe implementation of Fig. 1 and Fig. 2. Although no die-flag structure is included, a die-flag could be included in other implementations. Although each lead is shown attached to only one of the connecting rods on an inside of the lead, in other implementations the leads could be attached to multiple connecting rods on the inside of the lead. Although the leadframe is made of copper or a copper alloy, a wide variety of electrically conductive materials or layers of electrically conductive materials can be used, including but not limited to aluminum, aluminum alloys, silver, silver alloys, tin, tin alloys, nickel, nickel alloys, any combination thereof, or any other type of electrically conductive material.

[0033] For leadframes or electrical connectors in substrates less than 0.2 mm thick, creating a wettable flank is difficult because the leadframe thickness is so thin that using a step-cutting process to partially expose the lead before plating becomes much more challenging. Using cut point reduction facilitates the use of a step-cutting process, as further disclosed herein. For example, if the leadframe thickness is approximately 0.123 mm, the cut point reduction is set to approximately 0.08 mm or more to achieve the desired step cut. In various implementations, the depth of the cut / step cut ranges from approximately 2% to approximately 10% of the thickness of the leadframe / electrically conductive layer in the substrate. If, instead of a step-cutting process, an increase in the leadframe thickness is desired (e.g.,If the leadframe were to be thinned from 128 microns to 256 microns, followed by an etching process to expose the leadframe flanks, the cost of this process would increase proportionally with the increased leadframe thickness. The other technical challenge is that, due to the significant time required to etch so much leadframe material, the etching process might not produce the desired flat flank surfaces. This problem is likely to be most acute where wet etching is used.

[0034] In various implementations, the leadframe can be formed by stamping, punching, etching, or cutting the leadframe pattern from a web of material and subsequently lowering the intersections by a stamping or other bending process. For substrates that are not leadframes, the lowered intersections can be formed by laminating, pressing, or by the layer-by-layer layup process during the manufacture of a printed circuit board.

[0035] With reference to Fig. 3 will be the Leadframe implementation 2 of Fig. Figure 2 illustrates the situation after an electrically insulating material 12 has been applied, exposing the surfaces of the conductors 8. In various implementations, the electrically insulating material can consist of a wide variety of materials, including, but not limited to, a molding compound, a resin, an encapsulating material, a polymer, an epoxy, a filler, a dye, any combination thereof, or any other type of electrically insulating material. Fig. Figure 3 shows the electrically insulating material 12 in a see-through view, so that the otherwise covered sections of the leadframe 2 are visible. Fig. Figure 3 illustrates the leadframe 2 after step cutting of the electrically insulating material 12 and the ends of the leads 8 using a sawing or etching process, resulting in a set of exposed flanks 14. It should be noted that the cut is a step cut, which does not completely sever the electrically insulating material 12, nor does it cut into, or substantially into, the intersection points 10 of the first set of connecting rods 4 and the second set of connecting rods 6. While most of the material of the first set of connecting rods 4 was removed by the cutting process, the reduced section was not removed, and the material of the second set of connecting rods 6 remains.

[0036] Since the second set of connecting rods 6 remains physically connected to each of the plurality of conductors 8 after the cut, the sections of the conductors exposed through the surfaces of the electrically insulating material 12 can be electroplated through the resulting electrical connection. These sections of the conductors 8 also include the exposed flanks 14. As illustrated, the entirety of the exposed flanks 14 can be electroplated because the exposed flanks 8 extend over the entire thickness of the plurality of conductors 8. This ability to electroplate the entire exposed flank over the full thickness of the conductor maximizes the wettable surface area of ​​the flank and can form solder joints covering approximately 75%, 80%, 85%, 90%, 95%, or 100% of the wettable surface area of ​​the flank.These solder joints can then contribute to improving the reliability of the connection and the optical inspectionability of the bonds. This wettability of the flank is achieved because the entire surface of the flank is exposed during the electroplating process, in contrast to processes with only partial cutting or with pitted wettable flanks, where only a portion of the flank remains exposed.

[0037] Fig. Figure 4 illustrates the leadframe 2 with the electrically insulating material 12 after the cutting process and shows the exposed conductors 8 and the exposed flanks 14. As illustrated, the cut is made only in one channel along the length of the first set of connecting rods and is designed so that the cut points 10 are not exposed through the electrically insulating material. By leaving 10 cut points exposed, the amount of electroplating that occurs on sections of the leadframe is reduced; these sections are ultimately cut away when the leadframe 2 is singulated in the second channel and the connecting rods are removed.

[0038] With reference to Fig. 5 will be a large number of semiconductor packages 16 after the singulation of the leadframe 2 of Fig. Figure 4 illustrates this. As illustrated, during singulation, the remaining material of the first set of connecting rods 4 is removed, and all of the material of the second set of connecting rods 6 is removed. The sections 17 of the plurality of conductors 8 attached to the connecting rods are also removed and are illustrated as being exposed through the electrically insulating material 12. It is also illustrated how the flanks 14 adjacent to the stepped / flanged sections of the electrically insulating material 12, which remain after cutting the remaining connecting rod and the electrically insulating material 12, are fully exposed. Because the flanks 14 were electroplated, the width of the cut made in the previously cut channel is narrowed to avoid removing / damaging the electroplated flank surfaces during the cut.

[0039] With reference to Fig. Figure 6 illustrates an implementation of a semiconductor package 18 in a cross-sectional view showing the semiconductor die 20 surrounded by electrically insulating material 22 and coupled to leads 24 and a leadframe 26. As illustrated, the flanks 28 of the leads 24 are covered with a coating of electroplated material 30, which helps to fully wet the flanks 28 with solder to form solder fillets 32. The ability to form solder fillets 32 is advantageous in this package implementation because the semiconductor package 18 is attached to the copper traces 34 of a printed circuit board 38, which enclose a gap 36 across which the semiconductor package 18 is connected. Thus, the tolerance for solder flowing into the gap is small, and the need to control the solder flow by means of the wettable flanks 28 prevents internal bridging that would lead to a short circuit.Since this semiconductor package 18 is a non-conductive package, its footprint is correspondingly small, which facilitates its bonding in a correspondingly small area of ​​the printed circuit board 38. As also illustrated, the stepped / flanged sections 40 of the electrically insulating material 22 adjacent to the flanks 28 support the formation of the fillet and the uniform distribution of the solder to create an optically visible bond and to control the movement of the solder around the outside of the package. These stepped / flanged sections 40 can also help to guide the solder flow and prevent solder from flowing into the gap 36.

[0040] The various package implementations disclosed herein can be formed using different methods for forming a semiconductor package. In various implementations, the method includes testing a leadframe with the connecting rod and the lead configurations disclosed herein. The method then includes coupling one or more semiconductor dies to the leadframe. With reference to Fig. 7 will be an implementation of a leadframe 42 in a reverse view to the one in Fig. Figure 2 illustrates that the side of the leadframe 42 facing the semiconductor die is oriented upwards. Fig. Figure 7 shows four semiconductor dies 44 after being connected / coupled to the leads 46 of the leadframe using a variety of systems and methods, such as, but without limitation, soldering, sintering, die mounting film, die mounting materials, adhesive, epoxy resin or any other material compatible with forming a bond between the material of the semiconductor die 44 and the material of the leadframe 42.

[0041] The method can also include forming a multitude of electrical connections using electrical connectors between the semiconductor die 44 and the multitude of conductors 46. Fig. Figure 8 illustrates the leadframe 42 after wire bonding to form a variety of wire bonds 48. Other types of electrical connectors could also be used to form electrical connections, including but not limited to clips, wires, pins, or any other type of electrical connector.

[0042] After the formation of the electrical connectors, the method includes the application of an electrically insulating material over the leadframe 42, the semiconductor die 44, and the plurality of conductors 46. With reference to Fig. Figure 9 illustrates the leadframe 42 after the application of the molding compound 50, with only the ends of the first set of connecting rods 52 and the second set of connecting rods 54 remaining exposed. After the application of the molding compound 50, the leadframe 42 is then turned over so that the side of the leadframe opposite the side to which the semiconductor dies are attached is facing upwards (towards the top), as shown in Fig. Figure 10 illustrates this. In this position, the Leadframe 42 is now ready for cutting.

[0043] Fig. Figure 11 illustrates the leadframe 42 after the formation of a channel / cut 58 in the molding compound material 50, the cutting of the material of the first set of connecting rods 52, and the cutting of the leads 46 to form flanks 56. As shown in Fig. As illustrated in Figure 11, the channel / section 58 is a stepped section formed using a sawing process. The flanks 56 and the conduits 56, along with the ends of the second set of connecting rods 54, are now exposed through the material of the molding compound 50.

[0044] Fig. Figure 12 illustrates the leadframe 42 after an electroplating process, in which an electrical circuit is formed between the ends of the second set of connecting rods 54, the leads 46, and the flanks 56. Since the leads are still electrically connected to the second set of connecting rods 54 within the molding compound 50, the electrical circuit enables the deposition of the electroplated material on the exposed surfaces of the leads 46 and the flanks 56. Because electroplating of the electroplated material is employed, the thickness of the electroplated material can be controlled to a desired thickness, which in certain implementations can be approximately 2 micrometers or more.The electroplated material can consist of a wide variety of materials that can be electroplated onto the respective substrate material, including, but not limited to, tin, nickel, gold, palladium, any alloys thereof, any combinations thereof, or any other electroplatable materials. In various process implementations, the electroplated material can be deposited as a single layer or as multiple layers of different materials through various electroplating process steps.

[0045] After electroplating, the process includes the singulation of semiconductor packages. As in Fig. Figure 13 illustrates a multitude of semiconductor packages 60 after singulation in the channel 58 and through the material of the second set of connecting rods. As illustrated, this singulation forms the steps / grooves 62 adjacent to the flanks 56 of the leads 46. Since these leads and flanks have now been electroplated, problems with wettability caused by corrosion of the base metal of the leads are essentially eliminated. The in Fig. The 13 illustrated enclosures are ultra-dual, flat, conductorless enclosures.

[0046] It is understood without further ado that where the foregoing description relates to particular implementations of semiconductor packages and implementing components, subcomponents, methods and sub-methods, a number of modifications may be made without deviating from their essence, and that these implementations, implementing components, subcomponents, methods and sub-methods may also be applied to other semiconductor packages.

Claims

[1] Substrate, comprising: a set of intersecting connecting rods forming a grid pattern, wherein each intersection point in the set of intersecting connecting rods is lowered by a plurality of conduits coupled within the grid pattern of the set of intersecting connecting rods. [2] Substrate according to claim 1, wherein a first group of the set of intersecting connecting rods is oriented substantially perpendicular to a second group of the set of intersecting connecting rods. [3] Substrate according to claim 1, wherein the thickness of the set of intersecting connecting rods and the plurality of conduits is less than 0.2 mm. [4] Substrate according to claim 3, wherein the reduction is 0.08 mm or more. [5] Substrate, encompassing: a first set of connecting rods; a second set of connecting rods; and a multitude of lines coupled between the first set of connecting rods and the second set of connecting rods; wherein the first set of connecting rods intersects with the second set of connecting rods; and wherein each intersection point of the first set of connecting rods and the second set of connecting rods is lowered by the multitude of conduits. [6] Substrate according to claim 5, wherein the first set of connecting rods and the second set of connecting rods intersect substantially perpendicularly. [7] Substrate according to claim 5, wherein the thickness of the first set of connecting rods and the second set of connecting rods is less than 0.2 mm. [8] Substrate according to claim 5, wherein the thickness of the plurality of conduits is less than 0.2 mm. [9] Substrate according to claim 5, wherein the reduction is 0.08 mm or more. [10] Method for forming a semiconductor package, the method comprising: Providing a substrate, including: a first set of connecting rods; a second set of connecting rods; and a multitude of lines coupled between the first set of connecting rods and the second set of connecting rods; wherein the first set of connecting rods and the second set of connecting rods are offset downwards at a plurality of intersection points; and Coupling a semiconductor die with the multitude of conductors; Applying an electrically insulating material over the substrate; Forming a channel in the electrically insulating material and forming a flank in each of the multitude of conductors; Electroplating the flank of each of the multiple conduits; and Singling out a semiconductor package by cutting the first set of connecting rods and the second set of connecting rods. [11] Method according to claim 10, wherein the electroplating of the flank of each of the plurality of conduits further comprises electroplating using the first set of connecting rods and the second set of connecting rods. [12] Method according to claim 10, wherein forming the flank in each of the plurality of lines further comprises completely cutting through a thickness of each of the plurality of lines. [13] Method according to claim 10, wherein forming the channel in the electrically insulating material further comprises partially cutting into the material of the electrically insulating material. [14] Method according to claim 10, wherein forming the channel in the electrically insulating material further comprises non-cutting the reduction of the plurality of intersection points. [15] Method according to claim 10, wherein the singulation of the semiconductor package further comprises cutting the channel in the electrically insulating material. [16] Method according to claim 10, wherein the substrate is a leadframe. [17] Method according to claim 16, wherein the leadframe is a plate. [18] Method according to claim 16, wherein the semiconductor package is a wireless semiconductor package. [19] Method according to claim 10, wherein after electroplating the flank of each of the plurality of conductors is a solder-wettable flank. [20] Method according to claim 10, wherein the electroplating of the flank of each of the plurality of conduits further comprises electroplating the entire flank.

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