Semiconductor layout pattern and high-frequency circuit layout pattern

Abstract

The invention provides a semiconductor layout pattern comprising: a substrate, an active region defined on the substrate, a plurality of gate structures arranged in the active region, and a plurality of doping regions arranged in the active region, wherein the plurality of gate structures and doping regions contained in the active region form a first amplifier and a second amplifier, the first amplifier and the second amplifier are connected in series, and a drain doping region of the first amplifier and a source doping region of the second amplifier share the same doping region. The advantage of the invention is that, firstly, space is saved, and secondly, the efficiency of the amplifier is improved.

Description

BACKGROUND OF THE INVENTION 1. AREA OF THE INVENTION

[0001] The invention relates to the field of semiconductors, in particular a semiconductor layout pattern suitable for power amplifiers, which has the advantages of space saving and improved performance. 2. DESCRIPTION OF THE STATE OF THE ART

[0002] Power amplifiers are a crucial component in RF power transmission. Their primary function is to amplify and output signals. They are typically positioned at the front end of the antenna element and are also the component with the highest power consumption in the entire RF front-end circuit.

[0003] Power amplifiers are mainly used in electronic products or devices that require a large bandwidth, e.g., in mobile phones, tablet computers, WiMAX, Wi-Fi, Bluetooth, RFID readers, satellite communications, and other network communication products.

[0004] The two-stage amplifier is a type of power amplifier consisting of two amplifiers connected in series. Its main purpose is to achieve higher overall gain through multi-stage amplification while simultaneously improving frequency response, distortion, and other problems that can occur with single-stage amplifiers.

[0005] A cascade amplifier (or cascode amplifier) ​​is a two-stage amplifier consisting of a common source (or emitter) connected in series with a common gate (or base). Compared to single-stage amplifiers, the common-source / common-gate amplifier combination can achieve the following characteristics: better shielding of input and output, higher input impedance, higher output impedance, and greater bandwidth. In modern circuits, cascade amplifiers can be composed of two different types of transistors (bipolar transistors and field-effect transistors). Because the cascode design offers better input / output isolation and less direct coupling between input and output stages, it can mitigate the influence of the Miller effect and thus achieve a wider bandwidth.Currently, there is still room for improvement in power amplifiers; for example, the layout pattern takes up a large area, which is not conducive to the miniaturization of products. SUMMARY OF THE INVENTION

[0006] The invention provides a semiconductor layout pattern comprising a substrate, wherein an active region is defined on the substrate and a plurality of gate structures are arranged in the active region, each gate structure being arranged parallel to one another along a first direction, and a plurality of doping regions in the substrate being arranged on both sides of each gate structure, wherein the plurality of gate structures contained in the active region comprise a first gate structure and a second gate structure, and the plurality of doping regions contained in the active region comprise a first source doping region, a first drain doping region, a second source doping region, and a second drain doping region, wherein the first gate structure, the first source doping region, and the first drain doping region form a first amplifier, and the second gate structurethe second source doping region and the second drain doping region form a second amplifier, and the first drain doping region and the second source doping region contain a common doping region among the multitude of doping regions, and the same doping region is defined as a common doping region.

[0007] The invention also provides a high-frequency circuit layout pattern comprising a substrate with an active area defined thereon, a plurality of gate structures arranged in the active area, wherein the gate structures are arranged parallel to each other along a first direction, a plurality of doping regions arranged in the active area, and each doped region in the substrate being arranged on both sides of each gate structure, wherein the plurality of gate structures and the plurality of doping regions contained in the active area form a first amplifier and a second amplifier, wherein a drain of the first amplifier and a source of the second amplifier are connected to each other, and both the drain of the first amplifier and the source of the second amplifier are arranged in a common doping region.

[0008] The present invention is characterized in that, to save space and reduce the influence of line impedance when creating the layout pattern of a two-stage amplifier, the two amplifiers are arranged in the same active area, so that both amplifiers contained in the two-stage amplifier can share a portion of the doping area; that is, there is no shallow trench insulation between the areas in which the two amplifiers are arranged. According to the concept of the invention, the size of the device can be effectively reduced, and the efficiency of the amplifier can also be improved because the influence of line impedance is reduced.

[0009] These and other features of the present invention will become clear to the person skilled in the art upon reading the following detailed description of the preferred embodiment, which is shown in the various figures and drawings. BRIEF DESCRIPTION OF THE FIGURES

[0010] To facilitate understanding of the following explanations, the reader may refer to the drawings and their detailed descriptions while reading the present invention. Based on the specific embodiments in this description and with reference to the corresponding drawings, the specific embodiments of the present invention are explained in detail, and the operating principle of the specific embodiments of the present invention is presented. Furthermore, for the sake of clarity, the features in the drawings may not be drawn to scale, so that the dimensions of some features in some drawings are intentionally enlarged or reduced. Fig. Figure 1 illustrates the circuit diagram of a cascade amplifier. Fig. Figure 2 is a schematic view illustrating the arrangement of a first amplifier and a second amplifier of a cascade amplifier according to two different embodiments. Fig. Figure 3 shows the arrangement of the first amplifier and the second amplifier in the active area according to some different embodiments of the present invention, wherein figures (a), (b), (c), (d) and (e) in Fig. Figure 3 illustrates five different arrangements each. The Fig. 4, Fig. 5 and Fig. Figure 6 illustrates the layout of several two-stage amplifiers according to different embodiments of the present invention. Fig. Figure 7 is a schematic view illustrating the layout of RF circuit patterns according to an embodiment of the present invention. Fig. Figure 8 illustrates the circuit diagram of a stacked MOS metal oxide semiconductor transistor (stacked MOS). Fig. Figure 9 is a schematic view of stacked MOS metal oxide semiconductor transistors according to an embodiment of the present invention. DETAILED DESCRIPTION

[0011] Preferred embodiments are described below for a better understanding of the present invention by those skilled in the field of technology. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the content and the effects to be achieved.

[0012] It should be noted that the drawings are for illustrative purposes only and are not necessarily to scale. The scale may be further modified depending on the specific design considerations. When the words "top" or "bottom" are used to describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be reversed to obtain a similar structure, and these structures should therefore not be excluded from the scope of the claims of the present invention.

[0013] Although the terms "first," "second," "third," etc., are used in the context of the present invention to describe elements, components, regions, layers, and / or sections, such elements, components, regions, layers, and / or sections should not be limited by such terms. These terms are used only to distinguish one element, component, region, layer, and / or block from another. They do not imply or represent any prior ordinal number of the element, nor do they represent the order of arrangement of one element and another element, or the sequence of manufacturing methods.Therefore, the first element, first component, first area, first layer or first block referred to below can also be called the second element, second component, second area, second layer or second block, without this deviating from the specific embodiments of the present invention.

[0014] The terms “approximately” or “essentially” used in the present invention generally mean that the quantity is within 20% of a certain value or range, e.g., within 10%, 5%, 3%, 2%, 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate; that is, the meaning of “approximately” or “essentially” can also be implied without explicitly stating “approximately” or “essentially”.

[0015] The terms “coupling” and “electrical connection” used in the present invention encompass all direct and indirect means of electrical connection. For example, when it is described that the first component is coupled to the second component, this means that the first component may be directly electrically connected to the second component or indirectly electrically connected to the second component via other devices or connecting means.

[0016] Although the present invention is described below with reference to specific embodiments, the inventive principles of the present invention can also be applied to other embodiments. Furthermore, certain details are omitted so as not to obscure the spirit of the present invention, and these omitted details are known to a person skilled in the art.

[0017] As mentioned in the previous paragraph, the two-stage amplifier belongs to a type of power amplifier. Different applications include various types of two-stage amplifiers, such as the previously mentioned cascade amplifier, or other common two-stage amplifiers, such as stacked MOS, Gilbert mixers, RF switches, and active inductors, all of which fall under the category of two-stage amplifier applications. To clarify the specifics of this case, the following paragraphs will focus primarily on the cascade amplifier, but those skilled in the art will know that the scope of the present invention also includes other types of two-stage amplifiers besides the cascade amplifier, which are described here first.

[0018] Fig. Figure 1 illustrates a circuit diagram of a cascade amplifier, and Fig. Figure 2 illustrates the schematic arrangement of a first amplifier and a second amplifier of the cascade amplifier according to two different embodiments. As shown in Fig. As illustrated in Figure 1, a cascade amplifier comprises a first amplifier CS, for example, a common source amplifier, and a second amplifier CG, for example, a common gate amplifier, with the first amplifier CS and the second amplifier CG connected in series. More precisely, the gate terminal CS-G of the first amplifier CS is connected to an input signal VG1 (or input signal Vin), and the source terminal CS-S of the first amplifier CS is connected to potential V- or ground. The gate terminal CG-G of the second amplifier CG is connected to a voltage source VG2, the drain terminal CG-D of the second amplifier CG is connected to the output signal Vout, and the drain terminal CS-D of the first amplifier CS is connected to the source terminal CG-S of the second amplifier CG. Furthermore, the circuit diagram in Fig. 1. A resistor R and a voltage source V+ are connected to the circuit. These components are part of the conventional circuit technology of cascade amplifiers and are not among the main features of the present invention, so they are not repeated here.

[0019] It should be noted that, as in Fig. Figure 1 illustrates that the drain terminal CS-D of the first amplifier CS is connected to the source terminal CG-S of the second amplifier CG. If the first amplifier CS and the second amplifier CG are formed together on a substrate (not illustrated), as in the left embodiment of Fig. Figure 2 shows the left side of Fig. Figure 2 shows a schematic view of the formation of the first amplifier CS and the second amplifier CG side by side on a substrate according to one of the embodiments. The first amplifier CS and the second amplifier CG are each formed in two active areas AA1 and AA2, and the two active areas AA1 and AA2 are separated by a shallow trench insulation STI. Subsequently, after the first amplifier CS and the second amplifier CG have each been formed in the active areas AA1 and AA2, the two amplifiers are connected in series by elements such as wires; for example, the drain terminal CS-D of the first amplifier CS is connected to the source terminal CG-S of the second amplifier CG. For simplicity, the layout structures in the first amplifier CS and the second amplifier CG, such as gate structures, source / doping regions, contact structures, wires, and other elements, are shown in Figure 2. Fig. 2 not shown. However, it should be clear to the expert that the layout structure falls within the area of ​​the in Fig. The first amplifier CS and the second amplifier CG shown in the diagram should fall.

[0020] On the left in Fig. In the embodiment shown in Figure 2, the two active surfaces AA1 and AA2 (forming the first amplifier CS and the second amplifier CG, respectively) are located as close together as possible. However, under the constrained process conditions, a shallow trench insulation (STI) of a certain width still exists between active surfaces AA1 and AA2. This presents two problems. One is that active surfaces AA1 and AA2 occupy a specific area and are adjacent to each other, which hinders miniaturization of the devices. Another problem is that the first amplifier CS and the second amplifier CG must be connected by wires and other elements, the wires themselves having a specific impedance.Thus, if the distance between the active area AA1 and the active area AA2 is large, the length of the wires also increases, and the impedance of the entire element is amplified, which does not improve the performance of the amplifier.

[0021] Therefore, based on the problems mentioned above, the applicant of the present invention proposes a different layout and arrangement pattern suitable for power amplifiers. As shown in the right half of Fig. 2 illustrates that, compared to the one in the left half of Fig. In the embodiment illustrated in Figure 2, the first amplifier CS and the second amplifier CG are formed together within the same active area AA, and the active area AA is surrounded by shallow trench insulation STI. Thus, since the first amplifier CS and the second amplifier CG share the same active area AA, and the shallow trench insulation STI is not located between the first amplifier CS and the second amplifier CG, the area of ​​the entire component can be reduced (because the same active area AA is shared). Furthermore, because the distance between the first amplifier CS and the second amplifier CG is reduced, the two amplifiers are less affected by line impedance after connection, which has a positive effect on the efficiency of the amplifiers.

[0022] In short, the concept of the present invention is to separate the original two amplifiers CS and CG within the same active area AA, thereby achieving the advantages of reduced device size and improved efficiency. According to this concept, various embodiments of the present invention can be formed depending on the different arrangements of the first amplifier CS and the second amplifier CG within the active area AA. Some embodiments are described in the following paragraphs.

[0023] Fig. Figure 3 shows the arrangement of the first amplifier and the second amplifier in the active area according to some different embodiments of the present invention, wherein figures (a), (b), (c), (d) and (e) in Fig. Figure 3 illustrates five different arrangements each. For simplicity, the layout structure of the first amplifier CS and the second amplifier CG is shown in Fig. 3 is not shown, but the expert should know that the layout structure is in the Fig. The area of ​​the first amplifier CS and the second amplifier CG should be included in the illustrated area AA. As illustrated in Fig. (a), both the first amplifier CS and the second amplifier CG are located next to each other in the active area AA. As illustrated in Fig. (b), a second amplifier CG is arranged between two first amplifiers CS in the active area AA. As illustrated in Fig. (c), the first amplifier CS, the second amplifier CG, the first amplifier CS, and the second amplifier CG are included, each from left to right. As illustrated in Fig. (d), a plurality of groups of first amplifier CS and second amplifier CG are arranged repeatedly from left to right (i.e., in the sequence first amplifier CS, second amplifier CG, first amplifier CS, second amplifier CG, etc.). As illustrated in Fig.(e) Illustrated, this embodiment also includes a contact metal layer CTM arranged in the vicinity of the amplifier, and the contact metal layer CTM can connect a plurality of gates (not illustrated) in the amplifier or connect a plurality of sources / drains in the amplifier. The contact metal layer CTM can be arranged on at least one side of the amplifier. For example, in Figure (e) of . Fig. 3 the contact metal layer CTM is arranged on the top, bottom and left and right sides of the first amplifier CS, while another part of the contact metal layer CTM is arranged on the top of the second amplifier CG, but not on the bottom of the second amplifier CG.

[0024] It should be noted that in Fig. Figure 3 shows several possible arrangements of the first amplifier and the second amplifier, but the present invention is not limited to these. For example, in the arrangements shown in Figure 3, it is possible to demonstrate the following: Fig. In the three illustrated embodiments, it is also possible to interchange the positions of the first amplifier CS and the second amplifier CG. For example, in Figure (a), the first amplifier CS is on the left and the second amplifier CG is on the right, but the positions of the two amplifiers can also be reversed (i.e., the first amplifier CS is on the right and the second amplifier CG is on the left), which is also within the scope of the present invention. Furthermore, the arrangement of the contact metal layer CTM illustrated in Figure (e) can be modified according to the actual requirements; for example, some contact metal layer CTM can be added to or removed from the area around the first amplifier CS and the second amplifier CG. All of the above-mentioned variations fall within the scope of the present invention.

[0025] The Fig. 4, Fig. 5 and Fig. Figure 6 illustrates the layout of several two-stage amplifiers according to different embodiments of the present invention. The one shown in the Fig. 4, Fig. 5 and Fig. The illustrated two-stage amplifier in Figure 6 serves as an example of the cascade amplifier. First, as shown in... Fig. Figure 4 illustrates an active area AA and a shallow trench insulation STI surrounding the active area AA, defined on a substrate Sub. A first amplifier CS and a second amplifier CG are then formed within the active area AA. However, depending on the arrangement of the first amplifier CS and the second amplifier CG, many different embodiments can be formed. For example, the one shown in Fig. 4. The embodiment shown in Figure (a) of Fig. The arrangement is illustrated in Figure 3. A first amplifier CS is formed in the left part of the active area AA, and a second amplifier CG is formed in the right part of the active area AA. A variety of gate structures G are formed in the active area AA as the gates of the first amplifier CS or the second amplifier CG, and source / drain doped areas SD can be formed on both sides of the gate structures G by doping, etc. Then, a variety of contact structures CT are formed on each gate structure G or the source / drain doped areas SD, with the contact structures CT being used to connect the gate structures G or the source / drain doped areas SD to other elements, such as metal wire layers M1, M2, etc.

[0026] In this embodiment, a plurality of gate structures G on the left side of the active region AA form the gate of the first amplifier CS, and a plurality of drain doping regions SD on the left side of the active region AA form the source / drain of the first amplifier CS. A plurality of gate structures G on the right side of the active region AA form the gate of the second amplifier CG, and a plurality of source / drain doping regions SD on the right side of the active region AA form the source / drain of the second amplifier CG. For a better understanding of the composition of the first amplifier CS and the second amplifier CG, see below. Fig. 4. The first source doping region S1, the second source doping region S2, the first drain doping region D1, the second drain doping region D2, the first gate structure G1, and the second gate structure G2 are defined. The first source doping region S1, the second source doping region S2, the first drain doping region D1, and the second drain doping region D2 all belong to the source / drain doping region SD, while the first gate structure G1 and the second gate structure G2 belong to the gate structure G. In this embodiment, the first source doping region S1, the first drain doping region D1, and the first gate structure G1 form a first amplifier CS, while the second source doping region S2, the second drain doping region D2, and the second gate structure G2 form a second amplifier CG. In addition, there are further gate structures G and source / drain doping areas SD in the active area AA.These gate structures G and source / drain doping areas SD can be connected in parallel with the first amplifier CS or the second amplifier CG, so that in the circuit diagram only the first amplifier CS or the second amplifier CG is still connected in series. In the actual manufacturing process, the number of gate structures G and source / drain doping areas SD can also be increased or decreased as needed.

[0027] Furthermore, as shown in the circuit diagram of view 1, the gate CS-G of the first amplifier CS is connected to the metal wire layer M1 via the contact structure CT and then to the voltage source VG1. The source CS-S of the first amplifier CS is connected to the second metal layer M2 and can be connected to the voltage source V- via the second metal layer M2. The gate CG-G of the second amplifier CG is connected to the metal conductor layer M1 via the contact structure CT and then to the voltage source VG2. The drain CG-D of the second amplifier CS is connected to the second metal layer M2 and can be connected to the output signal Vout of the voltage source via the second metal layer M2.In this and the following embodiments, signal sources such as Source S, Drain D, Drain CS-D of the first amplifier CS, Gate CS-G of the first amplifier CS, Source CS-S of the first amplifier CS, Drain CG-D of the second amplifier CG, Gate CG-G of the second amplifier CG, Source CG-S of the second amplifier CG, voltage source VG1, voltage source VG2, etc., are directly marked in the figure. Further detailed information on the connection can be found in the [reference to be inserted here]. Fig. The circuit diagram shown in section 1 is not repeated here.

[0028] It should be noted that the first amplifier CS and the second amplifier CG share a portion of the source / drain doping area SD to connect the first amplifier CS and the second amplifier CG. As shown in Fig. As illustrated in Figure 4, the drain CS-D of the first amplifier CS and the source CG-S of the second amplifier CG share the same source doping area, i.e., the one shown in Figure 4. Fig. 4. The source doping area SD3 is marked. Here, the source / drain doping area SD3 can be defined as a shared doping area SD3. In this embodiment, the first amplifier CS and the second amplifier CG are formed together in the same active area AA and share a portion of the doping area SD3. Therefore, the distance between the first amplifier CS and the second amplifier CG can be significantly reduced.

[0029] The in Fig. The illustrated layout pattern 4 is one embodiment of the present invention. In other embodiments of the present invention, the arrangement positions of the first amplifier CS and the second amplifier CG can also be changed within the same active area AA. For example, in Fig. 5 the first amplifier CS and the second amplifier CG are also arranged in the active area AA, but in this embodiment the second amplifier CG is located between the two first amplifiers CS, and the layout arrangement of this embodiment is similar to that in Figure (b) of Fig. Figure 3 illustrates this. Similarly, in this embodiment, the first amplifier CS and the second amplifier CG share a portion of the doping area SD3, thus achieving the benefits of reduced component size and improved amplifier efficiency. Other elements or connection types of this embodiment are similar to those of the embodiment above and are therefore not repeated here.

[0030] In other embodiments, such as in Fig. As shown in Figure 6, the first amplifier CS and the second amplifier CG are formed in the active area AA, but in this embodiment the first amplifier CS and the second amplifier CG are arranged alternately and repeatedly, and the layout arrangement of this embodiment is similar to that shown in the aforementioned Figure (d) of Fig. Figure 3 illustrated. Similarly, in this embodiment, the first amplifier CS and the second amplifier CG share a portion of the doping area SD3, thus achieving the benefits of reduced component size and improved amplifier efficiency. Other elements or connection types of this embodiment are similar to those of the embodiment above and are therefore not repeated here.

[0031] As from the Fig. 4, Fig. 5 and Fig. As can be seen in Figure 6, the first amplifier CS and the second amplifier CG are located together in the same active area AA and share part of the doping area SD3. Therefore, the distance between the first amplifier CS and the second amplifier CG is significantly smaller than in the embodiment where the two amplifiers are arranged in different active areas (for example, in the embodiment shown on the left). Fig. 2) Since the distance between the two amplifiers is reduced, the distance between the wires is also shortened, which reduces the influence of the line impedance and improves the efficiency of the amplifiers. According to the applicant's experimental results, compared to the left half of Fig. 2 illustrated embodiment in the embodiments in the Fig. 4, Fig. 5 and Fig. 6 of the present invention reduces the area of ​​the amplifier by more than 20% and improves the efficiency of the amplifier by more than 11%.

[0032] The amplifier according to the invention can also be used for high-frequency (HF) amplifiers. Fig. Figure 7 is a schematic view illustrating the layout of RF circuit patterns according to one embodiment of the present invention. As shown in Fig. As illustrated in 7, in this embodiment most of the elements are the same as those in the above-mentioned Fig. 4 to 6 are similar, such as the active area AA, the gate structures G, the contact structures CT, the metal wire layer M1, and the metal wire layer M2, etc. These elements are designated with the same reference numerals, and the source / drain doping regions in this embodiment are the active regions AA on both sides of the gate structure G, which are not labeled for simplicity. In this embodiment, a layout pattern of RF amplifiers is proposed in which a first amplifier T1 and a second amplifier T2 are contained in the active area AA. The first amplifier T1 and the second amplifier T2 are connected in series, and the first amplifier T1 and the second amplifier T2 are formed together in the same active region AA and share a portion of the source / drain doping region.Therefore, the layout pattern applied to the RF amplifier in this embodiment also has the advantage of reducing the number of components and improving performance. Other details about the RF amplifier are part of the well-known technology in this field, so I will not repeat them here.

[0033] In the embodiments mentioned above, the concept of the present invention is applied to the cascade amplifier and the RF amplifier. However, as mentioned above, the concept of the present invention can also be applied to other types of circuits, e.g., to the series connection of more than two transistors. Fig. Figure 8, for example, illustrates a circuit diagram of a stacked MOS metal oxide semiconductor transistor (stacked MOS), and Fig. Figure 9 illustrates a layout plan of the stacked MOS metal oxide semiconductor transistor according to an embodiment of the present invention. As shown in Fig. As illustrated in Figure 8, in the circuit diagram of the stacked MOS metal-oxide-semiconductor transistor, the gates of the first amplifier T1 and the second transistor T2 are connected together (connected to the voltage source VG), and the drain of the first amplifier T1 and the source of the second amplifier T2 are connected together. The corresponding layout is shown below. Fig. The active area AA comprises elements such as the gate structure G, the source / drain doping area SD, the contact structure CT, the metal wire layer M1, and the metal wire layer M2. The features of these elements are the same as in the embodiments described above and are therefore not repeated here. In this embodiment, the drain of the first amplifier T1 and the source of the second amplifier T2 are connected and share a portion of the drain doping area SD3, which also allows for a reduction in the size of the component. Therefore, the invention can be applied to cascade amplifiers, RF amplifiers, and other two-stage amplifiers, including the stacked MOS metal-oxide-semiconductor transistors (stacked MOS) or Gilbert mixers, RF switches, active inductors, etc., described herein.

[0034] Based on the above description and the drawings, a semiconductor layout pattern of the present invention comprises a substrate Sub, an active region AA defined on the substrate Sub, a plurality of gate structures G arranged in the active region AA, wherein the gate structures are arranged parallel to each other along a first direction (for example, along the X direction), and a plurality of doping regions SD arranged in the active region AA, with each doping region SD in the substrate Sub arranged on both sides of each gate structure G, wherein the gate structures G contained in the active region AA comprise a first gate structure G1 and a second gate structure G2, and the doping regions SD contained in the active region AA comprise a first source doping region S1, a first drain doping region D1,comprising a second source doping region S2 and a second drain doping region D2. The first gate structure G1, the first source doping region S1, and the first drain doping region D1 form a first amplifier CS, and the second gate structure G2, the second source doping region S2, and the second drain doping region D2 form a second amplifier CG, wherein the first drain doping region D1 and the second source doping region S2 contain the same doping region among a plurality of doping regions, and the same doped region is defined as a common doping region SD3 (see the in , Fig. 4 (depiction shown).

[0035] In some embodiments of the present invention, a plurality of doping regions SD are arranged parallel to each other along a first direction (for example, the X direction), and a plurality of doping regions SD and a plurality of gate structures G are arranged alternately along the first direction.

[0036] In some embodiments of the present invention, viewed from above, the plurality of gate structures G and the plurality of doping regions SD are all long strips, and the long sides of the long strips SD extend along a second direction (for example, the Y direction), wherein the second direction (Y direction) and the first direction (X direction) are perpendicular to each other.

[0037] In some embodiments of the present invention, the common doping area SD3 is arranged in the top view between the first gate structure G1 and the second gate structure G2, and the common doping area SD3 borders the first gate structure G1 and the second gate structure G2.

[0038] In some embodiments of the present invention, the common drain doping area SD3 is arranged on one side of the first gate G1, the first source doping area S1 is arranged on the other side of the first gate G1 relative to the common doping area SD3, the common drain doping area SD3 is arranged on one side of the second gate G2, and the second drain doping area D2 is arranged on the other side of the second gate G2 relative to the common drain doping area SD3.

[0039] In some embodiments of the present invention, the first amplifier CS comprises a common source amplifier, the second amplifier comprises a common gate amplifier CG, and the first amplifier CS and the second amplifier CG are connected in series to form a cascade amplifier.

[0040] In some embodiments of the present invention, the first gate structure G1 is connected to a voltage source VG1 and the second drain doping area is connected to an output signal Vout.

[0041] In some embodiments of the present invention, the active area AA further comprises a plurality of common source amplifiers CS and a plurality of common gate amplifiers CG, wherein each area containing the common source amplifier CS is defined as a first area, and each area containing the common gate amplifier CG is defined as a second area.

[0042] In some embodiments of the present invention, at least one of the plurality of first regions is arranged between two adjacent second regions, and at least one of the plurality of second regions is arranged between two adjacent first regions (for example, in Figure (d) of Fig. 3 (a multitude of first areas and a multitude of second areas arranged alternately).

[0043] In some embodiments of the present invention, there is no shallow trench isolation structure between the doping regions SD in the active region AA.

[0044] The invention also provides a high-frequency circuit layout pattern comprising a substrate Sub, wherein an active region AA is defined on the substrate Sub, a plurality of gate structures G are arranged in the active region AA, each gate structure G being arranged parallel along a first direction (for example, the X direction), and a plurality of doped regions SD are arranged in the active region AA, with each doped region SD being arranged on both sides of each gate structure G in the substrate Sub, wherein a plurality of gate structures G and a plurality of doped regions SD contained in the active region AA form a first amplifier CS and a second amplifier CG, wherein a drain CS-D of the first amplifier CS and a source CG-S of the second amplifier CG are connected to each other.and the drain CS-D of the first amplifier CS and the source CG-S of the second amplifier CG both lie in a common doping region SD3.

[0045] In some embodiments of the present invention, a plurality of doping regions SD are arranged parallel to each other along a first direction (X-direction), and a plurality of doping regions SD and a plurality of gate structures G are arranged alternately along the first direction.

[0046] In some embodiments of the present invention, viewed from above, the gate structures G and the doping regions SD are all long strips, and the long sides of the long strips all extend along a second direction (for example, the Y direction), wherein the second direction (Y direction) and the first direction (X direction) are perpendicular to each other.

[0047] In some embodiments of the present invention, the gate structures G comprise a first gate structure G1 and a second gate structure G2, and the doped regions SD contained in the active area AA comprise a first source doping region S1, a first drain doping region D1, a second source doping region S2, and a second drain doping region D2. The first gate structure G1, the first source doping region S1, and the first drain doping region D1 form a first amplifier CS, and the second gate structure G2, the second source doping region S2, and the second drain doping region D2 form a second amplifier CG, wherein the first drain doping region D1 and the second source doping region S2 contain the same doping region among a plurality of doping regions SD, and the same doping region is defined as a common doping region SD3.

[0048] In some embodiments of the present invention, the common doping area SD3 is arranged in the top view between the first gate structure G1 and the second gate structure G2, and the common doping area SD3 is arranged adjacent to the first gate structure G1 and the second gate structure G2.

[0049] In some embodiments of the present invention, the common drain doping area SD3 is arranged on one side of the first gate G1, the first source doping area S1 is arranged on the other side of the first gate G1 relative to the common doping area SD3, the common drain doping area SD3 is arranged on one side of the second gate G2, and the second drain doping area D2 is arranged on the other side of the second gate G2 relative to the common drain doping area SD3.

[0050] In some embodiments of the present invention, the first amplifier CS comprises a common source amplifier and the second amplifier CG comprises a common gate amplifier, and the first amplifier CS and the second amplifier CG are connected in series to form a cascade amplifier.

[0051] In some embodiments of the present invention, the active area AA further comprises a plurality of common source amplifiers and a plurality of common gate amplifiers, wherein each area comprising the common source amplifier CS is defined as a first area, and each area comprising the common gate amplifier CG is defined as a second area.

[0052] In some embodiments of the present invention, at least one of the plurality of first regions is arranged between two adjacent second regions, and at least one of the plurality of second regions is arranged between two adjacent first regions (for example, in Figure (d) of Fig. 3 (a multitude of first areas and a multitude of second areas arranged alternately).

[0053] In some embodiments of the present invention, there is no shallow trench isolation structure between the doping regions SD in the active region AA.

[0054] In summary, the present invention is characterized in that, to save space and reduce the influence of line impedance when creating the layout pattern of a two-stage amplifier, the two amplifiers are arranged in the same active area, so that both amplifiers contained in the two-stage amplifier can share a portion of the doping area; that is, there is no shallow trench insulation between the areas in which the two amplifiers are arranged. Within the framework of the concept according to the invention, the overall size can be effectively reduced, and the efficiency of the amplifier can also be improved, since the influence of line impedance is reduced.

[0055] The person skilled in the art will readily recognize that numerous modified examples and changes to the apparatus and the method can be implemented while maintaining the teaching of the invention. Accordingly, the foregoing disclosure should be considered limited only by the boundaries and objectives of the appended claims.

Claims

[1] Semiconductor layout patterns, including: a substrate on which an active area is defined; a multitude of gate structures arranged in the active area, wherein the gate structures are arranged parallel to each other along a first direction; a multitude of doping regions arranged in the active area, with each doping region located in the substrate on one of the two sides of each gate structure; wherein the gate structures contained in the active area comprise a first gate structure and a second gate structure, and the doping regions contained in the active area comprise a first source doping region, a first drain doping region, a second source doping region and a second drain doping region, wherein the first gate structure, the first source doping region and the first drain doping region form a first amplifier, the second gate structure, the second source doping region and the second drain doping region form a second amplifier, and the first drain doping region and the second source doping region contain an equal doping region among the plurality of doping regions, and the equal doping region is defined as a common doping region. [2] Semiconductor layout pattern according to claim 1, wherein the plurality of doping regions are arranged parallel to each other along the first direction and the plurality of doping regions and the plurality of gate structures are arranged alternately along the first direction. [3] Semiconductor layout pattern according to claim 1, wherein, viewed from above, the plurality of gate structures and the plurality of doping regions are both long strips and the long sides of the long strips extend along a second direction, the second direction being perpendicular to the first direction. [4] Semiconductor layout pattern according to claim 1, wherein the common doping area is arranged between the first gate structure and the second gate structure and the common doping area is arranged adjacent to the first gate structure and the second gate structure in the top view. [5] Semiconductor layout pattern according to claim 4, wherein the common doping region is arranged on one side of the first gate, the first source doping region is arranged on the other side of the first gate relative to the common doping region, the common doping region is arranged on one side of the second gate and the second drain doping region is arranged on the other side of the second gate relative to the common doping region. [6] Semiconductor layout pattern according to claim 1, wherein the first amplifier comprises a common source amplifier and the second amplifier comprises a common gate amplifier, and the first amplifier and the second amplifier are connected in series to form a cascade amplifier. [7] Semiconductor layout pattern according to claim 6, wherein the first gate structure is connected to a voltage source VG1 and the second drain doping area is connected to an output signal Vout. [8] Semiconductor layout pattern according to claim 1, wherein the active area further comprises a plurality of common source amplifiers and a plurality of common gate amplifiers, wherein each region containing the common source amplifiers is defined as a first region and each region containing the common gate amplifiers is defined as a second region. [9] Semiconductor layout pattern according to claim 8, wherein at least one of the plurality of first regions is arranged between two adjacent second regions, and at least one of the plurality of second regions is arranged between two adjacent first regions. [10] Semiconductor layout pattern according to claim 1, wherein a flat trench isolation structure between the doping regions in the active region is not included. [11] High-frequency (RF) circuit layout pattern, comprising: a substrate on which an active area is defined; a multitude of gate structures arranged in the active area, wherein the gate structures are arranged parallel to each other along a first direction; a multitude of doping regions arranged in the active area, with each doping region located in the substrate on both sides of each gate structure; wherein the multitude of gate structures and the multitude of doping regions contained in the active area form a first amplifier and a second amplifier, wherein a drain of the first amplifier and a source of the second amplifier are connected together and both the drain of the first amplifier and the source of the second amplifier are arranged in a common doping region. [12] High-frequency circuit layout pattern according to claim 11, wherein the plurality of doping regions are arranged parallel to each other along the first direction and the plurality of doping regions and the plurality of gate structures are arranged alternately along the first direction. [13] High-frequency circuit layout pattern according to claim 11, wherein, viewed from above, the plurality of gate structures and the plurality of doping regions are all long strips, and the long sides of the long strips extend along a second direction, the second direction being perpendicular to the first direction. [14] High-frequency circuit layout pattern according to claim 11, wherein the plurality of gate structures comprises a first gate structure and a second gate structure, and the plurality of doping regions contained in the active area comprises a first source doping region, a first drain doping region, a second source doping region and a second drain doping region, wherein the first gate structure, the first source doping region and the first drain doping region form the first amplifier, the second gate structure, the second source doping region and the second drain doping region form the second amplifier, and the first drain doping region and the second source doping region contain the same doping region among the plurality of doping regions, and the same doping region is defined as the common doping region. [15] High-frequency circuit layout pattern according to claim 14, wherein, viewed from above, the common doping area is arranged between the first gate structure and the second gate structure and the common doping area is arranged adjacent to the first gate structure and the second gate structure. [16] High-frequency circuit layout pattern according to claim 15, wherein the common doping area is located on one side of the first gate, the first source doping area is located on the other side of the first gate relative to the common doping area, the common doping area is located on one side of the second gate and the second drain doping area is located on the other side of the second gate relative to the common doping area. [17] High-frequency circuit layout pattern according to claim 11, wherein the first amplifier comprises a common source amplifier and the second amplifier comprises a common gate amplifier and the first amplifier and the second amplifier are connected in series to form a cascade amplifier. [18] High-frequency circuit layout pattern according to claim 11, wherein the active area further comprises a plurality of common source amplifiers and a plurality of common gate amplifiers, wherein each area containing the common source amplifiers is defined as a first area and each area containing the common gate amplifiers is defined as a second area. [19] High-frequency circuit layout pattern according to claim 18, wherein at least one of the plurality of first areas is arranged between two adjacent second areas and at least one of the plurality of second areas is arranged between two adjacent first areas. [20] High-frequency circuit layout pattern according to claim 11, wherein a shallow trench isolation structure between the doping areas in the active area is not included.

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