System-on-a-chip in loop operation for simulation in a closed loop of a control system

Abstract

System-on-Chip-in-the-Loop (SoCIL) simulation is used to simulate a closed-loop control system comprising a system-on-chip (SoC) field-programmable gate array (FPGA) board. The SoC FPGA board includes a target controller, which is an electronic control unit (ECU). The target controller includes one or more target controller soft processors. The SoC FPGA includes a real-time computer, which is a general-purpose computer. The real-time computer includes one or more real-time soft processors. The SoC FPGA includes one or more high-frequency simulation modules, which operate at a clock speed in the megahertz range, and one or more physical high-frequency equipment models.The one or more target control soft processors of the target control, the one or more real-time soft processors of the real-time computer, and the one or more physical high-frequency plant models of the one or more high-frequency simulation modules are in electronic communication with each other via an on-chip communication bus protocol.

Description

INTRODUCTION

[0001] The present disclosure relates to a system-on-chip-in-the-loop (SoCIL) for simulation in a closed loop of a control system. In particular, the SoCIL is implemented on a system-on-chip (SoC) field-programmable gate array (FPGA) board comprising a plurality of software processors.

[0002] Traditionally, real-time simulation systems comprise an embedded controller with its own hardware and software architecture, combined with a software-based representation of the physical plant implemented by a general-purpose computer. The embedded controller and the general-purpose computer implementing the physical plant are integrated through hard-wired connections known as hardware-in-the-loop (HIL). The term "in-the-loop" means that parts of the software environment, such as the physical plant or hardware, are simulated. While hardware-in-the-loop is efficient for testing control software interactions with hardware, it can present challenges in terms of integration and maintenance.

[0003] The original goal of hardware-in-the-loop (HID) was to test real-time hardware interactions without the need for a physical system. Understandably, HID is extremely popular. However, not all software changes need to be verified through real-time simulations. Consequently, in many cases, HID is used for applications for which it was not originally intended. Efforts have been made to replace HID systems with other, less complex virtual testing approaches. However, these less complex virtual approaches can face challenges such as accuracy, performance, and software reusability when attempting to integrate the virtual objects of each component within a system.For example, a virtual hardware-in-the-loop system involves creating software-based emulations of hardware components and is referred to as a virtual electronic control unit (ECU). However, virtual electronic control units suffer from performance limitations when used in real-time applications.

[0004] Virtual hardware-in-the-loop systems also tend to have significantly slower execution times, and lack the necessary hardware functionality for real-time testing applications.

[0005] Software-in-the-loop testing refers to testing embedded software, either with or without an environment model, using a general-purpose computer and not the hardware associated with an ECU. Software-in-the-loop simulations focus on evaluating software functionality with a limited hardware interface. Widely used in automotive testing, software-in-the-loop allows software to be tested before the hardware prototyping phase begins, significantly accelerating the development cycle.

[0006] While current real-time simulation systems thus achieve their intended purpose, there is a need in engineering for an in-the-loop simulation approach. DESCRIPTION

[0007] According to several aspects, a system-on-a-chip in-loop (SoCIL) for closed-loop simulation of a control system is disclosed. The SoCIL comprises a system-on-a-chip (SoC) field-programmable gate array (FPGA) board. The SoC FPGA board includes a target controller, which is an electronic control unit (ECU), wherein the target controller comprises one or more target controller soft processors. The SoC FPGA board includes a real-time computer, which is a general-purpose computer, wherein the real-time computer comprises one or more real-time soft processors. The SoC FPGA board includes one or more high-frequency simulation modules, comprising a clock speed with a frequency in the megahertz range and one or more physical high-frequency plant models.The one or more target control soft processors of the target control, the one or more real-time soft processors of the real-time computer, and the one or more physical high-frequency plant models of the one or more high-frequency simulation modules are in electronic communication with each other via an on-chip communication bus protocol.

[0008] In another aspect, the on-chip communication bus protocol is based on the Advanced Microcontroller Bus Architecture (AMBA) specification.

[0009] In yet another aspect, the on-chip communication bus protocol is one of the following: the Advanced eXtensible Interface (AXI) bus protocol, the Advanced High Performance Bus (AHB) protocol, the Advanced Peripheral Bus (APB) protocol, the AXI Coherence Extensions (ACE), and the Coherent Hub Interface (CHI).

[0010] In one aspect, the one or more high-frequency simulation modules include a basic step size that is measured in microseconds.

[0011] In another aspect, at least one of the one or more physical high-frequency system models of the one or more high-frequency simulation modules represents a vehicle system.

[0012] In yet another aspect, the target control is implemented based on a 32-bit Reduced Instruction Set Computer (RISC) architecture.

[0013] In one aspect, the one or more target control soft processors execute one of the following: a specific real-time operating system and bare-metal code.

[0014] In another aspect, one or more target control software processors implement a Board Support Package (BSP) that runs a Linux distribution operating system.

[0015] In yet another aspect, the real-time computer includes a simulator that runs one or more guest applications.

[0016] In one aspect, the one or more guest applications of the real-time computer each represent a physical plant model.

[0017] In another aspect, the physical plant model of the real-time computer represents a vehicle system.

[0018] In yet another aspect, the target control executes one or more guest applications, each representing an algorithm that controls the one or more guest applications of the real-time computer.

[0019] In one aspect, the one or more physical high-frequency system models of the high-frequency simulation modules are expressed in a hardware description language (Hardware Description Language - HDL).

[0020] In another aspect, a SoCIL for simulation in a closed loop of a control system is disclosed. The SoCIL comprises a SoC-FPGA board. The SoC-FPGA board includes a target controller, which is an electronic control unit (ECU), and the target controller includes one or more target controller soft processors. The SoC-FPGA board also includes a real-time computer, which is a general-purpose computer, and the real-time computer includes one or more real-time soft processors.The SoC-FPGA board comprises one or more high-frequency simulation modules, which include a clock speed with a frequency in the megahertz range, and one or more physical high-frequency plant models, wherein the one or more high-frequency simulation modules include a basic step size measured in microseconds, and the one or more target control soft processors of the target control, the one or more real-time soft processors of the real-time computer, and the one or more physical high-frequency plant models of the one or more high-frequency simulation modules are in electronic communication with each other through an on-chip communication bus protocol based on the Advanced Microcontroller Bus Architecture (AMBA) specification.

[0021] In another aspect, the on-chip communication bus protocol is one of the following: the Advanced eXtensible Interface (AXI) bus protocol, the Advanced High-Performance Bus (AHB) protocol, the Advanced Peripheral Bus (APB) protocol, the AXI Coherence Extensions (ACE), and the Coherent Hub Interface (CHI).

[0022] In yet another aspect, at least one of the one or more physical high-frequency system models of the one or more high-frequency simulation modules represents a vehicle system.

[0023] In one aspect, the real-time computer includes a simulator that runs one or more guest applications.

[0024] In another aspect, one or more guest applications of the real-time computer each represent a physical plant model.

[0025] In yet another aspect, the target control executes one or more guest applications, each representing an algorithm that controls the one or more guest applications of the real-time computer.

[0026] In one aspect, a System-on-a-Computer-Integrated Logic (SoCIL) for closed-loop simulation of a vehicle control system is disclosed. The SoCIL comprises a SoC-FPGA board. The SoC-FPGA board includes a target controller, which is an electronic control unit (ECU), and the target controller comprises one or more target controller soft processors. The SoC-FPGA board includes a real-time computer, which is a general-purpose computer, and the real-time computer comprises one or more real-time soft processors. The SoC-FPGA board also includes one or more high-frequency simulation modules, which include a clock speed with a frequency in the megahertz range, and one or more physical high-frequency plant models, each representing a vehicle system. The one or more high-frequency simulation modules include a basic step size, which is measured in microseconds.The one or more target control soft processors of the target control, the one or more real-time soft processors of the real-time computer, and the one or more physical high-frequency plant models of the one or more high-frequency simulation modules are in electronic communication with each other through an on-chip communication bus protocol based on the Advanced Microcontroller Bus Architecture (AMBA) specification.

[0027] Further areas of application will become apparent from the description provided herein. It is understood that the description and specific examples serve only for illustrative purposes and are not intended to limit the scope of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein serve only for illustrative purposes and are not intended to limit the scope of the present disclosure in any way. The figure illustrates a schematic diagram of the disclosed system-on-a-chip-in-the-loop (SoCIL) according to an exemplary embodiment. DETAILED DESCRIPTION

[0029] The following description is merely exemplary and is not intended to limit the present disclosure, application or uses.

[0030] With reference to the figure, a schematic diagram of the disclosed system-on-a-chip-in-a-loop (SoCIL) 10 for simulation in a closed loop of a control system for a vehicle 12 is illustrated. The control system can represent any type of control system comprising one or more physical systems that the SoCIL 10 simulates, such as an engine control system or one or more electric motors that provide propulsion power for the vehicle 12. It is understood that the vehicle 12 can be any type of vehicle, such as, but not limited to, a sedan, a truck, an off-road vehicle, a van, or a motorhome. It is also understood that, although the figure illustrates the SoCIL 10 as part of a vehicle, such as an in-vehicle application for a software-defined vehicle (SDV), the SoCIL 10 can also be used in a variety of other applications.For example, the SoCIL 10 can be used in a different embodiment during the design and development of the vehicle 12. Furthermore, it is understood that the SoCIL 10 is not limited to vehicles and can also be used in applications such as, for example, aerospace and aviation applications. By way of example only, the SoCIL 10 can be used in avionics systems, flight management and navigation systems, flight control systems, aircraft engine control systems, and aviation environment control systems.

[0031] The SoCIL 10 comprises a system-on-a-chip (SoC) field-programmable gate array (FPGA) board 14. It is understood that the SoCIL 10 refers to a closed-loop control system integrated into an SoC. The SoC FPGA board 14 comprises a target controller 20, a real-time computer 22, and one or more high-frequency simulation modules 24. As explained below, the target controller 20 and the real-time computer 22 each comprise soft processors 36 and 46, respectively, implemented based on a soft processor architecture that enables the execution of bare-metal code in their hardware implementations. A soft processor architecture refers to a customizable microcontroller device that executes a hardware description language (HDL).When deployed on hardware at the gate level, the soft processor architecture functions as a real microcontroller that can be programmed as a microcontroller with a fixed architecture.

[0032] The target controller 20 is a production target controller, also referred to as an electronic control unit (ECU). In one embodiment, the target controller 20 is implemented based on a 32-bit reduced instruction set computer (RISC) architecture. The target controller 20 executes one or more user-level or guest applications 30. The target controller 20 also includes one or more lower-level software layers 32, one or more intermediate software layers 34, and one or more target controller soft processors 36.

[0033] The one or more guest applications 30 of the target controller 20 each represent an algorithm that controls one or more guest applications 40 executed by the real-time computer 22. An example of a programming language that can be used for the one or more guest applications 30 of the target controller 20 is the C programming language. The one or more guest applications 30 of the target controller 20 can be any algorithm for interacting with either the guest applications 40 executed by the real-time computer 22 or with plant models or physical devices that are part of the SoC-FPGA board 14, such as a diagnostic service algorithm, a library processing algorithm, and filters.

[0034] The one or more lower-level software layers 32 of the target controller 20 comprise one or more lower-level software layers, such as, among others, a board support package (BSP) layer, a basic software layer (BSW), and a runtime environment (RTE). The one or more intermediate-level software layers 34 of the target controller 20 comprise one or more intermediate-level software layers, such as, among others, a microcontroller abstraction layer. It is understood that the microcontroller abstraction layer is implemented for automotive or vehicle-based control applications.

[0035] The one or more target control soft processors 36 of the target controller 20 implement an on-chip communication bus protocol to communicate with one or more peripheral devices located on the SoC FPGA board 14. Specifically, the one or more target control soft processors 36 of the target controller 20 communicate with the one or more real-time soft processors 46 of the real-time computer 22 and one or more physical high-frequency equipment models 52 of the high-frequency simulation modules 24 based on an on-chip communication bus protocol. In one embodiment, the on-chip communication bus protocol is based on the Advanced Microcontroller Bus Architecture (AMBA) specification.Some examples of on-chip communication bus protocols based on the AMBA specification include the Advanced eXtensible Interface (AXI) bus protocol, the Advanced High Performance Bus (AHB) protocol, the Advanced Peripheral Bus (APB) protocol, the AXI Coherence Extensions (ACE), and the Coherent Hub Interface (CHI).

[0036] The one or more target control soft processors 36 of the target controller 20 execute either a specific real-time operating system or bare-metal code. Alternatively, in another embodiment, the one or more target control soft processors 36 implement a board support package (BSP) adapted to run a Linux distribution operating system for more specific applications where a developer may need to access and configure the hardware of the entire SoC FPGA board 14, such as telecommunications equipment, aerospace systems, and defense systems.

[0037] The real-time computer 22 is a general-purpose computer. In one embodiment, the real-time computer 22 comprises a 64-bit architecture and runs a real-time Linux operating system. The real-time computer 22 runs one or more guest applications 40. The real-time computer 22 includes a simulator 42, a host real-time operating system (RTOS) kernel 44, and one or more real-time soft processors 46. The one or more guest applications 40 of the real-time computer 22 each represent a physical plant model implemented as a mathematical model expressed in a programming language, such as the C programming language. The physical plant model represents a physical system that simulates the SoCIL 10.For example, in one embodiment the physical plant model represents a vehicle system, such as an engine, one or more electric motors to provide drive power for the vehicle 12.

[0038] The simulator 42 of the real-time computer 22 is a simulation engine that runs the one or more guest applications 40. The RTOS kernel 44 of the real-time computer 22 manages the system resources of the real-time computer 22, such as memory and devices. The one or more real-time switch processors 46 of the real-time computer 22 implement the on-chip communication bus protocol to communicate with one or more peripheral devices located on the SoC FPGA board 14, the one or more target control switch processors 36 of the target controller 20, and the one or more physical high-frequency equipment models 52 of the one or more high-frequency simulation modules 24.

[0039] The one or more high-frequency simulation modules 24 comprise the one or more physical high-frequency equipment models 52 and one or more peripheral devices 54. The one or more high-frequency simulation modules 24 comprise a clock speed with a frequency in the megahertz range and comprise a basic step size measured in microseconds.

[0040] The one or more physical high-frequency plant models 52 of the high-frequency simulation modules 24 each represent a physical plant model implemented as a mathematical model expressed in a hardware description language, such as a very high-speed integrated circuit hardware description language (VHDL) or a hardware description language based on the Institute of Electrical and Electronics Engineers (IEEE) Standard 1364 (VERILOG®). As mentioned above, the physical plant model represents a physical system that simulates the SoCIL 10. For example, in one embodiment, the physical plant model represents a vehicle system.

[0041] The one or more peripheral devices 54 of the one or more high-frequency simulation modules 24 implement the on-chip communication bus protocol to communicate between the one or more physical high-frequency equipment models 52 and one or more peripheral devices located on the SoC FPGA board 14, the one or more target control soft processors 36 of the target controller 20, and the one or more real-time soft processors 46 of the real-time computer 22. In other words, the one or more target control soft processors 36 of the target controller 20, the one or more real-time soft processors 46 of the real-time computer 22, and the one or more physical high-frequency equipment models 52 of the one or more high-frequency simulation modules 24 are in electronic communication with each other through the on-chip communication bus protocol.

[0042] With general reference to the figure, the disclosed SoCIL provides various technical effects and advantages. In particular, the disclosed SoCIL comprises a fully integrated hardware design that enables real-time simulations on a single chip while maintaining the independence and modularity of the SoCIL's internal components. The SoCIL also provides an approach for closed-loop simulation of multi-domain control systems while addressing problems such as performance, accuracy, and reusability that commonly arise in current real-time simulation systems, such as virtual hardware-in-the-loop. In particular, the SoCIL solves the hardware accuracy problem by transitioning from software-based to hardware-based emulations.Furthermore, the reusability problem is addressed by using a soft processor architecture as part of the SoCIL, which enables the execution of bare-metal code in the hardware implementation of the SoCIL.

[0043] The modules can refer to or be part of an electronic circuit, a combinational logic circuit, a field-programmable gate array (FPGA), a processor (shared, dedicated, or group) that executes code, or a combination of some or all of the above, such as in a system-on-a-chip. Additionally, the modules can be microprocessor-based, such as a computer with at least one processor, memory (RAM and / or ROM), and associated input and output buses. The processor can operate under the control of an operating system residing in memory. The operating system can manage computer resources so that computer program code, embodied as one or more computer software applications, such as an application residing in memory, can contain instructions to be executed by the processor.In an alternative embodiment, the processor can execute the application directly, in which case the operating system can be omitted.

[0044] The description of the present revelation is merely exemplary, and variations that do not deviate from the core of the present revelation are to be considered within the scope of the present revelation. Such variations should not be regarded as a deviation from the spirit and scope of the present revelation.

Claims

[1] System-on-Chip-in-the-Loop (SoCIL) for simulation in a closed loop of a control system, wherein the SoCIL comprises: a system-on-a-chip (SoC) field-programmable gate array (FPGA) board, wherein the SoC FPGA board comprises: a target control unit which is an electronic control unit (ECU) wherein the target control unit comprises one or more target control soft processors; a real-time computer that is a general-purpose computer, wherein the real-time computer comprises one or more real-time soft processors; and one or more high-frequency simulation modules comprising a clock speed with a frequency in the megahertz range and one or more physical high-frequency equipment models, wherein the one or more target control soft processors of the target control, the one or more real-time soft processors of the real-time computer and the one or more physical high-frequency equipment models of the one or more high-frequency simulation modules are in electronic communication with each other by means of an on-chip communication bus protocol. [2] SoCIL according to claim 1, wherein the on-chip communication bus protocol is based on the Advanced Microcontroller Bus Architecture (AMBA) specification. [3] SoCIL according to claim 1, wherein the on-chip communication bus protocol is one of the following: the Advanced eXtensible Interface (AXI) bus protocol, the Advanced High Performance Bus (AHB) protocol, the Advanced Peripheral Bus (APB) protocol, the AXI Coherence Extensions (ACE) and the Coherent Hub Interface (CHI). [4] SoCIL according to claim 1, wherein the one or more high-frequency simulation modules comprise a basic step size measured in microseconds. [5] SoCIL according to claim 1, wherein at least one of the one or more physical high-frequency system models of the one or more high-frequency simulation modules represents a vehicle system. [6] SoCIL according to claim 1, wherein the target control is implemented based on a 32-bit Reduced Instruction Set Computer (RISC) architecture. [7] SoCIL according to claim 1, wherein one or more target control soft processors execute one of the following: a specific real-time operating system and bare-metal code. [8] SoCIL according to claim 1, wherein one or more target control software processors implement a board support package (BSP) that runs a Linux distribution operating system. [9] SoCIL according to claim 1, wherein the real-time computer comprises a simulator that runs one or more guest applications. [10] SoCIL according to claim 9, wherein the one or more guest applications of the real-time computer each represent a physical plant model.

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