ELECTRONIC DEVICE

Abstract

A plurality of wirings included in a wiring substrate includes: a plurality of first wirings for propagating a first clock signal and a first chip select signal to first and second memory devices mounted on a front side; and a plurality of second wirings for propagating a second clock signal and a second chip select signal to third and fourth memory devices mounted on a back side. The plurality of first wirings are provided in a wiring layer of a plurality of wiring layers that is closer to the front side, and the plurality of second wirings are provided in a wiring layer of the wiring layers that is closer to the back side.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The disclosure of Japanese Patent Application No. 2023-221744, filed on December 27, 2023, including the specification, drawings, and abstract, is hereby incorporated by reference in its entirety. BACKGROUND

[0002] The present invention relates to an electronic device and relates, for example, to an electronic device comprising a control device and a plurality of storage devices mounted on a wiring substrate.

[0003] A technique listed below is disclosed.

[0004] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2015-35159

[0005] Patent Document 1 discloses an electronic device capable of mitigating the influence of signal reflections even when branch wirings for a fly-by topology are long. The electronic device includes a mounting substrate on which a plurality of first semiconductor components and a second semiconductor component for controlling the first semiconductor components are mounted. The mounting substrate includes main wiring and branch wirings for electrically connecting the second semiconductor component and the first semiconductor components. Chip resistors are connected in series at the center of the branch wirings leading to the first semiconductor components. SUMMARY

[0006] In recent years, there is a need to downsize electronic devices, in other words, to reduce a mounting area of each device in a wiring substrate. Moreover, especially with higher speed of the electronic device, there is a need to improve a waveform integrity (quality) of each signal propagated in the wiring substrate. As a method for improving the waveform integrity, a method of providing a resistance device for use in attenuating reflected signals is proposed, as described in, for example, Patent Document 1. However, the resistance device increases the mounting area. Therefore, a mechanism for improving the waveform integrity without providing such a resistance device is expected.

[0007] Further objects and novel features will become apparent from the description of this specification and the drawings.

[0008] An electronic device according to an embodiment comprises: a wiring substrate having a first surface, a second surface opposite the first surface, a plurality of wiring layers, and a plurality of wirings; a first memory device and a second memory device mounted on the first surface; a third memory device and a fourth memory device mounted on the second surface; and a control device. The control device is mounted on the first surface, is configured to access each of the first and second memory devices using a common first clock signal and a common first chip select signal, and is configured to access each of the third and fourth memory devices using a common second clock signal and a common second chip select signal.The plurality of wirings includes: a plurality of first wirings through which the common first clock signal and the common first chip select signal are transmitted; and a plurality of second wirings through which the common second clock signal and the common second chip select signal are transmitted. The plurality of first wirings are provided in a wiring layer of the plurality of wiring layers that is closer to the first surface than to the second surface, and the plurality of second wirings are provided in a wiring layer of the plurality of wiring layers that is closer to the second surface than to the first surface.

[0009] The waveform integrity of the signal may be improved by using an electronic device according to one embodiment. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a plan view showing an exemplary schematic configuration of an electronic device according to a first embodiment. Fig. 1B is a plan view showing an exemplary schematic configuration of the electronic device according to the first embodiment. Fig. 2 is a plan view showing an exemplary configuration of an interesting sub-area in Fig. 1A and Fig. 1B shows. Fig. 3 is a circuit diagram illustrating exemplary connections between memory interfaces and memory devices in Fig. 2 shows. Fig. 4A is a cross-sectional view showing an exemplary schematic configuration for clock signals and chip select signals along line AA' of Fig. 2 shows. Fig. 4B is a cross-sectional view showing an exemplary schematic configuration for clock signals and chip select signals along line BB' of Fig. 2 shows. Fig. 5 is a cross-sectional view showing an exemplary schematic configuration for command address signals along the line AA' of Fig. 2 shows. Fig. 6 is an impedance diagram showing an exemplary impedance characteristic of a via portion for signal propagation and an open stub in Fig. 4A and Fig. 4B shows. Fig. Figure 7 is a diagram showing exemplary calculation results of how strongly a quarter length of a wavelength “λ” of a propagating signal depends on a Nyquist frequency. Fig. Figure 8A is a circuit diagram showing an exemplary equivalent configuration for signal propagation paths to rank 1, in Fig. 4A. Fig. Figure 8B is a timing diagram conceptually illustrating a mechanism for canceling reflected signals in Fig. 8A. Fig. 9 is a waveform diagram showing exemplary simulation results targeting a memory device closer to the control device in Fig. 4A, and result from the observation of input waveforms of a chip select signal. Fig. 10 is a waveform diagram showing exemplary simulation results targeting a memory device closer to the control device in Fig. 4A, and a memory device further away therefrom, and result from the observation of input waveforms of a clock signal. Fig. 11A is a cross-sectional view showing a more detailed exemplary configuration along line AA' of Fig. 2 represents. Fig. 11B is a cross-sectional view showing a more detailed exemplary configuration along line BB' of Fig. 2 represents. Fig. 12 is a cross-sectional view showing an expanded exemplary configuration of a configuration of Fig. 4A. Fig. 13 is a cross-sectional view showing an exemplary schematic configuration for clock signals, chip select signals, and command address signals along the line AA' of Fig. 2 in an electronic device according to a second embodiment. Fig. 14 is a table showing combinations to be avoided with “n” and “m” for the wiring length between the control device and a storage device of Fig. 13 shows. Fig. 15A is a diagram for schematically explaining exemplary problems in a typical electronic device. Fig. 15B is a diagram for schematically explaining exemplary problems in a typical electronic device. Fig. 16 is a diagram showing exemplary waveforms of clock signals generated by two memory devices in Fig. 15A must be entered. Fig. 17A is a cross-sectional view showing an exemplary configuration of an electronic device according to a comparative example, different from that of Fig. 4A. Fig. 17B is a cross-sectional view showing an exemplary configuration of the electronic device according to the comparative example, different from that of Fig. 4B. DETAILED DESCRIPTION

[0010] In the embodiments described below, the invention will be described in a plurality of sections or embodiments for the sake of simplicity. However, these sections or embodiments are not irrelevant to each other unless otherwise specified, and one refers to the whole or part of the other as a modification example, detail, or supplementary explanation thereof. Also, in the embodiments described below, when referring to the number of elements (including number of pieces, values, quantity, range, and the like), the number of elements is not limited to a specific number unless otherwise specified or except in the case where the number is obviously fundamentally limited to a specific number. The number greater or smaller than the specified number is also applicable.

[0011] Furthermore, in the embodiments described below, it is obvious that the components (including element steps) are not always indispensable unless otherwise specified or except in the case where the components are obviously indispensable in principle. Similarly, in the embodiments described below, when the shape of the components, their positional relationship, and the like are mentioned, the substantially approximate and similar shapes and the like are included therein unless otherwise specified or except in the case where it is conceivable that they are obviously excluded in principle. The same applies to the numerical value and range described above.

[0012] The embodiments will be described in detail below with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and repeated descriptions thereof will be omitted. Furthermore, the description of the same or similar parts will generally not be repeated unless expressly required in the following embodiments. (First Embodiment)<Overview of the Entire Electronic Device>

[0013] The Fig. 1A and Fig. 1B are plan views each showing an exemplary schematic configuration of an electronic device according to a first embodiment. Fig. 1A and Fig. The electronic device 10 shown in Figure 1B includes a wiring substrate PCB, a plurality of memory devices ME, and a control device CTL. The electronic device 10 is particularly suitable for signal processing devices or information processing devices, such as data centers, network base stations, and game terminals, that require broadband and large-capacity storage.

[0014] The wiring substrate PCB has a front surface (first surface) 20, a back surface (second surface) 21 opposite to the front surface 20, a plurality of wiring layers, and a plurality of wirings. Fig. 1A and Fig. 1B show the exemplary configurations of the front side 20 and the back side 21 of the wiring substrate PCB, respectively. In this specification, the mutually orthogonal directions are assumed to be an X-axis direction, a Y-axis direction, and a Z-axis direction, and planar directions of the wiring substrate PCB are referred to as the X-axis direction and the Y-axis direction, while a thickness direction of the wiring substrate PCB is referred to as the Z-axis direction.

[0015] Each of the memory devices ME is, for example, a DDR5 SDRAM (double data rate 5 synchronous dynamic random access memory) or the like. In this example, 32 memory devices ME are mounted on the front side 20 and the back side 21 of the wiring substrate PCB, respectively. The 32 memory devices ME mounted on the front side 20 are arranged in a form of, for example, two rows by 16 columns along the outer circumference (three sides of the four sides) of the wiring substrate PCB. The 32 memory devices ME mounted on the back side 21 are arranged to face the 32 memory devices ME mounted on the front side 20 in the Z-axis direction.

[0016] The control device CTL is, for example, a system-on-chip (SoC) or the like, which includes various circuit blocks represented by a processor. The control device CTL is mounted on the front side 20 of the wiring substrate PCB and, in this example, is located near the center of the wiring substrate PCB. The control device CTL includes a plurality of memory interfaces for accessing the memory devices ME. In this example, two memory interfaces MIF1 and MIF2 of the memory interfaces are shown.

[0017] Fig. Figure 2 is a plan view showing an exemplary configuration of an interesting sub-area 11 in Fig. 1A and Fig. 1B shows. In Fig. 2, the memory interface MIF1 is connected via a plurality of wirings WR1 in the wiring substrate PCB to two memory devices ME1 and ME2 mounted on the front side 20 of the wiring substrate PCB, and two memory devices ME3 and ME4 mounted on the rear side 21 facing these memory devices. Similarly, the memory interface MIF2 is connected via a plurality of wirings WR2 in the wiring substrate PCB to two memory devices ME5 and ME6 mounted on the front side 20 of the wiring substrate PCB, and to two memory devices ME7 and ME8 mounted on the rear side 21 facing these memory devices.

[0018] The two storage devices ME1 and ME2 are arranged side by side in the X-axis direction. The two storage devices ME5 and ME6 are also arranged side by side in the X-axis direction. The storage device ME1 and the storage device ME5 are arranged side by side in the Y-axis direction in an area closer to the control device CTL. The storage device ME2 and the storage device ME6 are arranged side by side in the Y-axis direction in an area farther from the control device CTL.

[0019] The memory interfaces MIF1 and MIF2 are arranged adjacent to each other in the X-axis direction. The memory interface MIF2 and its external terminal are arranged closer to an interior of the control device CTL than the memory interface MIF1 and its external terminal. In other words, the memory interface MIF1 is arranged closer to the outer periphery of the control device CTL than the memory interface MIF2.

[0020] In particular, sets of memory interfaces MIF1 and MIF2, as in Fig. 2, side by side along the outer circumference of the control device CTL in Fig. 1A. In the example of Fig. 1A, eight sets of memory interfaces MIF1 and MIF2 are arranged. Since the memory interfaces MIF1 and MIF2 are arranged side by side in the X-axis direction rather than in the Y-axis direction as described above, the outer circumference of the control device CTL can be shortened, thereby reducing the size of the control device CTL and, consequently, the electronic device 10.

[0021] Fig. 3 is a circuit diagram showing exemplary connections between the memory interfaces MIF1, MIF2 and the memory devices ME1 to ME8 in Fig. 2. Each of the memory devices ME1 to ME8 mainly outputs / outputs a "k+1"-bit data signal DQ[k:0] in response to input of control signals including a clock signal CK, a chip select signal CS, and an "i+1"-bit command address signal CA[i:0]. Specifically, the clock signal CK consists of a positive-polarity clock signal CK(t) and a negative-polarity clock signal CK(c), which form a differential pair.

[0022] Each of the memory devices ME1, ME2, ME5, and ME6 mounted on the front side 20 of the wiring substrate configures a rank 0 memory device. Each of the memory devices ME3, ME4, ME7, and ME8 mounted on the back side of the wiring substrate configures a rank 1 memory device. The memory interface MIF1 accesses the rank 0 memory devices ME1 and ME2 using a common clock signal CKO and a common chip select signal CS0.

[0023] The memory interface MIF1 accesses the rank-1 memory devices ME3 and ME4 using a common clock signal CK1 and a common chip select signal CS1, which are different from the clock signal CK0 and the chip select signal CS0. Furthermore, the memory interface MIF1 outputs a common command address signal CA to the rank-0 and rank-1 memory devices ME1 to ME4.

[0024] When accessing the memory devices ME1 and ME2 with rank 0, the memory interface MIF1 inputs / outputs the data signal DQ of the memory device ME1 as the low data signal DQ-L and outputs the data signal DQ of the memory device ME2 as the high data signal DQ-U. In contrast, when accessing the memory devices ME3 and ME4 with rank 1, the memory interface MIF1 inputs / outputs the data signal DQ of the memory device ME3 as the low data signal DQ-L and outputs the data signal DQ of the memory device ME4 as the high data signal DQ-U.

[0025] Similar to memory interface MIF1, memory interface MIF2 accesses rank-0 memory devices ME5 and ME6 using a common clock signal CK2 and a common chip select signal CS2. Memory interface MIF2 accesses rank-1 memory devices ME7 and ME8 using a common clock signal CK3 and a common chip select signal CS3. Furthermore, memory interface MIF2 outputs a common command address signal CA to rank-0 and rank-1 memory devices ME5 to ME8.

[0026] When accessing the memory devices ME5 and ME6 with rank 0, the memory interface MIF2 inputs / outputs the data signal DQ of the memory device ME5 as the low data signal DQ-L and inputs / outputs the data signal DQ of the memory device ME6 as the high data signal DQ-U. In contrast, when accessing the memory devices ME7 and ME8 with rank 1, the memory interface MIF2 inputs / outputs the data signal DQ of the memory device ME7 as the low data signal DQ-L and inputs / outputs the data signal DQ of the memory device ME8 as the high data signal DQ-U.

[0027] The clock signal CK0 and the chip select signal CS0 are output simultaneously with the clock signal CK2 and the chip select signal CS2. Similarly, the clock signal CK1 and the chip select signal CS1 are output simultaneously with the clock signal CK3 and the chip select signal CS3. Therefore, in the relationship between the memory interface MIF2 and the memory devices ME5 to ME8, the clock signals CK2, CK3 and the chip select signals CS2, CS3 may be the clock signals CK0, CK1 and the chip select signals CS0, CS1, respectively.

[0028] For example, it is assumed here that the data signal DQ[k:0] consists of eight bits, in other words, one byte. In this case, the control device CTL accesses the memory devices ME with rank 0 in Fig. 1A using the clock signal CK0 and the chip select signal CS0, thereby inputting / outputting the data signals DQ-L and DQ-U of a total of 32 bytes. Similarly, the control device CTL accesses the memory devices ME with rank 1 in Fig. 1B using the clock signal CK1 and the chip select signal CS1, thereby inputting / outputting the data signals DQ-L and DQ-U with a total of 32 bytes. <Schematische Querschnittskonfiguration der elektronischen Vorrichtung>

[0029] Fig. 4A is a cross-sectional view showing an exemplary schematic configuration for clock signals and chip select signals along line AA' of Fig. 2 shows. Fig. 4B is a cross-sectional view showing an exemplary schematic configuration for clock signals and chip select signals along line BB' of Fig. 2. The cross-sectional configuration along line AA' is shown divided into two figures for a clear explanation of the configuration. The same applies to the cross-sectional configuration along line B-B'.

[0030] In Fig. 4A, the control device CTL includes a semiconductor chip CP and a package substrate PKG on which the semiconductor chip CP is mounted. The memory interface MIF1 formed on the semiconductor chip CP is connected to the package substrate PKG via an external terminal of the semiconductor chip CP. The memory interface MIF1 is connected to an external terminal PNc1 of the control device CTL via internal wiring of the package substrate PKG.

[0031] The wiring substrate PCB includes a plurality of wiring layers sequentially stacked in the Z-axis direction through an intervening insulating layer, a wiring formed in each wiring layer, and a plurality of through-via wirings VAt1 to VAt3 and VAb1 to VAb3. In this specification, the through-via wirings are collectively referred to as through-via wirings VA. In a space between the front surface 20 and the back surface 21 of the wiring substrate PCB, the through-via wirings VA penetrate the wiring layers. A plurality of wirings formed in predetermined wiring layers includes a plurality of wirings WR1t and a plurality of wirings WR1b.

[0032] The clock signal CK0 and the chip select signal CSO, which are transmitted from the external terminal PNc1 through the via wiring VAt1, propagate to the memory devices ME1 and ME2 with rank 0 through the wirings WR1t. At this time, the via wiring VAt2 connects the wirings WR1t to an external terminal PNm of the memory device ME1 only of the memory devices ME1 and ME3. The via wiring VAt3 connects the wirings WR1t to an external terminal PNm of the memory device ME2 only of the memory devices ME2 and ME4.

[0033] In contrast, the clock signal CK1 and the chip select signal CS1, transmitted from the external terminal PNc1 via the via wiring VAb1, propagate through the wirings WR1b to the rank-1 memory devices ME3 and ME4. At this time, the via wiring VAb2 connects the wirings WR1b to an external terminal PNm of only the memory device ME3 of the memory devices ME1 and ME3. The via wiring VAb3 connects the wirings WR1b to an external terminal PNm of only the memory device ME4 of the memory devices ME2 and ME4.

[0034] Specifically, the number of wirings WR1t is three to transmit the paired clock signals CK0 and the chip select signal CS0. The same applies to the number of wirings WR1b. Similarly, the external terminals PNc1, the via wirings VAt1 to VAt3, and the via wirings VAb1 to VAb3 are also provided as the same number of signals.

[0035] In contrast, in Fig. 4B, the memory interface MIF2 formed on the semiconductor chip CP is connected to the package substrate PKG via an external terminal of the semiconductor chip CP. Furthermore, the memory interface MIF2 is connected to an external terminal PNc2 of the control device CTL via an internal wiring of the package substrate PKG. The memory interface MIF2 is configured to be closer to an interior of the semiconductor chip CP than the memory interface MIF1 of Fig. 4A. Accordingly, the external terminal PNc2 is arranged so that it is closer to an interior of the control device CTL than the external terminal PNc1 of Fig. 4A.

[0036] The wiring substrate PCB includes a plurality of via wirings VAt4 to VAt6 and VAb4 to VAb6 in addition to the wiring layers and the wirings. A plurality of wirings formed in predetermined wiring layers include a plurality of wirings WR2t and a plurality of wirings WR2b. Through the wirings WR2t, the clock signal CK0 and the chip select signal CSO, which are transmitted from the external terminal PNc2 through the via wiring VAt4, propagate to the memory devices ME5 and ME6 of rank 0. At this time, the via wiring VAt5 connects the wirings WR2t to an external terminal PNm of only the memory device ME5 of the memory devices ME5 and ME7. The through-hole wiring VAt6 connects the wirings WR2t to an external terminal PNm of only the memory device ME6 of the memory devices ME6 and ME8.

[0037] In contrast, through the wirings WR2b, the clock signal CK1 and the chip select signal CS1, which are transmitted from the external terminal PNc2 through the via wiring VAb4, propagate to the memory devices ME7 and ME8 with rank 1. At this time, the via wiring VAb5 connects the wirings WR2b to an external terminal PNm of only the memory device ME7 of the memory devices ME5 and ME7. The via wiring VAb6 connects the wirings WR2b to an external terminal PNm of only the memory device ME8 of the memory devices ME6 and ME8. It should be noted that the specific number of the wirings WR2b and the like is the same as those of Fig. 4A.

[0038] Fig. 5 is a cross-sectional view showing an exemplary schematic configuration for command address signals along the line AA' of Fig. 2. Although not shown, the cross-sectional configuration along line BB' is similar to that of Fig. 5. In Fig. 5, the memory interface MIF1 formed on the semiconductor chip CP is connected to the package substrate PKG via the external terminal of the semiconductor chip CP. Furthermore, the memory interface MIF1 is connected to an external terminal PNc of the control device CTL via an internal wiring of the package substrate PKG. The wiring substrate PCB includes a plurality of via wirings VA1 to VA3 in addition to the wiring layers and the wirings.

[0039] A plurality of wirings formed in predetermined wiring layers includes a plurality of wirings WR1tb. Through the wirings WR1tb, a plurality of command address signals CA transmitted from the external terminal PNc via the via wiring VA1 propagate to the memory devices ME1 to ME4 of ranks 0 and 1. At this time, the via wiring VA2 commonly connects the wirings WR1tb to the external terminals PNm of the memory devices ME1 and ME3. The via wiring VA3 commonly connects the wirings WR1tb to the external terminals PNm of the memory devices ME2 and ME4. Specifically, the number of wirings WR1tb and the like is defined based on the number of command address signals CA. <Problemdetails und Vergleichsbeispiel>

[0040] The Fig. 15A and Fig. 15B are diagrams each provided for schematically explaining exemplary problems in a typical electronic device. Fig. Figure 15A shows simplified components used in the exemplary configuration of Fig. 4A are associated with rank 0. Fig. Figure 15B shows exemplary signal waveforms used in the configuration of Fig. 15A can be transferred.

[0041] For example, an electronic device configuring a next-generation network processor or the like may require a large-capacity broadband memory. As described in Fig. Therefore, as shown in Figure 15A, a wiring WR for transmitting a control signal is branched into two by two via wirings VA, thereby connecting the same wirings WR to the two memory devices ME1 and ME2. This allows the small-bit memory to be handled as if it were a large-bit memory, thus achieving the wider memory bandwidth. Such a system is also called a fly-by system.

[0042] However, by using the fly-by system, a reflected signal SG2, which is reflected at the branch further from the control device CTL, is superimposed with an input signal SG1 into the memory device ME1, which is arranged at the branch closer to the control device CTL, as in Fig. 15A and Fig. 15B. Consequently, the waveform integrity of the input signal "SG1 + SG2" to the memory device ME1 located at the branch closer to the control device CTL is particularly reduced, and there is a risk of an error in accessing the memory device ME1 or the like.

[0043] To achieve the larger capacity memory, memory devices ME with two ranks separated by chip select signals CS can be mounted on both surfaces of the wiring substrate PCB, as shown in Fig. 4A and the like. Such a system is also called a clamshell. However, in newer, more sophisticated systems, the number of wiring layers tends to be large, and the wiring substrate PCB tends to be thick. Accordingly, each length of the via wiring VA is also increased by using the clamshell configuration. Consequently, the magnitude of the reflected signal SG2 may further increase, and the waveform integrity may further decrease.

[0044] Therefore, as in Fig. As shown in Figure 15A, a resistance device Rd, which is an attenuation resistor, may be inserted in series with the wiring near the external terminal PNm of the storage device ME1 located at the nearer branch of the control device CTL. This attenuates the reflected signal SG2 caused at the branch farther from the control device CTL before it is input to the storage device ME1 located at a branch closer to the control device CTL. However, the resistance device Rd attenuates not only the reflected signal SG2 but also the normal input signal SG1. That is, the attenuation of the normal input signal SG1 and the attenuation of the reflected signal SG2 are in a trade-off relationship.

[0045] The attenuation of the normal input signal SG1 means a waste of energy. If the resistance devices Rd, as in Fig. As shown in Figure 15A, as many signals as are provided may increase the mounting area in the PCB wiring substrate, and it may be difficult to downsize the electronic device. Furthermore, the cost of components and the like may increase due to the attached resistance devices Rd. Therefore, it is desirable to improve waveform integrity without providing the resistance device Rd. The via wirings VA cause signal reflection due to impedance mismatch and attenuate the transmission signals as much as the reflection. It is also desirable to reduce signal attenuation as much as possible.

[0046] Fig. 16 is a diagram showing exemplary waveforms of the clock signals CK generated by the two memory devices ME1 and ME2 in Fig. 15A. Another problem is that the signal reflection is repeated at the branch point by using the fly-by system, causing the waveform of the clock signal CK input from the memory device ME1 and the waveform of the clock signal CK input from the memory device ME2 to be asymmetrical with each other. This is because the amount and timing of the combined reflected signals are different between the side closer to the control device CTL and the side farther away from it.

[0047] In Fig. 16, for example, the waveform of the negative polarity clock signal CK(c) input to the memory device ME1 and the waveform of the positive polarity clock signal CK(t) input to the memory device ME2 are desirably the same. In Fig. 16, however, the waveforms are completely different from each other. This leads, for example, to a reduction in operating tolerance.

[0048] Fig. 17A is a cross-sectional view showing an exemplary configuration of an electronic device in a comparative example, which is different from that shown in Fig. 4A differs. Fig. 17B is a cross-sectional view showing an exemplary configuration of the electronic device in the comparative example, which is different from that shown in Fig. 4B differs. Fig. 17A and Fig. 17B show exemplary configurations based on typical considerations. For example, when wiring is drawn from the control device CTL mounted on the front side 20 of the wiring substrate PCB, typically, a wiring drawn from one end of the control device CTL is assigned to a wiring layer closer to the front side, while a wiring drawn from the inside of the control device CTL is assigned to a wiring layer closer to the back side. This allows the wiring to be configured so that the wiring drawn from the end of the control device CTL does not interfere with the wiring drawn from the inside thereof.

[0049] Based on these considerations, if the memory interfaces MIF1 and MIF2 are configured as in Fig. 2, the wirings WR1 drawn from the memory interface MIF1 at the end of the device are assigned to the wiring layer closer to the front. In contrast, the wirings WR2 drawn from the memory interface MIF2 located inside the device are assigned to the wiring layer closer to the back. That is, the wiring layers to be assigned are defined by the positions of the memory interfaces MIF1 and MIF2.

[0050] Accordingly, in the example of Fig. 17A, both the wirings WR1t and the wirings WR1b are assigned to a wiring layer 15 that is closer to the front side. Similar to the case of Fig. 4A, through the wirings WR1t, the clock signal CK0 and the chip select signal CS0 propagate from the memory interface MIF1 to the memory devices ME1 and ME2 with rank 0. Through the wirings WR1b, the clock signal CK1 and the chip select signal CS1 propagate from the memory interface MIF1 to the memory devices ME3 and ME4 with rank 1.

[0051] In contrast, in the example of Fig. 17B, both the wirings WR2t and the wirings WR2b are assigned to a wiring layer 16 that is closer to the rear side. Similar to the case of Fig. 4B, through the wirings WR2t, the clock signal CK0 and the chip select signal CS0 propagate from the memory interface MIF2 to the memory devices ME5 and ME6 with rank 0. Through the wirings WR2b, the clock signal CK1 and the chip select signal CS1 propagate from the memory interface MIF2 to the memory devices ME7 and ME8 with rank 1.

[0052] For example, if the signal paths of the chip select signals CS0 and CS1 in Fig. 17A, the lengths of the via wirings VA along the signal paths are different between the rank 0 access and the rank 1 access. In particular, the via wiring VAt3 for connecting to the rank 0 memory device ME2 includes a via portion SBt1 for signal propagation and an open stub SBo1.

[0053] The signal propagation via section SBt1 is a via section for propagating a signal to a target memory device ME. The signal propagation via section SBt1 consists of a section between the connection point to the wirings WR1t and the front side 20 of the wiring substrate PCB. The open stub SBo1 is a stub with an open end. The open stub SBo1 described here consists of a section between the connection point to the wirings WR1t and the back side 21 of the wiring substrate PCB.

[0054] Similarly, the via wiring VAb3 for connecting to the rank-1 memory device ME4 also includes a via section SBt2 for signal propagation and an open stub SBo2. Unlike the via wiring VAt3, the via section SBt2 for signal propagation consists of a section between the connection point with the wirings WR1b and the back side 21 of the wiring substrate PCB. In contrast, the open stub SBo2 consists of a section between the connection point with the wirings WR1b and the front side 20 of the wiring substrate PCB.

[0055] When accessing rank 0, the length of the via section SBt1 for signal propagation is "h1." In contrast, when accessing rank 1, the length of the via section SBt2 for signal propagation is "h2" longer than "h1." In other words, while the length of the open stub SBo1 is "h2," the length of the open stub SBo2 is "h1" shorter than "h2."

[0056] Also in Fig. 17B, similar to the case of Fig. 17A, the lengths of the via wirings VA along the signal paths are different between rank 0 access and rank 1 access. That is, the length of the via section SBt1 for signal propagation in the via wiring VAt6 for rank 0 access is "h2." In contrast, the length of the via section SBt2 for signal propagation in the via wiring VAt6 for rank 1 access, "h1," is smaller than "h2." The description here is made using the example signal paths of the chip select signals CS0 and CS1. However, the same applies to the signal paths of the clock signals CK0 and CK1.

[0057] As described above, when the lengths of the via wirings VA along the signal paths between rank 0 access and rank 1 access are different, the reflected signal waveforms are as shown in Fig. 15A and Fig. 15B, the operating margin differs between rank 0 access and rank 1 access. As a result, the signals reaching the memory devices ME on the front and back are asymmetrical to each other. This may lead to a decrease in the operating margin at the time of access to the memory device ME. This is because the overall operating margin is defined based on the worse waveform integrity. The decrease in the operating margin may lead to an error at the time of access to the memory device ME.

[0058] The chip select signals CS are particularly important for switching between rank 0 and rank 1, and therefore, operating margin is desirably increased by improving waveform integrity such as signal symmetry. This desirably results in the error being zeroed at the time of access to the memory device ME. Furthermore, the clock signals CK are also important for determining signal timing, and therefore, it is desirable to improve waveform integrity such as signal symmetry. <Detail der elektronischen Vorrichtung (Ausführungsbeispiel)>

[0059] It is advantageous to use the exemplary configurations of the Fig. 4A and Fig. 4B. The exemplary configurations of the Fig. 4A and Fig. 4B differ from the exemplary configurations of the Fig. 17A and Fig. 17B in the following two points. The first difference is that the wirings WR1t, WR1b, WR2t and WR2b for propagating the clock signals CK and the chip select signals CS are Fig. 4A and Fig. 4B the wiring layers by a different method than in Fig. 17A and Fig. 17B. The second difference is that a distance between two storage devices ME that are adjacent to each other in Fig. 4A and Fig. 4B is set to a predetermined value for each rank. <<Verfahren zur Zuordnung zur Verdrahtungsschicht> >

[0060] The first difference is that in the example configuration of Fig. 4A, the wirings WR1t from the memory interface MIF1 to the memory devices ME1 and ME2 with rank 0 are provided in the wiring layer 15, which is closer to the front side of the wiring layers, in other words, in the wiring layer closer to the front side 20 than to the back side 21. In contrast, the wirings WR1b from the memory interface MIF1 to the memory devices ME3 and ME4 with rank 1 are provided in the wiring layer 16, which is closer to the back side of the wiring layers, in other words, in the wiring layer closer to the back side 21 than to the front side 20.

[0061] Similar to the example configuration of Fig. 4B, the wirings WR2t from the memory interface MIF2 to the memory devices ME5 and ME6 with rank 0 are provided in the wiring layer 15, which is closer to the front side. In contrast, the wirings WR2b from the memory interface MIF2 to the memory devices ME7 and ME8 with rank 1 are provided in the wiring layer 16, which is closer to the back side. In this way, in Fig. 4A and Fig. 4B, the wiring layers are determined based on the arrangement not of the memory interfaces MIF1 and MIF2, but of the memory devices ME, in other words based on the rank, unlike in Fig. 17A and Fig. 17B.

[0062] Together with the configuration, the length “h1” of the via section SBt1, SBt2 is required for signal propagation in the Fig. 4A is smaller than the length "h2" of the open stub SBo1, SBo2. Similarly, the length "h1" of the through-hole section SBt1, SBt2 for signal propagation in the Fig. 4B shown through-hole wiring VAt6, VAb6 is smaller than the length “h2” of the open stub SBo1, SBo2.

[0063] That is, in Fig. 4A and Fig. 4B, the signal propagation via sections SBt1 and SBt2 are configured to be short, regardless of whether they access rank 0 or rank 1. In this specification, the signal propagation via sections SBt1 and SBt2 are collectively referred to as the signal propagation via section SBt. The open stubs SBo1 and SBo2 are collectively referred to as the open stub SBo.

[0064] The effects provided by this configuration are to reduce the load capacitance in the signal propagation via section SBt, and consequently, to reduce reflected signals and improve the integrity of the transmitted signals. The clock signals CK and the chip select signals CS are transmitted only to the memory device ME mounted on either the front side 20 or the back side 21. Thus, each of the signal propagation via wirings VA necessarily includes the open stub SBo.

[0065] Fig. 6 is an impedance diagram showing an exemplary impedance characteristic of the via portion SBt for signal propagation and the open stub SBo in the Fig. 4A and Fig. 4B. As shown in the impedance diagram shown in Fig. 6 is a Smith chart, the impedance of the open stub SBo is infinite at a length of zero or zero at a length of one-quarter the wavelength λ of the propagating signal. The longer the open stub SBo or the higher the frequency of the propagating signal, the larger the range of clockwise rotation of the feature point at the outer perimeter of the chart. The impedance decreases accordingly.

[0066] In contrast, if, for example, an input terminal of the memory device ME is assumed to terminate at 50 Ω by on-die termination (ODT), the impedance of the signal propagation via section SBt is 50 Ω at a length of zero. In contrast, if the signal propagation via section SBt has a finite length, the input capacitance of the memory device ME and the coupling capacitance with the wiring substrate PCB act as a parallel connection capacitance, acting as a kind of short stub. The coupling capacitance is increased by increasing the length of the signal propagation via section SBt.Therefore, the feature point of the via section SBt for signal propagation rotates clockwise on the equiconductance circle from the point of 50 Ω by increasing the length of the via section SBt or increasing the frequency of the propagation signal. The impedance decreases accordingly.

[0067] Considering such a property, when the length of the open stub SBo is sufficiently shorter than λ / 4, the relationship of expression (1) per unit length of the via wiring VA is established. In contrast, when the length of the open stub SBo is brought close to λ / 4 by increasing the frequency of the propagation signal, the open stub SBo is transformed into the short stub and quickly has a large capacitance. Consequently, the relationship of expression (1) is reversed to that of expression (2). Capacitive load of SBo <Kapazitive Last von SBt Capacitive load of SBo>Capacitive load of SBt

[0068] The contradictory expressions (1) and (2) mean that if the length of the open stub SBo is sufficiently smaller than λ / 4, the signal reflection can be made smaller in the case of the longer open stub SBo and the shorter via portion SBt for signal propagation, thereby improving the signal transmission characteristic. That is, as can be seen from Fig. As can be seen from Figure 6, when the length of the open stub SBo is sufficiently smaller than λ / 4, the impedance of the open stub SBo is sufficiently higher than that of the via portion SBt for signal propagation. Thus, the reflection characteristic at the branch point is mainly defined by the capacitance characteristic of the via portion SBt for signal propagation. If the via portion SBt for signal propagation is shortened, the impedance can be brought closer to 50 Ω, thereby reducing the reflected signal.

[0069] In this way, it is important to shorten the length of the open stub SBo to at least less than λ / 4, taking into account λ / 4. Fig. Figure 7 is a diagram showing exemplary calculation results of how strongly a quarter of the wavelength λ of the propagation signal depends on a Nyquist frequency. The calculation results are shown under the assumption that the relative permittivity ε r of a dielectric material from which the PCB wiring substrate is made is 4.0. It should be noted that the Nyquist frequency corresponds to the clock frequency in DDR5_SDRAM. For example, the quarter wavelength λ at the highest Nyquist frequency, i.e., 3.6 GHz, applicable to DDR5_SDRAM is about 10.4 mm.

[0070] In contrast, the thickness of the PCB substrate is typically about 1.0 to 4.0 mm. Thus, the length of the open stub SBo at the Nyquist frequency of 3.6 GHz is sufficiently smaller than λ / 4, i.e., 10.4 mm. The quarter wavelength length λ at a Nyquist frequency of 8.0 GHz is 4.7 mm. Even in this case, the length of the open stub SBo is smaller than λ / 4, i.e., 4.7 mm. That is, unless the extremely thick PCB substrate is used, it can be said that expression (1) holds until it almost exceeds a signal propagation speed of about 16 Gbit / s.

[0071] Therefore, it is advantageous to shorten the length of the via section SBt for signal propagation, as shown in the Fig. 4A and Fig. 4B, particularly in the electronic device 10 on which the memory devices ME such as DDR5_SDRAM are mounted. This minimizes the total load capacitance of the via wirings VA, reduces reflected signals, and increases transmitted signals. Consequently, waveform integrity can be improved. Distance between storage devices

[0072] For the second difference, in the exemplary configuration of Fig. 4A, a distance Lm between the memory device ME1 and the memory device ME2 with rank 0 is defined based on a propagation delay time given by Expression (3). That is, the distance Lm is defined based on the wiring length of the wiring WR1, which corresponds to the propagation delay time given by Expression (3). A term "Tck" in Expression (3) is one cycle of the clock signal CK. The distance Lm between the memory device ME3 and the memory device ME4 with rank 1 is also defined based on the propagation delay time given by Expression (3). The exemplary configuration of Fig. 4B is also to that of Fig. 4A similar. Lm=Tck / 2

[0073] More preferably, the distance Lm between the two storage devices ME located next to each other is defined based on the propagation delay time given by expression (4). A term "τva ” in expression (4) is the propagation delay time of the via section SBt for signal propagation and is given by expression (5). A term “ε r " in expression (5) is the relative permittivity of the dielectric material constituting the wiring substrate PCB. A term "c0" is a speed of light in vacuum. It should be noted that the distance Lm between two memory devices ME is also a distance between two via wirings VA through which the same signal propagates, such as a distance between the via wiring VAt2 and the via wiring VAt3 in Fig. 4A. Lm=Tck / 2−τva τva=(length of SBt)×√(εr) / c0

[0074] By applying such a distance, the reflected signals can be canceled as described below. However, in practice, it is not easy to completely cancel the reflected signals. Therefore, it is advantageous to also use the wiring layer mapping method. That is, it is desirable to reduce the reflected signals beforehand through the wiring layer mapping method.

[0075] Fig. Figure 8A is a circuit diagram showing an exemplary equivalent configuration for signal propagation paths to rank 0 in Fig. 4A shows. Fig. Figure 8B is a timing diagram that conceptually illustrates a mechanism for canceling the reflected signals in Fig. 8A shows. In Fig. 8A, a transmission line LN3, which corresponds to the wiring WR1 for transmitting the chip select signal CS, is provided between the two memory devices ME1 and ME2. The propagation delay time of the transmission line LN3 is defined by Expression (3).

[0076] A branch node N1 at one end of the transmission line LN3 is connected to a receiver RV of the memory device ME1 via a transmission line LN1 corresponding to the via portion SBt for signal propagation. Further, the branch node N1 leads to an open end via a transmission line LN2 corresponding to the open stub SBo. Similarly, a branch node N2 at the other end of the transmission line LN3 is connected to a receiver RV of the memory device ME2 via a transmission line LN4 corresponding to the via portion SBt for signal propagation. Further, the branch node N2 leads to an open end via a transmission line LN5 corresponding to the open stub SBo.

[0077] Fig. 8B shows the clock signal CK, the chip select signal CS, and the reflected signals CSr1, CSr2 at the branch node N1, and the chip select signal CS and the reflected signal CSr2 at the branch node N2. The clock signal CK and the chip select signal CS are signals output from the unillustrated control device CTL. The reflected signal CSr1 is a reflected signal of the chip select signal CS reflected at the branch node N1. The reflected signal CSr2 is a reflected signal of the chip select signal CS reflected at the branch node N2. In this example, for simplicity, it is assumed that the phase components of the reflection coefficients at the branch nodes N1 and N2 are zero.

[0078] In Fig. 8B, the reflected signal CSr1 having the same phase as the chip select signal CS is generated at the branch node N1. In contrast, the chip select signal CS passing through the branch node N1 is delayed by "Tck / 2" and reaches the branch node N2. Accordingly, the reflected signal CSr2 is also generated at the branch node N2, similar to the case of the branch node N1. The reflected signal CSr2 is delayed by "Tck / 2" and returns to the branch node N1.

[0079] Once the reflected signal CSr2 reaches the branch node N1, the reflected signal CSr1 with the opposite polarity from the previous one is generated or caused at the branch node N1. The reflected signal CSr1 with the opposite polarity and the reflected signal CSr2 output from the branch node N2 cancel each other out at the branch node N1. In fact, the reflection coefficients at the branch nodes N1 and N2 have a phase component, i.e., a reactance component. Thus, the reflected signal is mainly caused in the rise / fall period of the chip select signal CS and has a different phase than the chip select signal CS. Even in this case, the mechanism becomes similar to that of Fig. 8B as long as the magnitude and phase of the reflection coefficient between the two branch nodes N1 and N2 are the same.

[0080] As described above, when expression (3) is satisfied, the reflection of the chip select signal CS operating in the single data rate (SDR) mode can be canceled at the branch node N1. The SDR mode is an operation mode in which the cycle Tck of the clock signal CK is regarded as a data unit. This can improve the waveform integrity, particularly in the memory device ME1 located at the branch closer to the control device CTL, as shown in Fig. 15A and Fig. 15B.

[0081] Strictly speaking, when the signal is reflected at the via wiring VA, the zero-delay reflection is not caused at the connection point between the wirings and the via wiring VA, and the reflection is caused in such a way that the signal returns to the original direction to a certain extent after entering the via wiring VA. Therefore, strictly speaking, it is necessary to determine the propagation delay time between two memory devices ME by considering the intrusion delay at this time. The intrusion delay is reflected in the propagation delay time τ. va in expression (4) and expression (5).

[0082] The forward and return delay time in the via wiring VA can be approximated to a typical relaxation time by Expression (6), where "e" is used as the base of a natural logarithm. The delay time per unit length in the via wiring VA is generally longer than the delay time of the wiring, and is almost 1.3 to 1.4 times longer than the delay time of the wiring, although this strictly depends on the layout. Therefore, substituting Expression (6) with a conventional signal delay yields Expression (7). (via delay)×(1 / e)×2 (Usual signal delay)×(1.3 to 1.4)×(2 / e)=(Usual signal delay)×(0.96 to 1.03)

[0083] As described above, the round-trip delay time VA in the through-hole wiring is almost equal to the one-way delay time in the ordinary signal wiring. By reflecting the result, Expressions (4) and Expression (5) are provided. When a wiring layer changes, the magnitude of the intrusion delay changes, and thus the degree of reflected signal cancellation effect changes slightly. However, as described later, the propagation delay time for defining the distance Lm has a certain tolerance, for example, 14%, for the delay change. Thus, it does not cause a major problem. Due to this tolerance, the distance Lm given by Expression (3) rather than Expression (4) can be applied. <taktsignal>

[0084] By applying the distance Lm between the memory devices ME and / or applying the allocation method to the wiring layers, the waveform integrity, such as the waveform symmetry of the clock signals CK, can be maintained as shown in Fig. 16. In particular, when expression (3) or expression (4) is set, the round-trip delay time of the clock signal CK between the memory devices ME is equal to the cycle of the clock signal CK. Thus, for example, almost equal amounts of reflected signals are combined at constant timing in the memory devices ME1 and ME2 with rank 0, as shown in Fig. 4A.

[0085] Consequently, the clock signals CK with symmetrical waveforms can be input to the memory devices ME1 and ME2 to which the fly-by system is applied. Further, for example, the wiring layer allocation method is also applied to the memory device ME1 and the memory device ME3 on the front side 20 and the back side 21 to which the clamshell is applied. Fig. 4A, thereby equalizing the reflection coefficients at the branch nodes corresponding to the respective memory devices ME. Therefore, the clock signals CK with almost the same waveforms can be input to the memory devices ME1 and ME3.

[0086] In this respect, for example, the length of the via section SBt1 for signal propagation for propagating the clock signal CK0 must be equal to the length of the via section SBt2 for signal propagation for propagating the clock signal CK1 in Fig. 4A. The same applies to the chip select signals CS. Therefore, the length of the signal propagation via portion SBt1 for propagating the chip select signal CS0 must be equal to the length of the signal propagation via portion SBt2 for propagating the chip select signal CS1. That is, the wirings WR1t and WR1b for propagating the same type of signals can be arranged to be symmetrical to each other with respect to the interlayer wiring in the wiring substrate PCB. <befehlsadresssignal>

[0087] As in Fig. 5 and the like, the wirings WR1tb for propagating the command address signals CA are commonly connected to the memory devices ME1 and ME3 on the front side 20 and the back side 21. This does not result in the effect of reducing the capacitance in the via wirings VA, that is, the effect achieved by the wiring layer allocation method. However, it results in the effect of canceling the reflected signals, that is, the effect provided by the distance Lm between the memory devices ME.

[0088] For example, a "2N mode" is supported for the command address signals CA in DDR5_SDRAM. The 2N mode is an operation mode in which two cycles "2 x Tck" of the clock signal CK are considered as one unit, as shown in Fig. 8B. In the 2N mode, the effect of canceling the reflected signals is slightly different from that in the chip select signals CSm operating in the SDR mode. That is, in the 2N mode, the reflected signals are phase-inverted for every two forward and backward propagations of the command address signal CA between two memory devices ME.

[0089] In the example of Fig. 8B, it should be noted that the reflected signal CSr2 caused by the first cycle of the clock signal CK and the reflected signal CSr1 caused by the third cycle of the clock signal CK are canceled in response to the command address signal CA. Thus, as long as the reflection continues, for any even number of round-trip propagations of the command address signal CA, such as two round-trip propagations, four round-trip propagations, six round-trip propagations, etc., the phase-reversed reflected signals cancel each other out. An odd number of round-trip propagations does not cause cancellation, and therefore, the effect of the reflected signal cancellation is almost half that of the chip select signals CS.

[0090] The error tolerance in the command address signals CA is greater than that of the chip select signals CS and the clock signals CK. Furthermore, since the timing tolerance or the like is increased by using the 2N mode, the occurrence of errors is less likely. Therefore, the required waveform integrity of the command address signals CA can be sufficiently achieved, especially by using the 2N mode. <simulationsergebnis>

[0091] Fig. 9 is a waveform diagram showing exemplary simulation results targeting the memory device ME1 located closer to the control device in Fig. 4A, and resulted from the observation of input waveforms of the chip select signal CS. Assuming a signal propagation speed of 5600 Mbps, the distance Lm between the two memory devices ME1 and ME2 is determined based on Expression (4) and defined as an optimal value. While maintaining the distance Lm between the memory devices ME1 and ME2, the signal propagation speed is changed to 4800 Mbps and 3200 Mbps.

[0092] Accordingly, at a signal propagation speed of 4800 Mbps, the distance Lm between the storage devices ME1 and ME2 was approximately 14.3% smaller than the optimal value. Similarly, at a signal propagation speed of 3200 Mbps, the distance Lm between the storage devices ME1 and ME2 was approximately 42.9% smaller than the optimal value.

[0093] In Fig. 9, at 5600 Mbps and 4800 Mbps, the reflected signals were almost eliminated, and the prominent waveforms of the chip select signal CS, that is, an eye pattern, were provided. In contrast, at 3200 Mbps, the reflected signals were not canceled and clearly observed. However, due to the use of the wiring layer allocation method, the magnitudes of the reflected signals were small. From the simulation results, it can be seen that the outstanding effect can be provided even if the distance Lm between the memory devices ME1 and ME2 changes by about 14%. If the optimal value of the distance Lm is defined based on a certain signal propagation speed as described above, this effect can be made small when the signal propagation speed decreases.

[0094] Fig. 10 is a waveform diagram showing exemplary simulation results targeting the memory device ME1 located closer to the control device CTL in Fig. 4A, and the memory device ME2, which is further away from it, and which results from an observation of the input waveforms of the clock signal CK. The evaluation index in this case is the waveform symmetry, as also in Fig. 16 described.

[0095] At a signal propagation speed of 5600 Mbps, sufficiently symmetrical waveforms were provided in the relationship between the clock signal CK input to the memory device ME1 and the clock signal CK input to the memory device ME2. That is, the waveforms of the negative polarity clock signal CK(c) and the positive polarity clock signal CK(t) input to the memory device ME1 were identical to the waveforms of the positive polarity clock signal CK(t) and the negative polarity clock signal CK(c) input to the memory device ME2.

[0096] Even at a signal propagation speed of 4800 Mbit / s, the waveforms were essentially symmetrical. In contrast, at a signal propagation speed of 3200 Mbit / s, the waveforms were asymmetrical. The simulation results show that the tolerance for the distance Lm between two memory devices ME is approximately 14%, similar to that of the chip select signals CS. <Detaillierte Querschnittskonfiguration der elektronischen Vorrichtung (Ausführungsbeispiel)>

[0097] Fig. 11A is a cross-sectional view showing a detailed exemplary configuration along the line AA' of Fig. 2 shows. As in Fig. 4A, shows Fig. 11A, the wiring WR1 for propagating the chip select signal CS0 to the front side 20 and the wiring WR1 for propagating the clock signal CK0 to the front side 20 are provided in the wiring layer 15, which is closer to the front side 20. In contrast, the wiring WR1 for propagating the chip select signal CS1 to the back side 21 and the wiring WR1 for propagating the clock signal CK1 to the back side 21 are provided in the wiring layer 16, which is closer to the back side 21. The external terminal PNc2 of the memory interface MIF2 is closer to the inside of the control device CTL than the external terminal PNc1 of the memory interface MIF1.

[0098] In this case, for example, both a length of a via portion SBt1k for signal propagation for propagating the clock signal CK0 toward the front side 20 and a length of a via portion SBt2k for signal propagation for propagating the clock signal CK1 toward the back side 21 have the same value "h1k". Likewise, both a length of a via portion SBt1s for signal propagation for propagating the chip select signal CS0 toward the front side 20 and a length of a via portion SBt2s for signal propagation for propagating the chip select signal CS1 toward the back side 21 have the same value "h1s".

[0099] The wiring WR1, through which the command address signal CA[i:0] propagates, is connected to all the memory devices ME1 to ME4 mounted on the front side 20 and the back side 21 in a "wired OR" form. A single wiring WR1 is shown here. However, specifically "i + 1" wirings WR1 are provided. The "i + 1" wirings WR1 may be distributed in the wiring layers accordingly.

[0100] In this example, eight wirings WR1 are provided through which an 8-bit data signal DQ[7:0] propagates to one of the two memory devices ME1 and ME3, and eight wirings WR1 through which an 8-bit data signal DQ[15:8] propagates to one of the two memory devices ME2 and ME4. A total of 16 wirings WR1 through which a data signal DQ[15:0] propagates can also be distributed accordingly in the wiring layers.

[0101] Fig. 11B is a cross-sectional view showing a detailed exemplary configuration along the line BB' of Fig. 2 shows. As in Fig. 4B, the wiring WR2 through which the chip select signal CS0 propagates to the front side 20 and the wiring WR2 through which the clock signal CK0 propagates to the front side 20 are in Fig. 11B in the wiring layer 15, which is closer to the front side 20. In contrast, the wiring WR2, through which the chip select signal CS1 propagates toward the back side 21, and the wiring WR2, through which the clock signal CK1 propagates toward the back side 21, are provided in the wiring layer 16, which is closer to the back side 21. As shown in Fig. 4B, shows Fig. 11B, the wiring WR2 through which the chip select signal CS0 propagates toward the front side 20 and the wiring WR2 through which the clock signal CK0 propagates toward the front side 20 are provided in the wiring layer 15, which is closer to the front side 20. In contrast, the wiring WR2 through which the chip select signal CS1 propagates toward the back side 21 and the wiring WR2 through which the clock signal CK1 propagates toward the back side 21 are provided in the wiring layer 16, which is closer to the back side 21. The lengths of the via portions for signal propagation are similar to those in Fig. 11A.

[0102] Similar to Fig. 11A, the "i + 1" wirings WR2 through which the command address signal CA[i:0] propagates may also be distributed in the wiring layers as appropriate. In this example, eight wirings WR2 are provided through which an 8-bit data signal DQ[23:16] propagates to one of the two memory devices ME5 and ME7, and eight wirings WR2 through which an 8-bit data signal DQ[31:24] propagates to one of the two memory devices ME6 and ME8. A total of 16 wirings WR2 through which a data signal DQ[31:16] propagates may also be distributed in the wiring layers as appropriate. <modifikationsbeispiel>

[0103] Fig. 12 is a cross-sectional view showing an expanded exemplary configuration of the configuration of Fig. 4A shows. In Fig. 12 are storage devices in even number, here four storage devices ME, including the storage devices ME1 and ME2 of Fig. 4A, mounted on the front side 20 of the wiring substrate PCB. The even number of memory devices ME configure rank 0 and are accessed using the common clock signal CK0 and the common chip select signal CS0.

[0104] Similarly, memory devices in even number, here four memory devices ME, including the memory devices ME3 and ME4 of Fig. 4A, mounted on the back side 21 of the wiring substrate PCB. The even number of memory devices ME configure rank 1 and are accessed using the common clock signal CK1 and the common chip select signal CS1.

[0105] The distance Lm between two memory devices ME that are adjacent to each other of the even-numbered memory devices ME mounted on the front side 20 is defined based on the propagation delay time given by Expression (3) or Expression (4). Similarly, the distance Lm between two memory devices ME that are adjacent to each other of the even-numbered memory devices ME mounted on the rear side 21 is also defined based on the propagation delay time given by Expression (3) or Expression (4).

[0106] When the fly-by system is used as described above, the number of branches can be increased to two or more. In this case, the adjacent storage devices ME can be arranged at an equal distance, as shown in Fig. 12. However, the number of memory devices ME mounted on each surface must be an even number. If the memory devices ME are mounted in odd numbers, the reflected signals may be mutually amplified in some combinations of the memory devices ME. It should be noted that the bit widths of the data signals DQ in the memory interfaces MIF1 and MIF2 are generally in units of 2. n Thus, in this respect too, the number of storage devices ME mounted on each surface can generally be an even number. <Hauptwirkung des ersten Ausführungsbeispiels>

[0107] As described above, in the first embodiment, the method for allocating the wirings through which the chip select signals and the clock signals propagate to the wiring layers and the spacing between the memory devices arranged side by side are mainly defined. The electronic device according to the first embodiment uses at least one or preferably both of the two technical elements. This typically improves the waveform integrity of the chip select signals and the clock signals. Furthermore, the waveform integrity can be improved without providing the resistance device as described in Patent Document 1. Consequently, the electronic device can be downsized. (Second embodiment)<Schematische Querschnittskonfiguration der elektronischen Vorrichtung>

[0108] Fig. 13 is a cross-sectional view showing an exemplary schematic configuration for clock signals, chip select signals, and command address signals along the line AA' of Fig. 2 in an electronic device according to a second embodiment. Fig. 13 shows a similar configuration to that of Fig. 4A and Fig. 5. Fig. 13 differs from Fig. 4A and Fig. 5 in that a wiring length LLc between the external terminal PNc for outputting a predetermined control signal from the control device CTL and the via wiring Vat2, VAtb2 for propagating the predetermined control signal to the memory device ME1, ME3 closer to the control device CTL is defined to a predetermined value.

[0109] Specifically, the wiring length LLc is defined based on a propagation delay time given by Expression (8). That is, the wiring length LLc indicates the wiring length of the wiring WR1t, WR1b, WR1tb corresponding to the propagation delay time. A term "Tck" in Expression (8) is one cycle of the clock signal CK. The terms "n" and "m" are integers that are not negative integers. A term "τ va " is the propagation delay time of the via section SBt for signal propagation, which is described in expression (5). It should be noted that the term "τ va " in expression (8) can be zero, similar to the relationship between expression (3) and expression (4). LLc=(Tck / 2)(n+m / 6)−τva

[0110] Fig. 14 is a table showing combinations to be avoided with "n" and "m" for the wiring length LLc between the control device CTL and the memory device ME1 of Fig. 13 shows. In Fig. 14, the priority is set in descending order of influence on waveform integrity. In Fig. 14, the command address signals CA are assumed to be in the 2N operating mode, and limitations in the 2N mode are shown. When the command address signals CA operate in the SDR mode, the rule for the chip select signals CS must be followed.

[0111] In the first embodiment, the reflected signals can affect not only the memory devices ME arranged side by side, but also the control device CTL and the memory devices ME. That is, the via wirings VAt1 and VAtb1 are also closer to the control device CTL, and therefore, the reflected signals from the via wirings VAt1 and VAtb1 affect the reflected signal cancellation effect described in the first embodiment.

[0112] At this time, the reflected signals from the via wirings VAt1 and VAtb1, which are closer to the control device CTL, are caused by the signals reaching the memory devices ME, which are not canceled but remain. Therefore, the signals other than the clock signals CK are less affected. In view of this, the priorities of the signals other than the clock signals CK are Fig. 14 lower.

[0113] In this case, even if there is no branch to the memory devices ME, the waveform integrity of the clock signals CK may be affected by the wiring length, more specifically, by the remainder obtained by dividing the delay by half the clock cycle. Thus, the inventors of this invention investigated the influence of the wiring delay in simulations, taking 1 / 6 of the half cycle "Tck / 2" of the clock signal CK as the resolution. Consequently, as shown in Fig. 14, at "m = 4" a tendency towards a decrease in waveform integrity was observed, particularly a tendency towards a decrease in the high frequency component.

[0114] For example, in Expression (8), "m = 2" and "m = 4" are timings that are symmetrical to each other with respect to "3 / 6" corresponding to the center timing of the clock signal CK, and signifies an equivalent condition. However, in actual clock driver circuits included in the memory interfaces, for example, the rising waveform and falling waveform of the clock signal CK may be asymmetrical to each other, and therefore, either "m = 2" or "m = 4" is a condition that must be avoided. That is, the timing in the clock driver circuits in the simulations happened to be "m = 4."

[0115] By applying the distance Lm between two memory devices ME, as described in the first embodiment, the symmetrical waveforms were provided for the clock signals CK observed at the input terminals of the two memory devices ME. As a result of observing the waveforms of the chip select signals CS operating in the SDR mode during the simulations, only a slight decrease in waveform integrity was observed at "n = 0" and "m = 3", where the wiring length LLc is short, as shown in Fig. 14 shown.

[0116] In contrast, the command address signals CA operate in the 2N mode and therefore have a slightly different result. As described above, the reflected signals in the 2N mode are canceled for every two round-trip transfers between two memory devices ME. It is assumed here that the wiring length LLc is Fig. 13 is twice the distance Lm between two storage devices ME, in other words, a condition of "n = 2" and "m = 0" is assumed in expression (8).

[0117] By using the wiring length LLc, the reflected signal cancellation condition in the command address signal CA is satisfied similarly to that of the chip select signal CS. That is, the reflected signals are further canceled between the control device CTL and the closer memory device ME1 in a unit of one round-trip propagation of the command address signal CA. Consequently, the waveform integrity is slightly improved. Signal shift in a unit of one cycle also leads to the same phenomenon, and therefore the reflected signal cancellation condition is satisfied both at "n = (even number)" and "m = 0." That is, the optimal condition is at "n = (even number)" as well as at "m = 0."

[0118] It is then assumed that the wiring length LLc of Fig. 13 is equal to the distance Lm between two memory devices ME for the command address signal CA, in other words, a condition of "n = 1" as well as "m = 0" is assumed in Expression (8). By using the wiring length LLc, the condition of cancellation of the reflected signals between the control device CTL and the memory device ME2 farther from it is undesirably satisfied. In this case, the fewer reflected signals are propagated from the memory device ME2 farther from the control device CTL to the memory device ME1 closer to it, and therefore the effect of cancellation of the reflected signals in the closer memory device ME1 is insufficient, and the waveform integrity may deteriorate. The same phenomenon also occurs in the case of signal shift in a unit of one cycle.

[0119] As described above, the conditions to be avoided for the command address signal CA are "n = (odd number)" and "m = 0", as shown in Fig. 14. Similar to the chip select signal CS, as a result of observing the waveforms of the command address signal CA during the simulations, the decrease in waveform integrity was observed at a point deviating by half the distance Lm from the optimal conditions "n = (even number)" and "m = 0". Thus, additional conditions to be avoided are "n = (even number)" and "m = 3", as shown in Fig. 14 shown. <Hauptwirkung des zweiten Ausführungsbeispiels>

[0120] Similar effects to various effects of the first embodiment can be provided by using the electronic device according to the second embodiment. In addition, in the second embodiment, the wiring length between the control device and the storage device closer thereto is limited. In this way, the phenomenon of interference of the reflected signal cancellation effect between the storage devices arranged adjacent to each other can be suppressed. Consequently, the waveform integrity can be further improved. Further, since the wiring length of the clock signal CK, which is not directly related to the reflected signal cancellation effect, is limited, the signal waveform integrity can be further improved. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-221744

[0001] JP 2015-35159

[0004] < / modifikationsbeispiel> < / simulationsergebnis> < / befehlsadresssignal> < / taktsignal>

Claims

[1] An electronic device comprising: a wiring substrate having a first surface, a second surface opposite the first surface, a plurality of wiring layers, and a plurality of wirings; a first storage device mounted on the first surface; a second storage device mounted on the first surface; a third storage device mounted on the second surface; a fourth storage device mounted on the second surface; and a control device mounted on the first surface, wherein the control device is configured to access each of the first memory devices and the second memory devices using a common first clock signal and a common first chip select signal, and wherein the control device is configured to access each of the third memory devices and the fourth memory devices using a common second clock signal and a common second chip select signal, wherein the plurality of wirings comprises: a plurality of first wirings through which the common first clock signal and the common first chip select signal are transmitted; and a plurality of second wirings through which the common second clock signal and the common second chip select signal are transmitted, wherein the plurality of first wirings are provided in a wiring layer of the plurality of wiring layers that is closer to the first surface than to the second surface, and wherein the plurality of second wirings are provided in a wiring layer of the plurality of wiring layers that is closer to the second surface than to the first surface. [2] The electronic device according to claim 1, wherein when it is assumed that both a cycle of the common first clock signal and a cycle of the common second clock signal is “Tck” and that both a distance between the first storage device and the second storage device and a distance between the third storage device and the fourth storage device is “Lm”, “Lm” is defined based on a propagation delay time of “Tck / 2”. [3] The electronic device according to claim 1, wherein, in a space between the first surface and the second surface, the wiring substrate comprises a plurality of via wirings each passing through the plurality of wiring layers, wherein the plurality of via wirings comprises: a first via wiring connecting the first wiring to one of the first memory device and the second memory device; and a second via wiring connecting the second wiring to one of the third memory device and the fourth memory device, the first via wiring comprising: a first via portion between a connection point with the first wiring and the first surface; and a first open stub between the connection point with the first wiring and the second surface, wherein the second via wiring comprises: a second via portion between a connection point with the second wiring and the second surface; and a second open stub between the connection point with the second wiring and the first surface, wherein a length of the first via portion is less than a length of the first open stub, and wherein a length of the second via portion is less than a length of the second open stub. [4] The electronic device according to claim 3, wherein, assuming that both a cycle of the common first clock signal and a cycle of the common second clock signal is “Tck”, that both a distance between the first storage device and the second storage device and a distance between the third storage device and the fourth storage device is “Lm”, and that both a propagation delay time of the first via portion and a propagation delay time of the second via portion are “τ va “, “Lm” based on a propagation delay time of “Tck / 2 - τ va “ is defined. [5] The electronic device according to claim 3, wherein, when a wavelength of a propagation signal propagating through both the first wiring and the second wiring is assumed to be "λ", both the length of the first open stub and the length of the second open stub are smaller than "λ / 4". [6] The electronic device according to claim 3, wherein, when the common first clock signal propagates through the first via wiring and the common second clock signal propagates through the second via wiring, the length of the first via section and the length of the second via section are equal, and wherein, when the common first chip select signal propagates through the first via wiring and the common second chip select signal propagates through the second via wiring, the length of the first via portion and the length of the second via portion are the same. [7] The electronic device according to claim 2, wherein the control device is configured to access each of the first memory device, the second memory device, the third memory device, and the fourth memory device using a common command address signal, and wherein the common instruction address signal is set as a 2N mode operating as a unit of two cycles of one of the common first clock signal and the common second clock signal. [8] The electronic device according to claim 7, wherein, in a space between the first surface and the second surface, the wiring substrate comprises a plurality of via wirings each passing through the plurality of wiring layers, wherein the plurality of via wirings includes a third via wiring connecting a wiring through which the common command address signal is transmitted to both the first memory device and the third memory device, and wherein, assuming that each of the cycle of the common first clock signal and the cycle of the common second clock signal is “Tck”, that a wiring length between an external terminal configured to output the common command address signal from the control device and the third via wiring is “LLc”, and that “n” is an even number, “LLc” is defined based on a propagation delay time of “(Tck / 2) x n”. [9] The electronic device according to claim 2, wherein an even number of memory devices, including the first memory device and the second memory device and configured to be accessed using the common first clock signal and the common first chip select signal, are mounted on the first surface, wherein an even number of memory devices, including the third memory device and the fourth memory device and configured to be accessed using the common second clock signal and the common second chip select signal, are mounted on the second surface, and wherein, when it is assumed that a distance between two storage devices arranged side by side of the even-numbered storage devices mounted on the first surface is “Lm”, and that a distance between two storage devices of the even-numbered storage devices mounted on the second surface is “Lm”, “Lm” is defined based on a propagation delay time of “Tck / 2”. [10] The electronic device according to claim 1, further comprising: a fifth storage device and a sixth storage device mounted on the first surface; and a seventh storage device and an eighth storage device mounted on the second surface, wherein the control device comprises: a first memory interface configured to access both the first memory device and the second memory device using the common first clock signal and the common first chip select signal, and configured to access both the third memory device and the fourth memory device using the common second clock signal and the common second chip select signal; and a second memory interface configured to access both the fifth memory device and the sixth memory device using a common third clock signal and a common third chip select signal, and configured to access both the seventh memory device and the eighth memory device using a common fourth clock signal and a common fourth chip select signal, and wherein an external terminal of the second memory interface is arranged closer to an inside of the control device than an external terminal of the first memory interface. [11] An electronic device comprising: a wiring substrate having a first surface, a second surface opposite the first surface, a plurality of wiring layers, and a plurality of wirings; a first storage device mounted on the first surface; a second storage device mounted on the first surface; and a control device mounted on the first surface or the second surface, the control device configured to access both the first memory device and the second memory device using a common clock signal and a common chip select signal, wherein, assuming that each of a cycle of the common first clock signal and a cycle of the common second clock signal is “Tck” and that a distance between the first memory device and the second memory device is “Lm”, “Lm” is defined based on a propagation delay time of “Tck / 2”. [12] The electronic device according to claim 11, wherein the wiring substrate comprises: a plurality of first wirings, which are some of the plurality of wirings and are configured to propagate the common clock signal and the common chip select signal; and a first via wiring provided to pass through the plurality of wiring layers between the first surface and the second surface and configured to connect the first wiring to one of the first memory device and the second memory device, and wherein the first via wiring comprises: a first via portion between a connection point with the first wiring and the first surface; and a first open stub between the connection point with the first wiring and the second surface. [13] The electronic device according to claim 12, wherein when it is assumed that a propagation delay time of the first via portion “τ va “, “Lm” based on a propagation delay time of “Tck / 2 - τ va “ is defined. [14] The electronic device according to claim 12, wherein a length of the first via portion is smaller than a length of the first open stub. [15] The electronic device according to claim 14, wherein, when a wavelength of a propagation signal propagating through the first wiring is assumed to be "λ", a length of the first open stub is less than "λ / 4".

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