Housing with a functional chip and with a physically separated detection chip and method for manufacturing

Abstract

A package (100) comprising a functional chip (102) for providing an electrical function using an electrical current and a sensing chip (104) for providing an electrical sensing signal characterizing the electrical current, wherein the functional chip (102) and the sensing chip (104) are physically separate chips.

Description

BACKGROUND OF THE INVENTIONField of the InventionThe present invention relates to a housing and a method for manufacturing a housing.Description of the Prior ArtA package, for example for automotive applications, provides a physical enclosure for one or more electronic chips having one or more integrated circuit elements. Examples of integrated circuit elements of packages are a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a diode.The printed publication DE 10 2016 111 248 B4 and the publication DE 10 2019 103 030 A1 relate to housings for semiconductor components which have both a functional semiconductor chip and a sensor chip in a housing.There is still potentially room to allow package fabrication with relaxed design constraints.Summary of the InventionThere may be a need for a housing with relaxed design constraints.A package is provided comprising a function chip for providing an electrical function using an electrical current and a sensing chip for providing an electrical sensing signal characterizing the electrical current, wherein the function chip and the sensing chip are physically separate chips and wherein the function chip and the sensing chip have specifications according to the same chip manufacturing technology.There is also provided a method of manufacturing a package, the method comprising providing a function chip for providing an electrical function using an electrical current, connecting a sensing chip to the function chip and providing the sensing chip for providing an electrical sensing signal characterizing the electrical current, and forming the function chip and the sensing chip as physically separate chips, and wherein the method comprises manufacturing the function chip and the sensing chip by the same chip manufacturing technology.According to an exemplary embodiment, a package (e.g., a semiconductor power package) is equipped with a function chip for providing an electrical function (e.g., an electrical switching function). Performing the electrical function by the function chip may use generating or providing an electrical current that may have characteristics of interest. The package may include a sensing chip configured to provide an electrical sensing signal (such as an electrical current signal). The electrical sensing signal may have characteristics that allow to characterize or obtain information that characterizes the above-mentioned electrical current involved in the functionality of the functional chip. Advantageously, the function chip and the sensing chip can be physically separate chips of a common housing, i.e. they do not form parts of one and the same semiconductor chip or the same electronic chip component. Providing a function chip and a sensing chip as separate chips may increase the flexibility of the package design, as there may be less severe or even no limitations of a common integrated function and sensing chip. In particular, providing a separate function chip and a separate sensing chip may allow each component of the package to be freely placed in the package as desired and where desired. For example, providing one or more separate terminals that may be necessary in a common integrated function and sensing chip to support sensing functionality may be unnecessary if a function chip and a sensing chip are provided separately. Moreover, providing a functional chip and a sensing chip as separate chips may allow optionally further connection elements (such as bond wires) to be advantageously arranged, for example, to avoid undesired crossing. Moreover, providing a separate sensing chip may allow only one additional function to be integrated into the sensing chip, for example in a free area thereof.DESCRIPTION OF FURTHER EXEMPLARY EMBODIMENTSFurther exemplary embodiments of the housing and of the method are explained below.In the context of the present application, the term "package" may particularly denote a device that may have, for example, two or more chips. For example, at least a part thereof can be mounted on a (in particular partially or completely electrically conductive) carrier. The components of the housing may optionally be at least partially encapsulated by an encapsulant. Further, a connection structure may form a part of the housing.In the context of the present application, the term "chip" may particularly denote a semiconductor chip (in particular a power semiconductor chip). The chip may be an active electronic device. In particular, the chip may be a semiconductor chip having at least one integrated circuit element (such as a monolithically integrated transistor) in a surface portion thereof. The chip may be a bare chip or may already be packaged or encapsulated. Semiconductor chips implemented according to example embodiments may be formed in silicon technology, gallium nitride technology, silicon carbide technology, etc., for example.In the context of the present application, the term "functional chip" may particularly denote a chip contributing to a main electrical function of the package. For example, if the package is a switch package, the function chip may contribute to the switching functionality. When the package is a processor package, the function chip may contribute to the processor function, etc.In the context of the present application, the term "sensing chip" may particularly denote a chip that performs the function of sensing an electrical signal that enables to characterize the operation of the functional chip, which may be electrically coupled to the sensing chip. For example, the sensing chip does not directly contribute to the main electrical function of the package. The electrical sensing signal sensed by the sensing chip may be correlated with or indicative of the electrical current involved in the functionality of the functional chip. In particular, a sensing chip may perform current sensing for the function chip (which may be a power MOSFET) to measure or determine a load current of the function chip. When a sensing chip is provided separately from a function chip, the sensing chip and the function chip may be connected such that a current flow is inversely shared with respect to resistances of the chips, and a relationship between the sensing electric signal of the sensing chip (in particular, a sensing current) and the electric current of the function chip (such as a source current) may be established. In one embodiment, the sensing chip may include one or more sensors that measure current through a magnetic sensing mechanism, such as Hall sensors or GMR (giant magnetoresistance) sensors. In another embodiment, the sensing chip may include one or more non-magnetic sensors.In the context of the present application, the term "physically separate chips" may particularly denote that the function chip and the sensing chip may be structurally distinct bodies (in particular semiconductor bodies) that may be handled independently of each other prior to package manufacture, for example prior to an encapsulation process. For example, the function chip may be a first semiconductor chip and the sensing chip may be a discrete second semiconductor chip.In the context of the present application, the term "main surface" of a body may particularly denote the largest body surface or one of the largest body surfaces. For example, a body (such as a chip or a carrier or a clip) may be plate-shaped or substantially plate-shaped and may then have two opposing major surfaces separated by body material in a thickness direction and joined together by a peripheral edge.In one embodiment, the function chip and the sensing chip have specifications according to the same chip fabrication technology. Accordingly, the method may include manufacturing the function chip and the sensing chip by the same chip manufacturing technology. Fabricating a function chip and a sensing chip by the same chip fabrication technology may indicate that the chips are fabricated by the same processes with the same characteristics and / or so as to exhibit the same dependencies on parameters such as temperature, electric current, and / or electric voltage. In short, the sensing chip may be a physically smaller version of the larger functional chip with corresponding technological properties. Thus, the sensing chip may behave during operation as the function chip behaves during operation. For example, the same processes may be performed for both chips during manufacture. As a result, the function chip and the sensing chip may have the same trench depth, pitch, and / or implantation. For example, the sensing chip may have a smaller outline but the same internal dimensions and materials as the functional chip. When the function chip and the sensing chip have specifications according to the same chip manufacturing technology, the electrical sensing signal sensed by the sensing chip is a precise and reliable indicator or fingerprint of the electrical current of the function chip.For example, at least one integrated circuit element (such as, for example, a monolithically integrated transistor, in particular a field effect transistor (FET), in particular a metal oxide semiconductor field effect transistor (MOSFET)) of the functional chip and at least one integrated circuit element (such as, for example, a further monolithically integrated transistor, in particular a further field effect transistor, in particular a further metal oxide semiconductor field effect transistor) of the detection chip have the same dimensions, the same spacing and / or the same implantation properties. A dimension may be a spatial dimension in a length, width, and / or depth direction. For example, such a dimension may be a gate length or a trench depth. A distance may be a characteristic distance between two adjacent structures of the respective chip or of a monolithically integrated circuit element thereof. Implantation properties may relate, for example, to a chemical element used as a dopant, a dopant concentration and / or a doping process.In an embodiment, an outline of the functional chip has larger dimensions than an outline of the sensing chip. Thus, the external dimensions and / or a volume of the functional chip may each be greater than the external dimensions and / or a volume of the sensing chip. The sensing chip may be a physically smaller variant of the functional chip. This may allow the housing to be manufactured in a compact manner. However, the characteristic dimensions of integrated circuit elements (such as a monolithically integrated field effect transistor) of the sensing chip and the functional chip may be the same. This can ensure that the electrical detection signal of the detection chip is characteristic of or indicates the electrical current of the function chip with high accuracy. Consequently, the use of the electrical detection signal for controlling or regulating the housing (in particular for driving the functional chip) may be justified and reliable.In an embodiment, a ratio between a main surface of the functional chip and a main surface of the sensing chip is at least five, for example at least ten. In short, the main surface of the functional chip may preferably be at least half or an order of magnitude larger than the main surface of the sensing chip, for example. For example, the main surface of the functional chip may be in a range of 2 mm2to 10 mm2(e.g. 5 mm2), whereas the main surface of the sensing chip may be in a range of 0.2 mm2to 1 mm2(e.g. 0.5 mm2). These design rules allow for the manufacture of the package with low space consumption, while still allowing for reliable and precise control of the functional chip based on an electrical sensing signal sensed at the sensing chip.In one embodiment, the housing has a further functional chip for providing a further electrical function which uses a further electrical current and interacts with the functional chip. The further function chip can provide, for example, the same electrical function as the above-mentioned function chip, for example an electrical switching function. For example, the function chip and the further function chip can cooperate as low-side switches and high-side switches of a half bridge. The function chip and the further function chip may have specifications according to the same chip manufacturing technology as explained above for the relationship between the function chip and the sensing chip. The outline of the function chip and of the further function chip can be different or the same. For example, if one of the function chip and the further function chip has a longer "on" percentage during a duty cycle than the other chip, this may be reflected in different physical dimensions of the function chips.In an embodiment, the function chip is a transistor chip and / or a power chip, for example a power transistor chip. In the context of the present application, the term "transistor chip" may particularly denote a chip, such as a semiconductor chip, in which at least one transistor may be integrated, particularly monolithically integrated. Optionally, the chip may comprise at least one further integrated circuit element, such as a diode or a further transistor. In particular, a respective integrated transistor chip may be a field effect transistor chip having a source terminal (or pad), a drain terminal (or pad) and a gate terminal (or pad). Alternatively, a respective integrated transistor chip may be a bipolar transistor chip having an emitter terminal (or pad), a collector terminal (or pad) and a base terminal (or pad). Specific examples of the transistor chips are a metal oxide semiconductor field effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT). In the context of the present application, the term "power chip" may particularly refer to a chip, such as a semiconductor chip, configured for a power application, for example a power switching application. In an embodiment, the transistor-equipped chip(s) is / are configured as power semiconductor chips. Thus, a corresponding chip (such as a semiconductor chip) may be used for power applications, for example in the automotive sector. Corresponding integrated circuit elements may be manufactured in silicon technology or based on wide band gap semiconductors (such as silicon carbide, gallium nitride or gallium nitride on silicon), for example. A semiconductor power package may include one or more inverter circuits, one or more half bridges, one or more full bridges, one or more drivers, one or more logic circuits, etc.In one embodiment, the further function chip is a further transistor chip and / or a further power chip, for example a further power transistor chip. Preferably, both the function chip and the further function chip can be a semiconductor power transistor chip.In one embodiment, the function chip and the further function chip are connected to form a half bridge. In the context of the present application, the term "half bridge" may particularly denote a circuit consisting of an upper transistor switch ("high side") and a lower transistor switch ("low side"). For example, the transistors may be MOSFETs. The transistors may be connected in a cascode arrangement. The two function chips may be configured as transistor switches that may be turned on and off complementarily to each other (in particular with a non-overlapping dead time) by applying corresponding voltage waveforms to control terminals (such as gate terminals). A desired result may be an idealised DC-DC conversion scenario in which a rectangular average voltage level switches between a first electrical potential (such as a DC (direct current) bus voltage) and a second electrical potential (such as ground). However, other forms of output signal that do not have a rectangular characteristic may be possible. The two transistors may be connected to each other with a mutual connection of their drains and with a mutual connection of their gates. The mentioned half-bridge configuration may be used as such or alone or may be combined with one or more further half-bridges (or other electrical circuits) to realize a more complex electrical function. For example, two such half bridges may form a full bridge.In one embodiment, the function chip and the further function chip are arranged next to one another. For example, the function chip and the further function chip can be arranged next to one another on the same vertical plane.In one embodiment, the sensing chip and the function chip are stacked on top of each other, for example, the sensing chip is stacked on the function chip. Corresponding embodiments are shown, for example, in FIGS. 3, 4 and 6. Stacking the sensing chip and the functional chip vertically on each other can result in a very compact package. Further, a stack of sensing chip and functional chip may allow to directly connect drains thereof to each other, which may advantageously result in short electrical paths.In an embodiment, the package comprises a control chip (which may also be referred to as a driver chip) for driving the function chip and the sensing chip and / or for sensing the electrical sensing signal. Such a control chip may provide a control signal to a gate terminal of the function chip and to a gate terminal of the sensing chip. Optionally, the control chip (or another control chip) can also supply a control signal to a gate terminal of a further function chip. The control chip (or another control chip) may also sense the electrical sensing signal of the sensing chip. The control chip may process the detected electrical sensing signal, for example, to adjust the control signal based on information derived from the electrical sensing signal characterizing the electrical current of the function chip. Thus, the detected electrical detection signal may be used in the form of a control loop.In one embodiment, the control chip is arranged with the sensing chip next to one another and / or arranged on a different vertical plane than the function chip and / or as the further function chip. A corresponding embodiment is shown in FIG. 3. While the control chip and the sensing chip may be arranged side by side on the same vertical plane and the function chip and (if present) the further function chip may be arranged on a different common vertical plane, the control chip and the sensing chip may preferably be arranged over the function chip and the further function chip. This may make the electrical connections between the different chips simple and efficient. A resulting design of the housing may be compact.In an embodiment, the package includes an electrically conductive clip disposed between the function chip and the sensing chip. In the context of the present application, the term "clip" may particularly denote a (in particular planar or three-dimensionally curved) plate-like connection element comprising an electrically conductive material (such as copper) and being an integral body with surface portions or portions to be connected to the function chip and the sensing chip. For example, such a clip may connect a drain terminal of the function chip to a drain terminal of the sensing chip. It is also possible for the clip to connect the control chip and / or the further function chip to the function chip and / or the detection chip and / or to one another. The clip may also be connected to a carrier (such as a leadframe structure) on which the function chip and optionally also the further function chip may be mounted. For example, the clip may be connected to a conductor portion of the carrier.In one embodiment, the housing has an at least partially electrically conductive carrier, for example a leadframe structure, which carries the function chip (and optionally also a further function chip). In the context of the present application, the term "carrier" may particularly denote a support structure (which may be at least partially electrically conductive) serving as a mechanical support for the electronic chip(s) to be mounted thereon and which may also contribute to the electrical connection between the electronic chip(s) and the periphery of the package. In other words, the carrier can fulfil a mechanical support function and an electrical connection function. A carrier may comprise or consist of a single part, multiple parts connected via encapsulation or other package components, or a sub-array of carriers. If the carrier forms part of a lead frame, it may be or comprise a chip pad. More generally, the mentioned carrier may be a lead frame structure (e.g. made of copper), a DAB (Direct Aluminum Bonding) substrate, a DCB (Direct Copper Bonding) substrate, etc. In addition, the carrier may also be configured as an AMB (Active Metal Brazing) substrate. In the context of the present application, the term "lead frame" may particularly denote a sheet metal structure which may be bent, stamped and / or structured to form lead frame structures as mounting portions for mounting chips and leads for electrically connecting the package to an electronic environment. In an embodiment, the lead frame may be a metal plate (in particular made of copper) which may be structured, for example by punching or etching. Forming the chip carrier as a lead frame is a cost-effective and mechanically and electrically very advantageous configuration in which a low-resistance connection of chips can be combined with a robust support capability of the lead frame. Moreover, a lead frame may contribute to the thermal conductivity of the package and may remove heat generated during operation of the chip(s) as a result of the high thermal conductivity of the metallic (in particular copper) material of the lead frame.In one embodiment, a source terminal of the sensing chip is electrically decoupled from a source terminal of the functional chip. Thus, electrical current or electrical signals may be separated at the sources of a transistor chip-like sensing chip and a function chip, such that the current or signals may be provided or processed independently of each other.In an embodiment, a drain terminal of the sensing chip is electrically coupled to a drain terminal of the function chip. Thus, the drains of the sensing chip and the function chip may be at the same electrical potential. For example, this can be achieved with a short connection path by drain-up arranging the function chip in a flip-chip configuration and arranging the sensing chip with a drain-down configuration.In an embodiment, a gate terminal of the sensing chip is electrically coupled to a gate terminal of the function chip. Thus, the gate terminals of the sensing chip and the functional chip may be at the same electrical potential. This configuration may allow a control chip to provide the same control signals to the gate terminals of the function chip and the sensing chip. This may form a suitable basis for obtaining by the sensing chip an electrical sensing signal characteristic of the electrical current assigned to or provided by the function chip.In one embodiment, the function chip is arranged drain-up and / or the sensing chip is arranged drain-down. Such a flip-chip arrangement of the functional chip in combination with an ordinary orientation of the sensing chip may result in an extremely short electrical connection path between the drains of the functional chip and the sensing chip. Electrical artifacts (such as loss and / or distortion) can thus be suppressed.In one embodiment, the housing has an encapsulation agent, for example a potting compound, which encapsulates at least part of the functional chip and at least part of the detection chip. Thus, a joint encapsulation of the function chip and the sensing chip may be achieved. Optionally, but advantageously, a control chip and / or a further function chip can also be at least partially encapsulated in the same encapsulation means. In the context of the present application, the term "encapsulant" may particularly denote a material, structure or element surrounding / the at least part of the chips (and optionally at least part of a carrier) to provide mechanical protection and optionally electrical insulation and / or a contribution to heat dissipation during operation. In particular, the encapsulation agent may be predominantly or even completely electrically insulating, for example a potting compound. A casting compound can have a matrix of flowable and curable material and filler particles embedded therein. For example, filler particles can be used to adjust the properties of the potting compound, in particular to improve the thermal conductivity. Alternatively to a potting compound (for example based on epoxy resin), the encapsulation agent can also be a potting compound (for example based on a silicone gel). In yet another embodiment, the encapsulant may be a laminate of stacked layers (e.g., comprising prepreg and / or resin films).In an embodiment, the sensing chip is configured to provide at least one additional function in addition to providing the electrical sensing signal. By providing the sensing chip as a physically separate chip with respect to the function chip, space for implementing at least one additional function (preferably at least one additional electrical function) may be present in a free area of the sensing chip. For example, the at least one additional function may include providing a temperature signal indicative of a temperature of the sensing chip. For example, a temperature sensor may be integrated (preferably monolithically integrated) into the sensing chip to generate the temperature signal. For example, such a temperature sensor may be embodied as a temperature sensing resistor. For example, a temperature sensing resistor may be implemented with four pads connected in a Kelvin manner to enable temperature sensing with four terminals. Due to the close spatial proximity of the sensing chip and the functional chip in the same package, preferably encapsulated by the same encapsulant, the temperature information provided by the sensing chip may also indicate the temperature of the functional chip. Based on the detected temperature information, a control of the function chip (and optionally also of the detection chip and / or of a further function chip) can be carried out by a control chip.However, in addition or as an alternative to the temperature sensor, at least one other function element can be integrated into the detection chip in order to provide at least one additional function. For example, the sensing chip may be configured to provide an electrical redistribution function in the context of the electronic functionality of the package.Moreover, by providing the sensing die as a physically separate body with respect to the functional die, location and orientation of the sensing die in the package may be selected to avoid cross-wires (such as bond wires).In an embodiment, at least one of the function chip, the sensing chip and the further function chip is configured to operate with a vertical current flow (in particular a current flow perpendicular to a plane in which a carrier and / or a clip extends). Chips configured for vertical current flow may have transistor terminals on both an upper main surface and a lower main surface of the chip, respectively. Particularly in such a vertical flow configuration, the package can be formed with extremely short current paths and thus with a rather simple layout.As substrate or wafer forming the base of the chip or chips, a semiconductor substrate, preferably a silicon substrate, can be used. Alternatively, a silicon oxide or other insulator substrate may be provided. It is also possible to implement a germanium substrate or a III-V semiconductor material. For example, example embodiments may be implemented in GaN or SiC technology.The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings, in which like parts or elements are denoted by like reference numerals.Brief Description of the DrawingsThe accompanying drawings, which are included to provide a further understanding of exemplary embodiments and form a part of the specification, illustrate exemplary embodiments.In the drawings, there are shown: FIG. 1 illustrates a layout of a package according to an example embodiment. FIG. 2 is a circuit diagram of a package according to an example embodiment. FIG. 3 shows three-dimensional views of a housing according to an exemplary embodiment with and without an encapsulant. FIG. 4 is a cross-sectional view of a housing according to an example embodiment. FIG. 5 is a cross-sectional view of a housing according to another exemplary embodiment. FIG. 6 is a cross-sectional view of a housing according to yet another exemplary embodiment.DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTSThe illustration in the drawing is schematic.Before further example embodiments are described in more detail, some basic considerations are summarized based on which example embodiments were developed.Current sensing power MOSFETs may enable measuring load current in a power conditioning circuit. In particular, in polyphase systems, current sensing for current compensation between different phases may be desired and may be used to provide feedback to a control loop. Current sensing may be obtained by various methods.A precise and low-loss arrangement is the fabrication of a sensing cell (such as a mirror FET) within a power FET. High current power stages may use a system-in-package architecture. Additional connection from the sensing cell within the power FET to a driver or control chip may be required. In vertical power FET technology using a flip-chip configuration, access to the sense cell may be available on the bottom of the low-side power FET. As a result, a dedicated exposed pad may be needed in the package.However, to improve cooling, it may be desirable to make a power ground area as large as possible because it provides a main heat path. This may be particularly critical for smaller package sizes. This can reduce the area for signal connections. For example, there are footprint specifications where no area for sense FET connections is considered. In such a case, a conventional single chip sense cell architecture including power FET and sense FET may be inadequate.Another approach is to determine an electrical current in a low-side transistor by measuring the voltage drop during the on-state (which may be referred to as RDS(on)-based current sensing). However, the accuracy of the detection may be degraded due to the heat dependency, the gate-source voltage dependency, and the process shift.In summary, current sensing in a power chip may still be a challenge and may limit design freedom.According to an exemplary embodiment, a package (such as a molded chip package) may include a function chip (e.g., a power transistor chip) that performs an actual electrical function of the package. During operation of the functional chip, an electric current may occur which is to be monitored in order to obtain information about the operation of the functional chip. To achieve this, the package may be equipped with an additional sensing chip (e.g. another transistor chip, which may be a physically smaller and technologically similar version of the above mentioned transistor chip) which may provide sensing functionality by providing an electrical sensing signal, which may be referred to as an electrical current sensing signal, for example. Illustratively, the electrical sensing signal may include information and / or may have characteristics or attributes that allow to derive a conclusion about characteristics or attributes of the electrical current assigned to or provided by the function chip. For example, the acquired information may be used to control or regulate the operation of the function chip. Advantageously, the function chip and the sensing chip may be provided as two physically or structurally separate chip bodies instead of as a common common chip body. This has advantages: If the function chip and the sensing chip are provided as two discrete semiconductor chips, the design of the package can be made more flexible by a package designer because both chips can be configured partially independently of each other. Although it may be desirable for both the function chip and the sense chip to be formed according to the same chip manufacturing technology to provide comparable electrical characteristics, severe constraints on pin design and the like may be relaxed. In particular, at least one separate sensing terminal of a function chip may not be necessary if the function chip and the sensing chip are provided as separate chips.Thus, an exemplary embodiment may fabricate a sensing device in a separate chip, i.e., a sensing chip that is physically separate from a functional chip (which may be a power FET). Advantageously, the sensing chip and the function chip may be manufactured according to the same chip manufacturing technology. This may ensure that the electrical sensing signal sensed at the sensing chip indicates or is meaningful to the characteristics of the electrical current involved in the operation of the functional chip.In one embodiment, the sensing chip may be connected on a folded function chip (in particular a power FET) such that the chip backsides (in particular drain terminals) are in electrical contact with each other. The contact may be made by a conductive interlayer. The top side of the sensing chip may be available for bonding, for example using bond wires.In an embodiment, the sensing chip may be connected to a gate of the function chip (such as a power FET). In addition, a connection to a source of the functional chip (in particular a power transistor) may be used to generate a well-defined potential for a field plate connection in the case of a field plate power transistor with buried source and to have the same reference voltage for the gate drive of the sensing chip (in particular a sensing FET). All of these signals may already be available for connection (e.g., by wire bonding) within the package.Thereby, a package comprising a functional chip and a separate sensing chip, which may be connected according to a current mirror configuration, with an industry-standard footprint may be created. In particular, this may be achieved using a leadframe without additional exposed pads. Thus, current sensing can be realized in a simple and precise manner and with a high degree of flexibility. In particular, there may be no exposed sensing pad in the package. This can be combined with the possibility of using an industry standard footprint with a simple leadframe.Advantageously, example embodiments may allow to use the concept of current sensing based on sensing FET mirroring, wherein thermal matching may be possible between the sensing chip and the functional chip (such as a power FET). Advantageously, the function chip and the sensing chip may be implemented with the same operating conditions (in particular the same gate-source voltage and drain-source voltage). A further advantage is the possibility of simple adjustment at only one temperature in order to obtain a high degree of adjustment accuracy.An example embodiment of the package may be a high current power stage. A corresponding housing can use, for example, a base area of 4 mm x 6 mm without an exposed pad for current detection. According to an exemplary embodiment, this can be achieved with a simple die embedding package having one or more functional chips and a separate sensing chip that meets the need for high precision current sensing that conforms to a standardized footprint. Further, exemplary embodiments can be manufactured with little effort and excellent current detection accuracy.FIG. 1 shows a layout of a package 100 according to an example embodiment. FIG. 2 shows a circuit diagram of the housing 100. FIG. 3 shows three-dimensional views of the housing 100 with (on a bottom side) and without (on a top side) an encapsulant 126.Referring to the circuit diagram of FIG. 2, a control chip 108 includes a gate driver 150 and a current sensing circuit 152. The gate driver 150 is configured to apply a common gate drive signal to a gate terminal 124 of a function chip 102 and to a gate terminal 118 of a sensing chip 104 that is physically separated from the function chip 102. The function chip 102 may be a low-side power transistor chip of a half bridge. A further component of the half bridge is a further function chip (not shown, but connected with the reference numeral 106). The further function chip 106 may be a high-side power transistor chip of the half bridge. However, in addition to the half bridge function, the package 100 is also configured as a current sensing arrangement. Namely, the sensing chip 104 is configured to provide an electrical sensing signal to the current sensing circuit 152 of the control chip 108, which may provide information to the control chip 108 about the characteristics of an electrical current at the function chip 102. The gate terminals 118, 124 are electrically coupled together. Further, a drain terminal 116 of the sensing chip 104 is electrically coupled to a drain terminal 120 of the function chip 102. The drain terminals 116, 120 are electrically coupled to the further function chip 106 and to a switching node 154. A tank inductor may also be coupled to the switching node 154 and may be present at reference numeral 156. Furthermore, a source terminal 114 of the sensing chip 104 may be electrically decoupled from a source terminal 122 of the functional chip 102. Through a connection line 158, the sensing chip 104 may provide an electrical sensing signal at its source terminal 114 to the current sensing circuit 152 of the control chip 108. The electrical sensing signal may be sensed or measured at the source terminal 114 of the sensing chip 104. The electrical sensing signal sensed at the sensing chip 104 may be a copy or fingerprint of a corresponding electrical current generated by the function chip 102. However, the electrical sensing signal may be scaled down with respect to the electrical current, for example, by a factor of at least 1000. Nevertheless, the electrical detection signal may be an indicator of the electrical current in the function chip 102. The control chip 108 may further process the electrical sensing signal, for example, to determine the signal quality. Through another connection line 160, the function chip 102 may provide an electrical signal at its source terminal 122 to the current sensing circuit 152 of the chip controller 108. While the switching node 154 may be at a floating electrical potential, the source terminal 122 of the function chip 102 may be coupled to a fixed electrical potential (PGND).Referring now to the layout of the package 100 shown in FIG. 1 and the three-dimensional views of the package 100 of FIG. 3, the package 100 according to the circuit diagram of FIG. 2 will be described in more detail.As already mentioned, the function chip 102 is provided for providing an electrical function that uses an electrical current. In the embodiment shown, the electrical function of the function chip 102 is that of a low-side MOSFET of a half bridge. In particular, the function chip 102 is a first power transistor chip of the half bridge. The function chip 102 is mounted on a leadframe structure-like carrier 112, which may be a patterned copper plate. For example, the functional chip 102 may be mounted on the electrically conductive carrier 112 by an electrically conductive connection medium, such as solder or electrically conductive adhesive. As shown in FIG. 2, the carrier 112 may include chip mounting plate portions 162, 164 (for mounting function chips 102, 106 thereon) and conductor portions 166 (which are to be exposed beyond an encapsulant 126 to enable electrical connection of the package 100 to an electronic periphery). Further, a plurality of bond wires 168 are shown for connecting different chip pads to other chip pads or to corresponding conductor portions 166. As can be seen from FIGS. 1 and 3, crossing of the bond wires 168 (which may involve a risk for a fault during a manufacturing process) may be reliably prevented thanks to the illustrated package design. In particular, this advantageous option is promoted by providing the sensing chip 102 separately, i.e. by providing the sensing chip 102 separately from the functional chips 102, 106, relaxing design constraints.The above-mentioned sensing chip 104 is configured to provide an electrical sensing signal characterizing the electrical current. The sensing chip 104 may be a smaller version of the functional chip 102 that has a smaller outline and smaller external physical dimensions than the functional chip 102, but is manufactured according to the same chip manufacturing technology as the functional chip 102. As a result of the same chip manufacturing technology, the function chip 102 and the sensing chip 104 may be made of the same materials and may have the same characteristic dimensions of their monolithically integrated circuit elements, in particular a monolithically integrated transistor of each of the function chip 102 and the sensing chip 104. As can be seen from FIG. 3, the sensing chip 104 is mounted over the function chip 102 and is physically separated from and electrically coupled to the function chip 102 by an electrically conductive clip 110. For example, the sensing chip 104 may be mounted on the electrically conductive clip 110 by an electrically conductive connection medium such as solder or electrically conductive adhesive. Consequently, an upper main surface portion of the functional chip 102 is electrically coupled to a lower main surface portion of the sensing chip 104.Advantageously, the function chip 102 and the sensing chip 104 are physically separate chips. Thus, the function chip 102 and the sensing chip 104 are implemented as two separate semiconductor chips rather than two portions of a common integrated semiconductor chip. Advantageously, this may allow the function chip 102 and the sensing chip 104 to be separately and individually designed and freely placed in the package 100 where appropriate for a desired specification. In contrast to conventional approaches, providing a dedicated pad for current sensing may also be unnecessary due to separately providing the function chip 102 and the sensing chip 104.As mentioned above, the function chip 102 and the sensing chip 104 may have specifications according to the same chip manufacturing technology. In particular, a monolithically integrated field effect transistor of the functional chip 102 and a monolithically integrated field effect transistor of the sensing chip 104 may have the same dimensions, the same distance and the same implantation characteristics. However, as may be seen from FIGS. 1 and 3, an outline of the function chip 102 may have larger dimensions than an outline of the sensing chip 104. As a rule of thumb, an upper main surface of the functional chip 102 may be, for example, about an order of magnitude larger than an upper main surface of the sensing chip 104. In short, the sensing chip 104 may be a physically smaller version of the functional chip 102, while both chips 102, 104 may preferably be manufactured according to the same chip manufacturing technology.As already mentioned in the context of the description of FIG. 2, the package 100 may comprise a further function chip 106 for providing a further electrical function that uses a further electrical current and interacts with the function chip 102. The sensing chip 104 (or another sensing chip, not shown) may be provided for providing an electrical sensing signal characterizing the further electrical current. In the embodiment shown, the electrical function of the further function chip 106 is that of a high-side MOSFET of the half bridge which is formed together with the function chip 102. Thus, the further function chip 106 is a further power transistor chip. The further function chip 106 is also mounted on the leadframe structure-like carrier 112 side by side and on the same vertical plane as the function chip 102. For example, the further functional chip 106 may be mounted on the electrically conductive carrier 112 by an electrically conductive connection medium, such as solder or electrically conductive adhesive.For example, the function chip 102 and the further function chip 106 may have specifications according to the same chip manufacturing technology. In particular, the monolithically integrated field effect transistor of the functional chip 102 and a monolithically integrated field effect transistor of the further functional chip 106 may have the same dimensions, the same spacing and the same implantation properties. However, as can be seen from FIGS. 1 and 3, an outline of the function chip 102 can have larger dimensions than an outline of the further function chip 106. Alternatively, an outline of the function chip 102 may have the same or even smaller dimensions than the outline of the further function chip 106. This size may be adjusted according to operating characteristics of the function chips 102, 106, for example according to different or identical "on" times of the function chips 102, 106 during operation of the package 100.FIGS. 1 and 3 also show the control chip 108 for driving the function chip 102 and the sensing chip 104, for sensing the electrical sensing signal from the sensing chip 104 and optionally for sensing a signal from the function chip 102. Although not shown, it is optionally possible for the control chip 108 (or alternatively another control chip) also to drive the further function chip 106.As best seen in FIG. 3, the control chip 108 is juxtaposed with the sensing chip 104 and is disposed on the same vertical plane as it. Also, the control chip 108 may be mounted on top of the clip 110. For example, the control chip 108 may be mounted on the electrically conductive clip 110 by an electrically conductive connection medium such as solder or electrically conductive adhesive. In another example, the control chip 108 may be mounted on the electrically conductive clip 110 by an electrically insulating bonding medium, such as electrically insulating adhesive. Furthermore, the control chip 108 is arranged on a different vertical plane than the function chip 102 and the further function chip 106, i.e. above it. The chip configuration shown in FIG. 3 is very compact.As illustrated on the bottom side of FIG. 3, an encapsulant 126, embodied here as a potting compound, encapsulates the function chip 102, the further function chip 106, the sensing chip 104, the control chip 108, the clip 110 and a part of the carrier 112. However, another portion of the carrier 112 may be exposed beyond the encapsulant 126 to allow for electrical and / or thermal connection of the encapsulated package 100 to an electronic environment (e.g., a mounting base such as a printed circuit board, PCB) and / or for heat dissipation. In order to establish the electrical connection, electrically conductive conductor sections 166 of the carrier 112 may be exposed beyond the encapsulant 126. For example, the exposed conductor portions 166 may be connected in an electrically conductive manner to a mounting base (such as a PCB, not shown) on which the housing 100 may be mounted. When a plate portion of the carrier 112 is exposed beyond the encapsulant 126, such exposed plate portion may be used to dissipate heat generated by the encapsulated chips during operation of the package 100, and / or may be connected to a heat sink (not shown).Advantageously, the sensing chip 104 may be configured to provide at least one additional function in addition to providing the electrical sensing signal. In the described embodiment, the sensing chip 104 may be equipped with a temperature sensor such that the sensing chip 104 may provide a temperature signal indicative of its temperature to the control chip 108. The integration of an additional function into the sensing chip 104 is possible due to the fact that the sensing chip 104 is provided as a separate semiconductor chip with respect to the function chips 102, 106.Although the package type of FIGS. 2 and 3 is that of a quad flat no lead package (QFN) power stage with sensing integrated circuit, the functionality described with reference to FIGS. 1-3 may be provided with other types of packages as well.FIG. 4 shows a cross-sectional view of a housing 100 according to an exemplary embodiment.In the package 100 according to FIG. 4, only a single function chip 102 is provided. The function chip 102 is vertically stacked with a smaller, but preferably technologically the same sensing chip 104 disposed over the function chip 102. A clip 110, such as a copper plate structure, is sandwiched between the bottom-side function chip 102 and the top-side sense chip 104. The bottom side of the functional chip 102 is mounted on a carrier 112, such as a leadframe structure.The function chip 102 may be a field effect transistor power chip that experiences a vertical current flow during operation and is arranged in a flip-chip configuration. Thus, a drain terminal 120 of the functional chip 102 is arranged on an upper main surface of the functional chip 102, whereas a source terminal 122 and a gate terminal 124 of the functional chip 102 are arranged on a lower main surface thereof and are connected to the carrier 112 in an electrically conductive manner.The sensing chip 104 may also be a field effect transistor chip that experiences a vertical current flow during operation and is a smaller, but preferably technologically equivalent, version of the functional chip 102. A drain terminal 116 of the sensing chip 104 is arranged on a lower main surface of the sensing chip 104, whereas a source terminal 114 and a gate terminal 118 of the sensing chip 104 are arranged on an upper main surface thereof.As shown, the source terminal 114 of the sensing chip 104 is electrically decoupled from the source terminal 122 of the function chip 102. However, the drain terminal 116 of the sensing chip 104 is electrically coupled to the drain terminal 120 of the function chip 102 through the clip 110. Moreover, the gate terminal 118 of the sensing chip 104 is electrically coupled to the gate terminal 124 of the function chip 102 by a bond wire 168.One skilled in the art will understand that the clip 110 and bond wires 168 implemented in the embodiments shown in the figures are only examples of electrically conductive interconnect structures. They can be replaced by other electrically conductive connection structures. For example, bond wires or bond tapes may be used instead of a clip or vice versa in each embodiment described herein. In addition or as an alternative to such electrically conductive connection structures, the carrier 112 can also fulfil a corresponding function.FIG. 5 shows a cross-sectional view of a housing 100 according to another exemplary embodiment.The embodiment of FIG. 5 differs from the embodiment of FIG. 4 in particular in that, according to FIG. 5, the function chip 102 and the detection chip 104 are arranged next to one another instead of being vertically stacked according to FIG. 4.The drain terminal 116 and the drain terminal 120 are electrically coupled to each other by mounting both on the carrier 112. The gate terminal 118 and the gate terminal 124 are electrically coupled to each other by both being connected to the carrier 112 by a respective bond wire 168. The source terminal 114 and the source terminal 122 are decoupled from one another.FIG. 6 shows a cross-sectional view of a housing 100 according to yet another exemplary embodiment.The embodiment of FIG. 6 differs from the embodiment of FIG. 4 in particular in that, according to FIG. 6, a further function chip 106 and a control chip 108 are additionally provided. The further function chip 106 is arranged next to the function chip 102 and has a drain terminal 170 which is mounted on the carrier 112. A source terminal 172 of the further function chip 106 is connected to a bottom side of the clip 110. A gate terminal 174 of the further function chip 106 is arranged on the same main surface of the further function chip 106 as its source terminal 172. Moreover, the control chip 108 is mounted with the sensing chip 104 side by side on the upper major surface of the clip 110.It should be noted that the term "comprising" does not exclude other elements or features and "a" or "an" does not exclude a plurality. Elements described in connection with different embodiments may also be combined. It should also be noted that reference numerals should not be interpreted as limiting the scope of the claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. Accordingly, the appended claims are intended to embrace such processes, machines, manufacture, compositions of matter, means, methods or steps.

Claims

A package (100) comprising: • a function chip (102) for providing an electrical function using an electrical current; and • a sensing chip (104) for providing an electrical sensing signal characterizing the electrical current; • wherein the function chip (102) and the sensing chip (104) are physically separate chips; • wherein the function chip (102) and the sensing chip (104) have specifications according to the same chip manufacturing technology.The package (100) of claim 1, wherein at least one integrated circuit element of the functional chip (102) and at least one integrated circuit element of the sensing chip (104) have the same dimensions, pitch and / or implantation characteristics.The package (100) of any of claims 1 to 2, wherein an outline of the functional chip (102) has larger dimensions than an outline of the sensing chip (104).The package (100) of any of claims 1 to 3, wherein a ratio between a main surface of the functional chip (102) and a main surface of the sensing chip (104) is at least five, for example at least ten.The package (100) according to any one of claims 1 to 4, comprising a further function chip (106) for providing a further electrical function that uses a further electrical current and interacts with the function chip (102).The package (100) according to any one of claims 1 to 5, wherein the function chip (102) is a transistor chip and / or a power chip, for example a power transistor chip.The package (100) according to claims 5 and 6, wherein the further function chip (106) is a further transistor chip and / or a further power chip, for example a further power transistor chip.The package (100) according to any one of claims 5 to 7, wherein the function chip (102) and the further function chip (106) are connected to form a half bridge.The package (100) according to any one of claims 5 to 8, wherein the function chip (102) and the further function chip (106) are arranged next to each other.The package (100) according to any one of claims 1 to 9, wherein the sensing chip (104) and the function chip (102) are stacked on top of each other, for example the sensing chip (104) is stacked on the function chip (102).The package (100) according to any one of the preceding claims, comprising a control chip (108) for driving the function chip (102) and the sensing chip (104) and / or for sensing the electrical sensing signal.The package (100) of claim 11, wherein the control chip (108) is arranged side by side with the sensing chip (104) and / or is arranged on a different vertical plane than the function chip (102) and / or as the further function chip (106).The package (100) of any of claims 1 to 12, comprising an electrically conductive clip (110) disposed between the function chip (102) and the sensing chip (104).The package (100) according to any one of claims 1 to 13, comprising an at least partially electrically conductive carrier (112), for example a lead frame structure, which carries the function chip (102).The package (100) according to any one of claims 1 to 14, comprising at least one of the following features: wherein a source terminal (114) of the sensing chip (104) is electrically decoupled from a source terminal (122) of the functional chip (102); wherein a drain terminal (116) of the sensing chip (104) is electrically coupled to a drain terminal (120) of the functional chip (102); wherein a gate terminal (118) of the sensing chip (104) is electrically coupled to a gate terminal (124) of the functional chip (102); wherein the functional chip (102) is arranged drain-up and / or the sensing chip (104) is arranged drain-down.The package (100) according to any one of claims 1 to 15, comprising an encapsulant (126), for example a potting compound, encapsulating at least a part of the functional chip (102) and at least a part of the sensing chip (104).The package (100) of any of claims 1 to 16, wherein the sensing chip (104) is configured to provide at least one additional function in addition to providing the electrical sensing signal, for example wherein the at least one additional function comprises providing a temperature signal indicative of a temperature of the sensing chip (104).A method of manufacturing a package (100), the method comprising: • providing a functional chip (102) for providing an electrical function using an electrical current; • connecting a sensing chip (104) to the functional chip (102) and providing the sensing chip (104) for providing an electrical sensing signal characterizing the electrical current; and • forming the functional chip (102) and the sensing chip (104) as physically separate chips; • wherein the method comprises manufacturing the functional chip (102) and the sensing chip (104) by the same chip manufacturing technology.

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