Semiconductor device and method for manufacturing the same

Abstract

In a semiconductor substrate, an n-type cathode region, an n-type trough region, and a p-type anode region are formed. The impurity concentration in the cathode region is higher than in the trough region. In a top view, the anode region includes the cathode region, and the trough region includes both the anode region and the cathode region. The depth of the trough region from the top surface of the semiconductor substrate is greater than the depth of the anode region from the top surface of the semiconductor substrate. The depth of the cathode region from the top surface of the semiconductor substrate is greater than the respective depths of the anode region and the trough region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The disclosure of Japanese Patent Application No. 2023-097745, filed on June 14, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. BACKGROUND

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device including a Zener diode and a method of manufacturing the same.

[0003] The semiconductor device includes a protection circuit to protect the MISFET (metal-insulator-semiconductor field-effect transistor) from surge voltages and the like.

[0004] A disclosed technique is listed below.

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-183039

[0006] For example, Patent Document 1 discloses a semiconductor device including a MISFET and a protection circuit and a Zener diode configuring this protection circuit. SUMMARY

[0007] A semiconductor device for driving a power device includes a DESAT (saturated collector voltage detection) circuit. The DESAT detection circuit must reduce the standard width of the DESAT detection voltage to prevent malfunction due to noise. Therefore, it is preferable that the variation in the absolute value of the generated voltage in the reference voltage generation part in the DESAT detection circuit be small and that the temperature characteristics of the reference voltage generation part be small.

[0008] For example, by configuring the reference voltage generation section with a BGR (Bandgap Reference Circuit), the standard width of the DESAT detection voltage can be reduced. However, since there are many components configuring the BGR circuit, the area of ​​the BGR circuit becomes large. Therefore, the application of the BGR circuit is not effective from the perspective of increasing the chip area.

[0009] To realize the reference voltage generation part in a small area, the present inventors have reconsidered configuring the reference voltage generation part using a Zener diode and an emitter-base diode connected in the forward direction. The reference voltage generation part using these diodes can reduce the area compared to the BGR circuit.

[0010] The Zener diode requires a small variation of the breakdown voltage Vz and stable temperature characteristics.

[0011] The generated voltage of the reference voltage generation part is determined by the breakdown voltage Vz of the Zener diode and the forward voltage Vf of the emitter-base diode. Therefore, when the breakdown voltage Vz changes, the generated voltage of the reference voltage generation part also changes. Since the DESAT detection voltage is determined by the generated voltage of the reference voltage generation part, it is not possible to narrow the standard width of the DESAT detection voltage due to the variation of the breakdown voltage Vz. Since the breakdown voltage Vz also affects the ratio of the positive and negative temperature characteristics of the Zener diode, the variation of the temperature characteristics of the Zener diode is affected by the variation of the absolute value of the breakdown voltage Vz. When the variation of the breakdown voltage Vz of the Zener diode is large, the variation of the temperature characteristics of the Zener diode tends to be large.As a result, the temperature characteristics of the reference voltage generation part may not be stable.

[0012] The present inventors discovered that there are two main factors that cause variations in the breakdown voltage Vz in conventional Zener diodes. The first factor is that the upper anode region was formed by two ion implantations, which resulted in a decrease in the impurity concentration profile of the anode region. The second factor is that the impurity concentration profile of the lower cathode region was not uniform. These two factors greatly increase the variation in the impurity concentration at the PN junction between the anode region and the cathode region, leading to a tendency for the variation in the breakdown voltage Vz to increase.

[0013] The main purpose of the present application is to suppress the variation of the breakdown voltage Vz of the Zener diode and thereby improve the performance of the semiconductor device.

[0014] Further objects and novel features will become apparent from the description of the present application text and the attached drawings.

[0015] The typical embodiments disclosed in the present application are briefly described as follows.

[0016] In one embodiment, a manufacturing method of a semiconductor device comprises: (a) forming a cathode region of a first conductivity type in a semiconductor substrate by ion implantation; (b) after (a), diffusing the cathode region through a first heat treatment; and (c) after (b), forming an anode region of a second conductivity type, opposite to the first conductivity type, in the semiconductor substrate by ion implantation. The cathode region is formed at a deeper position from the top surface of the semiconductor substrate than the anode region.

[0017] In one embodiment, the semiconductor device includes a cathode region of a first conductivity type, a well region of the first conductivity type, and an anode region of the second conductivity type opposite to the first conductivity type, each formed in the semiconductor substrate. The impurity concentration of the cathode region is higher than the impurity concentration of the well region. In plan view, the anode region includes the cathode region. In plan view, the well region includes the anode region and the cathode region. The well region is formed at a deeper position from the top surface of the semiconductor substrate than the anode region. The cathode region is formed at a deeper position from the top surface of the semiconductor substrate than the anode region and the well region.

[0018] According to one embodiment, the performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a semiconductor device in a first embodiment. Fig. 2 is a cross-sectional view showing the semiconductor device in the first embodiment. Fig. 3 is a cross-sectional view showing the semiconductor device in the first embodiment. Fig. 4 is a graph showing the impurity concentration profile of each of the anode region, the cathode region, and the well region in the first embodiment. Fig. 5 is a cross-sectional view showing the first application example of the Zener diode in the first embodiment. Fig. 6 is a cross-sectional view showing the second application example of the Zener diode in the first embodiment. Fig. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. Fig. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device according to Fig. 7 shows. Fig. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device according to Fig. 8 shows. Fig. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device according to Fig. 9 shows. Fig. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device according to Fig. 10 shows. Fig. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device according to Fig. 11 shows. Fig. 13 is a plan view showing a semiconductor device in a second embodiment. Fig. 14 is a cross-sectional view showing the semiconductor device in the second embodiment. Fig. 15 is a graph showing the impurity concentration profile of the cathode region in a third embodiment. DETAILED DESCRIPTION

[0019] In the following, embodiments will be described in detail with reference to the drawings. In all the drawings illustrating the embodiments, elements having the same functions are denoted by the same reference numerals, and repetitive descriptions thereof will be omitted. In the following embodiments, descriptions of the same or similar parts will not be repeated in principle unless particularly necessary.

[0020] Furthermore, the X-direction, Y-direction, and Z-direction described in this application intersect and are orthogonal to each other. In this application, the Z-direction refers to the up-and-down direction, depth direction, height direction, or thickness direction of a particular structure. Furthermore, the term "plan view" used in this application means that the plane formed by the X-direction and Y-direction is a "plane," and the "plane" is viewed from the Z-direction. First Embodiment Structure of the Semiconductor Device

[0021] The semiconductor device (semiconductor chip) in the first embodiment will be described below with reference to the Fig. 1 to Fig. 4 described. Fig. Figure 1 shows a plan view of a Zener diode ZD included in the semiconductor device. Fig. 2 and Fig. 3 show cross-sectional views along the line AA shown in Fig. 1 is shown.

[0022] As in Fig. As shown in Figure 1, the Zener diode ZD includes an n-type cathode region NZ, a p-type anode region PZ, an n-type well region NW, an n-type high-concentration region NR, and an element isolation section STI. In plan view, the anode region PZ includes the cathode region NZ. The anode region PZ and the cathode region NZ constitute the main body of the Zener diode ZD.

[0023] The high-concentration NR region is separated from the anode region PZ and the cathode region NZ. The element isolation section STI is formed between the high-concentration NR region and the anode region PZ and surrounds both the high-concentration NR region and the anode region PZ. In plan view, the trough region NW includes the anode region PZ, the cathode region NZ, and the high-concentration NR region. The high-concentration NR region is electrically connected to the cathode region NZ via the trough region NW and serves as a contact portion of the cathode region NZ.

[0024] As in Fig. As shown in Figure 2, the Zener diode ZD is formed in a semiconductor substrate SUB. The semiconductor substrate SUB is made of silicon. Here, the semiconductor substrate SUB is a laminated body of a support substrate SB and a semiconductor layer NEP, but is not limited to the laminated body. The support substrate SB is a laminated body of, for example, a p-type silicon substrate and a p-type silicon layer formed on the silicon substrate by an epitaxial growth method. The semiconductor layer NEP is an n-type silicon layer formed on the support substrate SB by an epitaxial growth method.

[0025] The element isolation section STI is formed in the semiconductor substrate SUB. The element isolation section STI includes a trench and a dielectric film. The trench is formed in the semiconductor substrate SUB and extends to a predetermined depth from the top surface of the semiconductor substrate SUB. The dielectric film is buried in the trench. The dielectric film is, for example, a silicon oxide film.

[0026] The semiconductor substrate SUB includes an n-type isolation region NBL, a p-type isolation region PBL, and a p-type isolation region PiSO. The isolation region NBL is formed at a predetermined depth in the semiconductor substrate SUB and is surrounded by the isolation region PBL. The isolation region PiSO is connected to the isolation region PBL. The Zener diode ZD is surrounded by the element isolation section STI, the isolation region NBL, the isolation region PBL, and the isolation region PiSO and is electrically isolated from other semiconductor elements.

[0027] The n-type cathode region NZ, the p-type anode region PZ, the n-type well region NW, and the n-type high-concentration NR region are formed in the semiconductor substrate SUB. The well region NW has a higher impurity concentration than the semiconductor layer NEP. The high-concentration NR region is formed in the well region NW and has a higher impurity concentration than the well region NW. The well region NW is formed at a deeper position from the upper surface of the semiconductor substrate SUB than the anode region PZ. That is, the depth of the well region NW from the upper surface of the semiconductor substrate SUB is greater than the depth of the anode region PZ from the upper surface of the semiconductor substrate SUB. The side surfaces of both the high-concentration NR region and the anode region PZ are in contact with the element isolation portion STI.

[0028] The depth of the cathode region NZ from the top surface of the semiconductor substrate SUB is greater than the depth of the anode region PZ from the top surface of the semiconductor substrate SUB and the depth of the well region NW from the top surface of the semiconductor substrate SUB. The bottom of the cathode region NZ is located in the semiconductor layer NEP. The impurity concentration of the cathode region NZ is higher than the impurity concentration of the well region NW.

[0029] A silicide film SI is formed on the anode region PZ and the high concentration region NR.

[0030] Fig. 3 shows the main current path of the Zener diode ZD. As in Fig. As shown in Figure 3, the semiconductor device includes an anode electrode AE ​​and a cathode electrode CE. Although not shown, the semiconductor device includes an interlayer dielectric film, a plug layer, and wiring. The anode electrode AE ​​is electrically connected to the anode region PZ, and the cathode electrode CE is electrically connected to the high-concentration region NR. The interlayer dielectric film is formed on the semiconductor substrate SUB. The plug layer is formed in the interlayer dielectric film, and wiring is formed on the interlayer dielectric film. The cathode electrode CE and the anode electrode AE ​​are, for example, the plug layer. The cathode electrode CE and the anode electrode AE ​​are electrically connected to other semiconductor elements via the wiring. The plug layer is, for example, a conductive film mainly composed of a tungsten film.For example, the wiring is a conductive film mainly composed of an aluminum alloy film or a copper film.

[0031] As indicated by the arrows in Fig. 3, the main current path of the Zener diode ZD is a path from the cathode electrode CE through the high concentration region NR, the trough region NW, the cathode region NZ and the anode region PZ to the anode electrode AE.

[0032] A feature of the Zener diode ZD of the first embodiment is that the cathode region NZ is formed at a deeper position from the upper surface of the semiconductor substrate SUB than the well region NW. As described above, the current flowing through the Zener diode ZD flows through the low-concentration well region NW. Here, when the cathode region NZ is formed shallower than the well region NW, the proportion of the resistance of the well region NW in the current path becomes large. Since the resistance of the well region NW is higher than the resistance of the cathode region NZ, the total resistance of the current path becomes high, and the breakdown voltage Vz of the Zener diode ZD is likely to fluctuate. By forming the high-concentration cathode region NZ deep, the total resistance of the current path can be reduced, making it easier to suppress fluctuations in the breakdown voltage Vz.

[0033] In addition, when a breakdown occurs near the element isolation section STI, electrons and holes generated at the time of breakdown may be injected into the element isolation section STI. If a breakdown occurs repeatedly, the electrons and holes accumulated in the element isolation section STI may change the width of the depletion layer spreading at the PN junction in contact with the element isolation section STI, making it difficult to stabilize the breakdown voltage.

[0034] In the first embodiment, as shown in Fig. As shown in Figure 1, the anode region PZ overlaps the cathode region NZ in plan view, includes the cathode region NZ, and forms a PN junction with the cathode region NZ. In other words, the outer periphery of the cathode region NZ is surrounded by the anode region PZ. In other words, the outer periphery of the anode region PZ is separated from the outer periphery of the cathode region NZ by a distance L1 in the X direction, and the outer periphery of the anode region PZ is separated from the outer periphery of the cathode region NZ by a distance L2 in the Y direction. The distances L1 and L2 are, for example, 1 µm or more and 3 µm or less.

[0035] The anode region PZ, located near the element isolation portion STI, does not overlap the cathode region NZ, and no impurities configuring the cathode region NZ are injected. Because the anode region PZ and the cathode region NZ are arranged in this way, the impurity concentration of the anode region PZ that does not overlap the cathode region NZ is relatively higher than the impurity concentration of the anode region PZ that overlaps the cathode region NZ. Therefore, breakdown is more likely to occur at the PN junction between the anode region PZ and the cathode region NZ than at the PN junction between the anode region PZ near the element isolation portion STI and the well region NW. Therefore, the breakdown voltage can be stabilized.

[0036] Fig. Figure 4 shows the impurity concentration profiles of the anode region PZ and the cathode region NZ along the depth direction Pro1, which are shown in Fig. 3, and the impurity concentration profile of the trough region NW along the depth direction Pro2.

[0037] The inventors of the present application have found that the factors causing variation in the breakdown voltage Vz in a conventional Zener diode are the occurrence of a reduction in the impurity concentration profile of the anode region PZ and the non-uniformity of the impurity concentration profile of the cathode region NZ.

[0038] As described in detail in the "Manufacturing Method of a Semiconductor Device" described later, in the first embodiment, the anode region PZ is formed by single ion implantation, thereby steepening the concentration gradient of the impurity concentration profile of the anode region PZ. In other words, no reduction in the impurity concentration profile of the anode region PZ occurs. Furthermore, although no heat treatment is applied to the cathode region in a conventional Zener diode, by applying heat treatment to the cathode region NZ at a sufficient temperature and for a sufficient time, the impurity concentration profile of the cathode region NZ is made as uniform as possible.

[0039] As in Fig. As shown in Figure 4, compared to the cathode region of a conventional Zener diode, the impurity concentration profile of the cathode region NZ is more uniform at a certain depth from the top surface of the semiconductor substrate SUB to the cathode region NZ. For example, in the first embodiment, the depth of the cathode region NZ from the top surface of the semiconductor substrate SUB is greater than 0.5 µm. Between the depth of about 0.5 µm and the top surface of the semiconductor substrate SUB, the impurity concentration of the cathode region NZ is within the range of ±0.5 × 10 cm -3 For example, between the depth of 0.5 µm and the upper surface of the semiconductor substrate SUB, the impurity concentration of the cathode region NZ is within the range of 1 × 10 18 cm -3 up to 1 × 10 19 cm -3 .

[0040] In other words, the concentration gradient of the impurity concentration profile of the cathode region NZ is smaller than the concentration gradient of the impurity concentration profile of the trough region NW. Furthermore, half the width of the impurity concentration profile of the anode region PZ and half the width of the impurity concentration profile of the trough region NW are smaller than half the width of the impurity concentration profile of the cathode region NZ.

[0041] Therefore, compared to the cathode region of a conventional Zener diode, since the impurity concentration profile of the cathode region NZ is more uniform, the impurity concentration profiles of the cathode region NZ and the anode region PZ intersect at an angle close to the vertical. For example, the impurity concentration profiles of the cathode region NZ and the anode region PZ intersect at an angle of 70 degrees or more and 90 degrees or less. Therefore, the variation in the impurity concentration at the PN junction is reduced, and the variation in the breakdown voltage Vz can be suppressed, which can improve the performance of the semiconductor device.

[0042] First application example of a Zener diode ZD Fig. 5 is a cross-sectional view of a reference voltage generating part of a DESAT detection circuit, to which the Zener diode ZD and an emitter-base diode EBD connected in the forward direction are applied. The emitter-base diode EBD is formed in a region different from the Zener diode ZD in the semiconductor device.

[0043] The structure of the emitter-base diode (EBD) is described below. The emitter-base diode (EBD) has an n-type well region (NV), a p-type base region (PB), an n-type collector region (NC), an n-type emitter region (NE), and a p-type high-concentration region (PR). As shown in Fig. As shown in Figure 5, the well region NV and the base region PB are formed in the semiconductor substrate SUB. The collector region NC is formed in the well region NV. The collector region NC has a higher impurity concentration than the well region NV. The emitter region NE and the high-concentration region PR are formed in the base region PB. The high-concentration region PR has a higher impurity concentration than the base region PB.

[0044] A dielectric film IF1 is selectively formed on the semiconductor substrate SUB to expose the collector region NC, the emitter region NE, and the high-concentration region PR. The silicide film SI is formed on the upper surface of the semiconductor substrate SUB, which is exposed from the dielectric film IF1 and the element isolation portion STI.

[0045] That is, the silicide film SI is formed on the collector region NC, the emitter region NE and the high concentration region PR.

[0046] The well region NV and the collector region NC form the collector of the bipolar transistor, the base region PB and the high-concentration region PR form the base of the bipolar transistor, and the emitter region NE forms the emitter of the bipolar transistor. The emitter-base diode EBD is formed by electrically shorting the collector and base.

[0047] By electrically connecting the anode region PZ to the reference voltage GND, electrically connecting the high concentration region NR (cathode region NZ) to the emitter region NE, and electrically connecting the collector region NC and the high concentration region PR (base region PB) to the power supply voltage Vcc, the reference voltage generation part of the DESAT detection circuit is formed.

[0048] In the Zener diode ZD of the first embodiment, the variation in the breakdown voltage Vz of the Zener diode ZD is suppressed. Therefore, it is possible to implement the DESAT detection circuit that can prevent malfunction due to noise by narrowing the standard width of the DESAT detection voltage. Since the variation in the breakdown voltage Vz of the Zener diode ZD is suppressed, the variation in the temperature characteristics of the Zener diode ZD can also be suppressed, and the temperature characteristics of the reference voltage generation part can be stabilized. Second application example of a Zener diode ZD

[0049] Fig. Figure 6 is a cross-sectional view of the reference voltage generation part of the DESAT detection circuit, to which two Zener diodes ZD connected in the forward direction are applied. The two Zener diodes ZD are formed in different regions in the semiconductor device.

[0050] By electrically connecting one anode region PZ to the reference voltage GND, electrically connecting one high concentration region NR (cathode region NZ) to the other high concentration region NR (cathode region NZ), and electrically connecting the other anode region PZ to the power supply voltage Vcc, the reference voltage generation part of the DESAT detection circuit is formed.

[0051] Since the variation of the breakdown voltage Vz of the two Zener diodes ZD is suppressed, it is also possible in the second application example to realize the DESAT detection circuit that can prevent malfunction due to noise by reducing the standard width of the DESAT detection voltage. Manufacturing method of a semiconductor device

[0052] Hereinafter, each manufacturing step included in the manufacturing method of the semiconductor device in the first embodiment will be described using the Fig. 7 to Fig. 12 described.

[0053] First, as in Fig. 7, the semiconductor substrate SUB made of silicon is prepared. As described above, the semiconductor substrate SUB is a laminated body of the support substrate SB and the semiconductor layer NEP. By photolithography and ion implantation, the isolation region NBL and the isolation region PBL are selectively formed in the support substrate SB. The isolation region NBL and the isolation region PBL are arranged at a predetermined depth from the upper surface of the semiconductor substrate SUB. On the support substrate SB, the semiconductor layer NEP is formed by introducing n-type impurities using the epitaxial growth method. In this way, the semiconductor substrate SUB is prepared.

[0054] As in Fig. As shown in Figure 8, the element isolation section STI and the isolation region PiSO are formed in the semiconductor substrate SUB. First, using photolithography techniques and ion implantation, the p-type isolation region PiSO is selectively formed in the semiconductor substrate SUB.

[0055] Next, a trench is formed in the semiconductor substrate SUB using photolithography techniques and etching treatment. The trench is formed to overlap the isolation region PiSO. Next, a dielectric film is formed on the upper surface of the semiconductor substrate SUB, for example, by the CVD method, to fill the trench. The dielectric film is, for example, a silicon oxide film or a silicon nitride film. Next, using methods such as CMP (chemical mechanical polishing), the dielectric film formed outside the trench is removed. Thus, the element isolation portion STI, which includes the trench and the dielectric film, is formed in the semiconductor substrate SUB.

[0056] As in Fig. As shown in Figure 9, an n-type cathode region NZa is formed in the semiconductor substrate SUB. First, a resist pattern RP1 is formed on the upper surface of the semiconductor substrate SUB. Next, the cathode region NZa is formed in the semiconductor substrate SUB by performing ion implantation using the resist pattern RP1 as a mask. Next, the resist pattern RP1 is removed by ashing.

[0057] The ion implantation of the cathode region NZa is performed using phosphorus (P) as an impurity, for example, with an implantation energy of 70 keV or more and 90 keV or less and a dose amount of 1.5 × 10 14 cm -2 or more and 6.0 × 10 14 cm -2 or less.

[0058] As in Fig. As shown in Figure 10, the cathode region NZa is diffused by heat treatment to form the cathode region NZ. The heat treatment is carried out in a nitrogen atmosphere, for example, at 1100 degrees Celsius or more for 60 minutes or longer. After the heat treatment, as shown in Fig. As shown in Figure 4, compared with the cathode region of a conventional Zener diode, the impurity concentration profile of the cathode region NZ becomes more uniform at a predetermined depth from the top surface of the semiconductor substrate SUB.

[0059] As in Fig. As shown in Figure 11, the n-type well region NW is selectively formed in the semiconductor substrate SUB using photolithography techniques and ion implantation.

[0060] The ion implantation of the well region NW is performed using phosphorus (P) as an impurity, for example, with an implantation energy of 40 keV or more and 60 keV or less and a dose amount of 1.0 × 10 13 cm -2 or more and 5.0 × 10 13 cm -2 or less.

[0061] As in Fig. As shown in Figure 12, the p-type anode region PZ and the n-type high concentration region NR are selectively formed in the semiconductor substrate SUB using photolithography techniques and ion implantation.

[0062] The ion implantation of the anode region PZ is performed using boron difluoride (BF2) as an impurity, for example, with an implantation energy of 50 keV or more and 70 keV or less and a dose amount of 1.0 × 10 15 cm -2 or more and 5.0 × 10 15 cm -2 or less.

[0063] The ion implantation of the high concentration NR region is carried out using arsenic (As) as an impurity, for example, with an implantation energy of 30 keV or more and 50 keV or less and a dose amount of 1.0 × 10 15 cm -2 or more and 5.0 × 10 15 cm -2 or less.

[0064] The heat treatment is carried out in a nitrogen atmosphere, for example, at 900 degrees Celsius or more and 950 degrees Celsius or less for 1 second or more and 10 seconds or less. The impurity concentration profiles of the trough region NW and the anode region PZ after the heat treatment are shown in Fig. 4. Note that this heat treatment does not significantly change the impurity concentration profile of the cathode region NZ. Furthermore, since the ion implantation of the anode region PZ is performed by single ion implantation, the concentration gradient of the impurity concentration profile of the anode region PZ becomes steeper.

[0065] Through the above manufacturing steps, the Zener diode ZD is formed in the semiconductor substrate SUB.

[0066] Subsequently, the Fig. 2 is obtained by the following manufacturing steps. First, the dielectric film IF1, made of, for example, a silicon oxide film, is formed on the upper surface of the semiconductor substrate SUB, for example, by a CVD method. (For the dielectric film IF1, see the emitter base diode EBD in Fig. 5.) Then the dielectric film IF1 is selectively patterned by photolithography technique and etching treatment.

[0067] Next, using an existing salicide technique, the silicide film SI is formed in the region exposed by the dielectric film IF1 and the element isolation portion STI. That is, in the Zener diode ZD, the silicide film SI is formed on the anode region PZ and the high-concentration region NR. Second embodiment

[0068] In the following, a semiconductor device in the second embodiment using the Fig. 13 and Fig. 14. Note that in the following description, differences from the first embodiment will be mainly described, and the description of overlapping points with the first embodiment will be omitted.

[0069] In the first embodiment, the element isolation portion STI is formed between the high concentration region NR and the anode region PZ.

[0070] In the second embodiment, as shown in the Fig. 13 and Fig. As shown in Figure 14, the element isolation portion STI is not formed between the high-concentration region NR and the anode region PZ. The high-concentration region NR and the anode region PZ are separated from each other, and the side surfaces of the high-concentration region NR and the anode region PZ are in contact with the trough region NW.

[0071] As described above, when breakdown occurs repeatedly near the element isolation portion STI, electrons and holes generated at the time of breakdown accumulate in the element isolation portion STI, making it difficult to stabilize the breakdown voltage. Therefore, in the second embodiment, by not forming the element isolation portion STI where electrons and holes can be injected near the PN junction between the anode region PZ and the well region NW, the breakdown voltage can be further stabilized.

[0072] Since the current does not bypass the element isolation section STI, the current path of the second embodiment is also shorter than that of the first embodiment. The resistance component of the current path of the Zener diode ZD passing through the well region NW is reduced. Therefore, the total resistance value of the current path can be reduced, and the fluctuation of the breakdown voltage Vz can be further suppressed.

[0073] However, by not forming the element isolation portion STI when forming the silicide film SI, the silicide film SI is also formed on the well region NW located between the high-concentration region NR and the anode region PZ. Then, the anode electrode AE ​​and the cathode electrode CE are connected via the silicide film SI. (See Fig. 3).

[0074] Therefore, the dielectric film IF1 is patterned so that the dielectric film IF1 remains on the well region NW located between the high-concentration NR region and the anode region PZ. This can suppress the formation of the silicide film SI between the high-concentration NR region and the anode region PZ and selectively form the silicide film SI on the high-concentration NR region and the anode region PZ. THIRD EMBODIMENT

[0075] In the following, a semiconductor device in the third embodiment using Fig. 15. Note that in the following description, differences from the first embodiment will be mainly described, and the description of overlapping points with the first embodiment will be omitted.

[0076] In the first embodiment, in the manufacturing step of Fig. 9 the ion implantation of the cathode region NZa was carried out by a single ion implantation.

[0077] In the third embodiment, as in Fig. As shown in Figure 15, the ion implantation of the cathode region NZa is performed by multiple ion implantations using different implantation energies. Here, an example of forming the cathode region NZa by two ion implantations is illustrated, but the number of ion implantations can be three or more. The conditions of impurities and dose amounts for multiple ion implantations are the same as the conditions of the manufacturing step in Fig. 9.

[0078] By performing multiple ion implantations, it becomes possible to form the cathode region NZa at a deeper position than the cathode region NZa in the first embodiment. Even if multiple ion implantations are performed, by performing the heat treatment in Fig. 10, the impurity concentration profile of the cathode region NZ at a predetermined depth from the top surface of the semiconductor substrate SUB is more uniform than that of the cathode region of the conventional Zener diode. In the third embodiment, the depth of the cathode region NZ from the top surface of the semiconductor substrate SUB is greater than 1.0 µm, and the impurity concentration of the cathode region NZ is within the range of ±0.5 × 10 cm. -3 between a depth of 1.0 µm and the top surface of the semiconductor substrate SUB. For example, the impurity concentration of the cathode region NZ is within the range of 1 × 10 18 cm -3 up to 1 × 10 19 cm -3 .

[0079] Therefore, compared to the first embodiment, the technique of the third embodiment can form the cathode region NZ with a more uniform impurity concentration profile at a deeper position. The technique described in the third embodiment can be combined with the technique of the second embodiment.

[0080] Although the present invention has been described in detail based on the above-described embodiments, the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-097745

[0001] JP 2013-183039

[0005]

Claims

[1] A method of manufacturing a semiconductor device, the method comprising: (a) forming a first cathode region of a first conductivity type in a semiconductor substrate by a first ion implantation; (b) after (a), diffusing the first cathode region by a first heat treatment to form a second cathode region; and (c) according to (b), forming an anode region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate by a second ion implantation, wherein a depth of the second cathode region from a top surface of the semiconductor substrate is greater than a depth of the anode region from the top surface of the semiconductor substrate. [2] The method of claim 1, wherein in plan view the anode region includes the second cathode region. [3] The method of claim 2, wherein the anode region forms a PN junction with the second cathode region. [4] The method according to claim 1, wherein in (c) the second ion implantation is performed by single ion implantation. [5] The method according to claim 1, wherein the first heat treatment is carried out at a temperature of 1100 degrees Celsius or higher and for 60 minutes or longer. [6] Method according to claim 5, wherein the depth of the second cathode region is greater than 0.5 µm, and wherein between the upper surface of the semiconductor substrate and a depth of 0.5 µm an impurity concentration of the second cathode region is within a range of ±0.5 × 10 cm -3 lies. [7] The method of claim 1, wherein in (a) the first ion implantation is performed by multiple ion implantations using different implantation energies. [8] A method according to claim 1, comprising: (d) between (b) and (c), forming a well region of the first conductivity type in the semiconductor substrate by a third ion implantation, wherein an impurity concentration of the second cathode region is higher than an impurity concentration of the well region, wherein in plan view the trough region includes the anode region and the second cathode region, wherein a depth of the well region from the upper surface of the semiconductor substrate is greater than the depth of the anode region, wherein the depth of the second cathode region is greater than the depth of the trough region. [9] The method of claim 8, wherein a concentration gradient of a concentration profile of the second cathode region is smaller than a concentration gradient of a concentration profile of the trough region. [10] The method of claim 8, wherein half a width of a concentration profile of the anode region and half a width of a concentration profile of the trough region are smaller than half a width of a concentration profile of the second cathode region. [11] A method according to claim 8, comprising: (e) after (d), forming a high concentration region of the first conductivity type in the well region by a fourth ion implantation, wherein an impurity concentration of the high concentration region is higher than the impurity concentration of the trough region, and wherein the high concentration region is separated from the anode region and the second cathode region. [12] A method according to claim 11, comprising: (f) before (a), forming a trench in the semiconductor substrate; and (g) between (f) and (a), filling the trench with a first dielectric film to form an element isolation portion including the trench and the first dielectric film, wherein the element isolation portion is formed between the high concentration region and the anode region, and wherein a side surface of the anode region is in contact with the element insulating portion. [13] The method of claim 11, wherein a side surface of the anode region is in contact with the trough region. [14] A semiconductor device comprising: a cathode region of a first conductivity type formed in a semiconductor substrate; a well region of the first conductivity type formed in the semiconductor substrate; and an anode region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate, wherein an impurity concentration of the cathode region is higher than an impurity concentration of the well region, where in plan view the anode area includes the cathode area, where in plan view the trough area includes the anode area and the cathode area, wherein a depth of the well region from a top surface of the semiconductor substrate is greater than a depth of the anode region from the top surface of the semiconductor substrate, and wherein a depth of the cathode region from the top surface of the semiconductor substrate is greater than the depth of the anode region and the depth of the well region. [15] A semiconductor device according to claim 14, where the depth of the cathode region is greater than 0.5 µm, and wherein between the upper surface of the semiconductor substrate and a depth of 0.5 µm, the impurity concentration of the second cathode region is within a range of ±0.5 × 10 cm -3 lies. [16] The semiconductor device according to claim 14, wherein a concentration gradient of a concentration profile of the cathode region is smaller than a concentration gradient of a concentration profile of the well region. [17] The semiconductor device according to claim 14, wherein a half width of a concentration profile of the anode region and a half width of a concentration profile of the well region are smaller than a half width of a concentration profile of the cathode region. [18] A semiconductor device according to claim 14, comprising: a high concentration region of the first conductivity type formed in the trough region, wherein an impurity concentration of the high concentration region is higher than the impurity concentration of the trough region, and wherein the high concentration region is separated from the anode region and the cathode region. [19] A semiconductor device according to claim 18, comprising: an element isolation area comprising: a trench formed in the semiconductor substrate; and a first dielectric film buried in the trench, wherein the element isolation portion is formed between the high concentration region and the anode region, and wherein a side surface of the anode region is in contact with the element insulating portion. [20] The semiconductor device according to claim 18, wherein a side surface of the anode region is in contact with the well region.

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