Semiconductor package with an electrical contact element for downwardly connecting a contact pad to a substrate

Abstract

A semiconductor device package (20; 30) comprising a semiconductor transistor die comprising a first main surface, a second main surface opposite the first main surface, a first contact pad (11B) arranged on the first main surface, and a second contact pad (11A) arranged on the second main surface, an encapsulant (12) embedding the semiconductor transistor die, wherein the encapsulant (12) comprises a first main surface and a second main surface opposite the first main surface, wherein the second main surface of the encapsulant (12) is coplanar with the second main surface of the semiconductor transistor die (11), and an electrical contact element (15; 25) connected to the encapsulant (12), wherein the electrical contact element (15; 25) comprises a first horizontal portion (15A; 25A) and side portions (15B; 25B) connected to opposite side edges of the first horizontal portion (15A;25A), wherein the first horizontal portion (15A; 25A) is connected to the second main surface of the encapsulant (12); and wherein the side portions (15B; 25B) extend along first opposite side surfaces of the encapsulant (12) and are configured as first electrical contact elements.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor package and a semiconductor module including the semiconductor package. BACKGROUND

[0002] Power semiconductor packages comprise a power semiconductor die, specifically a power semiconductor transistor die, embedded in a molding compound. The contact pads of the semiconductor transistor die, such as the source pad and the drain pad, are connected to external contact elements that enable the package to be mounted on a substrate, such as a printed circuit board (PCB). Due to the high currents of up to 10A and higher flowing in the load path of the semiconductor transistor, excessive heat is generated that must be dissipated efficiently. Conducting the high electrical currents and simultaneously dissipating the excess heat requires an improved electrical connection routing concept.

[0003] For these and other reasons, there is a need for the present disclosure.

[0004] A first aspect of the present disclosure relates to a semiconductor device package comprising a semiconductor transistor die comprising a first main surface, a second main surface opposite the first main surface, a first contact pad arranged on the first main surface, and a second contact pad arranged on the second main surface, an encapsulant embedding the semiconductor transistor die, wherein the encapsulant comprises a first main surface and a second main surface opposite the first main surface, wherein the second main surface of the encapsulant is coplanar with the second main surface of the semiconductor transistor die, and an electrical contact element connected to the encapsulant, wherein the electrical contact element comprises a first horizontal portion and side portions, wherein side portions are connected to opposite side edges of the first horizontal portion,wherein the first horizontal portion is connected to the second main surface of the encapsulant, and wherein the side portions extend along first opposite side surfaces of the encapsulant and are configured as first electrical contact elements.

[0005] According to an embodiment of the semiconductor package of the first aspect, the side portions of the electrical contact element each comprise a vertical portion connected to the first horizontal portion and second horizontal portions connected to the vertical portions, wherein outer surfaces of the second horizontal portions are coplanar with the first main surface of the encapsulant.

[0006] According to an embodiment of the semiconductor housing of the first aspect, the side sections of the electrical contact element each comprise a vertical section connected to the horizontal section, wherein the vertical sections extend beyond the first main surface of the encapsulant.

[0007] According to an embodiment of the semiconductor package of the first aspect, one or more side portions are connected to the opposite side edges of the first horizontal portion.

[0008] According to one embodiment of the semiconductor package of the first aspect, the package further comprises second electrical contact elements connected to the first contact pad of the semiconductor transistor die. According to one example thereof, the second electrical contact elements are partially embedded in the encapsulant and extend through at least one second side surface of the encapsulant, which is oriented perpendicular to the first side surfaces of the encapsulant. According to another example thereof, the second electrical contact elements extend through two opposite side surfaces, both of which are perpendicular to the first opposite side surfaces of the encapsulant.

[0009] According to an embodiment of the semiconductor device of the first aspect, the semiconductor transistor die comprises one or more of a vertical semiconductor transistor die, a power semiconductor transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die, in particular a SiC transistor die or a GaN transistor die.

[0010] According to an embodiment of the semiconductor device of the first aspect, the first contact pad of the semiconductor transistor die is a source / emitter contact pad and the second contact pad is a drain / collector contact pad.

[0011] According to an embodiment of the semiconductor device of the first aspect, the horizontal portion of the electrical contact element is connected to the second main surface of the encapsulant by means of a solder layer, a sinter layer or an adhesive layer.

[0012] A second aspect of the present disclosure relates to a semiconductor device comprising a substrate and a semiconductor package according to the first aspect mounted on the substrate.

[0013] According to an embodiment of the semiconductor device of the second aspect, the substrate comprises electrical contact surfaces, wherein the second horizontal portions of the electrical contact element are connected to the electrical contact surfaces of the substrate.

[0014] According to an embodiment of the semiconductor device of the second aspect, the substrate comprises through holes, wherein lower ends of the vertical portions of the electrical contact element are inserted through the through holes of the substrate.

[0015] According to an embodiment of the semiconductor device of the second aspect, the substrate comprises a circuit board.

[0016] According to an embodiment of the semiconductor device of the second aspect, the device further comprises a heat sink mounted on the surface of the first horizontal portion of the electrical contact element of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description.

[0018] The elements of the drawings are not necessarily to scale relative to one another. Like reference numerals indicate corresponding, similar parts. Fig. 1 includes Fig. 1A and Fig. 1B and shows a perspective view of a semiconductor package with an exposed upper contact pad of a semiconductor chip (A) and an electrical contact element intended to be connected to the contact pad (B). Fig. 2 includes Fig. 2A and Fig. 2B and shows a semiconductor package to be mounted by surface mount technology (A) and a semiconductor package to be mounted by through-hole technology. Fig. 3 includes Fig. 3A and Fig. 3B and shows the semiconductor package of Fig. 2A, which is mounted on a substrate (A), and the semiconductor package of Fig. 2B, which is mounted on a substrate (B). DESCRIPTION OF EMBODIMENTS

[0019] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the disclosure may be practiced. In this regard, directional terminology such as "top," "bottom," "front," "back," etc., is used with reference to the orientation of the described figure(s). Because components of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure.The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0020] It is understood that the features of the various exemplary embodiments described herein may be combined with one another unless expressly stated otherwise.

[0021] As used in this specification, the terms "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" are not intended to imply that the elements or layers must be brought into direct contact with each other; intermediate elements or layers may be provided between the "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" elements. However, according to the disclosure, the above-mentioned terms may optionally also have the specific meaning that the elements or layers are brought into direct contact with each other, i.e., that no intermediate elements or layers are provided between the "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" elements.

[0022] Furthermore, the word "over," used in reference to a part, element, or layer of material formed or disposed "over" a surface, may be used herein to mean that the part, element, or layer of material is disposed "indirectly upon" (e.g., placed, formed, deposited, etc.) the implied surface, with one or more additional parts, elements, or layers disposed between the implied surface and the part, element, or layer of material. However, the word "over," used in reference to a part, element, or layer of material formed or disposed "over" a surface, may optionally also have the specific meaning that the part, element, or layer of material is disposed "directly upon," e.g., in direct contact with, the implied surface (e.g., placed, formed, deposited, etc.). DETAILED DESCRIPTION

[0023] Fig. 1 includes Fig. 1A and Fig. 1B and shows a perspective view of a semiconductor package with an exposed upper contact pad of a semiconductor chip (A) and an electrical contact element intended to be connected to the contact pad (B).

[0024] The Fig. The semiconductor package 10 shown in Figure 1A comprises a semiconductor chip, of which only the outwardly exposed contact pad 11A on an upper first main surface of the semiconductor chip is visible. The contact pad 11A may, for example, be the drain pad. Otherwise, the semiconductor chip is embedded in an encapsulant 12 such that a source pad and a gate pad, both arranged on a second lower main surface of the semiconductor chip, are covered by the encapsulant 12. The source pad and the gate pad are electrically connected to a plurality of pins 14 extending through opposite side surfaces of the encapsulant. In the Fig. In the example shown in Figure 1, the pins 14 include horizontal outer ends, so that they are configured to be connected to a PCB according to the surface mount technology. However, it is also possible for the outer ends of the pins to be formed vertically, so that they are configured to be connected to a PCB according to the through-hole technology.

[0025] The semiconductor chip may comprise one or more of a vertical semiconductor transistor die, a power semiconductor transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die, in particular a SiC transistor die or a GaN transistor die.

[0026] The encapsulant 12 may be made of a conventional molding compound, such as a resin material, in particular an epoxy resin material. Furthermore, the encapsulant 12 may be made of a thermally conductive material to enable efficient heat dissipation to external application heat sinks. The material of the encapsulant 12 may, in particular, comprise a resin such as an epoxy resin material filled with particles, such as SiO or other ceramic particles, or thermally conductive particles, such as Al2O3, BN, AlN, Si3N4, diamond, or any other thermally conductive particles, to increase the thermal conductivity of the encapsulant 12.

[0027] The Fig. The electrical contact element 15 shown in Figure 1B comprises a plate made of a metal, such as copper. The electrical contact element 15 comprises a central portion 15A and opposite side portions 15B connected to opposite edges of the central portion 15A. Fig. The example shown in Figure 1B shows 4 side sections on each side of the central section 15A. However, any other integer number of side sections is also possible, even if only one side section on each side is conceivable.

[0028] As in Fig. As can be seen in Figure 2, the electrical contact element 15 is intended to be connected to the exposed upper contact pad 11A of the semiconductor chip 11. In particular, the dimensions of the central portion 15A are preferably such that the horizontal portion 15A completely covers the contact pad 12A. It may be provided that grooves are formed in the surface at the transitions between the central portion 15A and the side portions 15B to facilitate subsequent bending of the side portions.

[0029] Fig. 2 includes Fig. 2A and Fig. 2B and shows a semiconductor device package to be mounted by surface mount technology (A) and a semiconductor package to be mounted by through-hole technology.

[0030] The Fig. 2A comprises a semiconductor package 10 such as that shown in Fig. 1A. The semiconductor package 10 comprises a semiconductor chip 11 having a first upper main surface and a second lower main surface opposite the first main surface. The semiconductor chip 11 further comprises a drain pad 11A arranged on the first main surface, a source pad 11B, and a gate pad 11C, both arranged on the second main surface. The semiconductor package 10 further comprises an encapsulant 12, wherein the semiconductor chip is embedded in the encapsulant such that the source pad 12B and a gate pad 12C are both covered by the encapsulant 12. The source pad is connected to a plurality of electrical connectors 13, and the gate pad is connected to one electrical connector 13. There may also be a source / sense pad, which is also connected to an electrical connector 13. The electrical connectors 13 are connected to the pins 14 arranged in Fig. 1A. The encapsulant 12 includes a first lower major surface and a second upper major surface. The drain pad 11A is exposed through the encapsulant 12 on the second upper major surface.

[0031] An electrical contact element 15 such as that in Fig. 1B is connected to the semiconductor package 10. In particular, the electrical contact element 15 comprises a first horizontal portion 15A and side portions 15B, wherein the side portions 15B are connected to opposite side edges of the first horizontal portion 15A. The first horizontal portion 15A is connected to the second main surface of the encapsulant 12 and thus to the exposed drain pad 11A of the semiconductor chip 11. The side sections 15B extend along first opposite side surfaces of the encapsulant 12. The side sections 15B of the electrical contact element 15 each comprise a vertical section 15B.1 connected to the first horizontal section 15A, and second horizontal sections 15B.2 connected to the vertical sections 15B.1, wherein outer surfaces of the second horizontal sections 15B.2 are coplanar with the first main surface of the encapsulant 12.

[0032] The semiconductor device package 20 is thus configured to be used as a surface mount device (SMD) which may later be used in conjunction with Fig. 3 can be seen.

[0033] The Fig. 2B is similar to the semiconductor device package 20 of Fig. 2A and differs therefrom only with respect to the structure of the electrical contact element 25, in particular the side sections 25B. The electrical contact element 25 comprises a first horizontal section 25A and side sections 25B, wherein the side sections 25B are connected to opposite side edges of the first horizontal section 25A. The first horizontal section 25A is connected to the second main surface of the encapsulant 12 and thus to the exposed drain pad 11A of the semiconductor chip 11. The side sections 25B extend along first opposite side surfaces of the encapsulant 12. The side sections 25B of the electrical contact element 25 each comprise a vertical section 25B which is connected to the horizontal section 25A, wherein the vertical sections 25B extend beyond the first main surface of the encapsulant 12.

[0034] The semiconductor device package is thus configured to be used as a through-hole device (TMD) which may later be used in conjunction with Fig. 3 can be seen.

[0035] An important feature of the semiconductor device packages 20 and 30 is that the electrical connector 15 or 25 has both an electrical function in the form of electrically contacting the semiconductor die 12 and dissipates the excessive heat generated during operation downwardly via the PCB or alternatively upwardly via a heat sink applied to the upper surface of the horizontal section.

[0036] Another important feature of the semiconductor device packages 20 and 30 is that the external conductors 14 and 15B or 25B are orthogonal to each other. While the external conductors 15B and 25B, as in Fig. 2A and Fig. 2B, the external pins 14, which are connected to the electrical connectors 13, are oriented perpendicular to the image plane. This results in a multiplication of the contacts between the electrical connectors 15 and 25 and the PCB, and thus, in addition to improved heat dissipation, a significant improvement in electrical performance, particularly a higher Imax value and a reduced Ron value.

[0037] Fig. 3 includes Fig. 3A and Fig. 3B and shows the semiconductor package of Fig. 2A, which is mounted on a substrate (A), and the semiconductor package of Fig. 2B, which is mounted on a substrate (B).

[0038] Fig. 3A shows a semiconductor module 40 with a substrate 41 and a semiconductor device package 20 such as that shown in Fig. 2A. The substrate 41 includes electrical contact pads, wherein the second horizontal portions 15B of the electrical contact element 15 of the semiconductor device package 20 are electrically connected to the electrical contact pads of the substrate 41. The connection of these elements can be carried out using a solder reflow process. It can be provided that the semiconductor device package 20 is first applied to the substrate 41 and then the electrical connector 15 is applied to the package 20 and connected to the electrical contact pads of the substrate 41. A simultaneous reflow soldering process can then be used to connect the electrical connector 15 to the package 20 and to the electrical contact pads. The substrate 41 can be a printed circuit board (PCB). Alternatively, the electrical connector 15 can also be glued to the package 20.This can then also be done before connecting to the substrate 41, so that in this case the electrical connector 15 with the housing 20 attached thereto is connected to the substrate 41.

[0039] Fig. 3B shows a semiconductor module 50 with a substrate 51 and a semiconductor device package 30 such as that shown in Fig.2B. The substrate 51 includes through-holes, and lower ends of the vertical portions 25B of the electrical contact element are inserted through these through-holes and connected thereto using a soldering process. It may be arranged that the semiconductor device package 30 is first applied to the substrate 51, and then the electrical connector 25 is applied to the package 30 and inserted through the through-holes. A simultaneous reflow soldering process may then be used to connect the electrical connector 25 to the package 30 in the same way as to the through-holes. Wave soldering, for example, may be used to connect to the through-holes. Alternatively, the electrical connector 25 may also be glued to the package 30.This can then also be done before connecting to the substrate 51, so that in this case the electrical connector 15 with the housing 30 attached thereto is connected to the substrate 51.

[0040] The substrate 41 or 51 may comprise a printed circuit board (PCB).

[0041] The semiconductor module 40 or 50 may further comprise a heat sink mounted on the surface of the first horizontal portion 15A or 25A of the electrical contact element 15 or 25 of the semiconductor package 10 or 20. EXAMPLES

[0042] Specific examples of the present disclosure are described below.

[0043] Example 1 is a semiconductor package comprising a semiconductor transistor die comprising a first main surface, a second main surface opposite the first main surface, a first contact pad arranged on the first main surface, and a second contact pad arranged on the second main surface, an encapsulant embedding the semiconductor transistor die, wherein the encapsulant comprises a first main surface and a second main surface opposite the first main surface, wherein the second main surface of the encapsulant is coplanar with the second main surface of the semiconductor transistor die, and an electrical contact element connected to the encapsulant, wherein the electrical contact element comprises a first horizontal portion and side portions connected to opposite side edges of the first horizontal portion,wherein the first horizontal portion is connected to the second main surface of the encapsulant, and wherein the side portions extend along first opposite side surfaces of the encapsulant and are configured as first electrical contact elements.

[0044] Example 2 is a semiconductor package according to Example 1, wherein the side portions of the electrical contact element each comprise a vertical portion connected to the first horizontal portion and second horizontal portions connected to the vertical portions, wherein outer surfaces of the second horizontal portions are coplanar with the first major surface of the encapsulant.

[0045] Example 3 is a semiconductor package according to Example 1, wherein the side portions of the electrical contact element each comprise a vertical portion connected to the horizontal portion, the vertical portions extending beyond the first main surface of the encapsulant.

[0046] Example 4 is a semiconductor package according to any of the preceding examples, wherein one or more side portions are connected to the opposite side edges of the first horizontal portion.

[0047] Example 5 is a semiconductor package according to any of the preceding examples, further comprising second electrical contact elements connected to the first contact pad of the semiconductor transistor die.

[0048] Example 6 is a semiconductor package according to Example 5, wherein the second electrical contact elements are partially embedded in the encapsulant and extend through at least one second side surface of the encapsulant that is oriented perpendicular to the first side surfaces of the encapsulant.

[0049] Example 7 is a semiconductor package according to Example 6, wherein the second electrical contact elements extend through two opposite side surfaces, both of which are perpendicular to the first opposite side surfaces of the encapsulant.

[0050] Example 8 is a semiconductor package according to any one of the preceding examples, wherein the semiconductor transistor die comprises one or more of a vertical semiconductor transistor die, a power semiconductor transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die, in particular a SiC transistor die or a GaN transistor die.

[0051] Example 9 is a semiconductor package according to any one of the preceding examples, wherein the first contact pad of the semiconductor transistor die is a source / emitter contact pad and the second contact pad is a drain / collector contact pad.

[0052] Example 10 is a semiconductor package according to any one of the preceding examples, wherein the horizontal portion of the electrical contact element is connected to the second main surface of the encapsulant by means of a solder layer, a sinter layer, or an adhesive layer.

[0053] Example 11 is a semiconductor module comprising a substrate and a semiconductor package according to any one of the preceding claims mounted on the substrate.

[0054] Example 12 is a semiconductor module according to Example 7 in conjunction with Example 2 or any of Examples 3 to 6 relating to Example 2, wherein the substrate comprises electrical contact pads, wherein the second horizontal portions of the electrical contact element are connected to the electrical contact pads of the substrate.

[0055] Example 13 is a semiconductor module according to Example 7 in conjunction with Example 3 or any of Examples 4 to 6 relating to Example 3, wherein the substrate comprises through holes, wherein lower ends of the vertical portions of the electrical contact element are inserted through the through holes of the substrate.

[0056] Example 14 is a semiconductor module according to any one of Examples 11 to 13, wherein the substrate comprises a circuit board.

[0057] Example 15 is a semiconductor module according to any one of Examples 11 to 14, further comprising a heat sink mounted on the surface of the first horizontal portion of the electrical contact element of the semiconductor package.

[0058] Although a particular feature or aspect of an embodiment of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for a given or particular application. Furthermore, to the extent that the terms "comprising," "having," "with," or other variations thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." Further, it is to be understood that embodiments of the disclosure may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programming means.Furthermore, the term "exemplary" is intended merely as an example and not as the best or optimal. It is further understood that features and / or elements depicted herein are illustrated with specific dimensions relative to one another for the purpose of simplicity and ease of understanding, and that actual dimensions may differ significantly from those illustrated herein.

[0059] Although specific embodiments have been illustrated and described herein, it will be understood by one of ordinary skill in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, this disclosure is intended to be limited only by the claims and the equivalents thereof.

Claims

[1] Semiconductor housing (20; 30) with - a semiconductor transistor die (11) having a first main surface, a second main surface opposite the first main surface, a first contact pad (11B) arranged on the first main surface, and a second contact pad (11A) arranged on the second main surface; - an encapsulant (12) embedding the semiconductor transistor die, the encapsulant (12) comprising a first main surface and a second main surface opposite the first main surface, the second main surface of the encapsulant (12) being coplanar with the second main surface of the semiconductor transistor die (11); and - an electrical contact element (15; 25) connected to the encapsulant (12), wherein the electrical contact element (15; 25) comprises a first horizontal portion (15A; 25A) and side portions (15B; 25B) connected to opposite side edges of the first horizontal portion (15A; 25A), wherein the first horizontal portion (15A; 25A) is connected to the second main surface of the encapsulant (12); and wherein the side portions (15B; 25B) extend along first opposite side surfaces of the encapsulant (12) and are configured as first electrical contact elements. [2] Semiconductor package (20) according to claim 1, wherein the side sections (15B) of the electrical contact element (15) each comprise a vertical section (15B.1) connected to the first horizontal section (15A) and second horizontal sections (15B.2) connected to the vertical sections (15B.1), wherein outer surfaces of the second horizontal sections (15B.2) are coplanar with the first main surface of the encapsulant (12). [3] The semiconductor package (30) of claim 1, wherein the side portions (25B) of the electrical contact element (25) each comprise a vertical portion connected to the horizontal portion (25A), the vertical portions extending beyond the first major surface of the encapsulant (12). [4] A semiconductor package (20; 30) according to any one of the preceding claims, wherein one or more side portions (15B; 25B) are connected to the opposite side edges of the first horizontal portion (15A; 25A). [5] Semiconductor package (20; 30) according to one of the preceding claims, further comprising second electrical contact elements (14) connected to the first contact pad of the semiconductor transistor die (11). [6] Semiconductor package (20; 30) according to claim 5, wherein the second electrical contact elements (14) are partially embedded in the encapsulant (12) and extend through at least one second side surface of the encapsulant (12) which is oriented perpendicular to the first side surfaces of the encapsulant (12). [7] Semiconductor package (20; 30) according to claim 6, wherein the second electrical contact elements (14) extend through two opposite side surfaces, both of which are perpendicular to the first opposite side surfaces of the encapsulant (12). [8] Semiconductor package (20; 30) according to one of the preceding claims, wherein the semiconductor transistor die (11) comprises one or more of a vertical semiconductor transistor die, a power semiconductor transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die, in particular a SiC transistor die or a GaN transistor die. [9] Semiconductor package (20; 30) according to one of the preceding claims, wherein the first contact pad of the semiconductor transistor die (11) is a source / emitter contact pad and the second contact pad is a drain / collector contact pad. [10] Semiconductor package (20; 30) according to one of the preceding claims, wherein the horizontal portion (15A; 25A) of the electrical contact element (15) is connected to the second main surface of the encapsulant (12) by means of a solder layer, a sintered layer or an adhesive layer. [11] Semiconductor module (40; 50) with a substrate (41; 51) and a semiconductor package (20; 30) according to one of the preceding claims, which is mounted on the substrate (41; 51). [12] Semiconductor module (40) according to claim 7 in conjunction with claim 2 or any one of claims 3 to 6 relating to claim 2, wherein the substrate (41) comprises electrical contact surfaces, wherein the second horizontal portions (15B) of the electrical contact element (15) are connected to the electrical contact surfaces of the substrate (41). [13] A semiconductor module (50) according to claim 7 in conjunction with claim 3 or any one of claims 4 to 6 relating to claim 3, wherein the substrate (51) comprises through-holes, lower ends of the vertical portions (25B) of the electrical contact element (25) being inserted through the through-holes of the substrate (51). [14] Semiconductor module (40; 50) according to one of claims 11 to 13, wherein the substrate (41; 51) comprises a printed circuit board. [15] Semiconductor module (40; 50) according to one of claims 11 to 14, further comprising a heat sink mounted on the surface of the first horizontal portion (15A; 25A) of the electrical contact element (15; 25) of the semiconductor package (20; 30).

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