Semiconductor package with adiabatic trough structure

Abstract

In one embodiment, a semiconductor package can include a photonic integrated circuit (PIC) die comprising a wavelength modulator and a heating element thermally coupled to the wavelength modulator. The semiconductor package can also include an interconnect structure on the PIC die, wherein the interconnect structure can comprise multiple conductive structural elements and a void. In a top view, the void overlaps the heating element and the wavelength modulator. The package can further include multiple conductive connectors above the interconnect structure, which are electrically connected to the multiple conductive structural elements.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US application No. 63 / 665,334 filed on June 28, 2024, which is hereby incorporated by reference into the present text. BACKGROUND

[0002] Electrical signal transmission and processing are among the techniques used for signal transmission and processing. Optical signal transmission and processing have been increasingly used in recent years, particularly thanks to the use of fiber optic applications for signal transmission.

[0003] Optical signaling and processing are typically combined with electrical signaling and processing to provide fully featured applications. For example, optical fibers can be used for long-distance signal transmission, while electrical signals can be used for short-distance signal transmission, as well as for processing and control. Accordingly, devices that integrate optical and electrical components are developed for converting between optical and electrical signals and for processing both. These packages can therefore include both optical (photonic) dies with optical devices and electronic dies with electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion.

[0005] Fig. Figures 1 to 6B illustrate the formation of a photonic IC die (Photonic Integrated Circuit, PIC die) at various stages of processing according to some embodiments.

[0006] Fig. Figures 7A to 10 illustrate cross-sectional views of semiconductor package structures with various arrangements of adiabatic troughs and thermal insulation structure elements according to some embodiments.

[0007] Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 to Fig. Figure 19 illustrates the formation of a PIC die at various stages of processing according to some embodiments.

[0008] Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28, Fig. 29, Fig. 30 to Fig. Figure 31 illustrates cross-sectional views of semiconductor package structures integrating photonic and electronic components with thermal management structural elements, according to some embodiments.

[0009] Fig. 32 and Fig. Figure 33 illustrates cross-sectional views of semiconductor package structures integrating photonic and electronic components with thermal management structural elements, according to some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed.

[0011] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0012] The semiconductor industry is constantly evolving; devices are becoming ever smaller, faster, and more complex. One area where this growth is taking place is silicon photonics, which integrates optical components with conventional electronic circuits. This integration allows for faster data transmission and processing, which can be advantageous for applications in telecommunications, data centers, and high-performance computing. As these devices become increasingly sophisticated, challenges arise with regard to thermal management.

[0013] Thermal management can be critical in silicon photonic devices due to the presence of sensitive optical components, such as wavelength modulators. These modulators may require precise temperature control to function effectively. Conventional heat dissipation methods that may work well in purely electronic devices may not be as effective when applied to integrated photonic-electronic systems. Excessive heat can lead to performance issues, reduced component lifetime, and device malfunctions.

[0014] This disclosure describes a thermal management approach through a packaging design. This design comprises a photonic integrated circuit (PIC) die that includes a wavelength modulator and a heating element. The heating element is thermally coupled to the modulator, which enables temperature control. The PIC die is integrated into the overall package structure in a specific manner.

[0015] The package features an interconnect structure on the top side of the PIC die. This interconnect structure includes conductive structural elements for electrical connections and a void. This void, or metal-free region, also known as an "adiabatic trough," is positioned to overlap the heating element and wavelength modulator when viewed from above. The void can act as a thermal barrier, isolating the heat-sensitive components from the rest of the package.

[0016] To improve thermal management capabilities, the package can incorporate additional structural elements such as a thermal insulation bump (TIB) and a die-internal sealing ring. These structures can interact with the adiabatic trough to provide thermal insulation. The TIB can surround the adiabatic trough and form a buffer zone to limit heat propagation to other parts of the package. The die-internal sealing ring can help mitigate the degradation of passivation materials that might occur due to heat exposure.

[0017] The disclosed embodiments offer several advantages over current prior art alternatives. The adiabatic trough structure provides superior thermal insulation compared to conventional copper manifold solutions and effectively prevents overheating of polyimide and underfill materials. By reducing the risk of polyimide delamination, the present disclosure increases the overall reliability and longevity of silicon photonic packages. Unlike copper manifolds, which can reduce heating efficiency by up to 26%, this disclosure allows independent heating control for the microring modulator without interference from heat dissipation structures. The disclosed embodiments eliminate the need for additional lithography processes to define structural elements, potentially reducing production costs and complexity.The adiabatic trough, thermal insulation hump, and substrate bore can be implemented in various shapes (circular, rectangular, triangular, etc.) to suit different package designs. The combination of these elements provides a multi-layered approach to thermal management that addresses heat-related problems more effectively than existing solutions. This disclosure enables effective thermal management without compromising the performance of the microring modulator or other silicon photonic components. Finally, the design principles can be applied to various sizes and configurations of silicon photonic packages, thus adapting them to different product requirements.

[0018] Fig. Figures 1 to 6B illustrate the formation of a photonic die at various processing stages according to some embodiments. With reference to Fig. Figure 1 illustrates a cross-sectional view of a section of a photonic IC die (PIC die) 20 (which can be referred to as a photonic die 20) at an intermediate processing stage. The photonic die 20 is part of a semiconductor package structure designed for thermal management in silicon photonic devices. The other sections of the photonic die 20 are described in the Fig. Discussed 20-31.

[0019] The in Fig. The section of the photonic die 20 shown in Figure 1 features an interconnect structure 32. The interconnect structure 32 can comprise several conductive structural elements, such as metal conductors and vias, which enable electrical connections within the device. The interconnect structure 32 can include one or more dielectric layers 28, a heater 24, and a microring modulator 26. The heater 24 provides thermal energy for the operation of the microring modulator 26. The microring modulator 26 and the heater 24 are thermally coupled, allowing precise temperature control of the microring modulator 26.

[0020] The one or more dielectric layers 28 can contain silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or the like. A metal via 34 extends upward from the interconnect structure 32 through the one or more dielectric layers 28. The metal via 34 provides an electrical connection between the interconnect structure 32 and other components or layers of the device. The metal via 34 can be formed by a single-damascus process by creating an opening in the dielectric layers 28 and filling the opening with conductive materials. The conductive materials can include a diffusion barrier formed from TiN, TaN, Ti, Ta, or the like, and a metallic material such as tungsten, copper, cobalt, or the like.A planarization process, such as a CMP process or a mechanical grinding process, can be performed to remove excess conductive material. The remaining sections of the diffusion barrier and the metallic material form the via 34.

[0021] A dielectric layer 110 is formed on one or more dielectric layers 28. The dielectric layer 110 can be an oxide layer or another suitable dielectric material. A buffer layer is formed on the dielectric layer 110. The buffer layer 112 can be a single layer or multiple layers. For example, the buffer layer 112 can be a stacked layer of silicon nitride, bismuth silicate, and silicon nitride.

[0022] An opening 114 is formed through the buffer layer 112 and the dielectric layer 110, which is aligned with the metal via 34. This opening 114 extends from the top of the buffer layer 112 down to the dielectric layer 28. The opening 114 can be formed by any suitable etching or structuring process.

[0023] The in Fig. Figure 1 shows a section of the photonic die 20 and illustrates the arrangement of various components involved in the thermal management and optical modulation functions of the device. The specific arrangement of these components, including the heater 24, the microring modulator 26, and the interconnect structure 32, can vary depending on the specific design and performance requirements of the photonic die 20.

[0024] With reference to Fig. 2. A passivation layer 116 is formed and structured above the buffer layer 112. The passivation layer 116 can be composed of an organic dielectric material, which may be a polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like. The passivation layer 116 serves to protect the underlying layers and components from environmental factors such as moisture and impurities.

[0025] The passivation layer 116 is structured to form two openings: a trough opening 118A and a redistribution layer (RDL) opening 118B. The trough opening 118A is a larger cavity positioned above the heater 24 and the microring modulator 26. This opening is designed to create an air gap or an "adiabatic trough" in subsequent processing steps, which can act as a thermal barrier to insulate these heat-sensitive components from the rest of the package.

[0026] In addition to the trough opening 118A, the RDL opening 118B is a narrower opening. This opening is designed to facilitate the formation of a redistribution layer in subsequent processing steps. The redistribution layer can include conductive structural elements that provide electrical connections between different components and layers of the device.

[0027] The structuring of the passivation layer 116 to form the trough opening 118A and the RDL opening 118B can be achieved by any suitable process. For example, photolithography and etching techniques can be used to selectively remove sections of the passivation layer 116, thus creating the openings. The specific dimensions and shapes of these openings can vary depending on the design and performance requirements of the photonic die 20. In some cases, the trough opening 118A and the RDL opening 118B can be formed simultaneously in a single structuring step.

[0028] With reference to Fig. Figure 3 illustrates a cross-sectional view of the photonic die 20 at a subsequent processing stage. At this stage, a redistribution layer 120 is formed in the RDL aperture 118B. The redistribution layer 120 extends from the top of the passivation layer 116 down to the dielectric layer 28 and connects to the metal via 34. The redistribution layer 120 can be composed of a conductive material and can be formed by any suitable process, such as deposition and structuring. For example, the conductive materials forming the redistribution layer 120 can include a diffusion barrier layer made of TiN, TaN, Ti, Ta, or the like, as well as a metallic material such as tungsten, copper, cobalt, or the like.The redistribution layer 120 serves to provide electrical connections between different components and layers of the device.

[0029] The formation of the redistribution layer 120 in the RDL opening 118B results in a structure where the redistribution layer 120 and the trough opening 118A lie adjacent to each other within the passivation layer 116. This arrangement allows for the simultaneous management of electrical connectivity and thermal insulation within the photonic die 20. The redistribution layer 120 provides electrical pathways for the operation of the device, while the trough opening 118A, which remains as an air gap, can serve as a thermal barrier to isolate the heat-sensitive components, such as the heater 24 and the microring modulator 26, from the rest of the package.

[0030] The interconnect structure 32 may include an empty or metal-free region, which is the area of ​​the structure that lacks conductive structural elements. In the context of this disclosure, the recess opening 118A can be considered part of this metal-free region. The absence of conductive material in this region contributes to its function as a thermal barrier, as it reduces the potential for heat conduction through the interconnect structure 32. In some embodiments, the metal-free region—viewed from a top view—overlaps the heating element 24 and the wavelength modulator 26. This arrangement can ensure that the heat generated by these components is effectively insulated, thus improving the thermal management of the device.

[0031] With reference to Fig. 4. A second passivation layer 122 is formed and structured over the first passivation layer 116 and the redistribution layer 120. The second passivation layer 122 can be composed of similar materials to the first passivation layer 116, such as an organic dielectric material. The formation of the second passivation layer 122 can involve deposition processes, and the structuring can be achieved by photolithography and etching techniques or other suitable methods.

[0032] The second passivation layer 122 is structured to form a connector opening 124 and to enlarge the trough opening 118A. The connector opening 124 is designed to expose a section of the redistribution layer 120, which facilitates the formation of electrical connectors in subsequent processing steps. The specific dimensions and shapes of the connector opening 124 and the enlarged trough opening 118A can vary depending on the design and performance requirements of the photonic die 20.

[0033] With reference to Fig. In section 5, an electrical connector 126 is formed in the connector opening 124. The electrical connector 126 extends from the top of the passivation layer 122 down to the redistribution layer 120 and establishes an electrical connection between these layers. The electrical connector 126 can be composed of a conductive material and can be formed by any suitable process, such as deposition and structuring. The conductive materials can resemble the redistribution layer 120 described above. The electrical connector 126 comprises a metal pillar 128 and a solder region 130. The metal pillar 128 provides a conductive path for the electrical connector 126, while the solder region 130 enables the bonding of the electrical connector 126 to other components or layers of the device.

[0034] The formation of the electrical connector 126 in the connector opening 124 results in a structure in which the electrical connector 126 and the recess opening 118A lie adjacent to each other within the passivation layer 122. This arrangement allows for the simultaneous management of electrical connectivity and thermal insulation within the photonic die 20. The electrical connector 126 provides the necessary electrical paths for the operation of the device, while the recess opening 118A, which remains as an air gap, can serve as a thermal barrier to isolate the heat-sensitive components, such as the heater 24 and the microring modulator 26, from the rest of the package.

[0035] In some embodiments, the electrical connector 126 can be part of several conductive connectors above the redistribution layer 120. These conductive connectors can be electrically connected to the conductive structural elements of the redistribution layer 120, enabling the routing of electrical signals within the device. The exact arrangement and configuration of these conductive connectors can vary depending on the design and performance requirements of the photonic die 20.

[0036] Fig. 6A and Fig. Figure 6B illustrates the photonic die 20 bonded to a substrate package 150. Fig. 6A is a cross-sectional view, and Fig. 6B is a top view, where Fig. 6A along line AA in Fig. 6B is running.

[0037] The substrate package 150 comprises a substrate 152, which can be a package substrate, a semiconductor substrate, or the like. Bonding the substrate package 150 to the photonic die 20 can be achieved by a solder melting process or other suitable bonding processes.

[0038] The bonding process leads to the formation of an adiabatic trough 140. The adiabatic trough 140 corresponds to the trough opening 118A previously formed in the passivation layers 116 and 122. The adiabatic trough 140 extends from the top of the buffer layer 112 to the bottom of the substrate 152. In some aspects, the adiabatic trough 140 may be filled with air, forming an air gap that acts as a thermal insulation layer.

[0039] The formation of the adiabatic trough 140 offers an advantage with regard to thermal management. The air gap within the adiabatic trough 140 acts as a thermal barrier and effectively insulates the heat generated by the heater 24 and the microring modulator 26 from the rest of the package. This thermal insulation can help prevent overheating of the photonic die 20 and the substrate package 150, thus increasing the reliability and performance of the device.

[0040] In some embodiments, the adiabatic trough 140 can be formed by removing specific layers above the heater 24 and the microring modulator 26. These layers may include passivation materials, redistribution layers, and other components typically present in the photonic die 20. Removing these layers can create a void or air gap (or a metal-free region) in the structure, which serves as the adiabatic trough 140.

[0041] With reference to Fig. Figure 6B is the trough opening 118A, which forms part of the adiabatic trough 140 and is shown as a circular region in the center of the structure. The trough opening 118A is aligned with the heater 24 and the microring modulator 26, which are the heat-generating components of the photonic die 20. This alignment ensures that the heat generated by these components is effectively insulated within the adiabatic trough 140. The adiabatic trough 140 surrounds the trough opening 118A and is shown as a larger circular region.

[0042] In some embodiments, the recess opening 118A, the adiabatic recess 140, and the electrical connectors 126 can be formed in various shapes, such as circular, rectangular, or triangular, depending on the specific design and performance requirements of the photonic die 20. The flexibility in the design of these structural elements allows for specific adaptation of the package structure, making it suitable for various applications and device configurations.

[0043] Fig. 7A and Fig. Figure 7B illustrates another embodiment of the photonic die 20. Fig. 7A is a cross-sectional view, and Fig. 7B is a top view, where Fig. 7A along line AA in Fig. 7B. This embodiment is similar to the one described in the Fig. Figures 1 to 6B illustrate the embodiment. Details of this embodiment, which are similar to those of the embodiment described above, are not repeated here.

[0044] In this embodiment, the trough opening 118A in the passivation layer 116 is formed with a tapered or conical shape. This tapered shape can offer certain advantages with regard to thermal management, as it can help to conduct heat away from the heater 24 and the microring modulator 26, thereby improving the thermal insulation capabilities of the adiabatic trough.

[0045] In some aspects, the tapered shape of the 118A trough opening can be achieved through a specific etching or texturing process. For example, an anisotropic etching process can be used to create the tapered profile of the 118A trough opening. The specific parameters of the etching process, such as the etch rate and etch time, can be adjusted to control the shape and dimensions of the 118A trough opening.

[0046] In this embodiment, the second passivation layer 122 is formed such that it covers the opening of the first passivation layer 116. This arrangement can help prevent moisture from penetrating the interface between the first passivation layer 116 and the second passivation layer 122. Preventing moisture ingress can be advantageous for the reliability and performance of the photonic die 20, since moisture can cause degradation of the passivation layers and other components of the device.

[0047] The in Fig. The structure shown in Figure 7A represents an alternative configuration of the adiabatic trough in the photonic die 20. This configuration illustrates how variations in the shape and arrangement of the trough opening 118A and the passivation layers 116 and 122 can affect the thermal management capabilities of the device.

[0048] Fig. 8A and Fig. Figure 8B illustrates another embodiment of the photonic die 20, which is bonded to the substrate package 150. Fig. 8A is a cross-sectional view, and Fig. 8B is a top view, where Fig. 8A along line AA in Fig. 8B. This embodiment is similar to the one described in the Fig. Figures 1 to 6B illustrate the embodiment. Details of this embodiment, which are similar to those of the embodiment described above, are not repeated here.

[0049] In this embodiment, the photonic die 20 comprises a thermal insulation structure, in particular a thermal insulation bump (TIB) 160, which surrounds the adiabatic trough 140. The TIB 160 can serve to trap the air within the adiabatic trough 140 and to provide a thermal buffer between the adiabatic trough 140 and the surrounding areas.

[0050] The TIB 160 comprises the TIB connectors 162 and 164, which can be formed simultaneously and through similar processes to the electrical connectors 126. The TIB connectors 162 and 164 can be composed of a conductive material and can be formed by any suitable process, such as deposition and structuring. The conductive materials can resemble the redistribution layer 120 described above. The TIB connectors 162 and 164 act as a thermal buffer to limit heat transfer to other parts of the package.

[0051] The TIB 160 utilizes several principles to provide thermal insulation. First, the TIB 160 traps air within the adiabatic trough 140. This air entrapment helps maintain the thermal insulation properties of the air gap. Second, the metal in the TIB 160 has thermal mass, meaning it requires energy to heat up. This property acts as a buffer, slowing the transfer of heat from the trough to the surrounding areas. Third, while metal is generally a good thermal conductor, the specific geometry and arrangement of the TIB 160 can create a longer path for heat to travel compared to direct conduction through a solid material. This longer path can reduce the rate of heat transfer, thus contributing to the thermal insulation function of the TIB 160.Fourth, by sealing the air gap, the TIB 160 can reduce convection currents that would otherwise transfer heat more efficiently. And finally, depending on the metal used, the TIB 160 could reflect some of the heat radiation back into the recess, further contributing to insulation.

[0052] The figure also specifies various distances for the design of the structure. The width of the adiabatic trough 140 at the level of the passivation layer 122, represented by D1, can range from 42 to 85 micrometers. D2, which is the distance between the side walls of the passivation layer 116, can range from 62 to 105 micrometers. The width of the heater 24, designated D3, can be approximately 4 micrometers. The width of the TIB 160 structure, represented by D5, can range from 20 to 70 micrometers. Furthermore, the difference between D2 and D1 can be approximately 10 micrometers. These dimensions can vary depending on the specific design and performance requirements of the photonic die 20, allowing for specific adaptation of the package structure to suit various applications and device configurations.

[0053] With reference to Fig. Figure 8B illustrates a top view of the semiconductor package structure. The figure also indicates various distances for the design of the structure. In some embodiments, the width of the adiabatic trough 140 at the level of the passivation layer 122, represented by D1, can be either 30 or 50 micrometers. In these embodiments, the overall width of the TIB structure 160, represented by D4, can range from 70 to 170 micrometers if D1 is 30 micrometers, or from 90 to 190 micrometers if D1 is 50 micrometers. The width of an electrical connector 126, designated D6, can be approximately 90 micrometers. The distance between the TIB 160 and an electrical connector 126, represented by D7, can be in the range of 20 to 70 micrometers if D1 is 30 micrometers, or can be in the range of 10 to 60 micrometers if D1 is 50 micrometers.These dimensions can vary depending on the specific design and performance requirements of the photonic die 20, allowing for specific adaptation of the package structure to make it suitable for different applications and device setups.

[0054] Fig. Figure 9 illustrates a package structure according to some embodiments. This embodiment is similar to the one shown in the Fig. 8A and Fig. 8B illustrates the embodiment. Details of this embodiment, which are similar to those of the embodiment described above, are not repeated here.

[0055] In this embodiment, a backfill material 170 is formed between the photonic die 20 and the substrate package 150, and an electrical connector 174 is formed on the substrate package 150. The backfill material 170 is located in the spaces between the electrical connectors 126 and other components, providing structural support and aiding in heat dissipation. The backfill material 170 can be composed of a thermally conductive material, such as a thermally conductive epoxy or another suitable material. The backfill material 170 can be applied in a liquid or semi-liquid state, filling the spaces between the components, and can then be cured or hardened to form a solid structure.The 170 underfill material can help increase the mechanical stability of the package, thus reducing the risk of displacement or damage to components due to mechanical stress or thermal expansion.

[0056] The electrical connector 174 can resemble the electrical connectors 126 and 154 and can be formed by similar processes. The electrical connector 174 comprises a metal pillar 176 and a soldered area 178, which enable the electrical connection between the substrate package 150 and an external structure.

[0057] The addition of the underfill material 170 and the electrical connector 174 in this embodiment can offer several advantages. The underfill material 170 can increase the mechanical stability of the package, thus improving the reliability and longevity of the device. The electrical connector 174 can provide an additional electrical connection point, which improves the electrical connectivity of the package. These structural elements, in combination with the thermal management capabilities of the adiabatic trough 140 and the TIB 160, can contribute to the overall performance and reliability of the semiconductor package.

[0058] Fig. Figure 10 illustrates a package structure according to some embodiments. This embodiment is similar to the one in Fig. 9. Details of this embodiment, which are similar to those of the embodiment described above, are not repeated here.

[0059] In this embodiment, the adiabatic trough 140 is filled with a heat-repellent material 180. The heat-repellent material 180 can serve as a thermal insulation layer, which improves the thermal insulation capabilities of the adiabatic trough 140.

[0060] The heat-dissipating material 180 can be composed of a material with low thermal conductivity, such as a gas or a foam. In some cases, the heat-dissipating material 180 may be a gas, such as carbon dioxide, which has a thermal conductivity of 0.015 W / M·K. In other cases, the heat-dissipating material 180 may be a foam, such as urethane foam, which has a thermal conductivity of 0.026 W / M·K. The exact type and properties of the heat-dissipating material 180 can vary depending on the design and performance requirements of the photonic die 20.

[0061] The heat-repellent material 180 can be introduced into the adiabatic trough 140 by a filling process. This process can involve injecting the heat-repellent material 180 in a liquid or gaseous state into the adiabatic trough 140 and then allowing it to solidify or stabilize within the trough. The filling process can be controlled to ensure that the heat-repellent material 180 completely fills the adiabatic trough 140, thereby maximizing the thermal insulation effect.

[0062] Adding the heat-dissipating material 180 to the adiabatic trough 140 can offer several advantages. The heat-dissipating material 180 can improve the thermal insulation capabilities of the adiabatic trough 140, thereby reducing heat transfer from the heater 24 and the microring modulator 26 to other parts of the package. This can help prevent overheating of the photonic die 20 and the substrate package 150, increasing the reliability and performance of the device. Furthermore, the use of a heat-dissipating material 180, compared to an air gap, can provide a more stable and durable thermal barrier, thus improving the longevity of the thermal management solution.

[0063] In some embodiments, the adiabatic trough 140, which is filled with the heat-repellent material 180, can be surrounded by a thermal insulation structure, such as the TIB 160. The TIB 160 can serve to enclose the heat-repellent material 180 within the adiabatic trough 140 and to provide a thermal buffer between the adiabatic trough 140 and the surrounding areas.

[0064] Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16 to Fig. Figure 17 illustrates the formation of a photonic die at various processing stages according to some embodiments. This embodiment is similar to that described in the Fig. Figures 1 to 5 and 8A and 8B illustrate the embodiment. Details of this embodiment, which are similar to those of the embodiment described above, are not repeated here.

[0065] With reference to Fig. Figure 11 illustrates a cross-sectional view of the photonic die 20 at an intermediate processing stage. At this stage, the passivation layer 116 is structured to form several openings. These openings include the trough opening 118A, the redistribution layer opening (RDL opening) 118B, and the sealing ring openings 118C. In some embodiments, the RDL openings 118B and the sealing ring openings 118C are smaller than the trough opening 118A.

[0066] With reference to Fig. In step 12, a mask 210 is formed and structured over the passivation layer 116. The mask 210 serves to define areas for the formation of redistribution layers and sealing ring structures in subsequent processing steps. The mask 210 is structured such that it covers the trough opening 118A and exposes the RDL opening 118B and the sealing ring openings 118C.

[0067] The mask 210 can be composed of a photosensitive material, such as a photoresist, which can be selectively exposed and developed to create the desired structure. The formation of the mask 210 can involve a coating process, such as spin coating or spray coating, to deposit a uniform layer of the mask material over the passivation layer 116. The structuring of the mask 210 can be achieved by a photolithographic process in which the mask 210 is exposed through a photomask with the desired structure, and then the exposed mask 210 is developed to remove the exposed or unexposed regions, depending on the type of photoresist used.

[0068] With reference to Fig. In step 13, the RDL 120 and the sealing ring RDL 220 are formed on the photonic die 20. The RDL 120 and the sealing ring RDL 220 are formed in the RDL opening 118B and the sealing ring openings 118C, respectively, which were previously structured in the passivation layer 116. The RDL 120 and the sealing ring RDL 220 can be composed of a conductive material and can be formed by any suitable process, such as deposition and structuring. The conductive materials can resemble the redistribution layer 120 described above.

[0069] The sealing ring RDL 220 is designed to surround the recess opening 118A. The sealing ring RDL 220 can serve to reduce degradation of passivation materials that could occur due to heat exposure or contact with liquids.

[0070] After the formation of the redistribution layer 120 and the sealing ring RDL 220, the mask 210 can be removed by any suitable process, such as ashing, lifting, or peeling. The exact method used to remove the mask 210 may depend on the material of the mask 210 and the requirements of the subsequent processing steps. Removing the mask 210 exposes the trough opening 118A.

[0071] With reference to Fig. In step 14, the second passivation layer 122 is formed and structured over the first passivation layer 116, the sealing ring RDL 220, and the RDL 120. In addition to widening the recess opening 118A and the connector opening 124, the second passivation layer 122 is also structured to form openings 222 that expose sections of the sealing ring RDL 220. These openings 222 can facilitate the formation of sealing ring connectors in subsequent processing steps.

[0072] With reference to Fig. In step 15, a mask 224 is formed and structured over the second passivation layer 122. The mask 224 serves to define areas for the formation of redistribution layers and sealing ring structures in subsequent processing steps. The mask 224 is structured so that it covers the recess opening 118A and exposes the sealing ring openings 222 and the connector opening 124. The mask 224 may resemble the mask 210, and its description is not repeated here.

[0073] With reference to Fig. The electrical connector 126 and sealing ring connector 230 are formed on the photonic die 20. The electrical connector 126 is formed in the connector opening 124. In addition to the electrical connector 126, sealing ring connectors 230 are also formed on the photonic die 20. The sealing ring connectors 230 are formed to surround the recess opening 118A and are coupled to the sealing ring RDL 220. The sealing ring connectors 230 comprise a sealing ring pillar 232 and a sealing ring solder region 234, which can be formed at the same time and by similar processes as the electrical connector 126. The sealing ring connectors 230 can be considered a dummy component, as they are not electrically coupled to the circuit and serve as a barrier or sealing ring to limit the degradation of passivation materials.The sections of the sealing ring connectors 230 above the top of the second passivation layer 122 can be considered a thermal insulation bump (TIB) and serve the same purpose as the TIB 160, while the section of the sealing ring RDL 220 and the sealing ring connectors 230 within the first and second passivation layers 116 and 122 form a sealing ring structure 240 (see . Fig. 17).

[0074] With reference to Fig. In 17, the photonic die 20 is bonded to the substrate package 150, and a backfill material 170 is formed. This embodiment includes the TIB 160 and a sealing ring structure 240. The sealing ring structure 240 comprises the sealing ring RDL 220 and sections of the sealing ring connectors 230 in the passivation layers 116 and 122 and is designed to surround the adiabatic trough 140. The sealing ring structure 240 can help prevent moisture from passing through the passivation layers 116 and 122 into or out of the adiabatic trough 140. This can be advantageous in high-humidity environments or in applications where the device is exposed to moisture.

[0075] The integration of the TIB 160 and the sealing ring structure 240 in this embodiment provides a comprehensive approach to thermal management in the photonic die 20. The TIB 160 and the sealing ring structure 240 work together with the adiabatic trough 140 to provide thermal insulation, reduce degradation of the passivation material, and prevent moisture ingress. This can increase the reliability and performance of the device, extend its service life, and improve its operational efficiency.

[0076] Fig. 18A and Fig. Figure 18B illustrates a package structure according to some embodiments. Fig. 18A is a cross-sectional view, and Fig. 18B is a top view, where Fig. 18A along line AA in Fig. 18B. This embodiment is similar to the one described in the Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16 to Fig. 17 illustrated embodiments. Details of this embodiment, which are similar to those of the embodiment described above, are not repeated here.

[0077] In this embodiment, a substrate opening 250 is formed in the substrate package 150. The substrate opening 250 is aligned with the adiabatic trough 140, thereby improving the thermal insulation capabilities of the adiabatic trough 140. The substrate opening 250 can be formed by any suitable process, such as drilling or etching, and can be filled with air or another heat-repellent material.

[0078] The addition of the substrate opening 250 offers an advantage in terms of thermal management, as the heat generated by the heater 24 and the microring modulator 26 can be effectively dissipated and does not affect the rest of the package. This can help prevent overheating of the photonic die 20s and the substrate package 150.

[0079] The substrate opening 250 can be filled with a heat-repellent material, for example a gas or a foam, to further improve the thermal insulation capabilities of the adiabatic trough 140. The exact type and properties of the heat-repellent material can vary depending on the design and performance requirements of the photonic die 20s.

[0080] In some embodiments, the recess opening 118A, the adiabatic recess 140, the TIB 160, and the electrical connectors 126 can be formed in various shapes, such as circular, rectangular, or triangular, depending on the specific design and performance requirements of the photonic die 20s. The flexibility in the design of these structural elements allows for specific adaptation of the package structure, making it suitable for various applications and device configurations.

[0081] Fig. Figure 19 illustrates a package structure according to some embodiments. This embodiment is similar to that shown in the Fig. 18A and Fig. The embodiment illustrated in Figure 18B is shown. Details of this embodiment, which are similar to those of the embodiment described above, are not repeated here.

[0082] In this embodiment, the substrate opening 250 is present, but the sealing ring structure 240 is not.

[0083] Fig. 20 and Fig. Figure 31 illustrates views of intermediate stages in the formation of a package comprising a photonic die, according to some embodiments in which a photonic die 20 of the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 to Fig. 19 is used.

[0084] With reference to Fig. A photonic wafer 20' is formed. In some embodiments, the photonic die 20' is part of an unsawled photonic wafer 20 that has several identical photonic dies 20'. The photonic die 20' can also be referred to as a PIC 20'.

[0085] The photonic die 20' can comprise a semiconductor substrate 12, which in some embodiments may be a silicon substrate. A dielectric layer 14 may optionally be present beneath the semiconductor substrate 12. A dielectric layer 16 is formed above the semiconductor substrate 12. In some embodiments, the dielectric layer 16 is an etch stop layer used in the subsequent formation of conductive structural elements. The material of the dielectric layer 16 may comprise silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxide, or the like.

[0086] In some embodiments, the photonic die 20' may include IC components (not shown) formed on a surface of the semiconductor substrate 12. According to some embodiments, the IC components (if formed) are used to support the functionality of the photonic die. The IC components may include active devices such as transistors and / or diodes. The IC components may also include passive devices such as capacitors, resistors, or the like. In some embodiments, no IC components are formed in the photonic die 20'.

[0087] The photonic die 20' can include photonic devices such as waveguides, grid couplers, modulators, and / or the like. The waveguides can include silicon waveguides and / or silicon nitride waveguides. In some embodiments, dielectric layers 28 are formed and can contain silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or the like.

[0088] In some embodiments, the photonic devices may include a grid coupler 30, which, according to some embodiments, may be formed from silicon. For example, a silicon layer may be formed on the dielectric layer 16 by, for example, bonding the silicon layer to the dielectric layer 16, followed by structuring the silicon layer by etching, so that waveguides, grid couplers, and the like are formed. In some embodiments, a heater 24 and a microring modulator 26 are located next to the grid coupler 30.

[0089] In some embodiments, dielectric layers 28 are formed over the grid coupler 30. The dielectric layers 28 can comprise transparent and low-loss dielectric materials such as silicon oxide. In some embodiments, the dielectric layers located beneath an etch stop layer 40 (if formed) can contain silicon oxide. The dielectric materials above the etch stop layer can comprise multiple dielectric layers formed from different materials. The multiple dielectric layers can include an inter-metal dielectric (IMD) that may contain one or more low-k dielectric materials, such as porous silicon oxynitride. Etch stop layers can also be formed between the low-k dielectric materials. The etch stop layer can comprise AlN, AlO, SiON, or the like, or multiple layers thereof.It is understood that the formation of multiple layers using different materials does not cause any insertion loss, as these materials are removed from the light path.

[0090] The interconnect structure 32 is formed, which may include the metal via 34, vias 36, and metal conductors 38, and the respective sections of dielectric layers 28. In some embodiments, the metal via 34 has a bottom surface that contacts the dielectric layer 16. The metal via 34 can be formed by a damascus process, such as a single-damascus process. The vias 36 and the metal conductors 38 can be formed by single-damascus and / or double-damascus processes.

[0091] For example, the vias 34, the vias 36, and the metal leads 38 can be formed by a single-damascus process by creating openings in the dielectric layers 28 and filling the openings with conductive materials. The conductive materials can include a diffusion barrier layer formed of TiN, TaN, Ti, Ta, or the like, and a metallic material such as tungsten, copper, cobalt, or the like. A planarization process, such as a CMP process or a mechanical grinding process, can be performed to remove excess conductive material. The remaining sections of the diffusion barrier layer and the metallic material form the vias 34 and 36 and the metal leads 38.

[0092] In some embodiments, an etch stop layer 40 is formed directly above the grid coupler 30 and within the dielectric layers 28. In other embodiments, the etch stop layer 40 is not formed. The material of the etch stop layer 40 differs from that of the subsequently refilled dielectric region ( Fig. 22). For example, the etch stop layer 40 can be formed from or comprise silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or the like, or it can comprise a metal-containing material such as a metal oxide (for example, aluminum oxide). In some embodiments, the formation of the etch stop layer 40 can include the deposition of a dielectric layer and the structuring of the dielectric layer to remove some sections of the etch stop layer, leaving the section of the etch stop layer directly above the grid coupler 30 intact.

[0093] In some embodiments, metal pads 44 are formed over the interconnect structure 32 and electrically connected to it. The metal pads 44 can be made of aluminum-copper, copper, nickel, or the like, or multiple layers thereof. Passivation layers 46 are formed over the metal pads 44. In some embodiments, the formation of the metal pads 44 can include depositing one of the passivation layers 46, forming openings in the passivation layer to expose the underlying metal pad in the interconnect structure 32, depositing a metal seed layer, forming a plating mask, plating a metal layer, and performing an etching process to remove exposed portions of the metal seed layer. The remaining portions of the metal layer form the metal pads 44. Each of the passivation layers 46 can have a single-layer or a multi-layer structure.For example, a passivation layer 46 can have several silicon oxide layers and several silicon nitride layers formed alternately.

[0094] Then, several dielectric layers 48 and 50 are formed. In some embodiments, the dielectric layer 48 can comprise an inorganic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The corresponding dielectric layer 48 can be formed by a deposition process followed by a planarization process such as a chemical-mechanical polishing (CMP) process or a mechanical grinding process. Alternatively, the dielectric layer 48 can be formed from or comprise an organic dielectric material, which may be a polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like. The corresponding process can include depositing a polymer in a flowable form and curing the polymer to a solid material, followed by a planarization process.The dielectric layers 50 can also contain silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like, and can also include etch stop layers. The top-side dielectric layer 50 can be planar and can be formed, for example, by deposition and planarization.

[0095] Fig. Figure 21 illustrates an etching process for forming an aperture 52 that extends through several dielectric layers in the photonic die 20'. In some embodiments, an etch mask (not shown), such as a photoresist, is formed and structured. The several dielectric layers in the photonic die 20' are etched, forming the aperture 52. In some embodiments where the etch stop layer 40 is formed, the etching process stops at the etch stop layer 40, followed by etching through the etch stop layer 40 to expose the underlying dielectric layer 28. In some embodiments where the etch stop layer 40 is not formed, a time-mode etching process is used to ensure that the etching process stops once the aperture 52 has a desired depth.

[0096] In some embodiments, the etching process is stopped when the one or more dielectric layers 28 located below the aperture 52 (and thus between the aperture 52 and the grating coupler 30) are all made of the same (homogeneous) material, such as silicon oxide. This can ensure that the insertion loss of an optical signal is minimized.

[0097] With reference to Fig. In 22, the opening 52 is filled with a translucent dielectric material. In this way, a dielectric region 54 is formed. In some embodiments, the dielectric region 54 comprises silicon oxide. In other embodiments, the dielectric region 54 may also comprise other dielectric materials, such as silicon oxynitride. Elements other than silicon and oxygen may be present in small amounts, for example, with an atomic percentage of less than 10 percent or 5 percent. The formation process may include: depositing a dielectric layer to completely fill the opening 52 and performing a planarization process, such as a CMP process or a mechanical grinding process, to remove excess sections of the dielectric layer.

[0098] With reference to Fig. 23 A conductive via 55 is formed. The conductive via 55 can comprise a conductive material such as copper, tungsten, or the like, and may optionally have a diffusion barrier formed of Ti, TiN, Ta, TaN, or the like, or multiple layers. According to some embodiments, the conductive via 55 can rest on the metal pad 44.

[0099] With reference to Fig. 23 A bond layer 56 is formed. In some embodiments, the bond layer 56 can have a multilayer or a single-layer structure. The material of the bond layer 56 can be the same as that of the dielectric region 54. For example, the bond layer 56 can comprise silicon oxide. If formed from the same material, the bond layer 56 can be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like. If the bond layer 56 has a multilayer structure, it can have sublayers with slightly different compositions. For example, one of the dielectric layers 56 can comprise silicon oxide, and the other can comprise silicon oxynitride. Alternatively, both dielectric layers 56 can comprise silicon oxynitride but can have different percentages of oxygen atoms.

[0100] Bond pads 58 are formed in the dielectric layers 56. In some embodiments, the bond pads 58 may comprise copper and may include a diffusion barrier, such as Ti, TiN, Ta, TaN, or the like. The formation process may include etching the bond layer 56 to create openings, depositing a conductive material to fill the openings, and performing a planarization process to remove the portions of the conductive material above the bond layer 56.

[0101] With reference to Fig. In section 24, another device die 60, which may be an electronic integrated circuit (EIC) die 60 (also referred to as an electronic die) or another type of die, such as an independent passive device die, an integrated voltage regulator (IVR) die, or the like, is coupled to the photonic die 20'. Throughout this description, the die 60 is referred to as an EIC die 60.

[0102] The EIC die 60 can comprise a metal pad 68, a via 66 connected to the metal pad 68, and a bond pad 64 electrically connected to the via 66. The metal pad 68 can be electrically connected to the integrated circuits in the EIC die 60. In some embodiments, the EIC die 60 comprises a semiconductor substrate 70 (which can be a silicon substrate) and the integrated circuits formed on a surface of the semiconductor substrate 70. A dielectric layer 72 can be formed on the semiconductor substrate 70. The integrated circuits include active devices such as transistors. These transistors can comprise gates formed on the semiconductor substrate 70 with gate spacers adjacent to the gates. Source / drain regions can be formed in the semiconductor substrate 70 on opposite sides of each gate.Contacts can be formed for electrical connection to the gates and the source / drain regions. The EIC die 60 can also include an interlayer dielectric (ILD) surrounding the gates, gate spacers, and contacts. An etch stop layer can be formed over the ILD and the contacts to facilitate the formation of subsequent layers. Additional metal interconnect layers and corresponding dielectric layers can be formed above the etch stop layer to create the interconnect structure of the EIC die 60. The EIC die 60 further includes a dielectric layer 62 as a bond layer, with bond pads 64 being formed in the bond layer 62.

[0103] The bond between the photonic die 20' and the EIC die 60 can be a direct metal-to-metal bond, a solder bond, or a hybrid bond that includes both a direct metal-to-metal bond and a fusion bond. For example, the bond layer 62 is bonded to the bond layer 56 by fusion bonding. In some embodiments, the material of the bond layer 62 differs from the material of the bond layer 56, allowing for heterogeneous bonding to improve bond strength.

[0104] In some embodiments, the EIC-Die 60 may include integrated circuits (not shown) for communication with the photonic die 20', such as circuits for controlling the operation of the photonic die 20'. For example, the EIC-Die 60 may include controllers, drivers, amplifiers, the like, or combinations thereof. The EIC-Die 60 may also include a CPU. In some embodiments, the EIC-Die 60 includes circuits for processing the electrical signals received from the photonic die 20'. The EIC-Die 60 may also control high-frequency signaling of the photonic die 20' according to electrical signals (digital or analog) received from another device or die. In some embodiments, the EIC-Die 60 may include a circuit providing serializer / deserializer functionality (SerDes functionality).In this way, the EIC can function as part of an I / O interface between optical signals and electrical signals.

[0105] It goes without saying that the ones in the Fig. 20, Fig. 21, Fig. 22, Fig. 23 to Fig. 24 illustrated processes take place at wafer level, wherein according to some embodiments several EIC dies 60 can be bonded to several photonic dies 20' of the photonic wafer 20. Fig. 25, Fig. 26 to Fig. Figure 27 illustrates a gap-filling process according to some embodiments, wherein the gaps between EIC dies 60 are filled to form dielectric regions (enclosing the EIC dies 60) which are also referred to as gap-filling regions.

[0106] With reference to Fig. 25 A dielectric barrier 74 is deposited. The deposition process comprises a conformal deposition process such as ALD, CVD, or the like. The material of the dielectric barrier 74 is selected to have good adhesion to the EIC dies 60. In some embodiments, the dielectric barrier 74 is formed from or comprises silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbide, or the like, wherein this material may differ from the material of the dielectric region 54 and the bond layer 56.

[0107] With reference to Fig. 26 An etch mask 76 is formed, which may be made of a structured photoresist. An etching process 78 is carried out to etch and structure the dielectric barrier 74 such that an opening 80 is formed and the underlying bond layer 56 is exposed. The etching process 78 is carried out using the bond layer 56 as an etch stop layer such that the opening 80 extends into the dielectric barrier 74 and the bond layer 56 is exposed. In some embodiments, the entire opening 80 is located directly above the bond layer 56, and no metal structural element in the bond layer 56 is exposed towards the opening 80. After the etching process 78, the etch mask 76 is removed, for example, by an ashenation process. In some embodiments, as a result of the etching process 78, the bond layer 56 is etched through, and the underlying dielectric region 54 is exposed.

[0108] With reference to Fig. 27 A dielectric region 82 is formed which is translucent. In some embodiments, the formation process may include the deposition of a dielectric material and the execution of a planarization process, such as a CMP process or a mechanical grinding process, on the deposited dielectric material. The planarization process may utilize the dielectric barrier 74 or the semiconductor substrate 70 as a CMP stop layer. The dielectric material of the dielectric region 82 may comprise silicon oxide, silicon oxynitride, or the like. The dielectric material (such as silicon oxide) of the dielectric region 82 may also be the same as that of the bond layer 56, the dielectric region 54, and the section of the dielectric layer 28 directly beneath the dielectric region 54.Throughout the entire description, the dielectric barrier 74 and the dielectric region 82 are referred to together as a gap-filling region 83.

[0109] Next, a bonding layer 84 is formed by a deposition process. In some embodiments, the bonding layer 84 is formed from or comprises silicon oxide, silicon oxynitride, or the like. In some embodiments, the bonding layer 84 is formed from the same material as that of the dielectric region 82. The bonding layer 84 and the dielectric region 82 may optionally be distinguishable from one another and may optionally have a distinguishable interface between them. Accordingly, the interface between the bonding layer 84 and the dielectric region 82 is shown with a dashed line to indicate that the interface may be distinguishable, but need not be.

[0110] With reference to Fig. 28 A support substrate 90 (which may be a wafer) is bonded to the bonding layer 84. In some embodiments, the support substrate 90 comprises a bonding layer 86 and a silicon substrate 88 attached to the bonding layer 84. The bonding layer 86 may be formed from or comprise a silicon-containing dielectric material such as silicon oxide, silicon oxynitride, silicon carbonitride, or the like. The bonding may include fusion bonding, wherein the bonding layer 86 is bonded to the bonding layer 84. In some embodiments, the material of the bonding layer 86 is similar to or the same as that of the bonding layer 84 and the dielectric regions 82 and 54, for example, including silicon oxide.

[0111] In some embodiments, the support substrate 90 has a microlens 92, which is formed as part of the silicon substrate 88, for example, by etching the silicon substrate 88. The support substrate 90 further has a protective layer 94, which is formed on the silicon substrate 88. The protective layer 94 also has a section in the recess in the silicon substrate 88 in which the microlens 92 is formed. The protective layer 94 can be a conformal layer formed from silicon oxide. According to some embodiments, the microlens 92 is vertically oriented towards the dielectric region 82, the opening 80 in the dielectric barrier layer 74, the dielectric region 54, and the grid coupler 30.

[0112] Next, the semiconductor substrate 12 and the dielectric layer 14 (and optionally the dielectric layer 16) are removed. The resulting structure is in Fig. Figure 29 shows that in some embodiments, where the photonic die 20' has active devices, the dielectric layer 14 and the semiconductor substrate 12 may remain. The ablation process (if performed) may include a CMP process, a mechanical grinding process, or the like.

[0113] In subsequent processes, such as in Fig. 30 shown, the ones in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 to Fig. The 19 illustrated structures were formed on the photonic die 20'. In this way, a reconstructed wafer 300 is formed.

[0114] In a subsequent process, a sawing process (also referred to as a singulation process) is performed to saw the reconstructed wafer 300 and form multiple optical engines 300', also referred to as an optical engine, packages, or photonic engines. The multiple optical units 300' are identical and each may comprise a photonic die 20s', an EIC die 60, a support substrate 90 sawn from the support substrate 90 at the wafer level, and a substrate package 150. In some embodiments, the singulation process is performed before the substrate package 150 is attached.

[0115] Fig. Figure 31 illustrates the use of the photonic engine 300' according to some embodiments. The photonic engine 300' can be bonded to a package component (not shown) located beneath the photonic engine 300' and electrically connected to it. The underlying package component can comprise an interposer, a package substrate, a printed circuit board, or the like. A fiber assembly unit (FAU) 314 is attached to the underlying structure. An optical fiber 318 is attached to a fiber connector 316. A laser beam 320 can be projected out of the optical fiber 318 and reflected in the FAU 314. The laser beam 320 is reflected by a reflective surface and is projected onto the microlens 92. The laser beam 320 traverses an optical path 322 to reach the grating coupler 30, which directs the optical signal into waveguides.The optical signals transmitted by the laser beam 320 are further processed by the photonic die 20' and the EIC die 60. For example, the photonic die 20' can convert the optical signals into electrical signals, and the electrical signals are transmitted to the EIC die 60. The photonic die 20 also includes the heater 24, the wavelength modulator 26, and the adiabatic trough 140, which were discussed above. In some embodiments, the heater 24 and the wavelength modulator 26 are thermally coupled to allow thermo-optical tuning of the optical substrate for resonant tuning. The adiabatic trough 140 (also referred to as the metal-free region) aids in the control and thermal insulation of these components from other components in the package.

[0116] In some embodiments, such as in Fig. As shown in Figure 31, the laser beam 320, used to transport optical signals, traverses an optical path 322 after converging through the microlens 92 to reach the grating coupler 30. The optical path 322 includes some sections of the bond layers 84 and 86, the dielectric region 82, the bond layer 56, the dielectric region 54, and the dielectric layer 28.

[0117] Fig. Figure 32 illustrates a package structure 400 according to some embodiments. The package structure 400 has an optical engine 300', which is described in the Fig. 30 and Fig. The optical engine 300' is mounted on an interposer 430, which provides interconnect links between different components of the package.

[0118] In addition to the optical engine 300' on the interposer 430, there is a memory die 420 and a logic die 410. The memory die 420 can be a high-bandwidth memory die (HBM die), and the logic die 410 can be a system-on-chip die (SoC die) that integrates various processing and control functions.

[0119] The Interposer 430 is mounted on a Substrate 440, which can be a package substrate. The Substrate 440 provides additional routing layers and serves as an interface between the package components and the external circuitry.

[0120] This setup allows for the direct integration of the optical engine 300' with high-performance storage and logic components, enabling faster data transmission and processing. The use of an interposer 430 supports efficient connectivity between these various components, while the substrate 440 provides a stable base and external connectivity for the package structure 400.

[0121] Fig. Figure 33 illustrates a package structure 500 according to some embodiments. This structure is similar to the one in Fig. 32 shown, except that here the optical engine 300' is attached directly to the substrate 440.

[0122] In this setup, the optical engine 300' is mounted directly on the substrate 440. The logic die 410 and the memory die 420 are mounted on an interposer 510. The interposer 510 is mounted on the substrate 440 along the optical engine 300'. This arrangement differs from Fig. 32 insofar as the optical engine 300' bypasses the interposer and is directly connected to the substrate 440.

[0123] The Substrate 440 can provide routing and external connections for the Optical Engine 300', the Interposer 510, and components mounted on the Interposer 510. This setup can offer advantages in terms of a reduced signal path for the Optical Engine 300', potentially improving its performance or integration flexibility.

[0124] Various embodiments can realize advantages. The present disclosure describes a thermal management approach through a packaging design. This design comprises a photonic die that includes a wavelength modulator and a heating element. The heating element is thermally coupled to the modulator, which allows for temperature control. The PIC die is integrated into the overall package structure in a specific manner.

[0125] The package features an interconnect structure on the top side of the PIC die. This interconnect structure includes conductive structural elements for electrical connections and a void, or metal-free region. This void, also known as an "adiabatic trough," is positioned to overlap the heating element and wavelength modulator when viewed from above. The void can act as a thermal barrier, isolating the heat-sensitive components from the rest of the package.

[0126] To improve thermal management capabilities, the package can incorporate additional structural elements such as a thermal insulation bump (TIB) and a die-internal sealing ring. These structures can interact with the adiabatic trough to provide thermal insulation. The TIB can surround the adiabatic trough and potentially form a buffer zone to limit heat propagation to other parts of the package. The die-internal sealing ring can help mitigate potential degradation of passivation materials that might occur due to heat exposure.

[0127] This approach to thermal management in semiconductor packaging can offer several potential advantages. It can help reduce the risk of overheating and material degradation, which can be problematic in high-power photonic devices. By potentially maintaining more stable temperatures for the wavelength modulator and other optical components, the package design can contribute to consistent performance and potentially extend the device's lifetime. This thermal management strategy can be implemented while maintaining the electrical connections required for device operation, as conductive connectors can still link the interconnect structure to other parts of the package.

[0128] In one embodiment, a semiconductor package can include a photonic integrated circuit (PIC) die comprising a wavelength modulator and a heating element thermally coupled to the wavelength modulator. The semiconductor package can also include an interconnect structure on the PIC die, wherein the interconnect structure can comprise multiple conductive structural elements and a void. In a top view, the void overlaps the heating element and the wavelength modulator. The package can further include multiple conductive connectors above the interconnect structure, which are electrically connected to the multiple conductive structural elements.

[0129] The described embodiments may also include one or more of the following aspects: the semiconductor package, wherein the void may contain an air gap; the semiconductor package, wherein the air gap extends from a top surface of the PIC die to a bottom surface containing multiple conductive connectors; the semiconductor package may include a thermal insulation structure surrounding the void; the semiconductor package, wherein the thermal insulation structure may include a metal pillar and a solder region; the semiconductor package, wherein the thermal insulation structure is configured to trap air within the void and provide a thermal buffer between the void and surrounding areas; the semiconductor package may include an electronic integrated circuit (EIC) die bonded to the interconnect structure.

[0130] In one embodiment, a method may include forming a photonic integrated circuit (PIC) die comprising a wavelength modulator and a heating element thermally coupled to the wavelength modulator. The method may further include forming an interconnect structure on the PIC die, wherein the interconnect structure may comprise multiple conductive structural elements and a metal-free region lacking any of the multiple conductive structural elements. In a top view, the metal-free region overlaps the heating element and the wavelength modulator. The method may further include forming multiple conductive connectors across the interconnect structure, wherein the conductive connectors are electrically connected to the multiple conductive structural elements.

[0131] The described embodiments may also include one or more of the following aspects: the method, wherein forming the metal-free region may include forming an air gap extending from a top side of the PIC die to a bottom side of the multiple conductive connectors; the method may include forming a thermal insulation structure surrounding the metal-free region; the method, wherein forming the thermal insulation structure may include forming a metal pillar and a solder region; the method, wherein the thermal insulation structure is configured to trap air within the metal-free region; the method may include bonding an electronic integrated circuit (EIC) die to the PIC die; the method may include forming optical components in the PIC die.

[0132] In one embodiment, a semiconductor device can comprise a photonic integrated circuit (PIC) die that includes an optical component. The semiconductor device can also include an interconnect structure on the PIC die, wherein the interconnect structure comprises a dielectric layer and conductive structural elements within the dielectric layer. The device can further include an adiabatic dimple in the interconnect structure, wherein the adiabatic dimple overlaps the optical component in a top view. The device can additionally include multiple conductive connectors above the interconnect structure, which are electrically connected to the conductive structural elements.

[0133] The described embodiments may also include one or more of the following aspects: the semiconductor device, wherein the optical component may include a microring modulator and a heater thermally coupled to the microring modulator; the semiconductor device may include a thermal insulation structure surrounding the adiabatic trough; the semiconductor device, wherein the adiabatic trough may contain air; the semiconductor device, wherein the adiabatic trough may include heat-dissipating material; the semiconductor device may include an electronic IC die (EIC die) bonded to the PIC die.

[0134] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 665,334

[0001]

Claims

[1] Semiconductor package, comprising: a photonic IC die (Photonic Integrated Circuit, PIC die) comprising a wavelength modulator and a heating element thermally coupled to the wavelength modulator; an interconnect structure on the PIC die, wherein the interconnect structure comprises several conductive structural elements and a void, the void overlapping the heating element and the wavelength modulator in a top view; and Several conductive connectors above the interconnect structure, which are electrically connected to the multiple conductive structural elements. [2] Semiconductor package according to claim 1, wherein the void comprises an air gap. [3] Semiconductor package according to claim 2, wherein the air gap extends from a top side of the PIC die to a bottom side of the multiple conductive connectors. [4] Semiconductor package according to any one of claims 1 to 3, further comprising a thermal insulation structure surrounding the void. [5] Semiconductor package according to claim 4, wherein the thermal insulation structure comprises a metal pillar and a solder region. [6] Semiconductor package according to claim 5, wherein the thermal insulation structure is configured to enclose air within the void and to provide a thermal buffer between the void and surrounding areas. [7] Semiconductor package according to any one of claims 1 to 6, further comprising an electronic IC die (Electronic Integrated Circuit, EIC die) bonded to the interconnect structure. [8] Procedures, comprehensive: Forming a photonic IC die (PIC die) comprising a wavelength modulator and a heating element thermally coupled to the wavelength modulator; Forming an interconnect structure on the PIC die, wherein the interconnect structure comprises several conductive structural elements and a metal-free region without any of the several conductive structural elements therein, the metal-free region overlapping the heating element and the wavelength modulator in a top view; and Forming multiple conductive connectors across the interconnect structure, wherein the conductive connectors are electrically connected to the multiple conductive structural elements. [9] Method according to claim 8, wherein forming the metal-free region comprises forming an air gap extending from a top side of the PIC die to a bottom side of the multiple conductive connectors. [10] The method of claim 9, further comprising forming a thermal insulation structure surrounding the metal-free region. [11] Method according to claim 10, wherein forming the thermal insulation structure comprises forming a metal pillar and a soldering region. [12] Method according to claim 11, wherein the thermal insulation structure is configured to enclose air within the metal-free region. [13] Method according to any one of claims 8 to 12, further comprising bonding an electronic IC die (EIC die) to the PIC die. [14] Method according to claim 13, further comprising forming optical components in the PIC die. [15] Semiconductor device comprising: a photonic integrated circuit die (PIC die) that includes an optical component; an interconnect structure on the PIC die, wherein the interconnect structure comprises a dielectric layer and conductive structural elements in the dielectric layer; an adiabatic trough in the interconnect structure, wherein the adiabatic trough overlaps the optical component in a top view; and Several conductive connectors above the interconnect structure, which are electrically connected to the conductive structural elements. [16] Semiconductor device according to claim 15, wherein the optical component comprises a microring modulator and a heater thermally coupled to the microring modulator. [17] Semiconductor device according to claim 16, further comprising a thermal insulation structure surrounding the adiabatic trough. [18] Semiconductor device according to any one of claims 15 to 17, wherein the adiabatic trough comprises air. [19] Semiconductor device according to any one of claims 15 to 17, wherein the adiabatic trough comprises heat-repellent material. [20] Semiconductor device according to any one of claims 15 to 19, further comprising an electronic IC die (EIC die) bonded to the PIC die.

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