Wafer test fixture

Abstract

A wafer testing apparatus according to the present disclosure comprises: an inspection stage on which a wafer having a plurality of semiconductor chips is mounted; and a probe card that inspects the plurality of semiconductor chips, wherein the inspection stage includes a temperature adjusting mechanism that can adjust a temperature of a part of the wafer, and the temperature adjusting mechanism includes a plurality of first heaters that are separately and independently controlled from each other.

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present disclosure relates to a wafer testing apparatus that tests a semiconductor device in a wafer state. Description of the state of the art

[0002] When testing whether a semiconductor chip meets a specification as a product, an accelerated test, performed by raising the temperature of the semiconductor chip, is often used to shorten the test time. For example, in a power semiconductor device, the test is often performed under test conditions of 25°C to 200°C.

[0003] Japanese Patent Application No. 2022-030909 discloses an inspection apparatus for a semiconductor device capable of locally adjusting a wafer temperature by light irradiation of a semiconductor device in a wafer state for an acceleration test.

[0004] In Japanese Patent Application No. 2022-030909, when raising the temperature of a portion of a semiconductor device in a wafer state, the temperature is raised by irradiating a portion to be heated with light. However, when the light irradiation method is used for characteristic inspection of the power semiconductor device, in addition to the problem of increased leakage current due to light energy, there is a problem that it is difficult to raise the temperature up to 200°C due to the temperature increase caused by light irradiation. SUMMARY

[0005] An object of the present disclosure is to provide a wafer testing apparatus capable of performing inspection at a high temperature without increasing a leakage current.

[0006] A wafer testing apparatus according to the present disclosure comprises: an inspection stage on which a wafer having a plurality of semiconductor chips is mounted; and a probe card that inspects the plurality of semiconductor chips, wherein the inspection stage includes a temperature adjusting mechanism that can adjust a temperature of a part of the wafer, and the temperature adjusting mechanism includes a plurality of first heaters that are separately and independently controlled from each other.

[0007] The wafer testing apparatus of the present disclosure can intensively raise the temperature of the semiconductor chip to be measured by the plurality of first heaters, and can shorten the inspection time because the leakage current is not increased by the light energy unlike the temperature rise by the light irradiation, and the temperature can be raised to a temperature of up to 200°C in a short time. Furthermore, by intensively raising the temperature of the semiconductor chip to be measured, the semiconductor chip is prevented from having a high temperature for a long time, and the accelerated test can be performed while preventing the precipitation of Ni from the electrode portion of the laminated structure.

[0008] These and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view for explaining a configuration of an inspection stage of a wafer testing apparatus according to a first preferred embodiment of the present disclosure; Fig. 2 is a cross-sectional view for explaining the configuration of the inspection stage of the wafer testing apparatus according to the first preferred embodiment of the present disclosure; Fig. 3 is a plan view illustrating an inspection stage before a wafer is mounted; Fig. 4 is a plan view schematically illustrating a state in which the temperature of a semiconductor chip to be measured is intensively increased in the inspection stage of the wafer testing apparatus according to the first preferred embodiment of the present disclosure; Fig. 5 is a cross-sectional view schematically illustrating a state in which the temperature of the semiconductor chip to be measured is intensively increased in the inspection stage of the wafer testing apparatus according to the first preferred embodiment of the present disclosure; Fig. 6 is a plan view schematically illustrating a function of a temperature adjusting mechanism in the inspection stage of the wafer testing apparatus according to a second preferred embodiment of the present disclosure; Fig. 7 is a plan view schematically illustrating a function of a temperature adjusting mechanism in the inspection stage of the wafer testing apparatus according to the second preferred embodiment of the present disclosure; Fig. 8 is a cross-sectional view for explaining the configuration of the wafer testing apparatus according to a third preferred embodiment of the present disclosure; Fig. 9 is a cross-sectional view for explaining the configuration of the wafer testing apparatus according to the third preferred embodiment of the present disclosure; Fig. 10 is a cross-sectional view for explaining the configuration of the wafer testing apparatus according to a fourth preferred embodiment of the present disclosure; Fig. 11 is a plan view of a probe card of the wafer testing apparatus according to the fourth preferred embodiment of the present disclosure, viewed from a lower surface side; Fig. 12 is a cross-sectional view for explaining the configuration of the wafer testing apparatus according to a fifth preferred embodiment of the present disclosure; Fig. 13 is a cross-sectional view for explaining the configuration of the wafer testing apparatus according to the fifth preferred embodiment of the present disclosure; Fig. 14 is a plan view of a probe card of the wafer testing apparatus according to the fifth preferred embodiment of the present disclosure, viewed from a lower surface side; Fig. 15 is a plan view for explaining the configuration of the wafer testing apparatus according to a sixth preferred embodiment of the present disclosure; Fig. 16 is a cross-sectional view for explaining the configuration of the wafer testing apparatus according to the sixth preferred embodiment of the present disclosure; Fig. 17 is a diagram illustrating a wafer test using the wafer testing apparatus according to the sixth preferred embodiment of the present disclosure; and Fig. 18 is a diagram illustrating a wafer test using the wafer testing apparatus according to the sixth preferred embodiment of the present disclosure. DESCRIPTION OF THE PREFERRED EMBODIMENTS< Introduction >

[0009] The drawings are schematically illustrated, and the relationship between the sizes and positions of images illustrated in different drawings is not necessarily described precisely and may be changed appropriately. Furthermore, in the following description, similar constituent elements are denoted by the same reference numerals, and their names and functions are also similar. Therefore, a detailed description thereof may be omitted.

[0010] In the following description, terms indicating specific positions and directions, such as "upper", "lower", "side", "front", or "rear", may be used, but these terms are used for convenience to facilitate understanding of the preferred embodiments and do not refer to the directions in the actual implementation. First preferred embodiment

[0011] A wafer testing apparatus according to a first preferred embodiment of the present disclosure will be described with reference to Fig. 1 to Fig. 5 described.

[0012] Fig. 1 is a plan view for explaining a configuration of an inspection stage 2 of a wafer testing apparatus 100 according to the first preferred embodiment, and Fig. 2 is a cross-sectional view along the line AA in Fig. 1.

[0013] As in Fig. 1, a wafer 1 in which a plurality of semiconductor chips 3 are constructed is mounted on the inspection stage 2. As shown in Fig. 2, a temperature adjustment mechanism 11 is provided within the inspection stage 2. The temperature adjustment mechanism 11 includes, for example, a plurality of heating devices 11a (first heating devices) and has a structure in which the plurality of heating devices 11a are separated from each other and independently controlled so as to be able to heat not the entire wafer 1, but only an arbitrarily selected part. Fig. 1 and Fig. 2, a probe card including a probe for testing the semiconductor chip 3 is not illustrated, but a conventional cantilever type probe card or a vertical type probe card may be used as the probe card.

[0014] Fig. 3 is a plan view illustrating the inspection stage 2 before mounting the wafer 1 thereon and the wafer 1, wherein an area on which the wafer 1 is to be mounted in the inspection stage 2 at the bottom is omitted for simplicity. As in Fig. As illustrated in Figure 3, the plurality of heaters 11a has a structure in which the heat-generating surface is arranged to face the back surface of the wafer 1, and each heater 11a can be individually turned on and off. Consequently, by intensively raising the temperature of the semiconductor chip 3 to be measured, not the entire wafer 1, it is possible to shorten the time during which the semiconductor chip 3 alone is at a high temperature. Although Fig. 3 illustrates the configuration in which the plurality of heaters 11a are arranged so as to divide the circular area, the present invention is not limited thereto, and the plurality of heaters 11a may be provided so as to divide a rectangle.

[0015] Since the heater 11a is provided within the inspection stage 2 and has no portion in direct contact with the wafer 1, a metal heater such as a nichrome wire heater can be used.

[0016] Fig. 4 and Fig. 5 are diagrams schematically illustrating a state in which the temperature of the semiconductor chip 3 to be measured is intensively increased in the inspection step 2 of the first preferred embodiment, wherein Fig. 4 is a plan view showing Fig. 1 corresponds, and Fig. 5 is a cross-sectional view showing Fig. 2. An area RM, which is indicated by a dashed line in Fig. 4 represents a temperature rise area and is an area that includes the three semiconductor chips 3. In Fig. 5, a state in which the heaters 11a included in the region RM generate heat is shown in hatched form. The three heaters 11a generate heat to raise the temperature of the three semiconductor chips 3 above them. After the temperature of the three semiconductor chips 3 to be measured is raised and the measurement by the probe card is completed, the temperature rise of the next three semiconductor chips 3 to be measured is started. By repeating the above, all the semiconductor chips 3 included in the wafer 1 are measured.

[0017] Although Fig. 5 illustrates an example in which three heaters 11a are controlled, the number of heaters to be controlled is not limited thereto, and only at least one heater 11a is required to be controlled. When the number of heaters 11a to be used is small, the influence of heat on the surrounding semiconductor chips 3 can be reduced.

[0018] In a power semiconductor device, screening inspection can be performed for quality assurance, and accelerated testing is performed to shorten inspection time by setting a semiconductor chip temperature higher than that in actual use. However, if the semiconductor chip is heated to a high temperature for a long time, there is a concern that nickel (Ni) will be deposited on the gold (Au) layer on the chip surface, and bonding failure may occur during package assembly.

[0019] That is, a SiC chip using a silicon carbide (SiC) substrate adopts a laminated structure in which, for example, a barrier metal made of titanium (Ti), an aluminum silicon (AlSi) layer, a nickel phosphorus (NiP) layer, and a Au layer are laminated on the SiC substrate in an electrode region, etc. However, because the SiC chip is kept at a high temperature for a long time, Ni may be deposited on a surface of the Au layer from the NiP layer. If the deposited Ni is oxidized to form an oxide film, for example, bonding failure may occur when wire bonding is performed on the Au layer.

[0020] Specifically, in the wafer test, compared to the chip test, the time during which a single chip is in a high-temperature state is extended, and the temperature condition is limited, and the inspection time is extended. For example, in a case where a test lasting 10 seconds per chip is performed, in the chip test, since the temperature of the chip alone is raised, the time during which the chip is in a high-temperature state is only 10 seconds. However, in the wafer test, since the temperature of the entire wafer is raised, the time of the high-temperature state is ten times the number of chips per wafer [sec]. Therefore, if 100 chips are included in the wafer, the single chip in the wafer test is in a high-temperature state for 100 times the time in the chip test.

[0021] Since the accelerated test can be performed when the wafer is heated to a high temperature, the test time can be shortened. However, Ni deposition is more likely when the wafer is heated to a higher temperature. Therefore, in the wafer test, the time during which the temperature is in the high-temperature state is longer than in the chip test. As a result, the temperature of the measurement condition cannot be increased, and the inspection time is extended.

[0022] On the other hand, in the inspection stage 2 of the first preferred embodiment, since the temperature of the semiconductor chip 3 to be measured is intensively raised, the accelerated test can be performed while preventing Ni deposition, thereby shortening the inspection time. Particularly, in the case of a SiC chip, it is necessary to perform a large number of screening objects due to many crystal defects, and the inspection time tends to be long, so the accelerated test at a high temperature is effective. Here, the high temperature refers to a temperature higher than room temperature (25°C). For example, in a case where the guaranteed temperature of the chip is 150°C, the screening test performed at 150°C can shorten the test time the most. In addition, since the temperature is raised by the heater 11a, the target temperature can be reached in a relatively short time. Second preferred embodiment

[0023] A wafer testing apparatus according to a second preferred embodiment of the present disclosure will be described with reference to Fig. 6 and Fig. 7 described. Fig. 6 and Fig. 7 are plan views schematically illustrating functions of the temperature adjustment mechanism in the inspection stage 2 of the wafer testing apparatus 200 according to the second preferred embodiment.

[0024] In the inspection stage 2 of the wafer testing apparatus 100 of the first preferred embodiment, the temperature adjustment mechanism 11 has a structure in which the plurality of heaters 11a are separated from each other and independently controlled to heat only a part of the wafer 1. After the temperature of the semiconductor chip 3 to be measured is intensively increased, the temperature of the semiconductor chip 3 to be measured is increased, and the measurement by the probe card is completed, the temperature increase of the next semiconductor chip 3 to be measured is started. By repeating the above, all the semiconductor chips 3 included in the wafer 1 were measured.

[0025] On the other hand, in the inspection stage 2 of the wafer testing apparatus 200 of the second preferred embodiment, the inspection order of the semiconductor chips 3 to be inspected is set, and the temperature adjusting mechanism 11 is controlled to adjust the temperature of the wafer 1 of the section according to the set inspection order.

[0026] For example, Fig. 6 shows an example in which the heating device 11a is controlled to be turned on and off to increase the temperature of the semiconductor chip 3 to be measured in units of one chip or a plurality of chips from left to right, from top to bottom, and from right to left along the inspection path of the arrow. In the example of Fig. 6, an interval corresponding to one semiconductor chip 3 is provided between the inspection paths indicated by arrows in the left-right direction, and the influence of the temperature rise along the inspection path indicated by an arrow does not reach the surrounding chips.

[0027] Fig. Fig. 7 illustrates an example in which the heater 11a is controlled to be turned on and off to increase the temperature of the semiconductor chip 3 to be measured in units of one chip or a plurality of chips from the top left to the bottom right along the inspection path of the arrow. In the example of Fig. 7, the inspection paths indicated by the four arrows are denoted by symbols A to D, the semiconductor chip 3 to be measured is heated in the order of the inspection paths A, B, C and D, the heating order is set to be every other inspection path indicated by the arrow, and the influence of the temperature rise along the inspection path indicated by an arrow does not reach the surrounding chips.

[0028] That is, even if the plurality of heating devices 11a are independently controlled separately to locally increase the temperature of the inspection stage 2, the inspection stage 2 itself is continuous, and therefore the temperature of the chips around the semiconductor chip 3 to be measured is also increased by heat conduction. Therefore, there is the semiconductor chip 3 whose temperature is continuously increased in a state where the influence of the temperature rise of the semiconductor chip 3 to be measured remains. However, as shown in Fig. 6 and Fig. 7 illustrates that by setting the inspection order of the semiconductor chips 3 to be inspected and setting the temperature of the corresponding region of the wafer 1 in the set order, the time during which the semiconductor chips 3 are continuously at high temperature can be reduced as much as possible. Third preferred embodiment

[0029] A wafer testing apparatus according to a third preferred embodiment of the present disclosure will be described with reference to Fig. 8 and Fig. 9 described. Fig. 8 and Fig. 9 are cross-sectional views for explaining the configuration of the wafer testing apparatus 300 according to the third preferred embodiment of the present disclosure.

[0030] Fig. Fig. 8 illustrates a state in which the probe card 6 is arranged over the wafer 1 mounted on the inspection stage 2, wherein the probe card 6 is a cross-sectional view. The cross-sectional configuration of the inspection stage 2 is the same as that of the inspection stage 2 shown in Fig. 2, and although not illustrated, the plurality of heating devices 11a includes a temperature adjusting mechanism 11, which are controlled separately and independently from each other.

[0031] The probe card 6 is a cantilever-type probe card with the probe 4, but may be a spring-type probe, and a plurality of heater holes 62 for accommodating the heater 5 (second heater) are provided in the outer wall 61 outside the area where the probe 4 is arranged. A heater hole 62 is provided so as to extend in the height direction (vertical direction) from the bottom surface of the outer wall 61, and a wiring 63 having elasticity, which is connected to the heater 5, supplies power for heating the heater 5, and suspends the heater 5 from the hole bottom, is provided within the heater hole. The wiring 63 has elasticity to bias the heater 5 in the vertical direction. In a state where the probe card 6 is arranged above the wafer 1, as shown in FIG. Fig. 8, the heater 5 is suspended from the wiring 63, and the wiring 63 is extended.

[0032] Fig. 9 illustrates a state in which the probe 4 of the probe card 6 is in contact with the wafer 1 and the end face of the heater 5 is also in contact with the wafer 1. In this state, a part of the heater 5 is received in the heater hole 62, the wiring 63 is compressed between the heater 5 and the hole bottom portion, and the end face of the heater 5 is strongly pressed against the wafer 1 by the repulsive force of the wiring 63.

[0033] In Fig. 8 and Fig. 9, for the sake of simplicity, only a part of the probe card is illustrated, that is, a housing portion for accommodating the probe 4, and actually the housing portion includes a probe card substrate including wiring, which is not illustrated.

[0034] When the probe 4 of the probe card 6 comes into contact with the wafer 1 and the heater 5 is energized in a state where the end face of the heater 5 is pressed against the wafer 1, as shown in Fig. As illustrated in Figure 9, the temperature of the semiconductor chip 3 to be measured is increased from the upper surface side by heat generation of the heater 5. The temperature is increased from the lower surface side of the semiconductor chip 3 by the temperature adjustment mechanism 11 in the inspection stage 2. In Fig. 9, an area in which the temperature of the semiconductor chip 3 is increased is shown hatched.

[0035] As described above, by raising the temperature of the semiconductor chip 3 not only from the lower surface side but also from the upper surface side, the temperature rise time can be shortened. From the perspective of raising the temperature of the semiconductor chip 3, the heater 5 can also be considered the temperature adjustment mechanism.

[0036] Furthermore, by preheating the probe 4 by the heating device 5, work associated with preheating can be simplified.

[0037] Preheating the probe 4 is a process of heating the probe 4 before performing a high-temperature measurement. Metal is generally used as a material for the probe 4, and the metal undergoes thermal expansion. If the probe 4, which is not preheated, is brought into contact with the semiconductor chip 3 at a high temperature, heat will be transferred to the probe 4 during the characteristic measurement, and there is a possibility that a needle of the probe 4 may become stuck in the semiconductor chip 3 due to thermal expansion.

[0038] Conventionally, preheating is performed by bringing the probe close to a stage heated to a high temperature for a certain period of time before measuring electrical characteristics. However, in the wafer testing apparatus 300 according to the third preferred embodiment, preheating of the probe 4 is performed by the heater 5 provided in the probe card 6, and then the temperature of the semiconductor chip 3 is raised by the temperature adjustment mechanism 11 in the inspection stage 2, whereby work associated with preheating can be simplified.

[0039] The number of heaters 5 to be arranged is not particularly limited, but desirably larger from the viewpoint of uniformly raising the temperature of the semiconductor chip 3, and four to eight heaters may be arranged as an example. Fourth Preferred Embodiment

[0040] A wafer testing apparatus according to a fourth preferred embodiment of the present disclosure will be described with reference to Fig. 10 and Fig. 11 described. Fig. 10 is a cross-sectional view for explaining the configuration of the wafer testing apparatus 400 of the fourth preferred embodiment, and illustrates a state in which the probe card 6A is arranged on the wafer 1 mounted on the inspection stage 2. Fig. 11 is a plan view of the probe card 6A, viewed from the lower surface side, and a cross section taken along the line BB in Fig. 11 corresponds to the cross-sectional view of Fig. 10. In probe map 6A of Fig. 10 are the same components as those of probe card 6, which are shown in Fig. 8 are designated by the same reference numerals and a repeated description is omitted.

[0041] In probe card 6A, which is in Fig. 10, the sensor hole 64 for receiving the temperature sensor 7, such as a resistance thermometer and a thermocouple, is provided on an outer wall 61 outside a region where the probe 4 is arranged, in addition to the plurality of heater holes 62 for receiving the heater 5.

[0042] As an example of the resistance thermometer, a platinum resistance thermometer can be used, which measures the temperature by measuring the resistivity of platinum using the fact that the resistivity of platinum changes depending on the temperature.

[0043] The sensor hole 64 is provided so that it extends in the height direction (vertical direction) from the bottom surface of the outer wall 61, and the wiring 65 with elasticity, which is connected to the sensor 7, detects an output signal of the sensor 7, and suspends the sensor 7 from the hole bottom, is provided within the sensor hole. The wiring 65 has elasticity to bias the sensor 7 in the vertical direction, and when the probe 4 of the probe card 6 is arranged so that it is in contact with the wafer 1, as shown in Fig. 10, the end face of the sensor 7 is also in contact with the wafer 1. In this state, a part of the sensor 7 is received in the sensor hole 64, the wiring 65 is compressed between the sensor 7 and the hole bottom portion, and the end face of the sensor 7 is strongly pressed against the wafer 1 by the repulsive force of the wiring 65.

[0044] As in Fig. As illustrated in Figure 11, the sensors 7 are provided at four locations outside the arrangement areas of the probes 4. The heaters 5 are provided at four locations where the probes 4 are not arranged. As described above, the probe card 6A includes the sensor 7, and the sensor 7 comes into contact with the semiconductor chip 3 at the time of inspecting the semiconductor chip 3 to be measured, whereby the temperature of the semiconductor chip 3 can be directly measured.

[0045] Traditionally, in a wafer-level test, the measured temperature of the chip is often not directly measured, and the measured temperature of the chip is determined by monitoring the temperature of the stage. However, since an in-plane temperature distribution occurs in the temperature of the stage, for example, the temperature at the end portion is lower than that in the center, a phenomenon occurs in the method of monitoring the temperature of the stage that prevents the chip temperature from being accurately measured.

[0046] However, in the wafer testing apparatus 400 according to the fourth preferred embodiment, since the temperature of the semiconductor chip 3 can be directly measured and an accurate temperature can be obtained, the temperature of the characteristic of the semiconductor chip 3 can be corrected, whereby the characteristics of the semiconductor chip 3 can be grasped in more detail.

[0047] In addition, by using a resistance thermometer, a thermocouple, and the like as the temperature sensor 7, the temperature sensor 7 can have a relatively simple structure. Fifth Preferred Embodiment

[0048] A wafer testing apparatus according to a fifth preferred embodiment of the present disclosure will be described with reference to Fig. 12 to Fig. 14 described. Fig. 12 and Fig. 13 are cross-sectional views for explaining the configuration of the wafer testing apparatus 500 of the fifth preferred embodiment, Fig. 14 is a plan view of the probe card 6B, viewed from the lower surface side, and a cross section taken along the line CC in Fig. 14 corresponds to the cross-sectional views of Fig. 12 and Fig. 13.

[0049] Fig. Fig. 12 illustrates a state in which the probe card 6B is arranged above the wafer 1 mounted on the inspection stage 2, wherein the probe card 6B is a cross-sectional view. In the probe card 6B of Fig. 12 are the same components as those of probe card 6, which are shown in Fig. 8 are designated by the same reference numerals and a repeated description is omitted.

[0050] The probe card 6B, which is in Fig. 12 is provided with a nozzle 9 of a blower (not illustrated) that blows hot air and cold air to the semiconductor chip 3, in addition to the heater 5 provided on the outer wall 61 outside the area where the probe 4 is arranged. Furthermore, a pressurizing wall 8 is provided that seals a space between the probe card 6B and the semiconductor chip 3 to be measured. The pressurizing wall 8 is provided so as to surround the outer wall 61 of the probe card 6B and is fixed to the outer wall 61 of the probe card 6B. The pressurizing wall 8 may be made of the same material as that of the outer wall 61, or it may be made of a different material. In the case of forming the pressurizing wall 8 with the same material as the outer wall 61, the pressurizing wall 8 may be formed integrally with the outer wall 61.

[0051] As in Fig. As illustrated in FIG. 14, the nozzles 9 are provided at four locations outside the arrangement areas of the probes 4. The heaters 5 are provided at four locations where the probes 4 are not arranged. The number of nozzles 9 to be arranged is not particularly limited, but from the viewpoint of uniformly increasing or decreasing the temperature of the semiconductor chip 3, it is desirably larger, and two to four heaters may be arranged as an example.

[0052] Fig. 13 illustrates a state in which the probe 4 of the probe card 6B is in contact with the wafer 1, and the end face of the heater 5 is also in contact with the wafer 1. In this state, a part of the heater 5 is accommodated in the heater hole 62, the wiring 63 is compressed between the heater 5 and the hole bottom portion, the end face of the heater 5 is strongly pressed against the wafer 1 by the repulsive force of the wiring 63, and the pressurizing wall 8 is in contact with the wafer 1, thereby sealing the space between the probe card 6B and the semiconductor chip 3 to be measured.

[0053] When the heater 5 is energized in this state, the temperature of the semiconductor chip 3 to be measured is raised from the upper surface side by heat generation of the heater 5, and the temperature is raised from the lower surface side of the semiconductor chip 3 by the temperature adjustment mechanism 11 in the inspection stage 2. Furthermore, by driving the fan to eject hot air from the nozzle 9, the temperature of the semiconductor chip 3 can be quickly raised from the upper surface side.

[0054] As described above, by raising the temperature of the semiconductor chip 3 not only from the lower surface side but also from the upper surface side, the temperature rise time can be shortened. From the perspective of raising the temperature of the semiconductor chip 3, the blower including the nozzle 9 can also be regarded as a temperature adjustment mechanism. In this case, the hot air has a temperature higher than room temperature (25°C) and is adjusted to the temperature at the time of inspection of the semiconductor chip 3 to be measured. The gas to be blown is not limited to air, and an inert gas such as nitrogen, argon, or neon can be used. However, when using Paschen's law, which will be described later, the discharge suppression effect varies depending on the type of gas to be blown, and thus the gas to be used should be adjusted with this in mind.

[0055] In addition, by setting the temperature of the blown gas to cold, that is, a temperature lower than room temperature (25 °C), the temperature of the semiconductor chip 3 can be quickly reduced, and the time during which the semiconductor chip 3 is in a high-temperature state can be shortened by controlling the temperature of the semiconductor chip 3.

[0056] In addition, by blowing gas to the semiconductor chip 3 in the space sealed by the pressurizing wall 8, a pressurized state is maintained, whereby discharge can be prevented.

[0057] That is, according to Paschen's law, the voltage at which spark discharge is caused increases by bringing the pressure close to vacuum or pressurization, whereby discharge can be suppressed at a withstand voltage of the power semiconductor device from 1200 V to 6500 V by setting the pressure to about 200 kPa (about 2 atm) to 500 kPa (about 5 atm). Therefore, it is possible to prevent discharge during the test by filling the space sealed by the pressurization wall 8 with a gas having such a pressure. Sixth Preferred Embodiment

[0058] A wafer testing apparatus according to a sixth preferred embodiment of the present disclosure will be described with reference to Fig. 15 to Fig. 18 described. Fig. 15 is a plan view for explaining a configuration of an inspection stage 2 of a wafer testing apparatus 600 according to the sixth preferred embodiment, and Fig. 16 is a cross-sectional view taken along the line DD in Fig. 15.

[0059] As in Fig. 15, the wafer 1 in which the plurality of semiconductor chips 3 are constructed is mounted on the inspection stage 2. As shown in Fig. 16, a movable stage 10 is provided within the inspection stage 2. The movable stage 10 is in contact with at least the back surface of the semiconductor chip 3 to be inspected of the wafer 1 mounted on the wafer placement table 21 of the inspection stage 2, and includes a heating device 11a therein to increase the temperature of at least the semiconductor chip 3 to be measured. In Fig. 15 and Fig. 16, the semiconductor chip 3 to be measured is surrounded by a dashed line, and in this example, three semiconductor chips 3 are to be measured, but the number of measurement targets is not limited to this.

[0060] When the semiconductor chip 3 is tested, the movable stage 10 moves directly under the semiconductor chip 3 to be measured, comes into contact with the back surface of the semiconductor chip 3 to be measured, and can intensively raise the temperature of the semiconductor chip 3 to be measured, not the entire wafer 1. Therefore, heat is less likely to diffuse at the inspection stage 2, and the temperature rise time can be shortened compared to the inspection stage 2 of the first preferred embodiment in which the inspection stage 2 is in contact with the entire wafer 1.

[0061] A movable mechanism (not illustrated) of the movable stage 10 is provided under the wafer placement table 21, whereby the movable stage 10 can cover the entire wafer 1, and is a mechanism capable of raising the temperature of the semiconductor chip 3 at the end of the wafer 1.

[0062] Fig. 17 and Fig. 18 are diagrams illustrating a wafer test using the wafer test apparatus 600, wherein Fig. 17 illustrates an example in which three semiconductor chips 3 are tested simultaneously, and Fig. 18 illustrates an example in which the semiconductor chips 3 are tested individually.

[0063] In the Fig. In the example illustrated in Figure 17, the movable stage 10 raises the temperatures of the three semiconductor chips 3, and the probes 4 extending from the three test circuits TB1, TB2, and TB3 of the probe card 6 are in contact with the three semiconductor chips 3 to be measured and are tested simultaneously. When the tests of the three semiconductor chips 3 are completed, the movable stage 10 moves under the next semiconductor chip 3 to be measured.

[0064] The Fig.The example illustrated in Figure 18 illustrates a state in which the movable stage 10 raises the temperatures of the three semiconductor chips 3A, 3B, and 3C, and the probe 4 extending from the test circuit TB1 of the probe card 6 comes into contact with the semiconductor chip 3A to be measured to perform a test. When the test of the semiconductor chip 3A is completed, the probe card 6 moves, and the probe 4 extending from the test circuit TB1 comes into contact with the semiconductor chip 3B to perform the test. When the test of the semiconductor chip 3B is completed, the probe card 6 moves, and the probe 4 extending from the test circuit TB1 comes into contact with the semiconductor chip 3C to perform the test. When the tests of the semiconductor chips 3A to 3C are completed, the movable stage 10 moves under the next semiconductor chip 3 to be measured.

[0065] It should be noted that in the present disclosure, each preferred embodiment can be freely combined, and each preferred embodiment can be appropriately changed or omitted within the scope of the disclosure.

[0066] The present disclosure described above is collectively referred to as the Appendices. (Appendix 1)

[0067] Wafer testing apparatus comprising: an inspection stage on which a wafer with a plurality of semiconductor chips is mounted; and a probe card that inspects the multitude of semiconductor chips, wherein the inspection stage includes a temperature adjustment mechanism capable of adjusting a temperature of a portion of the wafer, and the temperature adjustment mechanism includes a plurality of first heating devices which are separately and independently controlled. (Appendix 2)

[0068] The wafer testing apparatus according to Appendix 1, wherein in the temperature adjusting mechanism, the plurality of first heaters are controlled to increase a temperature of at least one semiconductor chip among the plurality of semiconductor chips. (Appendix 3)

[0069] Wafer testing apparatus according to Appendix 1, wherein the plurality of first heating devices are provided within the inspection stage. (Appendix 4)

[0070] A wafer testing apparatus according to any one of appendices 1 to 3, wherein in the temperature adjusting mechanism, the plurality of first heaters are controlled to increase a temperature of a corresponding portion of the wafer according to a preset inspection order of the plurality of semiconductor chips. (Appendix 5)

[0071] Wafer test device according to Appendix 4, wherein the inspection order of the plurality of semiconductor chips is set to have a plurality of inspection paths based on a layout of the plurality of semiconductor chips, and the plurality of inspection paths are set so that they are spaced apart from each other by a width of at least one semiconductor chip. (Appendix 6)

[0072] The wafer testing apparatus according to Appendix 1, wherein the probe card includes a second heater disposed above the inspection stage and contacting a surface of a semiconductor chip to be measured among the plurality of semiconductor chips through a probe brought into contact with the semiconductor chip to be measured. (Appendix 7)

[0073] The wafer testing apparatus according to Appendix 6, wherein the probe card further includes a temperature sensor that comes into contact with the surface of the semiconductor chip to be measured by the probe that is brought into contact with the semiconductor chip to be measured. (Appendix 8)

[0074] Wafer test apparatus according to Appendix 7, wherein the temperature sensor comprises a resistance thermometer or a thermocouple. (Appendix 9)

[0075] The wafer testing apparatus according to Appendix 6, wherein the probe card further includes a nozzle of a blower that blows hot air or cold air to the semiconductor chip to be measured in a state where the probe is in contact with the semiconductor chip to be measured. (Appendix 10)

[0076] The wafer testing apparatus according to Appendix 9, wherein the probe card includes a pressurizing wall that seals a space between the probe card and the semiconductor chip to be measured in a state where the probe is in contact with the semiconductor chip to be measured. (Appendix 11)

[0077] Wafer testing apparatus according to Appendix 1, wherein the inspection stage is a movable stage partially in contact with the wafer in a state where the wafer is mounted thereon, and the movable stage is controlled to come into contact with a surface of a semiconductor chip to be measured among the plurality of semiconductor chips to raise the temperature of the semiconductor chip to be measured, and to move when the measurement of the semiconductor chip to be measured is completed.

[0078] While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations may be developed. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2022-030909

[0004]

Claims

[1] Wafer test apparatus comprising: an inspection stage (2) on which a wafer (1) with a plurality of semiconductor chips (3) is mounted; and a probe card (6) which inspects the plurality of semiconductor chips, wherein the inspection stage includes a temperature adjustment mechanism (11) capable of adjusting a temperature of a part of the wafer, and the temperature adjusting mechanism includes a plurality of first heating devices (11a) which are controlled separately and independently from each other. [2] The wafer testing apparatus according to claim 1, wherein in the temperature adjusting mechanism, the plurality of first heaters are controlled to increase a temperature of at least one semiconductor chip among the plurality of semiconductor chips. [3] A wafer testing apparatus according to claim 1, wherein the plurality of first heaters are provided within the inspection stage. [4] A wafer testing apparatus according to any one of claims 1 to 3, wherein in the temperature adjusting mechanism, the plurality of first heaters are controlled to increase a temperature of a corresponding region of the wafer according to a preset inspection order of the plurality of semiconductor chips. [5] A wafer testing apparatus according to claim 4, wherein the inspection order of the plurality of semiconductor chips is set to have a plurality of inspection paths based on a layout of the plurality of semiconductor chips, and the plurality of inspection paths are set to be spaced apart from each other by a width of at least one semiconductor chip. [6] A wafer testing apparatus according to claim 1, wherein the probe card includes a second heater (5) disposed above the inspection stage and coming into contact with a surface of a semiconductor chip to be measured among the plurality of semiconductor chips through a probe (4) brought into contact with the semiconductor chip to be measured. [7] A wafer testing apparatus according to claim 6, wherein the probe card further includes a temperature sensor (7) that comes into contact with the surface of the semiconductor chip to be measured by the probe that is brought into contact with the semiconductor chip to be measured. [8] A wafer testing apparatus according to claim 7, wherein the temperature sensor comprises a resistance thermometer or a thermocouple. [9] A wafer testing apparatus according to claim 6, wherein the probe card further includes a nozzle (9) of a blower that blows hot air or cold air to the semiconductor chip to be measured in a state where the probe is in contact with the semiconductor chip to be measured. [10] A wafer testing apparatus according to claim 9, wherein the probe card includes a pressurizing wall (8) that seals a space between the probe card and the semiconductor chip to be measured in a state where the probe is in contact with the semiconductor chip to be measured. [11] Wafer testing apparatus according to claim 1, wherein the inspection stage is a movable stage (10) partially in contact with the wafer in a state in which the wafer is mounted thereon, and the movable stage is controlled to come into contact with a surface of a semiconductor chip to be measured among the plurality of semiconductor chips to raise the temperature of the semiconductor chip to be measured, and to move when the measurement of the semiconductor chip to be measured is completed.

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