Wafer mounting apparatus, semiconductor manufacturing apparatus, method for manufacturing a semiconductor device, and semiconductor device

Abstract

A ring (12) is mounted on a satellite disk (13) such that a terrace part (12t) is supported by a front surface (13d) of a peripheral part of a peripheral part (13p) of the satellite disk (13). A SiC wafer (14) is mounted on three lifting pins (15) on a front surface of the terrace part (12t). An upper disk space (S13) is formed between a front surface (13s) of an upper layer part (13u) of the satellite disk (13) and a rear surface of the SiC wafer (14). A wall part (12b) of the ring (12) is arranged to face a flat orientation part (14k) via a gap space (S12). On the back surface side of the SiC wafer (14), an annular groove (2) (groove (2k)) is formed along an outer periphery of an opening (O12) in a plan view, and a side surface of the groove (2) is a side surface of the upper layer part (13u).

Description

Background of the inventionField of the invention

[0001] The present disclosure relates to a wafer mounting apparatus for mounting a semiconductor wafer, characterized by a susceptor used for epitaxial growth of a SiC layer on a SiC single crystal wafer. Description of the state of the art

[0002] A susceptor used for epitaxial growth of a SiC layer on a SiC single-crystal wafer is generally known as a conventional wafer mounting device. A conventional susceptor is disclosed, for example, in Japanese Patent Application Laid-Open No. 2016-119472.

[0003] Japanese Patent Application Laid-Open No. 2016-119472 features a technique in which a step between a top surface of a susceptor and a top surface of a silicon wafer is set to 1 mm or more, and by using a susceptor having this characteristic, an epi-crown phenomenon is suppressed, which will be described later. Furthermore, Japanese Patent Application Laid-Open No. 2014-27006 or Japanese Patent Application Laid-Open No. 7-226349 (1995) also discloses a conventional technique for suppressing an epi-crown phenomenon.

[0004] As a technology developed from a wafer mounter typed as a susceptor, a SiC epitaxial growth apparatus, which is a semiconductor manufacturing apparatus including the wafer mounter, can be considered. Furthermore, a method for manufacturing a semiconductor device using a SiC epitaxial growth apparatus and a semiconductor device manufactured by the method for manufacturing a semiconductor device are also conceivable.

[0005] When an epitaxial layer is formed on the front surface of a semiconductor wafer, such as a silicon wafer, a wafer-susceptor peak distance exists, which indicates a length in a height direction between the top surface of the susceptor and the front surface of the semiconductor wafer, as an index related to the film thickness of the epitaxial layer. If the wafer-susceptor peak distance is set relatively large, the epitaxial thickness, which is the film thickness of the epitaxial layer, is affected in a peripheral region, which is the outermost peripheral part of the semiconductor wafer, and in-plane uniformity of the epitaxial thickness deteriorates. Summary

[0006] The present disclosure has been made to solve the problems described above, and it is an object of the present disclosure to obtain a wafer mounting apparatus that improves intra-plane uniformity in an epitaxial layer formed on a front surface of a semiconductor wafer.

[0007] A wafer mounting apparatus according to the present disclosure is a wafer mounting apparatus that mounts a semiconductor wafer having a cut-out portion, and a disk, a ring, and a plurality of lifting members.

[0008] The disc has a convex upper layer.

[0009] The ring is arranged on the disc and has an opening in the middle.

[0010] The plurality of lifting elements are arranged on a lifting region provided on the disk or the ring, and they support the semiconductor wafer from a rear surface.

[0011] The ring has a protruding wall part of the cut-out side, which protrudes towards the opening.

[0012] A semiconductor wafer mounting state is a state in which the semiconductor wafer is mounted on the plurality of lifting members so that the semiconductor wafer fits into the opening in plan view without being in contact with the ring.

[0013] In the wafer mounting state, the projecting wall portion of the cut-out side faces the cut-out portion of the semiconductor wafer, and an upper wafer space is formed between a front surface of the upper layer portion of the wafer and a rear surface of the semiconductor wafer except for a formation region of the plurality of lifting members.

[0014] In the wafer mounting state, an annular groove having an annular shape is formed along an outer periphery of the opening in a plan view between the upper layer part of the disk and the ring on one side of the back surface of the semiconductor wafer.

[0015] In the wafer mounting state, a side surface of the upper layer part of the disk is a side surface of the annular groove.

[0016] The wafer mounting apparatus of the present disclosure may provide an upper wafer space between the back surface of the semiconductor wafer and the front surface of the wafer during the semiconductor wafer mounting state.

[0017] Moreover, in the wafer mounting apparatus of the present disclosure, during the semiconductor wafer mounting state, an annular groove having a ring shape is formed between the upper layer part of the disk and the ring on the back side of the semiconductor wafer, and a side surface of the upper layer part of the disk is a side surface of the annular groove.

[0018] Therefore, when the source gas is supplied above the front surface of the semiconductor wafer in the semiconductor wafer mounting state, a part of the source gas can be intentionally discharged into the upper wafer space on the rear side of the semiconductor wafer via the annular groove.

[0019] Therefore, when an epitaxial layer is formed on the front surface of the semiconductor wafer in the semiconductor wafer mounting state by an epitaxial growth process, it is possible to suppress the occurrence of the epi-crown phenomenon in which the epi thickness, which is the film thickness of the epitaxial growth layer, is locally increased.

[0020] As a result, the wafer mounting apparatus of the present disclosure has an effect of being able to form an epitaxial layer having an epi thickness with excellent in-plane uniformity on the upper surface of the semiconductor wafer in the semiconductor wafer mounting state.

[0021] These and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying figures. Short description of the characters Fig. 1 is an explanatory view schematically illustrating a planar configuration of a susceptor, which is a basic configuration of a first preferred embodiment; Fig. Fig. 2 is an explanatory view schematically showing a configuration of an A1-A1 cross section of Fig. 1 illustrates; Fig. 3 is an explanatory view schematically showing a configuration of a B1-B1 cross section of Fig. 1 illustrates; Fig. Fig. 4 is an explanatory view schematically showing a configuration of a C1-C1 cross section of Fig. 1 illustrates; Fig. 5 is an explanatory view schematically showing an enlarged cross-sectional configuration of Fig. 2 illustrates; Fig. 6 is an explanatory view schematically illustrating a planar configuration of a susceptor which is a first modification of the first preferred embodiment; Fig. Fig. 7 is an explanatory view schematically illustrating a configuration of a cross section taken along a line A11-A11 in Fig. 6; Fig. Fig. 8 is an explanatory view schematically illustrating a configuration of a cross section taken along a line B11-B11 in Fig. 6; Fig. Fig. 9 is an explanatory view schematically illustrating a configuration of a cross section taken along a line C11-C11 in Fig. 6; Fig. 10 is an explanatory view schematically illustrating a planar configuration of a susceptor which is a second modification of the first preferred embodiment; Fig. 11 is an explanatory view schematically illustrating a configuration of a cross section taken along a line A12-A12 in Fig. 10 is taken; Fig. Fig. 12 is an explanatory view schematically illustrating a configuration of a cross section taken along a line B12-B12 in Fig. 10 is taken; Fig. 13 is an explanatory view schematically illustrating a configuration of a cross section taken along a line C12-C12 in Fig. 10 is taken; Fig. 14 is an explanatory view schematically illustrating a planar configuration of a susceptor which is a basic configuration of a second preferred embodiment; Fig. 15 is an explanatory view schematically showing a configuration of an A2-A2 cross section in Fig. 14 illustrates; Fig. 16 is an explanatory view schematically showing a configuration of a B2-B2 cross section of Fig. 14 illustrates; Fig. Fig. 17 is an enlarged explanatory view showing a focused region R2 in Fig. 14 illustrates; Fig. 18 is an explanatory view schematically illustrating a planar configuration of a susceptor as a basic configuration of a third preferred embodiment; Fig. 19 is an explanatory view schematically showing a configuration of an A3-A3 cross section of Fig. 18 illustrates; Fig. 20 is an explanatory view schematically showing a configuration of a B4-B4 cross section in Fig. 18 illustrates; Fig. 21 is an explanatory view schematically showing a configuration of a C4-C4 cross section of Fig. 18 illustrates; Fig. 22 is an explanatory view schematically illustrating a planar configuration of a susceptor which is a basic configuration of a fourth preferred embodiment; Fig. 23 is an explanatory view schematically showing a configuration of an A4-A4 cross section in Fig. 22 illustrates; Fig. 24 is an explanatory view schematically showing a configuration of a B4-B4 cross section in Fig. 22 illustrates; Fig. 25 is an explanatory view schematically illustrating a cross-sectional structure of a semiconductor manufacturing apparatus having a susceptor used in a preferred embodiment of the present disclosure; Fig. 26 is an explanatory view schematically illustrating a planar configuration of the semiconductor manufacturing apparatus; Fig. 27 is a flowchart illustrating a processing procedure of a method of manufacturing a semiconductor device using a semiconductor manufacturing apparatus; Fig. 28 is a cross-sectional view illustrating a cross-sectional structure of a semiconductor device manufactured by the method for manufacturing a semiconductor device; Fig. Fig. 29 is an explanatory view schematically illustrating an epi-crown phenomenon; Fig. 30A and Fig. 30B are explanatory views schematically illustrating a conventional susceptor; Fig. 31 is a diagram illustrating an epi crown height when an epitaxial layer is grown using the method shown in Fig. 30A and Fig. 30B illustrated susceptor; Fig. 32 is a diagram schematically illustrating a relationship between a measurement point and a reference point on a front surface of a SiC wafer; Fig. 33 is a diagram illustrating a correlation of an epi-crown height at an OF center portion when a wafer-susceptor tip distance is changed; Fig. 34 is a diagram illustrating a correlation between an average epi thickness of an outer peripheral part of a wafer and the wafer-susceptor tip distance; Fig. 35 is a diagram illustrating an epi thickness when a wafer-susceptor tip distance is 0.7 mm; Fig. 36 is a diagram illustrating an epi thickness when a wafer-susceptor tip distance is 2.5 mm; Fig. 37 is an explanatory view schematically illustrating a planar configuration of a conventional susceptor; Fig. 38 is a diagram illustrating an example of an epi crown height when an epitaxial layer is formed on a front surface of a semiconductor wafer using a Fig. 37 illustrated susceptor; Fig. 39 is an explanatory diagram illustrating a fluid simulation result with respect to a fluid velocity of a source gas; Fig. 40 is a diagram illustrating an epi crown height based on a difference in a method of mounting a SiC wafer; and Fig. 41 is a diagram illustrating an epi thickness based on a difference in a method of mounting a SiC wafer. Description of the preferred embodiments<Basis der vorliegenden Offenbarung>

[0022] As a basic technology related to a susceptor that is a wafer mounting apparatus of the present disclosure, a conventional example and its problems will be described. In recent years, there has been an increasing demand for single-crystal epitaxial wafers containing SiC as a material as a substrate for high-withstand voltage electronic devices and the like.

[0023] When manufacturing a power device using a SiC single-crystal wafer (hereinafter referred to as "SiC wafer"), it is common to grow a thin SiC single-crystal layer on the SiC wafer by a thermal chemical vapor deposition method (hereinafter referred to as "thermal chemical vapor deposition (CVD) method"), block a basal plane dislocation (BPD) on the SiC wafer, and form the device in a layer in which a doping concentration of impurities is controlled. When epitaxial growth is performed by a thermal CVD method, a SiC wafer is placed on a susceptor in an apparatus, and a silicon source gas such as a silane gas or a chlorosilane gas, or a carbon source gas such as propane or methane, along with a carrier gas such as hydrogen, is supplied to the wafer while the susceptor is rotated to perform epitaxial growth.The silicon source gas and the carbon source gas described above serve as source gases for epitaxial growth.

[0024] In order to prevent the SiC wafer from shifting during epitaxial growth, the susceptor is generally provided with a depression (recess) corresponding to the wafer thickness, and the above-described source gas is caused to flow laterally toward the SiC wafer inserted therein so that it flows substantially horizontally to the front surface of the SiC wafer.

[0025] In a 6-inch or larger SiC wafer, warpage of the SiC wafer increases during epitaxial growth, so a bowl-shaped (recessed) counterbore surface is used as a wafer mounting surface. By holding the SiC wafer at an outer peripheral portion of the wafer, it is possible to prevent contact between a center portion of the wafer and the counterbore surface during film formation, and to prevent a decrease in the temperature of the center portion of the wafer. This effect improves the in-plane uniformity of the film thickness and the carrier concentration of an epitaxial layer.

[0026] In-plane uniformity of layer thickness and carrier concentration is an important characteristic of the epitaxial growth layer. For example, layer thickness unevenness is likely to occur in the outermost peripheral part of the SiC wafer, and a region of several mm from the outermost peripheral part of the wafer cannot be used for device fabrication. This unusable region is called edge exclusion or end cut. However, if this region can be reduced, the region in which semiconductor chips can be formed can be expanded, and the yield of the semiconductor chip can be improved. It is preferable that the edge exclusion and end cut are small.

[0027] Fig. Figure 29 is an explanatory view schematically illustrating an epi-crown phenomenon. As illustrated in the figure, an N -Epitaxial layer 62 is formed on a front surface of a SiC wafer 61w.

[0028] During epitaxial growth on the semiconductor area, as in Fig. 29, it is known that the layer thickness of the N - Epitaxial layer 62 increases at the outer peripheral part of the wafer, which is a region near an end part of a front surface of the SiC wafer 61w, and as a result, an epi-crown 62t is formed by an epi-crown height H62 higher than a front surface of the other region of the N epitaxial layer 62. When the epi-crown 62t is formed, it is necessary to increase the edge exclusion, so the elimination of the epi-crown 62t is required.

[0029] Various methods for resolving epi-crowns have been proposed so far. The technique disclosed in Japanese Patent Application Laid-Open No. 7-226349 (1995) is a technique for thinning the film thickness of the outer peripheral part of the SiC wafer in advance, along with the growth of the epi-crown, and preventing the film thickness of the outer peripheral part from becoming thicker than the region even when the epi-crown occurs.

[0030] The technique disclosed in Japanese Patent Application Laid-Open No. 2014-27006 is a technique for removing the formed epi crown after epitaxial growth. Furthermore, the technique disclosed in Japanese Patent Application Laid-Open No. 2016-119472 discloses a technique for increasing a wafer-susceptor tip distance, which is a step length between the front surface of the SiC wafer and the top surface of the susceptor, to suppress supply of source gas to the outer peripheral part of the wafer.

[0031] However, in the method of thinning the outer peripheral part of the wafer in advance as disclosed in the technology in Japanese Patent Application Laid-Open No. 7-226349 (1995), it is necessary to remove the outer peripheral part in accordance with the film thickness of the epitaxial layer to be formed and the film thickness of the epi crown to be formed at that time, and the wafer having the thinner outer peripheral part is a dedicated wafer for forming an epitaxial layer having a specific thickness.

[0032] In an actual manufacturing facility, since the specifications of the epitaxial layer vary depending on the type of device to be manufactured, it is not desirable to prepare and store wafers associated with specific layer formation conditions because the production efficiency will be significantly deteriorated.

[0033] As in the technique disclosed in Japanese Patent Application Laid-Open No. 2014-27006, in the case of removing the epi-crown after the epitaxial layer is grown, since the area around the epi-crown is scraped off by grinding, there is also a problem that the epitaxial layer is roughened due to damage during grinding. A semiconductor device formed on such a polished surface is likely to exhibit poor performance, and thus, the yield of the semiconductor chip is not necessarily improved. Furthermore, the methods disclosed in Japanese Patent Application Laid-Open No. 2014-27006 and Japanese Patent Application Laid-Open No. 7-226349 (1995) also have a problem that the number of steps for removing the epi-crown increases.

[0034] In contrast, the technique disclosed in Japanese Patent Application Laid-Open No. 2016-119472 is excellent in that there is no wafer processing compared with Japanese Patent Application Laid-Open No. 2014-27006 and Japanese Patent Application Laid-Open No. 7-226349 (1995), but it has recently been found that the following problems exist while the investigation is continuing.

[0035] The Fig. 30A and Fig. 30B are explanatory views schematically illustrating a conventional susceptor used for film formation. Fig. Figure 30A illustrates a planar configuration of the susceptor, and Fig. Figure 30B illustrates a cross-sectional structure of the susceptor.

[0036] As in the Fig. 30A and Fig. As illustrated in Figure 30B, a SiC wafer 73 is housed in a circular depression 72 of a susceptor 71. A source gas G1 is supplied along a source gas supply direction F1 above a front surface of the SiC wafer 73. In this way, the source gas G1 serving as a source gas for epitaxial growth is supplied along a source gas flow F2.

[0037] As in Fig. 30B, the distance between the top surface of the susceptor 71 and the front surface of the SiC wafer 73 is a wafer-susceptor tip distance DT.

[0038] By performing a thermal CVD process for heating the SiC wafer 73 by a heating mechanism (not illustrated) provided on the susceptor 71 in a state where the source gas G1 is supplied, an epitaxial layer can be formed on the front surface of the SiC wafer 73.

[0039] Fig. Fig. 31 is a diagram illustrating a result of normalizing an epi crown height (four points in a plane) when an epitaxial layer is grown on a front surface of a 6-inch SiC wafer 73 using the susceptor 71 shown in Figs. Fig. 30A and Fig. 30B, by an average epi thickness of the wafer. Fig. 32 is an explanatory diagram schematically illustrating a relationship between measurement points P1 to P4 and reference points B1 to B4 on the front surface of the SiC wafer 73.

[0040] Four points within the plane that are in Fig. 31 are measurement points P1 to P4 along an outer periphery of the SiC wafer 73. It should be noted that an epi-crown height, which is determined by an epi-crown change L1 in Fig. 31 indicates a difference between an epi-thickness of the outermost peripheral part and an epi-thickness of a position of about 5 mm inward from the end of the SiC wafer 73. That is, there is indicated a difference in an epi-thickness between a measurement point Pi (any one of i = 1 to 4) which is in Fig. 32 and a reference point Bi. A distance DP, which is Fig. 32 indicates a distance of approximately 5 mm inward from the end of the SiC wafer 73.

[0041] As in Fig. As illustrated in Figure 31, an epi-crown height at the measurement point P1 where the measurement angle θ corresponds to 0° (360°) is the maximum value. As described above, it can be seen that a high epi-crown is formed, projecting toward the center of a flat orientation portion 73k in an outer peripheral portion of the front surface of the SiC wafer 73. For convenience, the flat orientation center portion may be simply referred to as an "OF center portion," and the flat orientation portion may be simply referred to as an "OF portion."

[0042] A characteristic corresponding to the “step between a top surface of a susceptor and a top surface of a silicon wafer” disclosed in Japanese Patent Application Laid-Open No. 2016-119472 is the wafer-susceptor tip distance DT, which is shown in the Fig. 30A and Fig. 30B is illustrated.

[0043] Fig. Figure 33 is a graph illustrating a result of an investigation into the correlation of the epi-crown height (normalized by an average epi-thickness) at the OF center portion when the wafer-susceptor tip distance DT is changed. Based on an epi-crown height change L2 at the OF center portion, which is Fig. As illustrated in Figure 33, when the wafer-susceptor tip distance DT is increased, a result is obtained in which the epi-crown at the OF center portion decreases, and the technique disclosed in Japanese Patent Application Laid-Open No. 2016-119472 appears to be effective. However, it has been newly discovered that the wafer-susceptor tip distance DT is a parameter that affects not only the epi-crown but also the epi-thickness of the entire outer peripheral portion of the wafer.

[0044] Fig. Figure 34 is a graph illustrating the correlation between the average epi thickness of the outer peripheral part of the wafer and the wafer-susceptor tip distance DT. As shown by the measurement points P11 to P17 in Fig. 34, the average epi thickness is a value obtained by normalizing measurement values ​​at the seven measurement points P11 to P17, excluding the region located 5 mm from the end part of the SiC wafer 73 and near the OF part, by the average epi thickness of the SiC wafer 73.

[0045] Based on an average epi-thickness change L3 in the Fig. 34, it can be seen that the epi thickness in the outer peripheral part of the SiC wafer 73 decreases as the wafer-susceptor tip distance DT increases.

[0046] Fig. 35 is a diagram illustrating an epi thickness along an X direction when the wafer-susceptor tip distance DT is 0.7 mm. Fig. Figure 36 is a graph illustrating an epi thickness along the X direction when the wafer-to-susceptor tip distance DT is 2.5 mm. Note that the epi thickness is represented by a value normalized by the average epi thickness of the SiC wafer 73.

[0047] In each of the Fig. 35 and Fig. 36, the origin “0” which intersects the X-axis and the Y-axis is a position at which a measuring distance ΔD corresponds to “0”, the measuring distance ΔD on a +X direction side is a positive distance [mm], and the measuring distance ΔD on a -X direction side is a negative distance [mm].

[0048] Based on an epi-thickness change L4, which Fig. 35 and an epi-thickness change L5, which is Fig. 36, it can be seen that the epi-thickness of the outer peripheral part of the SiC wafer 73 changes significantly as the wafer-susceptor tip distance DT increases. Furthermore, from the epi-thickness change L5 shown in Fig. 36, it can be seen that the epi thickness decreases sharply near the end part of the SiC wafer 73 where the measuring distance ΔD is approximately ±70 mm.

[0049] Although the epi crown generated in the outer peripheral part of the SiC wafer 73 can be suppressed, if the epi thickness of the outer peripheral part of the wafer is significantly reduced, the technique disclosed in Japanese Patent Application Laid-Open No. 2016-119472 cannot be incorporated into a semiconductor chip manufacturing process and reduces the wafer yield in the epitaxial growth process, which is undesirable.

[0050] The wafer mounting apparatus (susceptor) of the present disclosure is intended to reduce an ineffective region of a wafer by suppressing an epi crown without extremely reducing the epi thickness of the outer peripheral part of the wafer.

[0051] The inventors of the wafer mounting apparatus of the present disclosure conducted various studies to investigate an influencing factor for forming a high epi-crown in the OF part and a region near it, and found one influencing factor. It is the distance between the wafer and the counterbore inner wall.

[0052] Fig. 37 is an explanatory view schematically illustrating a planar configuration of a conventional susceptor. As illustrated in the figure, a susceptor 132 includes three semiconductor wafers 131, such as SiC wafers, mounted in a depression 133. Source gas G1 is supplied along the source gas supply direction F1 above the three semiconductor wafers 131, while the susceptor 132 rotates along a susceptor rotation direction R132.

[0053] Fig. 38 is a diagram illustrating an example of an epi crown height when an epitaxial layer is formed on a front surface of the semiconductor wafer 131 using the method shown in Fig. 37. It should be noted that the epi-crown height, which is characterized by an epi-crown change L6, is normalized by the average epi-thickness.

[0054] As in Fig. As illustrated in Figure 38, the Epi-Crown has two peaks on the opposite side of the OF part, and the part indicating the peak corresponds to the part indicated by “A” in Fig. 37. If this is combined with the Fig. 31, it can be seen that the distance between the outer periphery of the wafer and the counterbore inner wall affects the epi-crown.

[0055] From these results, it can be concluded that it is important to use a counterbore in which the counterbore inner wall and the wafer end are not extremely separated, that is, a counterbore with a shape that matches the wafer shape, in order to suppress the epi-crown.

[0056] Fig. Figure 39 is an explanatory diagram illustrating a fluid simulation result regarding the fluid velocity of the source gas G1. A point concentration in the figure has a negative correlation with a flow rate of the source gas G1, and a region having a higher point concentration indicates that the flow rate of the source gas G1 is lower.

[0057] As in Fig. As illustrated in Fig. 39, the source gas G1, which has flowed over the susceptor 132, flows through the wafer mounting surface, collides with the end part of the SiC wafer 73 such as the flat orientation part 73k, and is then supplied to the front surface of the SiC wafer 73. That is, the peripheral end region R73 of the SiC wafer 73 is a region where the flow rate of the source gas G1 is the slowest.

[0058] Therefore, the peripheral end region R73 in which the flow rate of the source gas G1 for epitaxial growth is the slowest is a region in which the extent of epitaxial growth is the highest, and consequently, it is conceivable that an epi-crown is formed in the peripheral end region R73.

[0059] Therefore, when the recess inner wall and the end part of the SiC wafer 73 are close to each other, the source gas G1 is supplied to the front surface of the semiconductor wafer 131 without flowing through the wafer mounting surface of the recess 133, and as a result, it is possible to avoid forming a region in which the flow velocity of the source gas G1 decreases, such as the peripheral end region R73 in Fig. 39, and thus it is conceivable that this is effective for suppressing the epi-crown.

[0060] Next, a method for holding a semiconductor wafer was studied. Fig. 40 is a diagram illustrating an epi crown height based on a difference in a method of mounting a SiC wafer.

[0061] An epi crown height variation L8 indicates a normalized value of the epi thickness when a 6-inch SiC wafer is used as the SiC wafer 73 and the SiC wafer 73 is placed directly on the mounting surface. An epi crown height variation L7 indicates a normalized value of the epi thickness when the SiC wafer 73 is lifted at multiple points and the back surface of the wafer and the susceptor are separated (hereinafter, this may be referred to as "lifting").

[0062] Note that the counterbore has a shape corresponding to the shape of the SiC wafer 73, and the wafer-susceptor tip distance DT is identical between the epi-crown height variation L7 and the epi-crown height variation L8. As indicated by the epi-crown height variation L8, even in the case of direct placement in the counterbore shape corresponding to the shape of the SiC wafer 73, a high epi-crown is still formed on the OF portion. In contrast, as indicated by the epi-crown height variation L7, when the SiC wafer 73 is lifted, the epi-crown in the OF portion decreases.

[0063] This is conceivable because a space is formed on the back surface side of the SiC wafer 73 by the lifting, and thus a part of the source gas G1 escapes to the back surface of the SiC wafer 73.

[0064] Fig. 41 is a diagram illustrating an epi thickness along the X direction based on a difference in a method for mounting the SiC wafer. An epi thickness change L9 indicates a normalized value of the epi thickness when the SiC wafer 73 is lifted, and an epi thickness change L10 indicates a normalized value of the epi thickness when the SiC wafer 73 is directly placed.

[0065] In Fig. 41, the origin is “0”, which intersects the X-axis and the Y-axis at a position at which a measuring distance ΔD corresponds to “0”, the measuring distance ΔD on a +X direction side is a positive distance [mm], and the measuring distance ΔD on a -X direction side is a negative distance [mm].

[0066] As shown by the epi-thickness changes L9 and L10 in Fig. 41, when both wafer-susceptor peak distances DT are identical to each other, no significant change occurs with respect to the distribution shape within the plane of the epi thickness.

[0067] Based on the above experimental results, the inventors have provided the wafer mounting apparatus of the present disclosure. In the wafer mounting apparatus of the present disclosure, a susceptor is provided having an opening with a wall portion corresponding to the shape of the semiconductor wafer, so that the distance between a cavity inner wall and a wafer end is not extremely separated, and the epitaxial growth process can be performed in a state where the semiconductor wafer is raised.

[0068] By lifting and mounting the semiconductor wafer, a space is formed on the back surface of the semiconductor wafer, and part of the source gas is discharged into the space so that the epi crown can be reduced.

[0069] One point of epi-crown reduction is to discharge a portion of the source gas G1 supplied to the surface of the semiconductor wafer to the back surface of the semiconductor wafer. Therefore, the wafer mounting apparatus of the present disclosure is characterized in that an annular groove having a ring shape is provided on the wafer mounting surface below the outermost peripheral part of the semiconductor wafer to ensure a flow path of the source gas G1, and a flow path of the source gas G1 formed around the OF part where the high epi-crown is formed is deeper than the other region.

[0070] The wafer mounting apparatus of the present disclosure obtained based on the above technical consideration is the wafer mounting apparatus described in the following first to fourth preferred embodiments. <Wafer-Montagegerät der vorliegenden Offenbarung> (Introduction)

[0071] The following describes a susceptor, which is a wafer mounting apparatus of the present disclosure, and a semiconductor manufacturing apparatus for a SiC wafer (SiC epitaxial wafer). Note that, in the figures used in the following description, in order to facilitate understanding of characteristics of the wafer mounting apparatus of the present disclosure, characteristic parts may be illustrated in an enlarged manner for convenience, and the size ratios and the like of the respective components may differ from the actual ones. Furthermore, materials, sizes, and the like explained in the following description are merely examples, and the present disclosure is not limited thereto and can be appropriately modified and implemented without changing its essence. (Semiconductor manufacturing device)

[0072] Fig. Fig. 25 is an explanatory view schematically illustrating a cross-sectional structure of a semiconductor manufacturing apparatus 50 including a susceptor 11 and the like according to the first preferred embodiment of the present disclosure. The semiconductor manufacturing apparatus 50 is also called a "SiC epitaxial wafer manufacturing apparatus" and is an apparatus for forming an epitaxial layer on a front surface of a SiC wafer. Although the semiconductor manufacturing apparatus 50 is not limited to the Fig. 25, in order to facilitate understanding, an embodiment described below will be described based on the configuration illustrated in Fig. 25 illustrated semiconductor manufacturing apparatus 50 is described.

[0073] The Fig. The semiconductor manufacturing apparatus 50 illustrated in Fig. 25 is an apparatus called a planetary susceptor type, and it comprises an upper plate 185 in an upper part in a chamber 181, a planetary susceptor 182 and an induction heating coil 188 in a lower part, and an injector 186 vertically penetrating the chamber 181 from a central part of the upper plate 185.

[0074] In a part of the planetary susceptor 182, a plurality of satellite disks 183 are arranged in a plurality of receiving regions 189 around a central portion 187. A SiC wafer 184 is inserted into the satellite disks 183. The source gas G1 flows radially from the injector 186, and epitaxial growth is performed on a front surface of the SiC wafer 184. Epitaxial growth on a front surface of the satellite disk 183 is performed in a temperature range of approximately 1400°C to 1700°C by heat treatment using the induction heating coil 188.

[0075] Subsequently, when the interior of the semiconductor manufacturing apparatus 50 reaches a desired temperature, a dopant gas is placed on the carrier gas, in addition to a silicon-based gas (silicon source gas) and a hydrocarbon gas. The source gas G1 is caused to flow from the side so that it is substantially horizontal to the SiC wafer 184, and an epitaxial growth process is performed. Silane (SiH4), dichlorosilane (SiCl2H2), trichlorosilane (SiCl3), silicon tetrachloride (SiCl4), and the like are conceivable as the silicon source gas, and propane (C3H8), ethane (C2H6), and the like are conceivable as the hydrocarbon gas as the carbon source gas.

[0076] For the purpose of improving the growth rate during the epitaxial growth process, HCl or the source gas G1 containing Cl such as SiH2Cl2 can be used. Since the source gas G1 for epitaxial growth, which is introduced from the injector 186, reaches the outside of the chamber 181 while being consumed for epitaxial growth, the growth rate and carrier concentration are different upstream and downstream. Thus, while the planetary susceptor 182 is mechanically rotated along a susceptor rotation direction R182 in a state where the source gas G1 is supplied, the satellite disk 183 is rotated along a disk rotation direction R183 by the disk rotation gas G2 blown onto a lower surface of the satellite disk 183.

[0077] Such an epitaxial growth process is performed to improve the uniformity of the carrier concentration and layer thickness in the epitaxial layer. When the epitaxial layer has a desired layer thickness, the supply of source gas G1 is stopped and the temperature is reduced. After the temperature drops to a predefined temperature, the SiC wafer 184 is removed, and a series of epitaxial growth processes ends.

[0078] Next, the susceptor of the present disclosure will be described. A ring is inserted into the above-described satellite disk 183 to prevent displacement of the SiC wafer 184 during film formation. A general name for a wafer holder heated by induction heating using the induction heating coil 188, a heater, or the like is referred to as a "susceptor."

[0079] Therefore, in the preferred embodiment described below, there is no problem if a combination of a satellite disk and a ring is referred to as a "susceptor," and hereinafter, a structure in which this combination is a main component will be described as a "susceptor" of the present disclosure for convenience.

[0080] An advantage of the susceptor, which comprises two satellite disks and the ring, is that the degree of freedom regarding usable materials and coating materials is increased, for example, by combining a SiC ring with a TaC-coated satellite disk. For example, if the epitaxial growth process is performed in an overlapping manner, it is conceivable that a deposit adhering to the inner wall of the ring could affect the semiconductor wafer, preventing the semiconductor wafer from being set. However, if a SiC ground ring is applied, the SiC is stable, so the deposit can be mechanically removed to ensure reuse, and unit costs can be kept low.

[0081] Furthermore, when a center portion of the semiconductor wafer is compared with an outer peripheral portion, which is a peripheral region of the center portion, the temperature of the outer peripheral portion is likely to decrease. However, when a ring covered with a coating material is applied to a carbon-based material, and the resistivity of the base material of the ring is made higher than that of the base material of the satellite disk, the heat generation of the ring becomes larger than that of the satellite disk at the time of induction heating, and it is also possible to suppress the temperature decrease of the outer peripheral portion of the semiconductor wafer. To maintain the degree of freedom, the present disclosure employs the susceptor having the combination of a satellite disk and a ring as a main component. <Erste bevorzugte Ausführungsform> (Basic configuration)

[0082] Fig. 1 is an explanatory view schematically illustrating a planar configuration of a susceptor 11 as a basic configuration of the first preferred embodiment of the present disclosure. Fig. Fig. 2 is an explanatory view schematically showing a configuration of an A1-A1 cross section of Fig. 1 illustrates, Fig. 3 is an explanatory view schematically showing a configuration of a B1-B1 cross section of Fig. 1 illustrates, and Fig. Fig. 4 is an explanatory view schematically showing a configuration of a C1-C1 cross section of Fig. 1 illustrates. Fig. 5 is an explanatory view showing an enlarged cross-sectional configuration of Fig. 2. It should be noted that in Fig. 1 planar structures of a ring 12 and a satellite disk 13, which are main components of the susceptor 11, are schematically illustrated in an easily recognizable manner.

[0083] A mounting target of the susceptor 11, which is a basic configuration of the wafer mounting apparatus of the first preferred embodiment, is a SiC wafer 14 having a flat orientation portion 14k. That is, the susceptor 11 of the first preferred embodiment is a wafer mounting apparatus on which the SiC wafer 14 having the flat orientation portion 14k is mounted. The SiC wafer 14 is a semiconductor wafer having the flat orientation portion 14k as a cutout portion.

[0084] As in the Fig. As illustrated in Figures 1 to 5, the susceptor 11 includes, as main components, a combination of the satellite disk 13, which is a disk having a circular shape and a prominent cross-section in a plan view, and the ring 12. The ring 12 is provided with a wall portion 12a and a wall portion 12b on an upper side, and has an opening O12 with the wall portion 12a and the wall portion 12b as outer peripheries. The opening O12 has a shape approximately corresponding to the wafer shape of the SiC wafer 14, and the opening O12 has a planar shape containing the SiC wafer 14 in a plan view and is slightly larger than the SiC wafer 14.

[0085] As in the Fig. 2 to 5, the cross-sectional structure of a portion having a terrace portion 12t of the ring 12 has a deformed T-shaped cross-sectional structure having a region protruding in a direction approaching and in a direction away from the opening O12.

[0086] The satellite disk 13, which is a disk of the basic configuration, has an upper layer part 13u, which is a projection, and has a peripheral part 13b around the upper layer part 13u. A peripheral part of the front surface 13d of the peripheral part 13p has a lower formation height than a front surface 13s of the upper layer part 13u, and as shown in Fig. 5, there exists a step Δ13 in a height direction from the surface 13d of the peripheral part to the front surface 13s.

[0087] The wall part 12b of the ring 12 functions as a projecting wall part of the cut-out side, which projects toward a side of the opening O12 corresponding to the flat orientation part 14k, which is a cut-out part of the SiC wafer 14. As shown in Fig. 1, the wall part 12b is provided parallel to the flat orientation part 14k in a plan view, and a gap space S12, in which a length in the lateral direction is a constant distance, exists between the wall part 12b and the flat orientation part 14k.

[0088] As in the Fig. 2 and Fig. As illustrated in Fig. 5, an upper surface of the wall portion 12b, which functions as a protruding wall portion of the cutout side, is provided as a part of an upper surface of the entire ring 12. That is, the formation height of the upper surface of the wall portion 12b coincides with the formation height of the upper surface of the ring 12. Further, the lower surface of the wall portion 12b has no contact relationship with the peripheral portion of the front surface 13d of the peripheral portion 13p of the satellite disk 13.

[0089] The ring 12 further comprises a terrace part 12t which projects towards the side of the opening O12 in an intermediate region in the height direction, and as shown in Fig. 1, the terrace part 12t does not overlap the wall part 12b, which is the protruding wall part of the cut-out side in a plan view.

[0090] The ring 12 is mounted on the satellite disk 13 such that the terrace portion 12t of the ring 12 is supported by the peripheral portion of the front surface 13d of the peripheral portion 13p of the satellite disk 13. That is, the satellite disk 13 supports the ring 12 by supporting the terrace portion 12t from the rear surface by the peripheral portion of the front surface 13d.

[0091] The three lifting pins 15, which are a plurality of lifting elements each having the same formation height, are individually mounted on the front surface of the terrace part 12t in the ring 12.

[0092] The three lift pins 15 hold the SiC wafer 14 by supporting the SiC wafer 14 from the rear surface. In the first preferred embodiment, the front surface of the terrace portion 12t is a lifting region for three lift pins 15.

[0093] Since the upper surface of the wall portion 12b is part of the upper surface of the ring 12, the formation height of the upper surface of the wall portion 12b coincides with the formation height of the upper surface of the entire ring 12. The upper surface of the wall portion 12b is set to be equal to or greater than the formation heights of the upper surfaces of the three lifting pins 15.

[0094] As described above, the susceptor 11, which is the basic configuration of the first preferred embodiment, has the ring 12, the satellite disk 13, and the three lifting pins 15 as main components.

[0095] In the susceptor 11 of the first preferred embodiment having such a configuration, the SiC wafer 14 can be held by mounting the SiC wafer 14 on the three lifting pins 15 such that the SiC wafer 14 fits into the opening O12 in a plan view without contacting the ring 12. This state of the semiconductor wafer mounting state refers to the SiC wafer 14.

[0096] In the semiconductor wafer state relating to the SiC wafer 14, the wall part 12b, which is the projecting wall part of the cut-out side, and the flat orientation part 14k are in a positional relationship by facing each other across the gap space S12 having a constant distance.

[0097] Since the SiC wafer 14 mounted in this manner is arranged in the opening O12 in a plan view without having a contact relationship with the ring 12, an annular gap is always formed between an outer peripheral surface of the SiC wafer 14 and the opening O12. The annular gap includes the gap space S12 described above.

[0098] Furthermore, since the opening O12 is formed approximately according to the shape of the SiC wafer 14, the annular gap is provided with a constant pitch without bias. This annular gap also functions as a gas escape flow path described later.

[0099] When the SiC wafer 14 is mounted on the three lifting pins 15, the upper disk space S13 is formed between the front surface 13s of the upper layer part 13u of the satellite disk 13 and the rear surface of the SiC wafer 14 except for a formation region of the three lifting pins 15.

[0100] Further, a groove 2, which is an annular groove having an annular shape along the outer periphery of the opening O12 in a plan view, is formed between the upper layer part 13u of the satellite disk 13 and the ring 12 on the back side of the SiC wafer 14.

[0101] The annular groove 2 has one side surface as a side surface of the upper layer part 13u and the other side surface as the wall part 12a. Then, the groove 2 formed in the formation region of the terrace part 12t is a space above the terrace part 12t with the terrace part 12t as a bottom surface.

[0102] On the other hand, as in the Fig. 2 and Fig. 5, in the region where the terrace part 12t is not formed, the groove 2 immediately below the wall part 12b is a groove 2k. Furthermore, as shown in Fig. As illustrated in Fig. 4, the groove 2 located immediately below both peripheral end regions of the wall part 12b is a groove 2m. Both the groove 2k and the groove 2m are spaces above the peripheral part of the front surface 13d with the front surface 13d of the peripheral part of the peripheral part 13p as the bottom surface.

[0103] Hereinafter, in the present specification, the annular groove 2 is described as including the groove 2k (groove 2n) and the groove 2m (groove 2m2) in a broader sense, and only the groove 2 with the terrace part 12t is specified as a floor surface in a narrower sense.

[0104] The annular gap formed between the outer peripheral surface of the SiC wafer 14 and the opening O12 and the groove 2, which is an annular groove described above, serve as a gas escape flow path for discharging the source gas G1 supplied from the front surface of the SiC wafer 14 to the upper wafer space S13.

[0105] The terrace portion 12t of the ring 12 is provided so as not to have a contact relationship with the side surface of the upper layer portion 13u of the satellite disk 13. Therefore, an auxiliary groove 2x communicating with the groove 2 in the depth direction may be provided between a front end of the terrace portion 12t and the side surface of the upper layer portion 13u. The auxiliary groove 2x makes it possible to increase the formation depth of a portion of the groove 2 and increase the volume of the gas escape flow path.

[0106] In the Fig. 1, Fig. 2, and Fig. 5, the lifting pins 15 are illustrated in a cylindrical shape, but they may have any shape, and while at least three lifting pins are required to hold the SiC wafer 14, the number of lifting pins is not limited as long as three or more lifting pins are provided.

[0107] A location where the lift pin 15 and the SiC wafer 14 are in contact with each other has a temperature different from other regions and may affect film quality. Therefore, for example, it is desirable to keep the SiC wafer 14 in an edge exclusion region. Therefore, it is desirable that the position of the lift pin 15 be provided as far outside as possible to be in contact with the wall part 12a of the ring 12.

[0108] Therefore, even if the lift pin 15 is provided so as not to come into contact with the wall part 12a, there is no problem, but there is a possibility that it becomes difficult to manufacture the ring 12 by machining and the like by means of an NC machining machine.

[0109] As in the Fig. 2 to 5, the terrace part 12t is formed to have a thickness in the height direction smaller than the step difference Δ13 between the upper layer part 13u and the peripheral part 13p in the satellite disk 13. Therefore, when the satellite disk 13 and the ring 12 are combined with each other, the annular groove 2 is always formed in the formation region of the terrace part 12t.

[0110] As described above, the formation position of the lower surface of the wall part 12b is located between the front surface of the ring 12 and the rear surface of the SiC wafer 14, but is desirably located between the front surface and the rear surface of the SiC wafer 14.

[0111] In Fig. 5, the lower surface of the wall portion 12b, which corresponds to the flat orientation portion 14k of the SiC wafer 14, is aligned in height with the upper surfaces of the three lifting pins 15 (the rear surface of the SiC wafer 14). Furthermore, the ring 12 is configured such that the terrace portion 12t is not formed at a location corresponding to the flat orientation portion 14k. Therefore, the groove 2k, which serves as a gas escape flow path for the source gas G1 to escape into the upper wafer space S13 on the rear side of the SiC wafer 14, can be formed deeper than the groove 2 with the terrace portion 12t as a bottom surface.

[0112] In a similar way, as in Fig. 4 illustrates that since the terrace part 12t is not formed in the peripheral end region of the flat orientation part 14k, the groove 2m serving as the gas escape flow path can be formed deeper than the groove 2 with the terrace part 12t as a bottom surface.

[0113] When the susceptor 11 of the first preferred embodiment having such a configuration is applied to the Fig. 25, the satellite disk 183 is replaced by the susceptor 11 comprising the ring 12, the satellite disk 13, and the three lifting pins 15, and the SiC wafer 184 is replaced by the SiC wafer 14.

[0114] When the susceptor 11 of the first preferred embodiment shown in the Fig. 1 to 5, to which in Fig. When applied to the semiconductor manufacturing apparatus 50 illustrated in FIG. 25, the source gas G1 is supplied from the outside of the rotating susceptor 132 in the planetary susceptor-type CVD apparatus. When the flat orientation portion 14k of the SiC wafer 14 approaches the injector 186 and the source gas G1 is supplied from the side of the flat orientation portion 14k, a portion of the source gas G1 flows into the upper wafer space S13 through the gap space S12 and the groove 2k between the SiC wafer 14 and the wall portion 12b.

[0115] Since the groove 2k is formed relatively deep as described above, the source gas G1 flowing from the gap space S12 between the SiC wafer 14 and the wall part 12b can be smoothly discharged to the upper wafer space S13 on the rear side of the SiC wafer 14 via the groove 2k serving as the gas escape flow path.

[0116] On the other hand, if the lower surface of the wall portion 12b is lower than the rear surface of the SiC wafer 14, the wall portion 12b protrudes toward the groove 2k, and there is a concern that the function of the groove 2k as a gas escape flow path will be hindered. Therefore, the position of the lower surface of the wall portion 12b is set to be equal to or higher than the height of the front surfaces of the three lift pins 15 (the rear surface of the SiC wafer 14).

[0117] In the susceptor 11, which is the basic configuration of the first preferred embodiment, the terrace part 12t is supported from below the front surface of the peripheral part 13p of the satellite disk 13 to hold the ring 12, and the formation of the terrace part 12t in the flat orientation part 14k and the region near it are omitted.

[0118] However, if there is no problem with strength, a plurality of partial terrace parts may be provided individually instead of the terrace part 12t being continuously provided in a region deviating from the flat orientation part 14k and the adjacent region thereof. Note that "no problem with strength" here means that the weight of the ring 12 can be supported by the terrace part 12t, and no problem occurs in the terrace part 12t.

[0119] In the susceptor 11, which is the basic configuration of the wafer mounting apparatus according to the first preferred embodiment of the present disclosure, the SiC wafer 14, which is a semiconductor wafer, is mounted on the three lifting pins 15, which are a plurality of lifting members, to achieve the semiconductor wafer mounting state related to the SiC wafer 14. Therefore, the upper wafer space S13 can be provided between the rear surface of the SiC wafer 14 and the front surface 13s of the satellite wafer 13.

[0120] Further, in the susceptor 11 of the first preferred embodiment, the groove 2, which is an annular groove, is formed between the upper layer part 13u of the satellite disk 13 and the ring 12 on the rear surface side of the SiC wafer 14 during the semiconductor wafer mounting state.

[0121] Therefore, when the source gas G1 is supplied above the front surface of the SiC wafer 14 in the semiconductor wafer mounting state, a part of the source gas G1 may be intentionally released to the upper wafer space S13 on the rear side of the SiC wafer 14 through the annular gap and the groove 2 along the outer periphery of the SiC wafer 14.

[0122] As a result, when the susceptor 11 of the first preferred embodiment performs the epitaxial growth process to form an epitaxially grown layer on the front surface of the SiC wafer 14 in the semiconductor wafer mounting state, the susceptor can prevent the occurrence of an epi-crown phenomenon in which the epi-thickness of the epitaxially grown layer locally increases. This epi-crown phenomenon mainly occurs at the outer peripheral part on the front surface of the SiC wafer 14.

[0123] As a result, the susceptor 11 of the first preferred embodiment has an effect of being able to form an epitaxial layer having an epi thickness with excellent in-plane uniformity on the front surface of the SiC wafer 14 in the semiconductor wafer mounting state. Note that an epi thickness and a carrier concentration (impurity concentration) are included as indices of in-plane uniformity.

[0124] Furthermore, since the height of the top surface of the ring 12 can be arbitrarily set, the wafer-susceptor tip distance DT, which is the difference in height between the front surface of the SiC wafer 14 mounted on the three lifting pins 15 and the top surface of the ring 12, can be set to an optimal length which does not cause an extreme decrease in the epi thickness at the outer peripheral part of the front surface of the SiC wafer 14.

[0125] In the susceptor 11 of the first preferred embodiment, since the ring 12 is mounted on the satellite disk 13 in a state where the terrace part 12t is supported on the peripheral part of the front surface 13d of the peripheral part 13p of the satellite disk 13, a combination structure of the satellite disk 13 and the ring 12 can be achieved without affecting the SiC wafer 14 as a mounting target.

[0126] Moreover, by making the thickness of the terrace part 12t thinner in the height direction than the step Δ13 between the upper layer part 13u and the peripheral part 13p of the satellite disk 13, the groove 2 can be formed with the terrace part 12t as a bottom surface in the formation region of the terrace part 12t.

[0127] The susceptor 11 of the first preferred embodiment can support the SiC wafer 14 by the three lifting pins 15, which are a plurality of lifting elements mounted on the terrace part 12t of the ring 12, with the lifting region as the surface region of the terrace part 12t.

[0128] In the susceptor 11 of the first preferred embodiment, since the terrace part 12t has no contact relationship with the side surface of the upper layer part 13u, the auxiliary groove 2X, which communicates with the groove 2 in the depth direction, can be formed between the side surface of the upper layer part 13u and the projecting distal end part of the terrace part 12t.

[0129] As a result, since the susceptor 11 of the first preferred embodiment can increase the volume of the groove 2 by the amount of the auxiliary groove 2X, it is possible to improve the function as a gas escape flow path through the groove 2 to discharge a part of the source gas G1 to the upper wafer space S13 on the back surface side of the SiC wafer 14, and to effectively suppress the epi-crown phenomenon.

[0130] Since the opening O12 of the ring 12 is shaped to contain the SiC wafer 14 and has a larger formation area than the SiC wafer 14, the SiC wafer 14 can be reliably mounted on the three lifting pins 15 without being brought into contact with the ring 12 having the wall part 12b serving as the projecting wall part of the cut-out side.

[0131] Furthermore, by causing the opening O12 to have an approximate shape corresponding to the shape of the SiC wafer 14, the susceptor 11 of the first preferred embodiment can effectively suppress the occurrence of the epi-crown.

[0132] Moreover, since the wall part 12b, which is the projecting wall part of the cut-out side, has no contact relationship with the peripheral part of the front surface 13d of the peripheral part 13p of the satellite disk 13, the function of the gas escape flow path of the groove 2k formed below the wall part 12b does not deteriorate.

[0133] In the susceptor 11 of the first preferred embodiment, since the formation height of the lower surface of the wall part 12b, which is the projecting wall part of the cut-out side, is set equal to or greater than the formation heights of the upper surfaces of the three lifting pins 15, the function of the groove 2k formed below the wall part 12b as the gas escape flow path does not deteriorate.

[0134] Furthermore, in the susceptor 11 of the first preferred embodiment, the upper surface of the wall portion 12b, which is the projecting wall portion of the cutout side, is provided to be a part of the upper surface of the ring 12. That is, the formation height of the upper surface of the wall portion 12b coincides with the formation height of the upper surface of the ring 12. Therefore, the groove 2k can be formed as the gas escape flow path below the wall portion 12b, which has a sufficient thickness.

[0135] Since the wall portion 12b, which is the protruding wall portion of the cutout side, is arranged to face the flat orientation portion 14k across the gap S12, which has a constant pitch during the semiconductor wafer mounting state, the amount of source gas G1 flowing through the groove 2k across the gap S12 can be limited so as not to exceed an upper allowable limit. This is because if the source gas G1 exceeding the upper allowable limit flows into the groove 2k through the gap S12, the source gas G1 supplied to the front surface of the SiC wafer 14 may fall below an appropriate amount.

[0136] Therefore, the susceptor 11 of the first preferred embodiment can supply an appropriate amount of the source gas G1 to the front surface of the SiC wafer 14 having the flat orientation part 14k. (First modification)

[0137] Fig. 6 is an explanatory view schematically illustrating a planar configuration of a susceptor 11B according to a first modification of the first preferred embodiment of the present disclosure. Fig. Fig. 7 is an explanatory view schematically illustrating a configuration of a cross section taken along the line A11-A11 in Fig. 6 is taken, Fig. Fig. 8 is an explanatory view schematically illustrating a configuration of a cross section taken along the line B11-B11 in Fig. 6 is taken, and Fig. Fig. 9 is an explanatory view schematically illustrating a configuration of a cross section taken along the line C11-C11 in Fig. 6. It should be noted that in Fig. 6 the planar structures of the ring 12 and the satellite disk 13B, which are main components of the susceptor 11B, are schematically illustrated in an easily recognizable manner.

[0138] Similar to the basic configuration, a mounting target of the susceptor 11B according to the first modification of the wafer mounting apparatus of the first preferred embodiment is the SiC wafer 14 having the flat orientation part 14k.

[0139] Below, similar components to those of the susceptor 11, which contains the Fig. 1 to 5, a description thereof will be appropriately omitted, and features of the susceptor 11B as the first modification will be mainly described.

[0140] As in the Fig. 6 to 9, the susceptor 11B has, as main components, a combination of a satellite disk 13B, which is a disk having a circular shape in a plan view and a projecting cross section, and a ring 12 having a deformed T-shaped cross-sectional structure with a terrace part 12t.

[0141] The satellite disk 13B, which is the disk of the first modification, has an upper layer part 13u, which is a protrusion, and a peripheral part 13p around the upper layer part 13u.

[0142] The front surface 13s of the upper layer portion 13u in the satellite disk 13B has a concave shape in which the central portion is recessed. That is, the front surface 13s has a concave portion that becomes deeper from the outer peripheral portion toward the central portion.

[0143] In the susceptor 11B according to the first modification of the first preferred embodiment having such a configuration, similar to the basic configuration, when the SiC wafer 14 is mounted on the three lift pins 15, an upper wafer space S13B is formed between the front surface 13s of the upper layer part 13u of the satellite wafer 13B and the rear surface of the SiC wafer 14 except for the formation region of the three lift pins 15.

[0144] The wafer upper space S13B has a larger volume than the wafer upper space S13 of the basic configuration because the formation depth increases from the outer periphery to the central part of the SiC wafer 14 on the rear surface side of the SiC wafer 14 compared to the wafer upper space S13.

[0145] The susceptor 11B of the first modification has similar effects to those of the susceptor 11 of the basic configuration, and also has the following unique effects.

[0146] Since the front surface 13s of the upper layer part 13u of the satellite disk 13 in the susceptor 11B of the first modification has a concave shape in which the central part is recessed, it is possible to form the upper disk space S13B larger than the upper space S13 of the basic configuration on the side of the rear surface of the SiC wafer 14.

[0147] As a result, the susceptor 11B of the first modification can discharge a part of the source gas G1 to the relatively large upper wafer space S13B via the groove 2, which is an annular groove, so that the flow of the source gas G1 to be discharged to the back surface side of the SiC wafer 14 can be made more uniform. (Second modification)

[0148] Fig. 10 is an explanatory diagram schematically illustrating a planar configuration of a susceptor 11C according to a second modification of the first preferred embodiment of the present disclosure. Fig. Fig. 11 is an explanatory view schematically illustrating a configuration of a cross section taken along a line A12-A12 of Fig. 10 is taken, Fig. Fig. 12 is an explanatory view schematically illustrating a configuration of a cross section taken along a line B12-B12 of Fig. 10 is taken, and Fig. Fig. 13 is an explanatory view schematically illustrating a configuration of a cross section taken along a line C12-C12 of Fig. 10. It should be noted that in Fig. 10 planar structures of a ring 121 and a satellite disk 13, which are main components of the susceptor 11C, are schematically illustrated in an easily recognizable manner.

[0149] Similar to the basic configuration, a mounting target of the susceptor 11C, which is the second modification of the wafer mounting apparatus of the first preferred embodiment, is the SiC wafer 14 having the flat orientation part 14k.

[0150] Below, components similar to those of the susceptor 11 of the Fig. 1 to 5 are designated by identical reference numerals, a description thereof will be appropriately omitted, and features of the susceptor 11C as a second modification will be mainly described.

[0151] As in the Fig. 10 to 13, the susceptor 11C has, as main components, a combination of a satellite disk 13, which is a disk having a circular shape and a prominent cross section in a plan view, and a ring 121 having a deformed T-shaped cross-sectional structure with a terrace part 121t.

[0152] The ring 121 in the susceptor 11C of the second modification is characterized by further comprising two terrace parts 121t, which are auxiliary terrace parts projecting toward the opening O12 side, in addition to the terrace part 12t.

[0153] As in Fig. As illustrated in Figure 10, the two terrace parts 121t, which are auxiliary terrace parts, are provided adjacent to both ends of the wall part 12b. That is, the two terrace parts 121t are provided between the terrace part 12t and the wall part 12b in a plan view.

[0154] As in Fig. As illustrated in Figure 13, the formation heights of the rear surfaces of the two terrace parts 121t coincide with the formation height of the rear surface of the terrace part 12t. Then, the terrace part 12t has a terrace thickness T1 in the height direction, and the terrace parts 121t have a terrace thickness T2 (<T1) in the height direction. As described above, the terrace parts 121t, which are auxiliary terrace parts, are set thinner in the height direction than the terrace part 12t.

[0155] As in Fig. As illustrated in FIG. 13, the ring 121 is mounted on the satellite disk 13 in a state where the terrace portion 12t and the terrace portions 121t are supported on the peripheral portion of the front surface 13d of the peripheral portion 13p of the satellite disk 13. Spaces above the terrace portions 121t are grooves 2m2, which serve as a gas escape flow path. That is, in the groove 2m, the terrace portion 121t is a bottom surface, the side surface of the upper layer portion 13u is a side surface, and the wall portion 12a is the other side surface.

[0156] The susceptor 11C of the second modification having such a configuration has similar effects to those of the susceptor 11 of the basic configuration, and further has the following unique effects.

[0157] In the susceptor 11C, which is the wafer mounting apparatus of the second modification, the ring 121 is mounted on the satellite disk 13 in a state in which the terrace part 12t and the terrace parts 121t are supported on the peripheral part of the front surface 13d of the peripheral part 13p of the satellite disk 13, so that the combination structure of the satellite disk 13 and the ring 121 with good stability can be achieved.

[0158] Furthermore, by specifying that the terrace parts 121t, which are auxiliary terrace parts, are thinner in the height direction than the terrace part 12t, the grooves 2m2, which are spaces above the terrace parts 121t, can be formed deeper than the groove 2, which is a space above the terrace part 12t. That is, the formation depths of the grooves 2m2, which are peripheral regions of both ends of the flat orientation part 14k, can be made deeper than the formation depth of the groove 2, which is the terrace part 12t as a floor surface.

[0159] As a result, the susceptor 11C of the second modification can minimize deterioration of the function of the groove 2m2 as a gas escape flow path for discharging the source gas G1 supplied to the periphery of the flat orientation part 14k as a cut-out part of the upper wafer space S13 on the back surface side of the SiC wafer 14. <Zweite bevorzugte Ausführungsform>(Basic configuration)

[0160] Fig. 14 is an explanatory view schematically illustrating a planar configuration of a susceptor 21, which is a basic configuration of a second preferred embodiment of the present disclosure. Fig. 15 is an explanatory view schematically showing a configuration of an A2-A2 cross section of Fig. 14 illustrates, Fig. 16 is an explanatory view schematically showing a configuration of a B2-B2 cross section of Fig. 14 illustrates, and Fig. Fig. 17 is an enlarged explanatory view showing a focused region R2 of Fig. 14. It should be noted that in Fig. 14 the planar structures of the ring 122 and the satellite disk 13, which are main components of the susceptor 21, are schematically illustrated in an easily recognizable manner.

[0161] A mounting target of the susceptor 21, which is the basic configuration of the wafer mounting apparatus according to the second preferred embodiment, is a SiC wafer 24 having a recess 24n having a recess length Ln (see Fig. 17). That is, the susceptor 21 of the second preferred embodiment is a wafer mounting apparatus on which the SiC wafer 24 having the recess 24n is mounted. The SiC wafer 24 is a semiconductor wafer having the recess 24n as a cutout portion.

[0162] Below, similar components to those of the susceptor 11 of the basic configuration of the Fig. 1 to 5, a description thereof will be appropriately omitted, and features of the susceptor 21 of the basic configuration of the second preferred embodiment will be mainly described.

[0163] As in the Fig. 14 to 17, the susceptor 21 includes, as main components, a combination of a satellite disk 13, which is a disk having a circular shape in a plan view and an outstanding cross section, and a ring 122, which has a deformed T-shaped cross-sectional structure with a terrace part 12t.

[0164] The ring 122 is provided with a wall portion 12a and a wall portion 12c on an upper side, and has an opening 122 with the wall portion 12a and the wall portion 12c as outer peripheries. The opening 122 has a shape approximately corresponding to the wafer shape of the SiC wafer 24, depicts the SiC wafer 24 in a plan view, and has a planar shape slightly larger than the SiC wafer 24.

[0165] The wall portion 12c of the ring 122 functions as a projecting wall portion of the cut-out side, which projects toward a side of the opening 0122 corresponding to the recess 24n, which is a cut-out portion of the SiC wafer 24. As shown in Fig. 14, the wall part 12c, which is the projecting wall part of the cut-out side, is arranged to fill a part of the recess 24n without coming into contact with the SiC wafer 24, which is a semiconductor wafer.

[0166] As in Fig. 15, the wall portion 12c serving as the projecting wall portion of the cut-out side has no contact relationship with the front surface 13d of the peripheral portion 13b of the satellite disk 13.

[0167] The ring 122 further comprises a terrace part 12t which projects towards the side of the opening 0122 in an intermediate region in the height direction, and as in Fig. 14, the terrace part 12t does not overlap the wall part 12c, which in a plan view is the projecting wall part of the cut-out side.

[0168] The ring 122 is mounted on the satellite disk 13 in such a manner that the terrace part 12t is supported on the peripheral part of the front surface 13d of the peripheral part 13p of the satellite disk 13.

[0169] In the susceptor 21, which is the basic configuration of the second preferred embodiment, a front surface of the terrace part 12t is a lifting region for the three lifting pins 15.

[0170] The three lifting pins 15, which are a plurality of lifting elements each having the same height, are mounted on the front surface of the terrace part 12t in the ring 122. The three lifting pins 15 hold the SiC wafer 24 by supporting the SiC wafer 24 from a rear surface.

[0171] As described above, the susceptor 21, which is the basic configuration of the second preferred embodiment, has the ring 121, the satellite disk 13, and the three lifting pins 15 as main components.

[0172] In the susceptor 21 of the second preferred embodiment having such a configuration, the SiC wafer 24 can be held by mounting the SiC wafer 24 on the three lifting pins 15 so that the SiC wafer 24 fits into the opening 0122 in a plan view without contacting the ring 122. This state of the semiconductor wafer mounting state refers to the SiC wafer 24.

[0173] During the semiconductor wafer mounting state relating to the SiC wafer 24, the wall part 12c, which is the projecting wall part of the cut-out side, faces the recess 24n so as to fill a part of the recess 24n.

[0174] Since the SiC wafer 24 mounted in this manner is arranged in the opening 0122 in a plan view without having a contact relationship with the ring 122, an annular gap is always formed between an outer peripheral surface of the SiC wafer 24 and the opening 0122. Furthermore, since the opening 0122 is formed to approximately match the shape of the SiC wafer 24, the annular gaps are provided with a constant pitch without any bias. This annular gap also functions as a gas escape flow path.

[0175] When the SiC wafer 24 is mounted on the three lifting pins 15, an upper disk space S13 is formed between the front surface 13s of the upper layer part 13u of the satellite disk 13 and the rear surface of the SiC wafer 24 except for the formation region of the three lifting pins 15.

[0176] Further, a groove 2, which is an annular groove having an annular shape along the outer periphery of the opening 0122 in a plan view, is formed between the upper layer part 13u of the satellite disk 13 and the ring 122 on the rear side of the SiC wafer 24.

[0177] The annular groove 2 has one side surface as a side surface of the upper layer part 13u and the other side surface as the wall part 12a. Then, the groove 2 formed in the formation region of the terrace part 12t is a space above the terrace part 12t with the terrace part 12t as a bottom surface.

[0178] On the other hand, as in Fig. 15 illustrates that in the region where the terrace portion 12t is not formed, the groove 2 immediately below the wall portion 12c forms a groove 2n. The groove 2n is a space above the front surface 13d of the peripheral portion with the front surface 13d of the peripheral portion of the peripheral portion 13p as a bottom surface.

[0179] The terrace portion 12t of the ring 122 is provided so as not to have a contact relationship with the side surface of the upper layer portion 13u of the satellite disk 13. Therefore, an auxiliary groove 2X communicating with the groove 2 in the depth direction may be provided between the front end of the terrace portion 12t and the side surface of the upper layer portion 13u.

[0180] The lower surface of the wall portion 12c is positioned between the front surface of the ring 122 and the rear surface of the SiC wafer 24 similar to the wall portion 12b of the preferred embodiment, but is desirably positioned between the front surface and the rear surface of the SiC wafer 24.

[0181] In the susceptor 21 of the second preferred embodiment, the lower surface of the wall portion 12c, which corresponds to the recess 24n of the SiC wafer 24, is aligned in height with the upper surfaces of the three lift pins 15 (the rear surface of the SiC wafer 24). Furthermore, the ring 122 is configured such that the terrace portion 12t is not formed at a location corresponding to the recess 24n and a region near it. Therefore, the groove 2n, which serves as a gas escape flow path for discharging the source gas G1 to the upper wafer space S13, can be provided deeper than the groove 2 with the terrace portion 12t as a bottom surface.

[0182] When the susceptor 21 of the second preferred embodiment is applied to the Fig. 25, the satellite disk 183 is replaced by the susceptor 21 having the ring 122, the satellite disk 13, and the three lifting pins 15, and the SiC wafer 184 is replaced by the SiC wafer 24.

[0183] In a case where the susceptor 21 of the Fig. 14 to 17 illustrated second preferred embodiment to the one shown in Fig. When applied to the semiconductor manufacturing apparatus 50 illustrated in FIG. 25, the source gas G1 is supplied from the outside of the rotating susceptor 132 in the planetary susceptor-type CVD apparatus. When the recess 24n of the SiC wafer 24 approaches the injector 186 and the source gas G1 is supplied from the recess 24n side, a portion of the source gas G1 flows into the upper wafer space S13 through the gap between the SiC wafer 24 and the wall portion 12c and the groove 2n.

[0184] As described above, since the groove 2n is formed deeper than the groove 2 with the terrace part 12t as a bottom surface, the source gas G1 supplied above the recess 24n of the SiC wafer 24 can be uniformly discharged to the upper wafer space S13 on the back surface side of the SiC wafer 24.

[0185] On the other hand, when the lower surface of the wall part 12c is lower than the rear surface of the SiC wafer 24, the wall part 12c protrudes toward the groove 2n and there is a concern that the function of the groove 2n as a gas escape flow path is impaired, and therefore the position of the lower surface of the wall part 12c is set equal to or higher than the heights of the upper surfaces of the three lifting pins 15 (rear surface of the SiC wafer 24).

[0186] The susceptor 21, which is the basic configuration of the wafer mounting apparatus according to the second preferred embodiment of the present disclosure, achieves the semiconductor wafer mounting state related to the SiC wafer 24 by mounting the SiC wafer 24, which is a semiconductor wafer, on the three lift pins 15. Therefore, the upper wafer space S13 can be provided between the rear surface of the SiC wafer 24 and the front surface 13s of the satellite wafer 13.

[0187] Further, in the susceptor 21 of the second preferred embodiment, the groove 2, which is an annular groove, is formed between the upper layer part 13u of the satellite disk 13 and the ring 122 on the rear surface side of the SiC wafer 24 during the semiconductor wafer mounting state.

[0188] Therefore, when the source gas G1 is supplied above the front surface of the SiC wafer 24 in the semiconductor wafer mounting state, a part of the source gas G1 may be intentionally released to the upper wafer space S13 on the rear side of the SiC wafer 24 through the annular gap and the groove 2 along the outer periphery of the SiC wafer 24.

[0189] As a result, when the susceptor 21 according to the second preferred embodiment performs the epitaxial growth process to form an epitaxially grown layer on the front surface of the SiC wafer 24 in the semiconductor wafer mounting state, the susceptor can suppress the occurrence of an epi-crown phenomenon in which the epi-thickness of the epitaxially grown layer locally increases. This epi-crown phenomenon mainly occurs at the outer peripheral part on the front surface of the SiC wafer 24.

[0190] As a result, the susceptor 21 according to the second preferred embodiment has an effect of being able to form an epitaxial layer with excellent in-plane uniformity on the front surface of the SiC wafer 24 in the semiconductor wafer mounting state. Note that an epitaxial thickness and a carrier concentration (impurity concentration) are included as indices of in-plane uniformity.

[0191] Furthermore, since the height of the top surface of the ring 122 can be set arbitrarily, the wafer-susceptor tip distance DT, which is the difference in height between the front surface of the SiC wafer 24 mounted on the three lifting pins 15 and the top surface of the ring 122, can be set to an optimal length that does not cause an extreme decrease in the epi thickness at the outer peripheral part of the front surface of the SiC wafer 24.

[0192] Since the opening 0122 of the ring 122 is shaped to contain the SiC wafer 24 and has a larger formation area than the SiC wafer 24, the SiC wafer 24 can be reliably mounted on the three lifting pins 15 without being brought into contact with the ring 122 including the wall part 12c serving as the projecting wall part of the cut-out side.

[0193] Furthermore, by causing the opening 0122 to have an approximate shape corresponding to the shape of the SiC wafer 24, the susceptor 21 according to the second preferred embodiment can effectively prevent an epi-crown from occurring.

[0194] Moreover, since the wall portion 12c, which is the projecting wall portion of the cut-out side, has no contact relationship with the front surface 13d of the peripheral portion 13b of the satellite disk 13, the function as the gas escape flow path of the groove 2n formed below the wall portion 12c is not deteriorated.

[0195] In the susceptor 21 of the second preferred embodiment, since the formation height of the lower surface of the wall part 12c, which is the projecting wall part of the cut-out side, is set equal to or greater than formation heights of the upper surfaces of the three lifting pins 15, the function of the groove 2n as the gas escape flow path is not deteriorated.

[0196] Furthermore, in the susceptor 21 of the second preferred embodiment, the upper surface of the wall portion 12c, which is the projecting wall portion of the cutout side, is provided as part of the upper surface of the ring 122. That is, the formation height of the upper surface of the wall portion 12c coincides with the formation height of the upper surface of the ring 122. Therefore, the groove 2n as the gas escape flow path can be formed below the wall portion 12c with a sufficient thickness.

[0197] Furthermore, the wall portion 12c, which is the protruding wall portion of the cutout side, faces the SiC wafer 24 in the semiconductor wafer mounting state and is arranged to fill a part of the recess 24n without contacting the SiC wafer 24, whereby the amount of the source gas G1 flowing through the groove 2n via the recess 24n can be limited so that it does not exceed an allowable upper limit. This is because if the source gas G1 exceeding the upper allowable limit flows into the groove 2n via the recess 24n, the source gas G1 supplied to the front surface of the SiC wafer 24 may fall below an appropriate amount.

[0198] Therefore, the susceptor 21 of the second preferred embodiment can supply a sufficient amount of the source gas G1 to the front surface of the SiC wafer 24 having the recess 24n.

[0199] As described above, the susceptor 21, which is the basic configuration of the second preferred embodiment, has similar effects to those of the susceptor 11, which is the basic configuration of the first preferred embodiment, except that the mounting target is changed from the SiC wafer 14 to the SiC wafer 24.

[0200] Also in the second preferred embodiment, modifications similar to the first and second embodiments of the Fig. 6 to 13 illustrated first preferred embodiment.

[0201] That is, as a first modification, the front surface 13s of the upper layer portion 13u of the satellite disk 13 may be changed into a concave shape with a recessed center portion. Furthermore, as in the second modification, two auxiliary terrace portions may be provided between the terrace portion 12t and the wall portion 12c in a plan view.

[0202] It should be noted that as in Fig. As illustrated in FIG. 17, since the recess length Ln, which is the length of the recess 24n in the radial direction, is shorter than the formation length of the flat orientation part 14k, it is assumed that the possibility of the epi-crown occurrence is relatively low. In this case, it is conceivable that the epi-crown phenomenon can be suppressed only by not providing the wall part 12c and not forming the recess 24n and the terrace part 12t in the vicinity thereof. If this possibility exists, a configuration in which the formation of the wall part 12c is omitted is conceivable.

[0203] However, in a case where the wall portion 12c is not formed in the ring 121 when the SiC wafer 24 is mounted, it may be difficult to align the recess 24n of the SiC wafer 24 with a terrace non-formation region in which the terrace portion 12t is not formed. Therefore, it is desirable to form the wall portion 12c on the ring 121. If the wall portion 12c is not formed, the above-described difficulty of alignment can be reduced by ensuring a large terrace non-formation region.

[0204] In the susceptor 21, which is the basic configuration of the second preferred embodiment, the terrace part 12t is supported from below on the front surface of the peripheral part 13p of the satellite disk 13, but if there is no problem in strength, a plurality of partial terrace parts may be individually formed instead of the terrace part 12t which is formed continuously as in the first preferred embodiment. <Dritte bevorzugte Ausführungsform> (Basic configuration)

[0205] Fig. 18 is an explanatory view schematically illustrating a planar configuration of a susceptor 31, which is a basic configuration of a third preferred embodiment of the present disclosure. Fig. 19 is an explanatory view schematically showing a configuration of an A3-A3 cross section of Fig. 18 illustrates, Fig. 20 is an explanatory view schematically showing a configuration of a B3-B3 cross section of Fig. 18 illustrates, and Fig. 21 is an explanatory view schematically showing a configuration of a C3-C3 cross section of Fig. 18. In Fig. 18, the planar structures of the ring 12 and the SiC wafer 34 as a mounting target, which are the main components of the susceptor 31, are schematically illustrated in an easily recognizable manner.

[0206] A mounting target of the susceptor 31, which is the basic configuration of the wafer mounting apparatus according to the third preferred embodiment, is a SiC wafer 34. In Fig. 18, the SiC wafer 34 is formally illustrated in a circular shape in a plan view, but the SiC wafer 34 illustrates the SiC wafer 14 or the SiC wafer 24. That is, the mounting target of the susceptor 31 of the third preferred embodiment is the SiC wafer 14 having the flat orientation part 14k or the SiC wafer 24 with the recess 24n.

[0207] Below are components similar to those of the susceptor 11 of the basic configuration of the Fig. 1 to 5 are designated by identical reference numerals, a description thereof will be appropriately omitted, and features of the susceptor 31 of the basic configuration of the third preferred embodiment will be mainly described.

[0208] It should be noted that the Fig. 18 to 21 illustrate the ring 12 assuming a case where the SiC wafer 34 is the SiC wafer 14. Therefore, if the SiC wafer 34 is the SiC wafer 24, the Fig. 14 to 16, ring 122 is used instead of ring 12.

[0209] Hereinafter, the susceptor 31 of the third preferred embodiment will be described for convenience of description, assuming that the SiC wafer 34 is the SiC wafer 14.

[0210] As in the Fig. 18 to 21, the susceptor 31 includes, as main components, a combination of a satellite disk 13, which is a disk having a circular shape in a plan view and a prominent cross section, and a ring 12.

[0211] The satellite disk 13, which is a disk of the basic configuration, has an upper layer part 13u which is a protrusion, and has a peripheral part 13b around the upper layer part 13u.

[0212] Three lifting pins 25, which are a plurality of lifting elements each having the same height, are mounted on the front surface 13s of the upper layer portion 13u of the satellite disk 13. The three lifting pins 25 hold the SiC wafer 34 by supporting the SiC wafer 34 from the rear surface.

[0213] In the susceptor 31 of the third preferred embodiment, the front surface 13s of the upper layer part 13u of the satellite disk 13 is a lifting region.

[0214] Furthermore, an annular support member 17 is arranged under the outer peripheral part of the rear surface of the satellite disk 13 in a plan view, and the satellite disk 13 is supported by the support member 17.

[0215] As described above, the susceptor 31, which is the basic configuration of the third preferred embodiment, has the ring 12, the satellite disk 13, the three lifting pins 25, and the support member 17 as main components.

[0216] In the susceptor 31 of the third preferred embodiment having such a configuration, the SiC wafer 34 can be held by mounting the SiC wafer 34 on the three lifting pins 25 such that the SiC wafer 34 fits into the opening O12 in a plan view without contacting the ring 12. This state of the semiconductor wafer mounting state refers to the SiC wafer 34.

[0217] When the SiC wafer 34 is mounted on the three lifting pins 25, an upper disk space S13 is formed between the front surface 13s of the upper layer part 13u of the satellite disk 13 and the rear surface of the SiC wafer 34 except for the formation region of the three lifting pins 25.

[0218] Further, a groove 2, which is an annular groove having an annular shape along the outer periphery of the opening O12 in a plan view, is formed between the upper layer part 13u of the satellite disk 13 and the ring 12 on the rear side of the SiC wafer 34.

[0219] The annular groove 2 has one side surface as a side surface of the upper layer part 13u and the other side surface as the wall part 12a. Then, the groove 2 formed in the formation region of the terrace part 12t is a space above the terrace part 12t with the terrace part 12t as a bottom surface.

[0220] On the other hand, as in Fig. 19 illustrates, in the region in which the terrace part 12t is not formed, the groove 2 immediately below the wall part 12b a groove 2k, and as in Fig. 21, the groove 2 positioned directly below both peripheral end regions of the wall part 12b is a groove 2m.

[0221] The terrace portion 12t of the ring 12 is provided so as not to have a contact relationship with the side surface of the upper layer portion 13u of the satellite disk 13. Therefore, an auxiliary groove 2X communicating with the groove 2 in the depth direction may be provided between the front end of the terrace portion 12t and the side surface of the upper layer portion 13u.

[0222] When the susceptor 31 of the third preferred embodiment is applied to the Fig. 25, the satellite disk 183 is replaced by the susceptor 31 comprising the ring 12, the satellite disk 13, the three lifting pins 25, and the support member 17, and the SiC wafer 184 is replaced by the SiC wafer 34.

[0223] The susceptor 31, which is the basic configuration of the wafer mounting apparatus according to the third preferred embodiment of the present disclosure, achieves the semiconductor wafer mounting state relating to the SiC wafer 34 by mounting the SiC wafer 34, which is a semiconductor wafer, on the three lifting pins 25, which are a plurality of lifting elements. Therefore, the upper wafer space S13 can be provided between the rear surface of the SiC wafer 34 and the front surface 13s of the satellite wafer 13.

[0224] Furthermore, in the susceptor 31 of the third preferred embodiment, in the semiconductor wafer state, the groove 2, which is an annular groove, is formed between the upper layer part 13u of the satellite disk 13 and the ring 12 on the back surface side of the SiC wafer 34.

[0225] As a result, the susceptor 31 according to the third preferred embodiment has an effect of being able to form an epitaxial layer with excellent in-plane uniformity on the front surface of the SiC wafer 34 in the semiconductor wafer mounting state, similar to the first and second preferred embodiments. Note that an epitaxial thickness and a carrier concentration (impurity concentration) are included as indices of in-plane uniformity.

[0226] As described above, the susceptor 31, which is the basic configuration of the third preferred embodiment, has similar effects to those of the susceptors 11 and 21, which are the basic configurations of the first preferred embodiment and the second preferred embodiment, and further has the following unique effects.

[0227] The susceptor 31 of the third preferred embodiment has the front surface 13s of the upper layer part 13u of the satellite disk 13 as a lifting region, and can stably support the SiC wafer 34 by the three lifting pins 25 mounted on the front surface 13s.

[0228] Moreover, in the susceptor 31 of the third preferred embodiment, the support member 17 supporting the satellite disk 13 from the rear surface can suppress the phenomenon that the satellite disk 13 on which the SiC wafer 34 is mounted warps via the three lifting pins 25.

[0229] Also in the third preferred embodiment, modifications similar to the first and second modifications of the first preferred embodiment can be configured.

[0230] That is, as a first modification, the front surface 13s of the upper layer portion 13u of the satellite disk 13 may be changed to a concave shape with a recessed center portion. However, in order to stably support the SiC wafer 34, it is desirable that the region where the three lift pins 25 are mounted on the front surface 13s of the upper layer portion 13u be flat.

[0231] Further, as a second modification, two auxiliary terrace parts may be provided between the terrace part 12t and the wall part 12b (wall part 12c) in a plan view. <Vierte bevorzugte Ausführungsform> (Basic configuration)

[0232] Fig. 22 is an explanatory view illustrating a planar configuration of a susceptor 41, which is a basic configuration of the fourth preferred embodiment of the present disclosure. Fig. 23 is an explanatory view schematically showing a configuration of an A4-A4 cross section of Fig. 22 illustrates, and Fig. 24 is an explanatory view showing a configuration of a B4-B4 cross section of Fig. 22. It should be noted that in Fig. 22 the planar structures of a ring 22 and a satellite disk 23, which are main components of the susceptor 41, are schematically illustrated in an easily recognizable manner.

[0233] A mounting target of the susceptor 41, which is the basic configuration of the wafer mounting apparatus according to the fourth preferred embodiment, is the SiC wafer 14 having the flat orientation portion 14k. That is, the susceptor 41 of the fourth preferred embodiment is a wafer mounting apparatus on which the SiC wafer 14 having the flat orientation portion 14k is mounted.

[0234] In the following, similar components to those of the susceptor 11 of the basic configuration of the first preferred embodiment shown in the Fig. 1 to 5 are designated by the same reference numerals, a description thereof will be appropriately omitted, and features of the susceptor 41 of the basic configuration of the fourth preferred embodiment will be mainly described.

[0235] As in the Fig. 22 to 24, the susceptor 41 has as main components a combination of the satellite disk 23, which is a disk having a circular shape and a prominent cross section in a plan view, and the ring 22.

[0236] The ring 22 is provided with a wall portion 22a and a wall portion 22b serving as inner peripheral surfaces. That is, in the ring 22, the wall portion 22b is selectively provided as a part of the inner peripheral surface of the ring 22, and the wall portion 22a serving as a uniform inner peripheral surface is provided in a region where the wall portion 22b is not provided.

[0237] The ring 22 has an opening O22 with the wall portion 22a and the wall portion 22b as its outer peripheries. The opening O22 has a shape approximately corresponding to the wafer shape of the SiC wafer 14, depicts the SiC wafer 14 in a plan view, and has a planar shape slightly larger than the SiC wafer 14.

[0238] The wall part 22b of the ring 22 functions as a projecting wall part of the cut-out side, which projects toward a side of the opening O22 corresponding to the flat orientation part 14k, which is a cut-out part of the SiC wafer 14. As shown in Fig. 22, the wall part 22b is provided parallel to the flat orientation part 14k in a plan view, and a gap space S22, in which a length in the lateral direction is a constant distance, exists between the wall part 22b and the flat orientation part 14k.

[0239] The satellite disk 23, which is a satellite disk of the basic configuration, includes an upper layer portion 23u, which is a protrusion, an intermediate peripheral portion 23m, which is a first peripheral portion around the upper layer portion 23u, and an outermost peripheral portion 23p, which is a second peripheral portion around the intermediate peripheral portion 23m. In the satellite disk 23, the formation height decreases in the order of a front surface 23s of the upper layer portion 23u, a front surface 23d of an intermediate peripheral portion of the intermediate peripheral portion 23m, and a front surface 23e of an outermost peripheral portion of the outermost peripheral portion 23p.

[0240] The ring 22 is mounted on the satellite disk 23 such that a bottom surface of the ring 22 is supported on the front surface 23e of the outermost peripheral part of the outermost peripheral part 23p, which is the second peripheral part of the satellite disk 23, along the entire circumference of the opening O22.

[0241] As in Fig. 23, the wall portion 22b serving as the projecting wall portion of the cut-out side has no contact relationship with the front surface 23d of the intermediate peripheral portion 23m of the satellite disk 23.

[0242] In the susceptor 41 having the mechanism configuration of the fourth preferred embodiment, the front surface 23s of the upper layer part 23u is a lifting region for the three lifting pins 25.

[0243] The three lifting pins 25, each having the same height, are mounted on the front surface 23s of the upper layer portion 23u of the satellite disk 23. The three lifting pins 25 hold the SiC wafer 14 by supporting the SiC wafer 14 from the rear surface.

[0244] In addition, an annular support member 27 is arranged under the outer peripheral part of the rear surface of the satellite disk 23 in a plan view, and the satellite disk 23 is supported by the support member 27.

[0245] As described above, the susceptor 41, which is the basic configuration of the fourth preferred embodiment, has the ring 22, the satellite disk 23, the three lifting pins 25, and the support member 27 as main components.

[0246] In the susceptor 41 of the fourth preferred embodiment having such a configuration, the SiC wafer 14 can be held by mounting the SiC wafer 14 on the three lifting pins 25 such that the SiC wafer 14 fits into the opening 022 in a plan view without contacting the ring 22. This state of the semiconductor wafer mounting state refers to the SiC wafer 14.

[0247] During the semiconductor wafer mounting state relating to the SiC wafer 14, the wall part 22b, which is the projecting wall part of the cut-out side, and the flat orientation part 14k are in such a positional relationship that they face each other across the gap space S22 at a constant distance.

[0248] When the SiC wafer 14 is mounted on the three lifting pins 25, an upper disk space S23 is formed between the front surface 23s of the upper layer part 23u of the satellite disk 23 and the rear surface of the SiC wafer 14 except for the formation region of the three lifting pins 25.

[0249] Further, a groove 2, which is an annular groove having an annular shape along the outer periphery of the opening O22 in a plan view, is formed between the upper layer part 23u of the satellite disk 23 and the ring 12 on the rear side of the SiC wafer 14.

[0250] The annular groove 2 has one side surface as a side surface of the upper layer part 23u and the other side surface as a wall part 12a. As shown in Fig. 23, the groove 2 directly below the wall part 12b is a groove 2k.

[0251] When the susceptor 41 of the fourth preferred embodiment is applied to the Fig. 25, the satellite disk 183 is replaced by the susceptor 41 comprising the ring 22, the satellite disk 23, the three lifting pins 25, and the support member 27, and the SiC wafer 184 is replaced by the SiC wafer 14.

[0252] The susceptor 41, which is the basic configuration of the semiconductor manufacturing apparatus according to the fourth preferred embodiment of the present disclosure, achieves the semiconductor wafer mounting state related to the SiC wafer 14 by mounting the SiC wafer 14 on the three lift pins 25. Therefore, the upper wafer space S23 can be provided between the rear surface of the SiC wafer 14 and the front surface 23s of the satellite wafer 23.

[0253] Moreover, in the susceptor 41 of the fourth preferred embodiment, the groove 2, which is an annular groove, is formed between the upper layer part 23u of the satellite disk 23 and the ring 22 on the back side of the SiC wafer 14 during the semiconductor wafer mounting state.

[0254] As a result, the susceptor 41 according to the fourth preferred embodiment has an effect of being able to form an epitaxial layer with excellent in-plane uniformity on the front surface of the SiC wafer 14 in the semiconductor wafer mounting state, similar to the first to third embodiments. Note that an epitaxial thickness and a carrier concentration (impurity concentration) are included as indices of in-plane uniformity.

[0255] As described above, the susceptor 41, which is the basic configuration of the fourth preferred embodiment, has similar effects to those of the susceptors 11, 21, and 31, which are the basic configuration of the first to third embodiments, and further has the following unique effects.

[0256] In the susceptor 41 of the fourth preferred embodiment, the ring 22 is mounted on the satellite disk 23 such that the bottom surface of the ring 22 is supported on the front surface 23e of the outermost peripheral part of the outermost peripheral part 23p, which is the second peripheral part of the satellite disk 23, along the entire circumference of the opening O22. Therefore, in the susceptor 41 of the fourth preferred embodiment, a combined structure of the satellite disk 23 and the ring 22 can be achieved without affecting the SiC wafer 14.

[0257] In addition, in the fourth preferred embodiment, a modification similar to the first modification of the first preferred embodiment may be configured.

[0258] That is, as a first modification, the front surface 23s of the upper layer portion 23u of the satellite disk 23 may be changed to a concave shape with a recessed center portion. However, in order to stably support the SiC wafer 14, it is desirable that the region where the three lift pins 25 are mounted on the front surface 23s of the upper layer portion 23u be flat.

[0259] Furthermore, the mounting target of the susceptor 41 of the fourth preferred embodiment is the SiC wafer 14, but it may be the SiC wafer 24 as in the susceptor 21 of the second preferred embodiment. In this case, a wall portion having a similar structure to the wall portion 12c is provided in the ring 22 instead of the wall portion 22b. <Anwendung des Halbleiterherstellungsgerätes>

[0260] As described above, the semiconductor manufacturing apparatus 50, which is used in Fig. 25 may be configured by using the wafer mounting apparatus described as a component in the first to fourth preferred embodiments.

[0261] When the susceptor 11 of the first preferred embodiment is applied to the semiconductor manufacturing apparatus 50, the satellite disk 183 is replaced by the susceptor 11 comprising the ring 12, the satellite disk 13, and three lifting pins 15, and the SiC wafer 184 is replaced by the SiC wafer 14.

[0262] Fig. Fig. 26 is an explanatory view schematically illustrating a planar configuration of the semiconductor manufacturing apparatus 51. The semiconductor manufacturing apparatus 51 is a novel semiconductor manufacturing apparatus in which the Fig. 25 is applied to the susceptor 11 of the first preferred embodiment.

[0263] As illustrated in the drawing, the planetary susceptor 182 houses eight susceptors 11, each of which has a ring 12, a satellite disk 13, and three lifting pins 15 as its main components. That is, in the upper layer portion of the planetary susceptor 182, eight susceptors 11 are arranged as eight satellite disks 183 around the central portion 187.

[0264] Each of the eight susceptors 11 is mounted to the SiC wafer 14 and rotates along the disk rotation direction R183. Furthermore, the planetary susceptor 182 itself also rotates along the susceptor rotation direction R182.

[0265] It should be noted that when the susceptor 21 of the second preferred embodiment is applied to the semiconductor manufacturing apparatus 50, the satellite disk 183 is replaced by the susceptor 21 including the ring 122, the satellite disk 13, and the three lifting pins 15, and the SiC wafer 184 is replaced by the SiC wafer 24.

[0266] When the susceptor 31 of the third preferred embodiment is applied to the semiconductor manufacturing apparatus 50, the satellite disk 183 is replaced by the susceptor 31 comprising the ring 12, the satellite disk 13, the three lifting pins 25, and the support member 17, and the SiC wafer 184 is replaced by the SiC wafer 34.

[0267] When the susceptor 41 of the fourth preferred embodiment is applied to the semiconductor manufacturing apparatus 50, the satellite disk 183 is replaced by the susceptor 41 comprising the ring 22, the satellite disk 23, the three lifting pins 25, and the support member 27, and the SiC wafer 184 is replaced by the SiC wafer 14.

[0268] The semiconductor manufacturing apparatus 51, which includes any of the wafer mounters of the first to fourth embodiments as a component, is a novel semiconductor manufacturing apparatus. Note that both the SiC wafer 14 and the SiC wafer 24 are semiconductor wafers that include silicon carbide as a material.

[0269] The semiconductor manufacturing apparatus 51 includes an induction heating coil 188 as a heating mechanism for heating a semiconductor wafer in the semiconductor wafer mounting state.

[0270] The novel semiconductor manufacturing apparatus 51 can form an epitaxial layer containing silicon carbide on the front surface of the SiC wafer 14 with good in-plane uniformity by supplying the source gas G1 for epitaxial growth above the front surface of the SiC wafer 14 in a state where the SiC wafer 14 is heated in the semiconductor wafer mounting state by the induction heating coil 188 as a heating mechanism. Note that an epitaxial thickness and a carrier concentration (impurity concentration) are included as indices of in-plane uniformity. <Verfahren zur Herstellung einer Halbleitervorrichtung und Halbleitervorrichtung, welche durch das Verfahren zur Herstellung hergestellt wird>

[0271] Fig. 27 is a flowchart illustrating a processing procedure of a method for manufacturing a semiconductor device using the novel semiconductor manufacturing apparatus 51. Next, a method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus 51 to which the susceptor 11 of the first preferred embodiment is applied will be described.

[0272] In step ST1, the SiC wafer 14 as a silicon carbide semiconductor substrate is mounted on the three lifting pins 15 through the susceptor 11.

[0273] That is, in step ST1, the SiC wafer 14 is mounted on the three lifting pins 15 such that the SiC wafer 14 fits into the opening O12 in a plan view without being in contact with the ring 12, thereby achieving the semiconductor wafer mounting state with respect to the SiC wafer 14.

[0274] In step ST2, the epitaxial growth process is performed on the front surface of the SiC wafer 14 in the semiconductor wafer mounting state. That is, the source gas G1 for epitaxial growth is supplied to the front surface of the SiC wafer 14, and the SiC wafer 14 is heated by the induction heating coil 188 as a heating mechanism.

[0275] As a result, an epitaxial layer is formed on the front surface of the SiC wafer 14 in the semiconductor wafer mounting state.

[0276] Subsequently, in step ST3, a semiconductor layer for element formation is formed in the epitaxial layer, and then in step ST4, a front surface structure for element formation is formed on the semiconductor layer for element formation.

[0277] As a result, a semiconductor element can be manufactured by the semiconductor layer and the front surface structure of the element formation.

[0278] Fig. 28 is a cross-sectional view illustrating a cross-sectional structure of a semiconductor device 100 as an example of a semiconductor device manufactured by the method for manufacturing the semiconductor device shown in Fig. 27 is illustrated.

[0279] As illustrated in the drawing, an N - Epitaxial layer 62 is provided as an epitaxial layer on the front surface of the SiC substrate 61, which corresponds to the SiC wafer 14. A P base layer 63 is selectively formed in an upper layer part of the N - epitaxial layer 62 is provided, an N source layer 64 is selectively provided in a front surface of the P base layer 63, and a P + Contact layer 65 is provided between N source layers 64 and 64 in the front surface of P base layer 63.

[0280] The gate electrode 67 is formed via a gate oxide layer 66 between the pair of N source layers 64 and 64, which are formed in the different P base layers 63 and are adjacent to each other. The gate electrode 67 is formed from the N source layer 64, which is provided in the front surface of a P base layer 63, to above the one P base layer 63, above the N - Epitaxial layer 62 is formed above the other P base layer 63 and above the N source layer 64 provided in the front surface of the other P base layer 63. An interlayer insulating layer 68 is provided so as to cover the gate oxide layer 66 and the gate electrode 67.

[0281] Such a combination of the gate oxide layer 66, the gate electrode 67, and the interlayer insulating layer 68 is formed at a plurality of locations. Therefore, the semiconductor device 100 has a plurality of gate oxide layers 66, a plurality of gate electrodes 67, and a plurality of interlayer insulating layers 68. Then, the source electrode 69 is formed on the entire surface of the N - Epitaxial layer 62 comprising the plurality of interlayer insulating layers 68 is formed, and a drain electrode 70 is provided on a back surface of the SiC substrate 61.

[0282] The following describes a process for producing the Fig. 28 by the method for manufacturing the semiconductor device 100 shown in Fig. 27 illustrated semiconductor device.

[0283] The processing in step ST1 is a processing for finally mounting the SiC wafer 14, which is to be the SiC substrate 61, on the susceptor 11.

[0284] The processing in step ST2 is a processing for supplying the source gas G1 for epitaxial growth on the front surface of the SiC wafer 14 mounted on the semiconductor manufacturing apparatus 51 and for heating the SiC wafer 14 by the induction heating coil 188.

[0285] As a result, the epitaxial growth process is carried out on the front surface of the SiC substrate 61, and the N - Epitaxial layer 62, which is an epitaxial layer, is formed on the front surface of the SiC substrate 61. Here, the concentration of the n-type impurity present in the SiC substrate 61 and the N -Epitaxial layer 62 is appropriately selected in accordance with the withstand voltage of the semiconductor device to be manufactured.

[0286] Next, a semiconductor layer is deposited to form the element in the N - Epitaxial layer 62 is formed. The P base layer 63, the N source layer 64, and the P + Contact layer 65 can be formed by implanting ions of the p-type impurities and the n-type impurities into the N - Epitaxial layer 62 and by diffusing the implanted ions in the N - Epitaxial layer 62 may be formed by heat treatment or the like.

[0287] The P base layer 63, the N source layer 64, and the P + Contact layer 65 serve as semiconductor layers for element formation. That is, the process of step ST3 is a process for forming the P base layer 63, the N source layer 64, and the P + Contact layer 65.

[0288] Next, the gate oxide layer 66, the gate electrode 67, and the interlayer insulating layer 68 are selectively deposited on the front surface of the N - Epitaxial layer 62 is formed, which comprises the P base layer 63, the N source layer 64, and the P + Contains contact layer 65.

[0289] First, the SiC wafer 14 is heated in an atmosphere containing oxygen to form the gate oxide layer 66 formed by SiO2 on the upper surface of the semiconductor layer for element formation. Then, polysilicon doped with n-type or p-type impurities is deposited on the gate oxide layer 66 using a chemical vapor deposition (CVD) method or the like to form the gate electrode 67.

[0290] Subsequently, the interlayer insulating layer 68 is formed on the gate electrode 67. A material of the interlayer insulating layer 68 is, for example, SiO2 or tetraethyl orthosilicate (TEOS). Through such steps, the plurality of gate oxide layers 66, the plurality of gate electrodes 67, and the plurality of source electrodes 69 are selectively formed.

[0291] Subsequently, mask processing is performed on the upper surface of the interlayer insulating layer 68, and a part of the interlayer insulating layer 68 is etched through the opening of the resist to form a contact hole 59 penetrating the interlayer insulating layer 68. The contact hole 59 is formed on the front surfaces of the N source layer 64 and the P + Contact layer 65 is formed.

[0292] Next, a barrier metal (not illustrated) is formed in the contact hole 59 of the interlayer insulating layer 68 and on the interlayer insulating layer 68. The barrier metal is formed by depositing Ti, TiN, or the like by a physical vapor deposition (PVD) method or a CVD method.

[0293] Next, the source electrode 69 is formed on the barrier metal. The source electrode 69 can be formed, for example, by depositing an aluminum-silicon alloy (Al-Si-based alloy) on a barrier metal using a PVD process such as sputtering or chemical vapor deposition.

[0294] Next, the drain electrode 70 is formed on the back surface of the SiC substrate 61. The drain electrode 70 is formed, for example, by depositing an aluminum-silicon alloy, titanium, or the like using a PVD method such as sputtering or evaporation. Furthermore, the drain electrode 70 can be formed by laminating a variety of metals such as an aluminum-silicon alloy, titanium, nickel, or gold.

[0295] The structure of the front surface for element formation is the gate oxide layer 66, the gate electrode 67, the interlayer insulating layer 68, the source electrode 69, and the drain electrode 70. That is, the processing of step ST4 is the processing for forming the gate oxide layer 66, the gate electrode 67, the interlayer insulating layer 68, the source electrode 69, and the drain electrode 70.

[0296] It should be noted that a plurality of semiconductor devices 100, which are silicon carbide semiconductor devices, are produced in a matrix on a SiC wafer 14, a SiC wafer 14 is cut into individual semiconductor devices 100 by laser dicing or blade dicing to be formed into chips, and the Fig. 28 illustrated semiconductor device 100 is completed.

[0297] As a result, it is possible to manufacture the semiconductor device 100 having a metal oxide semiconductor field effect transistor (NMOSFET) as a semiconductor element configured by a semiconductor layer for element formation and a front surface structure.

[0298] As described above, in the semiconductor device 100 manufactured by the method for manufacturing a semiconductor device using the semiconductor manufacturing apparatus 51 including the planetary susceptor 182, the N - Epitaxial layer 62 has a high intra-plane uniformity such as an epi thickness, and it is possible to form a structure having poor electrical properties in one step after forming the N - epitaxial layer 62, so that productivity is improved.

[0299] Moreover, since it is possible to suppress the occurrence of poor electrical characteristics when a semiconductor layer for element formation is formed by ion implantation or the like, it is possible to obtain a semiconductor device 100 having a highly reliable NMOSFET.

[0300] The process for producing the Fig. 27 comprises at least the following steps (a) to (c).

[0301] Step (a) is a step of mounting the SiC wafer 14 (SiC substrate 61) on the three lifting pins 15 so that the SiC wafer 14 fits into the opening O12 in a plan view without being in contact with the ring 12, and achieving the semiconductor wafer mounting state related to the SiC wafer 14.

[0302] Step (b) is a step of supplying the source gas G1 for epitaxial growth of the front surface of the SiC wafer 14 in the semiconductor wafer mounting state.

[0303] Step (c) is a step of heating the SiC wafer 14 in the semiconductor wafer mounting state by the induction heating coil 188 as a heating mechanism.

[0304] Step (a) corresponds to step ST1, which is Fig. 27, and steps (b) and (c) correspond to step ST2 shown in Fig. 27 is illustrated.

[0305] Therefore, after performing steps (a) to (c) described above, the Fig. 28 illustrated N - Epitaxial layer 62 is formed on the front surface of the SiC substrate 61, which corresponds to the semiconductor wafer.

[0306] In the method for manufacturing a semiconductor device using the novel semiconductor manufacturing apparatus 51 by performing steps (a) to (c), the N -Epitaxial layer 62, which is to be an epitaxial layer containing silicon carbide, is formed with good in-plane uniformity on the front surface of the SiC wafer 14 in the semiconductor wafer mounting state. Note that an epitaxial thickness and a carrier concentration (impurity concentration) are included as indices of in-plane uniformity.

[0307] That is, the uniformity within the level of N - Epitaxial layer 62 formed on the SiC wafer 14 in the semiconductor wafer mounting state can be improved by the semiconductor device manufacturing method using the novel semiconductor manufacturing apparatus 51.

[0308] In the semiconductor device 100, which is a semiconductor device manufactured by the method for manufacturing a semiconductor device using the novel semiconductor manufacturing apparatus 51, it is possible because the semiconductor layer for element formation in the N - Epitaxial layer 62 is formed which has high intra-plane uniformity to increase the reliability of the NMOSFET, which is the semiconductor element having the semiconductor layer for element formation.

[0309] It should be noted that in the present disclosure, each preferred embodiment can be freely combined, and each preferred embodiment can be appropriately modified or omitted within the scope of the disclosure.

[0310] Below, different aspects of the present disclosure are described collectively as appendices. (Appendix 1)

[0311] A wafer mounting apparatus that mounts a semiconductor wafer having a cut-out portion, the wafer mounting apparatus comprising: a disc having a prominent upper layer portion; a ring disposed on the disc and having an opening in a center; a plurality of lifting elements arranged on a lifting region provided on the disk or the ring and supporting the semiconductor wafer from a rear surface, wherein the ring has a projecting wall part of the cut-out side which projects towards the opening, and in a semiconductor wafer mounting state, the semiconductor wafer is mounted on the plurality of lifting elements such that the semiconductor wafer fits into the opening in a plan view without being in contact with the ring, the projecting wall portion of the cutout side faces the cutout portion of the semiconductor wafer, an upper disk space is formed between a front surface of the upper layer portion of the disk and a rear surface of the semiconductor wafer except for a formation region of the plurality of lifting members, an annular groove is formed along an outer periphery of the opening in a plan view between the upper layer portion of the disk and the ring on a rear surface side of the wafer, and a side surface of the upper layer portion of the disk is a side surface of the annular groove. (Appendix 2)

[0312] Wafer mounting device according to Appendix 1, wherein the disc has a peripheral part around the upper layer part, a front surface of the peripheral part has a formation height which is lower than a front surface of the upper layer part, and a step exists from the front surface of the peripheral part to the front surface of the upper layer part, the ring has a terrace part which projects towards one side of the opening, and the terrace part does not overlap the projecting wall part of the cut-out side in a plan view, the ring is mounted on the disc in such a way that the terrace part is supported on a front surface of the peripheral part of the disc, and a thickness of the terrace part in one height direction is thinner than the step on the disc. (Appendix 3)

[0313] Wafer mounting device according to Appendix 2, wherein the plurality of lifting elements are mounted on a front surface of the terrace part of the ring, and the lifting region has a front region of the terrace part. (Appendix 4)

[0314] Wafer mounting device according to Appendix 2 or 3, wherein the terrace part has no contact relationship with a side surface of the upper layer part. (Appendix 5)

[0315] Wafer mounting device according to one of the appendices 2 to 4, wherein the opening is shaped to contain the semiconductor wafer and has a larger formation area than the semiconductor wafer, and the projecting wall portion of the cut-out side has no contact relationship with a front surface of the peripheral portion of the disc. (Appendix 6)

[0316] Wafer mounting device according to Appendix 5, where a formation height of a lower surface of the projecting wall part of the cut-out side is set equal to or greater than a formation height of upper surfaces of the plurality of lifting elements. (Appendix 7)

[0317] Wafer mounting device according to Appendix 5 or 6, wherein an upper surface of the projecting wall portion of the cut-out side is part of an upper surface of the ring. (Appendix 8)

[0318] Wafer mounting apparatus according to one of the appendices 1 to 7, wherein the part of the upper layer of the disc has a recessed shape in which a central part is recessed. (Appendix 9)

[0319] Wafer mounting device according to Appendix 3, where which further comprises an auxiliary terrace part projecting toward the side of the opening in addition to the terrace part, and the auxiliary terrace part is provided between the terrace part and the projecting wall part of the cut-out side in a plan view, and has a thickness in a height direction which is smaller than the thickness of the terrace part, and the ring is mounted on the disc in a state in which the terrace part and the auxiliary terrace part are supported on a front surface of the peripheral part of the disc. (Appendix 10)

[0320] Wafer mounting device according to Appendix 2, wherein the plurality of lifting elements are mounted on the upper layer part of the disc, and the lifting region has a front side region of the upper layer part. (Appendix 11)

[0321] Wafer mounting device according to Appendix 10 further comprising: a support element that supports the disc from a rear surface. (Appendix 12)

[0322] Wafer mounting device according to Appendix 1, wherein the disc has a first peripheral part around the upper layer part and a second peripheral part around the first peripheral part, and a formation height decreases in an order of a front surface of the upper layer part, a front surface of the first peripheral part, and a front surface of the second peripheral part, and the ring is mounted on the disc such that a bottom surface of the ring is supported on the front surface of the second peripheral part of the disc along an entire circumference of the opening. (Appendix 13)

[0323] Wafer mounting apparatus according to one of the appendices 1 to 12, wherein the cut-out part has a flat orientation part, and the projecting wall portion of the cut-out side is arranged to face the flat orientation portion across a gap having a constant distance in the semiconductor wafer mounting state. (Appendix 14)

[0324] Wafer mounting apparatus according to one of the appendices 1 to 12, wherein the cut-out part has a recess, and the projecting wall portion of the cut-out side is arranged to fill a part of a recess without coming into contact with the semiconductor wafer in the semiconductor wafer mounting state. (Appendix 15)

[0325] A semiconductor manufacturing apparatus comprising the wafer mounting apparatus according to any one of Appendices 1 to 14, wherein the semiconductor wafer has silicon carbide as a material, and the wafer mounting device also has: a heating mechanism that heats the semiconductor wafer in the semiconductor wafer mounting state. (Appendix 16)

[0326] A method of manufacturing a semiconductor device using the wafer mounting apparatus according to any one of Appendices 1 to 14, wherein the semiconductor wafer has silicon carbide as a material, the wafer mounting apparatus further comprises a heating mechanism which heats the semiconductor wafer, the method comprises the steps of: (a) achieving the semiconductor wafer mounting state by mounting the semiconductor wafer on the plurality of lifting members so that the semiconductor wafer fits into the opening in a plan view without being in contact with the ring; (b) supplying a source gas for epitaxial growth to a front surface of the semiconductor wafer in the semiconductor wafer mounting state; and (c) heating the semiconductor wafer in the semiconductor wafer mounting state by the heating mechanism, andafter steps (a) to (c) are performed, an epitaxial layer is formed on a front surface of the semiconductor wafer in the semiconductor wafer mounting state. (Appendix 17)

[0327] Semiconductor device comprising: the epitaxial layer formed by the method for manufacturing a semiconductor device according to Appendix 16; and a semiconductor layer for element formation formed in the epitaxial layer.

[0328] While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations may be devised. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2016-119472 [0002, 0003, 0030, 0034, 0042, 0043, 0049] JP 2014-27006 [0003, 0030, 0033, 0034] JP 7-226349 [0003, 0029, 0031, 0033, 0034]

Claims

[1] A wafer mounting apparatus (11, 11B, 11C, 21, 31, 41) which mounts a semiconductor wafer (14, 24, 34) having a cut-out portion (14k, 24n), the wafer mounting apparatus comprising: • a disc (13, 13B, 23) having a projecting upper layer part (13u); • a ring (12, 22, 121, 122) arranged on the disc and having an opening (O12, O22, O122) in a center; • a plurality of lifting elements (15, 25) mounted on a lifting region (12t, 13s) provided on the disk or the ring and supporting the semiconductor wafer from the rear surface, wherein • the ring has a projecting wall part (12b, 12c) of the cut-out side, which projects towards the opening, and • in a semiconductor wafer mounting state, the semiconductor wafer is mounted on the plurality of lifting elements such that the semiconductor wafer fits into the opening in a plan view without being in contact with the ring, • the projecting wall part of the cut-out side faces the cut-out part of the semiconductor wafer, an upper disk space (S13) is formed between a front surface (13s) of the upper layer part of the disk and a rear surface of the semiconductor wafer except for a formation region of the plurality of lifting elements, an annular groove (2, 2k, 2m, 2n) having an annular shape is formed along an outer periphery of the opening in a plan view between the upper layer part of the disk and the ring on a rear surface of the wafer side, and a side surface of the upper layer part of the disk is a side surface of the annular groove. [2] Wafer mounting apparatus according to claim 1, wherein • the disc has a peripheral part (13p) around the upper layer part, a front surface (13d) of the peripheral part has a formation height which is lower than a front surface (13s) of the upper layer part, and a step (Δ13) exists from the surface of the peripheral part to the front surface of the upper layer part, • the ring has a terrace part (12t) which projects towards one side of the opening, and wherein the terrace part does not overlap the projecting wall part of the cut-out side in a plan view, • the ring is mounted on the disc in such a way that the terrace part is supported on a front surface of the peripheral part of the disc, and • a thickness of the terrace part in one height direction is thinner than the step on the disc. [3] Wafer mounting apparatus according to claim 2, wherein • the plurality of lifting elements (15) are mounted on a front surface of the terrace part of the ring, and • the lifting region comprises a front region of the terrace part. [4] The wafer mounting apparatus according to claim 2 or 3, wherein the terrace portion has no contact relationship with a side surface of the upper layer portion. [5] Wafer mounting apparatus according to one of claims 2 to 4, wherein • the opening is shaped to contain the semiconductor wafer and has a larger formation area than the semiconductor wafer, and • the projecting wall portion of the cut-out side has no contact relationship with a front surface of the peripheral portion of the disc. [6] The wafer mounting apparatus according to claim 5, wherein a formation height of a lower surface of the projecting wall part of the cut-out side is set equal to or greater than a formation height of upper surfaces of the plurality of lifting members. [7] The wafer mounting apparatus according to claim 5 or 6, wherein an upper surface of the projecting wall portion of the cut-out side is a part of an upper surface of the ring. [8] A wafer mounting apparatus according to any one of claims 1 to 7, wherein the part of the upper layer of the wafer has a recessed shape in which a central part is recessed. [9] Wafer mounting apparatus according to claim 3, wherein • the ring further comprises an auxiliary terrace part (121t) which projects towards the side of the opening in addition to the terrace part, and the auxiliary terrace part is provided between the terrace part and the projecting wall part of the cut-out side in a plan view, and has a thickness in a height direction which is smaller than the thickness of the terrace part, and • the ring is mounted on the disc in a state where the terrace part and the auxiliary terrace part are supported on a front surface of the peripheral part of the disc. [10] Wafer mounting apparatus according to claim 2, wherein • the plurality of lifting elements (25) are mounted on the upper layer part of the disc, and • the lifting region comprises a front side region of the upper layer part. [11] A wafer mounting apparatus according to claim 10, further comprising a support member (17) supporting the wafer from a rear surface. [12] Wafer mounting apparatus according to claim 1, wherein • the disc (23) has a first peripheral part (23m) around the upper layer part and a second peripheral part (23p) around the first peripheral part, and a formation height decreases in an order of a front surface (23s) of the upper layer part, a front surface (23d) of the first peripheral part, and a front surface (23e) of the second peripheral part, and • the ring is mounted on the disc such that a bottom surface of the ring (22) is supported on the front surface of the second peripheral part of the disc along an entire circumference of the opening. [13] Wafer mounting apparatus according to one of claims 1 to 12, wherein • the cut-out part has a flat orientation part (14k), and • the projecting wall portion (12b) of the cut-out side is arranged to face the flat orientation portion via a gap (S12) at a constant distance in the semiconductor wafer mounting state. [14] Wafer mounting apparatus according to one of claims 1 to 12, wherein • the cut-out part has a recess (24n), and • the projecting wall portion (12c) of the cut-out side is arranged to fill a part of the recess without being in contact with the semiconductor wafer in the semiconductor wafer mounting state. [15] A semiconductor manufacturing apparatus comprising the wafer mounting apparatus according to any one of claims 1 to 14, wherein • the semiconductor wafer has silicon carbide as a material, and • the wafer mounting apparatus further comprises a heating mechanism (188) which heats the semiconductor wafer in the semiconductor wafer mounting state. [16] A method of manufacturing a semiconductor device using the wafer mounting apparatus according to any one of claims 1 to 14, wherein • the semiconductor wafer has silicon carbide as a material, • the wafer mounting apparatus further comprises a heating mechanism (188) which heats the semiconductor wafer, • the procedure comprises the steps of: ◯ (a) achieving the semiconductor wafer mounting state by mounting the semiconductor wafer on the plurality of lifting members so that the semiconductor wafer fits into the opening in a plan view without being in contact with the ring; ◯ (b) supplying a source gas (G1) for epitaxial growth to a front surface of the semiconductor wafer in the semiconductor wafer mounting state; and ◯ (c) heating the semiconductor wafer in the semiconductor wafer mounting state by the heating mechanism, and • after steps (a) to (c) have been performed, an epitaxial layer (62) is formed on a front surface of the semiconductor wafer in the semiconductor wafer mounting state. [17] Semiconductor device comprising: • the epitaxial layer formed by the method for manufacturing a semiconductor device according to claim 16; and • a semiconductor layer (63 to 65) which is designed for element formation in the epitaxial layer.

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