semiconductor device

Abstract

A semiconductor device comprises a semiconductor substrate (10), an alloy layer (20) containing a constituent element of the semiconductor substrate (10) as a main component, and an upper metal layer (30) formed on the alloy layer (20). A plurality of minute regions (31) containing an inert gas are discretely arranged at an interface between the alloy layer (20) and the upper metal layer 30. Not less than 90% of a plurality of the minute regions (31) have an arc shape, the opening of which is the widest portion.

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present disclosure relates to a semiconductor device. Description of the background technology

[0002] For example, Japanese Patent Application Laid-Open No. 2001-223178 discloses a technique for suppressing the generation of voids caused by the incorporation of Ar gas into a silicide film by using a metal that forms a silicide with multiple metal compositions in an initial silicide reaction, such as Co, as a barrier metal when forming a silicide layer on a semiconductor substrate. According to this technique, it is possible to prevent deterioration of the contact resistance between the silicide film and the electrode formed thereon.

[0003] Incidentally, for example, in Peter Hatton, et al., “Inert gas bubble formation in magnetron sputtered thin-film CdTe solar cells,” Proc. of the Royal Soc. A, Vol. 476, Issue 2239, a phenomenon was reported in which voids are formed by the aggregation of inert gas elements contained in a metal film upon heat treatment.

[0004] Furthermore, WO 2021 / 246241 A discloses a technique for forming a keyhole-shaped (a shape having an inlet narrower than an internal space) recess in a cross-sectional view on a surface of an electrode in order to improve the connection strength between the electrode and an upper electrode thereon by an anchor effect.

[0005] In the technique disclosed in Japanese Patent Application Laid-Open No. 2001-223178, a uniformly dense silicide film is formed at the contact portion between the semiconductor substrate and the electrode, so that the bonding strength between the semiconductor substrate and the electrode can be increased. However, if the bonding strength between the semiconductor substrate and the electrode is too high, a breakdown caused by external stress is likely to extend to the active cell of the semiconductor substrate, causing a serious accident such as a short-circuit breakdown. SUMMARY

[0006] An object of the present disclosure is to reduce the adhesion strength between an alloy layer and a metal film while preventing the deterioration of the contact resistance between the alloy layer formed on the semiconductor layer and the metal layer thereon.

[0007] A semiconductor device according to the present disclosure includes a semiconductor substrate, an alloy layer containing a constituent element of the semiconductor substrate as a main component, and an upper metal layer formed on the alloy layer. A plurality of minute regions containing an inert gas are individually or discretely disposed at an interface between the alloy layer and the upper metal layer. 90% or more of a plurality of the minute regions have an arc shape in which the opening is the widest portion.

[0008] According to the present disclosure, it is possible to reduce the adhesion strength between the alloy layer and the metal film while preventing the deterioration of the contact resistance between the alloy layer formed on the semiconductor layer and the metal layer (upper metal layer) thereon.

[0009] These and other objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view illustrating the basic structure of the contact portion of a semiconductor device according to a first preferred embodiment; Fig. 2A to 2C are views for explaining a method of forming the contact portion of the semiconductor device according to the first preferred embodiment; Fig. 3A to 3C are views for explaining the method of forming the contact portion of the semiconductor device according to the first preferred embodiment; Fig. 4 is a view illustrating a specific example of the contact portion of the semiconductor device according to the first preferred embodiment; Fig. 5 is a view illustrating an atomic number contrast image of the contact portion of the semiconductor device according to the first preferred embodiment; Fig. 6 is a view showing an atomic number contrast image of a conventional contact portion without a minute portion; Fig. Figure 7 is an enlarged view of a portion near a tiny area in the atomic number contrast image of Fig. 5; Fig. 8 is a view illustrating an element distribution pattern of Si in the contact portion of the semiconductor device according to the first preferred embodiment; Fig. 9 is a view illustrating an element distribution pattern of Ar in the contact portion of the semiconductor device according to the first preferred embodiment; Fig. 10 is a diagram illustrating an EDX spectrum of the contact portion of the semiconductor device according to the first preferred embodiment; and Fig. 11 is a view illustrating the structure of the contact portion of the semiconductor device according to the first preferred embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS<Erste bevorzugte Ausführungsform>

[0010] Fig. 1 is a view illustrating the basic structure of the contact portion of a semiconductor device according to a first preferred embodiment. As shown in Fig. 1, the “contact portion” in the present preferred embodiment refers to a portion in which a semiconductor substrate 10 and an upper metal layer 30 are connected via an alloy layer 20.

[0011] The semiconductor substrate 10 contains, for example, a compound containing Si, SiC, or Ga as a constituent element. The alloy layer 20 is formed on the upper surface of the semiconductor substrate 10 and is made of an alloy containing a constituent element of the semiconductor substrate 10 as a main component. When the semiconductor substrate 10 is a wide band-gap semiconductor such as SiC or GaN, a semiconductor device that operates excellently at high voltage, high current, and high temperature is obtained, compared to the case of silicon.

[0012] An n-type layer or a p-type layer containing a donor or an acceptor as a dopant may be selectively formed on the surface portion of the semiconductor substrate 10. The alloy layer 20 may be in contact with an n-type layer or a p-type layer, or both, formed on the semiconductor substrate 10. Furthermore, the alloy layer 20 may be formed by alloying the surface portions of the n-type layer or the p-type layer, or both, formed on the semiconductor substrate 10.

[0013] The alloy layer 20 is formed by, for example, depositing a metal film (corresponding to a "metal film 21" to be described later) on the semiconductor substrate 10 by a sputtering method or a chemical vapor deposition (CVD) method, and alloying the metal film and the semiconductor substrate 10 by subjecting them to a chemical reaction through heat treatment. Therefore, the alloy layer 20 contains, as main components, the constituent elements of the semiconductor substrate 10 and the constituent elements of the metal film before alloying. As the metal film before alloying, for example, a film containing Ti, Ni, Co, or the like as a main component is assumed. When the semiconductor substrate 10 is Si or SiC, the alloy layer 20 is preferably a silicide compound.

[0014] The upper metal layer 30 is formed on the alloy layer 20. The upper metal layer 30 is made of, for example, Ti, Ni, W, Cu, Al, or an alloy (for example, TiN) containing one or more of Ti, Ni, W, Cu, Al, or the like, and is formed, for example, by a sputtering method or a CVD method. Above the upper metal layer 30, another upper metal layer may be further formed, which may be composed of a component different from that of the upper metal layer 30. Furthermore, a multilayer structure obtained by stacking a metal composed of a different component, a metal of the same type as the upper metal layer 30, and the like may be formed on the upper metal layer 30.

[0015] A plurality of tiny regions 31 containing an inert gas are discretely formed at an interface between the alloy layer 20 and the upper metal layer 30. The tiny region 31 has a shape that erodes the alloy layer 20, that is, a shape that penetrates into the alloy layer 20 from the interface between the alloy layer 20 and the upper metal layer 30. Furthermore, the tiny region 31 has an arc shape whose opening is the widest portion in a cross-sectional view. Since the tiny regions 31 having such a shape are discretely formed between the alloy layer 20 and the upper metal layer 30, it is possible to reduce the adhesive strength between the alloy layer 20 and the upper metal layer 30 while preventing the deterioration of the contact resistance between the alloy layer 20 and the upper metal layer 30.The inert gas can be Ar, N2 or another noble gas element.

[0016] As in Fig. 1, here, the depth of the tiny region 31 is defined as t1, the width of the tiny region 31 is defined as w1, and the thickness of the alloy layer 20 is defined as t2. The thickness t2 of the alloy layer 20 is preferably, for example, 10 nm or more and 50 nm or less. The depth t1 of the tiny region 31 is preferably, for example, 5 nm or more and less than t2. The width w1 of the tiny region 31 is preferably, for example, 5 nm or more and less than 100 nm. It is desirable that 90% or more of a plurality of the tiny regions 31 have an arc shape whose opening in the cross-sectional view is the widest portion.

[0017] In the semiconductor device, the upper metal layer 30 is used as an electrode electrically connected to the semiconductor substrate 10 via the alloy layer 20. For example, if the semiconductor device is a power control semiconductor device (a so-called power device), the adhesion strength of the electrode may be an important design parameter in a stress test such as a power cycle (P / C) test or a thermal cycle (H / C) test.

[0018] If the adhesion strength of the upper metal layer 30 as an electrode is too low, the upper metal layer 30 will be peeled off during a stress test, and the lifetime of the semiconductor device will be reduced. However, if the adhesion strength of the upper metal layer 30 is too high, the disturbance from the stress test will not extend to the interface between the upper metal layer 30 and the alloy layer 20, but will extend to the interior of the semiconductor substrate 10. The disturbance of the interior of the semiconductor substrate 10 may short-circuit the semiconductor device. For example, if a semiconductor device capable of withstanding a voltage of several hundred volts to several thousand volts is short-circuited, serious disruption of the entire system on which the semiconductor device is mounted will be caused.

[0019] By applying the contact portion structure according to the first preferred embodiment to an electrode of the semiconductor device, the adhesion strength of the electrode can be controlled. By adjusting the adhesion strength of the electrode within a desired range, it is possible to control the interference at the interface between the alloy layer 20 and the upper metal layer 30 without affecting the durability in the stress test, and it is possible to suppress the short circuit of the semiconductor device.

[0020] Conventionally, there was a problem that the contact resistance of the upper metal layer 30 was deteriorated by the formation of voids in the alloy layer 20. Since it was difficult to control the composition, shape, and size of a void, it was assumed that the void should disappear completely.

[0021] The inventors of the technology according to the present disclosure have succeeded in discretely arranging the tiny regions 31 other than the cavities at the interface between the alloy layer 20 and the upper metal layer 30 through a detailed analysis of the semiconductor manufacturing process.

[0022] As more preferable parameters for controlling the adhesion strength without deteriorating the contact resistance of the upper metal layer 30, the thickness t2 of the alloy layer 20 is preferably 30 nm or more, the width w1 of the minute region 31 is preferably less than 100 nm, and the depth t1 of the minute region 31 is preferably less than t2. In addition, the occupancy of the minute region 31 at the interface between the alloy layer 20 and the upper metal layer 30 is desirably less than 50%. The atomic concentration of the inert gas in the minute region 31 is desirably 0.5 wt% or more and less than 20.0 wt%, and the atomic density of the constituent element of the alloy layer 20 in the minute region 31 is desirably 80.0 wt% or more.

[0023] The atomic concentration of the minute region 31 may be a value quantitatively evaluated by a general elemental analysis method such as energy dispersive X-ray spectroscopy (EDX). In the elemental analysis method, in a case where an evaluation range is on the order of nm or so, it is assumed that a value involving a range other than the evaluation target is output, but there is no problem as long as the element can be detected in the minute region 31, as shown in Fig. 8 and Fig. 10, which will be described later.

[0024] If the width w1 of the tiny region 31 is too wide, the substantial thickness of the alloy layer 20 decreases and the contact resistance deteriorates. Furthermore, if the depth t1 of the tiny region 31 is too large, the upper metal layer 30 and the semiconductor substrate 10 come into contact with each other, and favorable ohmic contact cannot be achieved, which also causes the deterioration of the contact resistance. Furthermore, if the occupancy of the tiny region 31 is too high, similar to the case where the width w1 of the tiny region 31 is too wide, the substantial thickness of the alloy layer 20 decreases and the contact resistance deteriorates.

[0025] Furthermore, if the tiny region 31 is not formed at the interface between the alloy layer 20 and the upper metal layer 30, the adhesion strength of the upper metal layer 30 increases, and the disturbance easily extends to the semiconductor substrate 10 during the stress test. Even in a case where the tiny region 31 has a keyhole shape such as the concave portion in WO 2021 / 246241 A described above, the adhesion strength of the upper metal layer 30 becomes excessively high due to the anchor effect, so that the disturbance easily extends to the semiconductor substrate 10 during the stress test. Therefore, it is important to control the width, depth, density, shape, and position of the tiny region 31 within preferable ranges.

[0026] Fig. 2A to 2C illustrate a method of manufacturing the semiconductor device according to the first preferred embodiment, particularly a method of forming the contact portion.

[0027] First, as in Fig. 2A, the metal film 21, which is to be a material for the alloy layer 20, is formed on the semiconductor substrate 10 by a sputtering method or a CVD method. Thereafter, a heat treatment is performed to chemically react the semiconductor substrate 10 with the metal film 21 to form the alloy layer 20. At this time, the minute region 31 on the surface of the alloy layer 20 can be formed as shown in Fig. 2B using the following method.

[0028] Here, a case will be described where the metal film 21 is formed by a sputtering method. The sputtering method is generally a film formation method in which a chamber is filled with an inert gas at a specific ratio, the inert gas is converted into plasma, the plasma is caused to collide with a target metal, bonds between atoms of the target material are physically severed to ionize (activate) metal atoms, and the metal atoms are deposited on the semiconductor substrate 10. The metal film 21 deposited on the semiconductor substrate 10 contains not only desired metal ions but also traces of inert gas ions converted by plasma. In the conventional manufacturing process, the content of inert gas ions is low, and the inert gas ions either volatilize and disappear during the heat treatment for alloying the metal film 21 or are incorporated into the alloy layer 20 without aggregating.

[0029] In the present preferred embodiment, by increasing the concentration of the inert gas contained in the master alloy metal film 21, the minute region 31 on the surface of the alloy layer 20 is formed as shown in Fig. 2B. In the minute region 31, the concentration in mass percent of the atoms constituting the alloy layer 20 is low, and the inert gas content is high. That is, the minute region 31 is a rough region where the atomic density is reduced due to the aggregation of the inert gas during the heat treatment.

[0030] Then, as in Fig. 2C, a metal film is deposited on the alloy layer 20 containing the minute region 31 to deposit the upper metal layer 30. After the upper metal layer 30 is formed, a heat treatment may be performed.

[0031] The alloying of the metal film 21 and the heat treatment for forming the minute regions 31 can be carried out after the deposition of the upper metal layer 30. That is, first, as shown in Fig. 3A, the metal film 21, which is to be a material for the alloy layer 20, is formed on the semiconductor substrate 10 and is then, as shown in Fig. 3B, the upper metal layer 30 is formed on the metal film 21. Thereafter, a heat treatment may be performed to chemically react the semiconductor substrate 10 with the metal film 21, as shown in Fig. 3C to form the alloy layer 20 and to form the minute region 31 on the surface of the metal layer 20.

[0032] The minute region 31 is common to or equivalent to voids in that the inert gas element contained in the metal film 21 before alloying is aggregated by the heat treatment; but the minute region 31 is controlled in width, depth, density, position, atomic density, and the like and is not a complete void.

[0033] The metal film 21 before alloying can be deposited using a CVD method. However, unlike the sputtering method, no inert gas is incorporated into the metal film 21. Therefore, after the metal film 21 is deposited, an inert gas must be introduced into the metal film 21 by, for example, an ion implantation method or the like. Even in a case where an inert gas is introduced after the metal film 21 is deposited, the inert gas is aggregated when a heat treatment is performed, and the minute region 31 is formed.

[0034] Next, a method for controlling the parameters of the minute region 31 will be described. Since the minute region 31 is formed by aggregation of inert gas atoms, it is necessary to control the amount of inert gas contained in the metal film 21 before alloying in order to control the parameters of the minute region 31.

[0035] To control the amount of inert gas incorporated into the metal film 21 when forming the metal film 21 by the sputtering method, it is only necessary to perform, for example, adjustment of the pressure in the chamber, adjustment of the plasma density, adjustment of the pull-in voltage for active species to the semiconductor substrate 10, and the like. The pressure in the chamber can be adjusted by the volume flow of the inert gas, and the volume flow of the inert gas can be adjusted in a range of, for example, 1 sccm to 100 sccm. The plasma density can be adjusted by a DC bias, which is one of the adjustment parameters, and the DC bias can be adjusted in a range of, for example, 1 kW to 50 kW. The pull-in voltage for the active species can be adjusted with an AC bias, and the AC bias can be adjusted in a range of, for example, 1 W to 1 kW.The temperature at the time of film formation can be set, for example, in a range from room temperature to 500°C.

[0036] In addition, the thicker the metal film 21 before alloying, the more the amount of inert gas atoms aggregated at the interface increases, and thus, it is preferable that the film thickness of the metal film 21 be thick. However, if the metal film 21 is too thick, the alloy layer 20 to be formed also becomes thick, the alloy layer 20 is formed deeper than the n-type layer or the p-type layer in the surface portion of the semiconductor substrate 10, and the contact resistance increases. Therefore, the thickness t2 of the alloy layer 20 is preferably, for example, 30 nm or more and 50 nm or less.

[0037] In addition, the heat treatment conditions after the deposition of the metal film 21 before alloying can also be an important parameter. For example, if the heat treatment is carried out at a high temperature for a long time, the aggregation of inert gas will be accelerated, and the tiny region 31 will become enormous. Accordingly, the width and depth of the tiny region 31 will increase, and the desired shape cannot be obtained. As heat treatment conditions, it is desirable that the temperature be in the range of 700°C to 900°C and the time be in the range of 10 seconds to 120 seconds.

[0038] The parameters of the tiny area 31 can be controlled by setting the above parameters.

[0039] The metal film 21 before alloying can be deposited using a CVD method. However, unlike the case where the sputtering method is used, the inert gas is not included during the deposition of the metal film 21. Therefore, it is necessary to include an inert gas after the deposition of the metal film 21, for example, by means of an ion implantation method or the like. Even in a case where an inert gas is introduced after the metal film 21 is deposited, the inert gas is aggregated when a heat treatment is performed, and the minute region 31 is formed.

[0040] Fig. 4 is a specific example of the contact portion of the semiconductor device according to the first preferred embodiment and schematically illustrates a cross section of the emitter (or source) contact of the power conversion semiconductor device. An interlayer insulating film 50 is formed on the semiconductor substrate 10. A contact hole reaching the semiconductor substrate 10 is formed in the interlayer insulating film 50, and the alloy layer 20 is formed on a surface portion of the semiconductor substrate 10 exposed at the bottom of the contact hole. The upper metal layer 30 is formed on the alloy layer 20, and the minute region 31 is formed at the interface between the alloy layer 20 and the upper metal layer 30. Furthermore, an upper metal layer 40 as a contact plug for embedding a contact hole is formed on the upper metal layer 30.

[0041] The semiconductor substrate 10 is, for example, a compound containing Si, SiC, or Ga. Furthermore, the alloy layer 20 is a silicide compound, an alloy mainly containing an element of the semiconductor substrate 10, or the like. The interlayer insulating film 50 is, for example, a TEOS film, a BPSG film, a thermal oxide film, or a multilayer film thereof, and is arranged to ensure insulation with a gate electrode (not shown).

[0042] The bottom width of the contact hole formed in the interlayer insulating film 50 (which is Fig. The contact bottom width (shown in Figure 4) is, for example, on the order of submicrometers from 0.2 µm to 1.0 µm (inclusive), and the aspect ratio (i.e., the thickness of the interlayer insulating film / the bottom width of the contact hole) with respect to the thickness of the interlayer insulating film 50 is, for example, 1.5 or more. Although not shown, the n-type or p-type emitter layer is selectively formed on the surface portion of the semiconductor substrate 10 at the bottom of the contact hole, and the alloy layer 20 is in contact with the emitter layer.

[0043] Fig. Fig. 5 is an atomic number contrast image obtained by a cross-sectional TEM of the contact portion of the semiconductor device according to the first preferred embodiment having the structure of Fig. 4 is obtained. In the atomic number contrast image, a sub-area with a lower atom density is shown darker in black. Therefore, the tiny area 31 is shown as a local dark black area. Fig. 5 it can be confirmed that the tiny regions 31 are discretely formed. Fig. Figure 6 shows an atomic number contrast image of a conventional contact portion without a tiny region as a comparison example.

[0044] At Fig. Figure 7 is an enlarged view and dimensions of a sub-area near the tiny area 31 in the atomic number contrast image of Fig. 5. By adjusting the inert gas element contained in the metal film 21 before alloying and the heat treatment conditions, the tiny region 31 with a width of 35 nm and a depth of 10 nm was successfully formed with a reduced atomic concentration. The dimensions of the upper metal layer 30, shown in Fig. 7, are just an example.

[0045] Fig. 8 and Fig. 9 show element map images of the contact portion of the semiconductor device according to the first preferred embodiment having the structure of Fig. 4. Fig. 8 is an element distribution diagram of Si, and Fig. 9 is an element distribution diagram of Ar. The constituent elements of the upper metal layer 30 do not include Si, and the constituent elements of the alloy layer 20 and the semiconductor substrate 10 include Si. Therefore, in the Fig. In the element distribution image of Si shown in Figure 8, the upper metal layer 30 is drawn with a dark contrast. In the boundary portion between the alloy layer 20 and the upper metal layer 30 (the area surrounded by the white dashed line), the tiny region 31 where the atomic concentration of Si has been reduced is locally drawn with a dark contrast. Although a bright contrast appears in a portion of the upper metal layer 40 that does not contain Si, it is confirmed from the EDX spectrum that this is due to background noise.

[0046] On the other hand, in the Fig. 9, the tiny region 31 in which the atomic concentration of Ar is increased is drawn with a locally bright contrast at the boundary portion (the area surrounded by the white dashed line) between the alloy layer 20 and the upper metal layer 30. Also in Fig. 9 confirms that the bright contrast of the portion of the upper metal layer 40 is background noise.

[0047] Fig. Figure 10 is a graph showing EDX spectra, which are original data of the element distribution images of the Fig. 8 and Fig. 9. Each dashed line is the spectrum of the portion of the alloy layer 20 that does not include the tiny region 31, and each solid line is the spectrum of the portion of the alloy layer 20 that includes the tiny region 31. In the portion containing the tiny region 31, the peak intensity of Si, which is a constituent element of the alloy layer 20, is reduced by about 3.1% with respect to the portion not including the tiny region 31. In addition, Ar, which is an element of the inert gas, is significantly detected in a portion containing the tiny region 31.

[0048] Out of Fig. 8, Fig. 9 and Fig. 10, it can be confirmed that the minute region 31 is a region where the concentration of the constituent element of the alloy layer 20 is low and the atomic concentration of the inert gas is high. <Zweite bevorzugte Ausführungsform>

[0049] In the second preferred embodiment, the minute region 31 described in the first preferred embodiment is applied to an electrode formed on an interlayer insulating film 50.

[0050] Fig. 11 is a diagram illustrating the basic structure of the contact portion of a semiconductor device according to the second preferred embodiment. As shown in Fig. As shown in Figure 11, the "contact portion" in the present preferred embodiment refers to a portion where a lower metal layer 41 formed on the interlayer insulating film 50 and the upper metal layer 42 are bonded thereto. The interlayer insulating film 50 is, for example, an oxide film.

[0051] In the contact portion of the semiconductor device according to the second preferred embodiment, a minute region 31 is formed at the interface between the lower metal layer 41 and the upper metal layer 42. The minute region 31 has a shape that erodes the lower metal layer 41, that is, a shape that penetrates into the lower metal layer 41 side from the interface between the lower metal layer 41 and the upper metal layer 42. It is desirable that 90% or more of a plurality of the minute regions 31 have an arc shape whose opening is the widest portion in the cross-sectional view.

[0052] In addition, the minute region 31 has an arc shape, the opening of which is the widest portion in the cross-sectional view. The width, depth, density, shape, position, and the like of the minute region 31 are the same as those in the first preferred embodiment. However, the lower metal layer 41 in which the minute region 31 is formed is formed on the interlayer insulating film 50 and is not alloyed with a semiconductor substrate 10. Therefore, the lower metal layer 41 does not contain the constituent element of the semiconductor substrate 10, and the constituent element of the semiconductor substrate 10 is not contained in the minute region 31. The atomic concentration of the constituent element of the lower metal layer 41 in the minute region 31 is desirably 80.0 wt% or more.

[0053] The minute region 31 can be formed by applying a heat treatment to the inert gas-sealing lower metal layer 41. The method for forming the contact portion is similar to the method for forming the contact portion described in the first preferred embodiment ( Fig. 2A to 2C and 3A to 3C), and therefore, its description is omitted here. The width, depth, density, shape, position, and the like of the minute region 31 are controlled by adjusting an inert gas element contained in the lower metal layer 41 and heat treatment conditions.

[0054] In the second preferred embodiment, it is possible to reduce the bonding strength between the lower metal layer 41 and the upper metal layer 42 formed on the interlayer insulating film 50 while preventing deterioration of the contact resistance between the lower metal layer and the upper metal layer. Even if the electrode on the interlayer insulating film 50 is peeled off during a stress test, it is possible to suppress the propagation of the fault into the semiconductor substrate 10 without affecting the durability in the stress test by adjusting the bonding strength to an appropriate bonding strength.

[0055] Note that the respective preferred embodiments can be freely combined, and can be modified and omitted as needed. < Appendix >

[0056] Various aspects of the present disclosure are described below together as appendices. (Appendix 1)

[0057] A semiconductor device comprising: a semiconductor substrate; an alloy layer containing a constituent element of the semiconductor substrate as a main component; and an upper metal layer formed on the alloy layer, wherein a plurality of minute regions containing an inert gas are discretely formed at an interface between the alloy layer and the upper metal layer, and not less than 90% of a large number of the tiny regions have an arc shape, the opening of which is the widest part. (Appendix 2)

[0058] The semiconductor device according to Annex 1, wherein an atomic concentration of a constituent element of the alloy layer in the minute region is not less than 80 wt%. (Appendix 3)

[0059] The semiconductor device as defined in Annex 1 or 2, where the alloy layer has a thickness of not less than 30 nm, the tiny region has a width of less than 100 nm and the tiny area has a depth of less than the thickness of the alloy layer. (Appendix 4)

[0060] The semiconductor device according to any one of Appendices 1 to 3, wherein an occupancy of the minute region at an interface between the alloy layer and the upper metal layer is less than 50%. (Appendix 5)

[0061] The semiconductor device according to any one of Annexes 1 to 4, further comprising: an interlayer insulating film formed on the semiconductor substrate; and a contact hole formed in the interlayer insulating film and reaching the semiconductor substrate, wherein the alloy layer and the upper metal layer are formed on the semiconductor substrate at a bottom of the contact hole, and a bottom width of the contact hole is in a range of not less than 0.2 µm to not more than 1.0 µm. (Appendix 6)

[0062] The semiconductor device according to Annex 5, wherein an aspect ratio between the bottom width of the contact hole and a thickness of the interlayer insulating film is not less than 1.5. (Appendix 7)

[0063] The semiconductor device according to any one of Appendices 1 to 6, wherein an atomic concentration of the inert gas in the minute region is not less than 0.5 wt% and less than 20.0 wt%. (Appendix 8)

[0064] The semiconductor device according to any one of Annexes 1 to 7, wherein the inert gas is Ar or N2. (Appendix 9)

[0065] The semiconductor device according to any one of Appendices 1 to 8, wherein the semiconductor substrate is made of a compound containing Si, SiC or Ga. (Appendix 10)

[0066] The semiconductor device according to any one of Annexes 1 to 8, wherein the semiconductor substrate consists of Si or SiC and the alloy layer is a silicide compound containing Ti or Ni. (Appendix 11)

[0067] The semiconductor device according to any one of Appendices 1 to 10, wherein the upper metal layer is made of a metal containing Ti, W or Al as a main component or a multilayer structure of a plurality of metals containing Ti, W or Al as a main component. (Appendix 12)

[0068] A semiconductor device comprising: a lower metal layer; and an upper metal layer formed on the lower metal layer, wherein a plurality of minute regions containing an inert gas are discretely formed at an interface between the lower metal layer and the upper metal layer, and not less than 90% of a large number of the tiny regions have an arc shape, the opening of which is the widest part. (Appendix 13)

[0069] The semiconductor device according to Annex 12, wherein an atomic concentration of a constituent element of the lower metal layer in the minute region is not less than 80 wt%.

[0070] While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive.

[0071] It is therefore understood that numerous modifications and variants can be designed. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2001-223178 [0002, 0005] WO 2021 / 246241 A [0004, 0025] Cited non-patent literature

[0000] Peter Hatton, et al., “Inert gas bubble formation in magnetron sputtered thin-film CdTe solar cells,” Proc. of the Royal Soc. A, Vol. 476, Issue 2239

[0003]

Claims

[1] A semiconductor device comprising: a semiconductor substrate (10); an alloy layer (20) containing a constituent element of the semiconductor substrate (10) as a main component; and an upper metal layer (30) formed on the alloy layer (20), wherein a plurality of minute regions (31) containing an inert gas are discretely formed at an interface between the alloy layer (20) and the upper metal layer (30), and not less than 90% of a plurality of the minute regions (31) have an arc shape, the opening of which is the widest portion. [2] A semiconductor device according to claim 1, wherein an atomic concentration of a constituent element of the alloy layer (20) in the minute region (31) is not less than 80 wt%. [3] A semiconductor device according to claim 1 or 2, wherein the alloy layer (20) has a thickness of not less than 30 nm, the tiny region (31) has a width of less than 100 nm and the tiny region (31) has a depth of less than the thickness of the alloy layer (20). [4] A semiconductor device according to any one of claims 1 to 3, wherein an occupancy of the minute region (31) at an interface between the alloy layer (20) and the upper metal layer (30) is less than 50%. [5] A semiconductor device according to any one of claims 1 to 4, further comprising: an interlayer insulating film (50) formed on the semiconductor substrate (10); and a contact hole formed in the interlayer insulating film (50) and reaching the semiconductor substrate (10), wherein the alloy layer (20) and the upper metal layer (30) are formed on the semiconductor substrate (10) at a bottom of the contact hole and a bottom width of the contact hole is in a range of not less than 0.2 µm to not more than 1.0 µm. [6] The semiconductor device according to claim 5, wherein an aspect ratio between the bottom width of the contact hole and a thickness of the interlayer insulating film (50) is not less than 1.

5. [7] A semiconductor device according to any one of claims 1 to 6, wherein an atomic concentration of the inert gas in the minute region (31) is not less than 0.5 wt% and less than 20.0 wt%. [8] A semiconductor device according to any one of claims 1 to 7, wherein the inert gas is Ar or N2. [9] A semiconductor device according to any one of claims 1 to 8, wherein the semiconductor substrate (10) is made of a compound containing Si, SiC or Ga. [10] A semiconductor device according to any one of claims 1 to 8, wherein the semiconductor substrate (10) consists of Si or SiC and the alloy layer (20) is a silicide compound containing Ti or Ni. [11] A semiconductor device according to any one of claims 1 to 10, wherein the upper metal layer (30) is made of a metal containing Ti, W or Al as a main component or a multilayer structure of a plurality of metals containing Ti, W or Al as a main component. [12] A semiconductor device comprising: a lower metal layer (41); and an upper metal layer (42) formed on the lower metal layer (41), wherein a plurality of minute regions (31) containing an inert gas are discretely formed at an interface between the lower metal layer (41) and the upper metal layer (42) and not less than 90% of a plurality of the minute regions (31) have an arc shape, the opening of which is the widest portion. [13] A semiconductor device according to claim 12, wherein an atomic concentration of a constituent element of the lower metal layer (41) in the minute region (31) is not less than 80 wt%.

Images