TRANSISTOR DEVICE AND METHOD FOR ITS MANUFACTURING

Abstract

A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device comprises a semiconductor body (100); a drift region (11) of a first doping type in the semiconductor body (100); a gate pad (41) formed over a first surface (101) of the semiconductor body (100); a shielding structure (2) arranged between the gate pad (41) and the drift region (11), comprising several shielding electrodes (21), each arranged in a respective shielding trench (22) and dielectrically insulated from the gate pad (41) and the semiconductor body (100); a source pad (42) formed over the first surface (101) of the semiconductor body (100) and connected to the shielding electrodes (21); and several transistor cells (3), each comprising a gate electrode (31) connected to the gate pad (41).

Description

TECHNICAL AREA

[0001] This disclosure relates generally to a transistor device, in particular a transistor device with an insulated gate (IG). BACKGROUND

[0002] A transistor device with an insulated gate, such as a MOSFET (metal-oxide-semiconductor field-effect transistor), comprises a load path between a source node, a drain node, and a gate node. The transistor device switches on or off depending on a voltage applied between the gate node and the source node (gate-source voltage). The gate node and the source node are capacitively coupled. Consequently, the gate node is also capacitively coupled to the drain node. Such coupling of the gate node to the drain node can cause the transistor device to switch on unintentionally when a voltage transient occurs in the load path voltage applied between the drain and the source node.Such unintentional switching can occur particularly when the gate-drain capacitance, which is the capacitance between the gate node and the drain node, is large relative to the gate-source capacitance, which is the capacitance between the gate node and the source node.

[0003] For example, US patent publication US 10930774 B2 discloses a MOSFET with a shielded gate trench in the active region and unconnected gate trenches in the edge termination region. Furthermore, channel stop gates are present, which prevent the formation of a leakage path between drain and source.

[0004] It is an object of the present invention to provide a transistor device with an insulated gate that is robust against unintentional switching. This object is achieved by the transistor device of claim 1. A further object of the present invention is to provide a method for manufacturing such a transistor device. This object is achieved by the method of claim 18. SUMMARY

[0005] Claim 1 relates to a transistor device. The transistor device comprises a semiconductor body; a drift region of a first doping type in the semiconductor body; a gate pad formed over a first surface of the semiconductor body; a shielding structure arranged between the gate pad and the drift region, comprising several shielding electrodes, each arranged in a respective shielding trench and dielectrically insulated from the gate pad and the semiconductor body; a source pad formed over the first surface of the semiconductor body and connected to the shielding electrodes; and several transistor cells, each comprising a gate electrode connected to the gate pad.

[0006] Claim 18 relates to a method for manufacturing a transistor device. The transistor device comprises a semiconductor body; a drift region of a first doping type in the semiconductor body; a gate pad formed over a first surface of the semiconductor body; a shielding structure arranged between the gate pad and the drift region, comprising several shielding electrodes, each arranged in a respective shielding trench and dielectrically insulated from the gate pad and the semiconductor body; a source pad formed over the first surface of the semiconductor body and connected to the shielding electrodes; and several transistor cells, each comprising a gate electrode connected to the gate pad. The method includes forming the shielding electrodes and the gate electrodes by the same process sequence.

[0007] Examples are explained below with reference to the drawings. The drawings serve to illustrate certain principles, so only aspects necessary for understanding these principles are depicted. The drawings are not to scale. In the drawings, the same reference symbols denote the same features. Fig. Figure 1 schematically illustrates a vertical cross-sectional view of a transistor device according to an example, wherein the transistor device comprises a gate pad, a shielding arrangement between the gate pad and a drift region, a source pad and several transistor cells, each having a gate electrode connected to the gate pad; Fig. Figure 2 illustrates a modification of the transistor device according to Fig. 1; Fig. 3A-3B illustrate transistor cells according to an example; Fig. 4A-4B illustrate transistor cells according to another example; Fig. Figure 5 shows a top view of the gate pad and a source pad of the transistor device according to an example; Fig. Figure 6 illustrates an example of connecting shielding electrodes of the shielding arrangement to a source runner and connecting gate electrodes of the transistor cells to the gate pad; Fig. Figure 7 illustrates an example of connecting the gate electrodes of transistor cells to a gate runner; and Fig. Figures 8A-8D illustrate an example of a method for manufacturing the gate electrodes of the transistor cells and the shielding electrodes of the shielding structure by the same process steps.

[0008] The following detailed description refers to the accompanying drawings. The drawings form part of the description and show examples of how the invention can be used and implemented. It is understood that the features of the various embodiments described herein can be combined unless expressly stated otherwise.

[0009] One of the examples described below relates to a transistor device. The transistor device comprises: a semiconductor body; a drift region of a first doping type in the semiconductor body; a gate pad formed over a first surface of the semiconductor body; a shielding structure arranged between the gate pad and the drift region, comprising several shielding electrodes, each arranged in a respective shielding trench and dielectrically isolated from the gate pad and the semiconductor body; a source pad formed over the first surface of the semiconductor body and connected to the shielding electrodes; and several transistor cells, each comprising a gate electrode connected to the gate pad.

[0010] According to one example, the gate electrode of each transistor cell is formed in a gate groove that extends from a first surface of the semiconductor into the semiconductor body.

[0011] According to one example, the transistor device further comprises a source runner formed over the first surface of the semiconductor body and connected to the source pad, wherein the shielding electrodes are connected to the source pad through the source runner.

[0012] According to one example, the shielding electrodes are elongated electrodes spaced apart in a first lateral direction of the semiconductor body and extending longitudinally in a second lateral direction. The shielding electrodes comprise a first longitudinal end and a second longitudinal end opposite the first. An end section adjacent to the first longitudinal end of each shielding electrode in the second lateral direction may protrude from below the gate pad and be connected to the source runner.

[0013] According to one example, the gate electrodes are elongated electrodes spaced apart in a third lateral direction and extending longitudinally in a fourth lateral direction. The third lateral direction can be the same as the first lateral direction, and the fourth lateral direction can be the same as the second lateral direction. The gate electrodes can comprise a first group of gate electrodes spaced apart from the shielding electrodes in the second lateral direction, and a second group of gate electrodes spaced apart from the shielding electrodes in the first lateral direction. The transistor device can further comprise a gate runner connected to the gate pad, wherein the gate electrodes of the first group can be directly connected to the gate pad, and wherein the gate electrodes of the second group can be connected to the gate pad via a gate runner.

[0014] According to one example, the transistor device further comprises a shielding region of the second doping type adjacent to the drift region, wherein the shielding electrodes are embedded in the shielding region.

[0015] According to one example, each transistor cell further comprises: a gate dielectric that dielectrically insulates the gate electrode from the semiconductor body; a source region of the first doping type, which is connected to the source pad; and a body region of the second doping type, which is adjacent to the gate dielectric and the source region and is located between the source region and the drift region. Each transistor cell may further comprise a cell shielding region of the second doping type, which is connected to the source pad and extends into the drift region in a vertical direction along the semiconductor body. The drift region may include a current propagation region that is adjacent to the gate trenches in the vertical direction and has a higher doping concentration than the rest of the drift region. The cell shielding region may be spaced from the gate trench in the first lateral direction.The cell shielding region can be connected to the source pad by a contact electrode located in a trench extending from the first surface into the semiconductor body. Furthermore, the cell shielding region can be adjacent to a side wall of the gate trench.

[0016] According to one example, the transistor device further comprises a drain region of the first doping type, which is coupled to the drift region.

[0017] Another example relates to a method for fabricating a transistor device. The transistor device comprises: a semiconductor body; a drift region of a first doping type in the semiconductor body; a gate pad formed over a first surface of the semiconductor body; a shielding structure arranged between the gate pad and the drift region, comprising multiple shielding electrodes, each arranged in a respective shielding trench and dielectrically insulated from the gate pad and the semiconductor body; a source pad formed over the first surface of the semiconductor body and connected to the shielding electrodes; and multiple transistor cells, each comprising a gate electrode connected to the gate pad. The method includes forming the shielding electrodes and the gate electrodes by the same process sequence.

[0018] Fig. Figure 1 schematically illustrates a vertical cross-sectional view of a section of a gate-controlled transistor device according to an example. The transistor device is, for example, a MOSFET.

[0019] The transistor device comprises a semiconductor body 100, a drift region 11 of a first doping type in the semiconductor body 100, a gate pad 41 formed over a first surface 101 of the semiconductor body 100, a source pad 42 spaced from the gate pad 41 and formed over the first surface 101 of the semiconductor body 100, and a shielding structure 2 arranged between the gate pad 41 and the drift region 11. For example, a doping concentration of the drift region 11 from an area between 1E15 cm³ -3 and 5E16 cm -3selected (e.g., in the case of an N-type transistor device). The shielding structure 2 comprises several shielding electrodes 21, each arranged in a respective shielding trench 22, each dielectrically isolated from the gate pad 41 and the semiconductor body 100, and each connected to the source pad 42. However, connections between the source pad 42 and the shielding electrodes 21 are in Fig. 1 not visible and are explained in more detail below. Furthermore, the transistor device comprises several transistor cells 3, each comprising a gate electrode 31 connected to the gate pad 41.

[0020] Fig. Figure 1 shows a vertical cross-sectional view of a section of the semiconductor body 100 in a vertical section plane that is essentially perpendicular to the first surface 101. Furthermore, the Fig. Figure 1 illustrates a vertical section plane essentially parallel to a first lateral direction x and a vertical direction z of the semiconductor body 100. The vertical direction z is essentially perpendicular to the first lateral direction x.

[0021] The transistor cells 3 are each connected between the source pad 42 and the drift region 11 and are each configured to be in an on state (conducting state) or an off state (blocking state) depending on a voltage (gate-source voltage) applied between the gate pad 41 and the source pad 42 during operation of the transistor device. The transistor cells 3 can be implemented in various ways and are described in Fig. Figure 1 is not illustrated in detail. Instead, each of the transistor cells 3 is illustrated as an electronic switch with a parallel diode, representing the functionality of the transistor cells 3 as switches with parallel diodes. The diodes are commonly referred to as body diodes. Detailed examples of implementing the transistor cells 3 are further explained below.

[0022] The semiconductor body 100 comprises a monocrystalline semiconductor material. According to one example, the semiconductor body is a SiC (silicon carbide) semiconductor body and comprises monocrystalline SiC, such as SiC of the 4H or 6H polytype. According to another example, the semiconductor body is a silicon (Si) semiconductor body and comprises monocrystalline silicon.

[0023] The shielding electrodes 21 are electrically conductive and comprise an electrically conductive material. In one example, the electrically conductive material is doped polysilicon. In another example, the electrically conductive material is a metal.

[0024] With reference to the above, the shielding electrodes 21 are dielectrically isolated from the gate pad 41 and the semiconductor body 100. Fig. Figure 1 includes the arrangement of a dielectric layer 23 between the shielding electrodes 21 and the semiconductor body 100 in the grooves 22. Furthermore, the gate pad 41 is formed above the dielectric layer 23, and the dielectric layer 23 is arranged between the shielding electrodes 21 and the gate pad 41. The dielectric layer 23, arranged between the shielding electrodes 21 and the gate pad 41, can extend into the grooves 22 and can cover sections of the first surface 101 of the semiconductor body 100.

[0025] The dielectric layer 23, which insulates the shielding electrodes 21 from the semiconductor body 100 and the gate pad 41, can be a homogeneous layer of the same dielectric material or can comprise two or more different layers of different dielectric materials. Examples of the dielectric material include, but are not limited to, oxides such as silicon oxides (SiO₂, SiO₂).x ), silicon nitride oxides (SiNO₃) x ), HfO2 or oxides of other elements; nitrides, such as silicon nitrides or oxynitrides; or high-k dielectrics.

[0026] According to an example that was in Fig. As illustrated in dashed lines 1, the shielding trenches 22 with the shielding electrodes 21 are embedded in a doped shielding region 24 of the second doping type, which is complementary to the first doping type.

[0027] In the following, a region or section 110 of the semiconductor body 100 in which the transistor cells 3 are integrated is referred to as the cell region or active device region, and the region or section 120 in which the shielding structure 2 is arranged and above which the gate pad 41 is arranged is referred to as the gate pad region or passive device region.

[0028] With reference to Fig. 1 The transistor device can further comprise a gate node G, a source node S, and a drain node D. The gate node G is a circuit node connected to or formed by the gate pad 41, the source node S is a circuit node connected to or formed by the source pad 42, and the drain node D is a circuit node connected to the drift region 11. The gate node G and the source node S serve to apply a drive voltage (gate-source voltage) to the transistor cells 3 in order to operate the transistor cells 3 in either the on-state or the off-state. When the transistor cells 3 are in the on state, a current can flow between the drain node D and the source node S if a corresponding load path voltage is applied between the drain node D and the source node S.The voltage blocking capability depends, among other things, on the doping concentration and the dimensions of the drift region 11 in the vertical direction z. According to one example, the drift region 11 is implemented such that the voltage blocking capability lies in a range between 400 V and 8 kV. Specific examples of voltage blocking capabilities include, but are not limited to, 400 V, 600 V, 800 V, 1.2 kV, 1.4 kV, 1.7 kV, 2.3 kV, 2.4 kV, 3.3 kV, and 6.5 kV.

[0029] Fig. Figure 2 shows a transistor device based on the transistor device according to Fig. 1 is based on and additionally includes a drain region 13 of the first doping type, which is connected to the drain node D. The drain region 13 has a higher doping concentration than the drift region 11. For example, a doping concentration of the drain region 13 from a range between 5 x 18 cm⁻¹ -3 and 1E19 cm -3selected (e.g., in the case of an N-type transistor device). The drain region 13 can be adjacent to a second surface 102 opposite the first surface 101 of the semiconductor body 100. According to one example, the drain region 13 is adjacent to the drift region 11, such that the drift region 11 is located between the first surface 101 and the drain region 13. According to another example, a first-type buffer region 14 is located between the drift region 11 and the drain region 13. According to one example, the buffer region 14 has a higher doping concentration than the drift region 11 and a lower doping concentration than the drain region 13. For example, a doping concentration of the buffer region 14 is from a range between 1E16 cm³. -3 and 5E18 cm -3 selected (e.g. in the case of an N-type transistor device).

[0030] The transistor device includes a first capacitance Cgs, hereinafter also referred to as the gate-source capacitance, between the gate node G and the source node S. Furthermore, the transistor device includes a second capacitance Cgd, hereinafter also referred to as the gate-drain capacitance, between the gate node G and the drain node D. These first and second capacitances Cgs and Cgd are described in the following. Fig. 1 and Fig. 2 illustrated examples are represented by circuit symbols of capacitors.

[0031] In the absence of the shielding electrodes 21 connected to the source pad 42, a capacitance would exist between the gate pad 41 and the drift region 11, increasing the gate-drain capacitance Cgd of the transistor device. However, a high gate-drain capacitance Cgd, especially a high gate-drain capacitance Cgd relative to the gate-source capacitance Cgs, is undesirable because it can lead to unintended switching of the transistor device when a transient of a load path voltage applied between the drain node D and the source node S occurs. Specifically, the load path transient can cause the gate-source voltage across the gate-source capacitance Cgs to reach a threshold voltage of the transistor device, thus causing the transistor device to switch on unintentionally.

[0032] In a transistor device of the in Fig. 1 and Fig. In the illustrated type 2, the shielding structure 2 with the shielding electrodes 21, which are connected to the source pad 41, capacitively shields the gate pad 41 from the drift region 11. In this way, this shielding structure 2 reduces the gate-drain capacitance and increases the gate-source capacitance compared to a scenario in which there is only a dielectric layer between the gate pad 41 and the drift region 11 and in which the shielding electrodes 21 are omitted. Such an increase in the gate-source capacitance Cgs and a reduction in the gate-drain capacitance Cgd results in high robustness of the transistor device against unintentional switching when a transient of the load path voltage applied between the drain node D and the source node S occurs.

[0033] In addition to the portion of the gate-source capacitance Cgs formed by the gate pad 41 and the shielding structure 2, further portions of the gate-source capacitance Cgs are formed by the transistor cells 3. The gate-drain capacitance Cgd is mainly formed by capacitances between the transistor cells 3 and the drift region 11. This is explained further below.

[0034] Fig. 3A-3B and Fig. 4A-4B illustrate transistor cells according to different examples, each of which Fig. 3A and Fig. Figure 4A shows a vertical cross-sectional view of several transistor cells 3. Fig. 3B shows an enlarged view of one of the in Fig. 3A illustrated transistor cells 3, and Fig. 4B shows an enlarged view of one of the in Fig. 4A illustrated transistor cells 3. In each of the Fig. 3A and Fig. 4A illustrates only a section of the transistor cell region 110 of the semiconductor body 100, and only the section of the semiconductor body 100 in which the transistor cells 3 are integrated is illustrated.

[0035] With reference to the Fig. 3A-3B and Fig. 4A-4B Each transistor cell 3 comprises a gate electrode 31, a gate dielectric 33 that dielectrically insulates the gate electrode 33 from the semiconductor body 100, a source region 34 of the first doping type, and a body region 35 of the second doping type. For example, a doping concentration of the source region 34 from a range between 1E19 cm -3 and 1E21 cm -3 selected, and the doping concentration of body region 35 is from a range between 1E17 cm -3 and 5E17 cm -3selected (e.g., in the case of an N-type transistor device). Each of the gate electrodes 31 is arranged in a respective gate trench 32, which extends from the first surface 101 into the semiconductor body 100. In each transistor cell 3, the body region 35 is located between the source region 34 and the drift region 11. Furthermore, the body region 35 borders the gate dielectric 33. In a conventional manner, the gate electrode 31 is configured, depending on the gate-source voltage applied between the gate node G and the source node S during operation of the transistor device, to control a conducting channel in the body region 35 along the gate dielectric 33 between the source region 34 and the drift region 11. The source region 34 of each transistor cell 3 is connected to the source pad 42.

[0036] Furthermore, each transistor cell 3 includes a cell shielding region 38 of the second doping type, which is connected to the source pad 42 and which can also be referred to as a cell shielding region. For example, a doping concentration of the cell shielding region 38 from a range between 5E19 cm -3 and 1E21 cm -3selected (e.g., in the case of an N-type transistor device). The cell shielding region 38 extends vertically, from the first surface 101, to below the gate trenches 32, such that cell shielding regions 38 of adjacent transistor cells, together with a section of the drift region 11 located between the cell shielding regions 38, form a JFET (junction field-effect transistor) under each gate trench 32.When the transistor device is in the off state, such that conducting channels in the body regions 35 are open, and when a voltage is applied between the drain and source nodes D, S, which reverse-biases a PN junction formed between the body regions 35 and the drift region 11, adjacent cell shielding regions 38 clamp the drift region segment formed between them and protect the gate dielectric 33 from high electric fields as the voltage applied between the drain and source nodes D, S continues to increase. This is generally known, so no further explanation is needed in this respect.

[0037] The gate electrodes 31 are dielectrically insulated from the source pad 42 by a dielectrically insulating layer 36. The dielectrically insulating layer 36 can, for example, comprise the same type of material as the gate dielectric 33.

[0038] In the in the Fig. In the transistor cells illustrated in Figures 3A-3B, the cell shielding regions 38 are spaced from the gate trenches 32 in the first lateral direction x, and each gate trench 32 borders a body region 35 on opposite trench sidewalls. In this example, the gate electrodes 31 of two transistor cells are formed by the same electrode located in a gate trench 32. Furthermore, the cell shielding region 38 of two transistor cells 3 is formed by the same doped region of the second doping type. Additionally, in this example, the cell shielding region 38 is electrically connected to the source pad 42 by a contact electrode 36 that extends from the first surface 101 of the semiconductor body 100 into the semiconductor body 100.

[0039] The contact electrode 36 comprises an electrically conductive material, such as a metal. According to one example, the contact electrode 36 is a homogeneous electrode made of the same electrically conductive material, such as tungsten (W). According to another example, which is given in Fig. As illustrated in dashed lines in Figure 3B, the contact electrode 36 comprises two or more electrically conductive layers, such as a first layer 361, which lines the bottom and sidewalls of a contact trench in which the contact electrode 36 is formed, and a second layer 362, which fills any residual trench remaining after the formation of the first layer 361. For example, the first layer 361 is a titanium (Ti) layer and the second layer 362 is a tungsten (W) layer.

[0040] In the in the Fig. In the transistor cells 3 illustrated in Figures 4A-4B, each gate trench 32 borders only one side wall of a respective body region 35. The cell shielding region 38 borders a second side wall opposite the first side wall of the gate trench 32. In this example, a conducting channel in the body region 35 can only be formed along one of the two side walls of each gate trench 32. In the vertical direction z, the cell shielding regions 38 extend to the source pad 42. Alternatively (not illustrated), the Fig. Figures 4A-4B illustrated transistor cells 3 each having a contact electrode that connects the respective cell shielding region 38 to the source pad 42.

[0041] With reference to the foregoing, a gate-source capacitance section is formed between the transistor cells 3 and the source pad 42. More precisely, gate-source capacitance sections are formed by the gate electrodes 31, the gate dielectrics, and the source regions 34, which are dielectrically isolated from the gate electrode 31 by the gate dielectrics 33. Furthermore, gate-drain capacitance sections are formed by the gate electrodes 31, the gate dielectrics 33 located between the gate electrodes 31 and the drift region 11, and the drift region itself.

[0042] The transistor device can be implemented as an N-type or a P-type transistor device. In an N-type transistor device, the doped regions of the first doping type, such as source region 34, drift region 11, drain region 13, and optional buffer region 14, are N-type regions, and the doped regions of the second doping type, such as body region 35, are P-type regions. In a P-type transistor device, the doped regions of the first doping type are P-type regions, and the doped regions of the second doping type are N-type regions.

[0043] According to an example (not illustrated), the transistor device is implemented as a supertransition device. In this example, the transistor device includes several compensation regions of second doping, arranged in the drift region 11, connected to the source node S, and extending in the vertical direction z from below the transistor cells 3 to the drain region 13 or the optional buffer region 14. The compensation regions may be adjacent to the cell shield regions 38 in order to be connected to the source node S via the cell shield regions 38. For example, the doping concentration of the compensation regions is in the same range as the doping concentration of the drift region 11.

[0044] It should be noted that the Fig. 3A-3B and Fig. Figures 4A-4B illustrate only two of a multitude of different examples for implementing the transistor cells 3, each comprising a trench electrode 31. In each example, the trench-gate electrodes 31 of the transistor cells 3 and the shielding electrodes 21 of the shielding structure 2 can be formed by the same process, so that no additional process steps are required to form the shielding electrodes 21. This results in a high efficiency of the method for fabricating the transistor device.

[0045] With reference to the Fig. 3A-3B and Fig. In 4A-4B, the drift region 11 can include a current propagation region 15, which has a higher doping concentration than the rest of the drift region 11. The current propagation region 15 helps to reduce the on-resistance of the transistor device, which is the electrical resistance between the drain and source nodes D, S in the on-state of the transistor cells 3. As an example, the current propagation region 15 is adjacent to the body regions 35 and is located between adjacent cell shield regions 38.

[0046] With reference to the Fig. 1 and Fig. In Figure 2, the shielding trenches 22 with the shielding electrodes 21 are spaced apart from each other in a lateral direction x of the semiconductor body 100. The lateral direction in which the shielding electrodes 21 are spaced apart from each other is, in this example, the first lateral direction x of the semiconductor body 100. Furthermore, the shielding electrodes 21 are elongated electrodes that extend longitudinally in a second lateral direction y. According to one example, the second lateral direction y is at least approximately perpendicular to the first lateral direction x.

[0047] With reference to the Fig. 3A and Fig. In 4A, the gate grooves 32 with the gate electrodes 31 are spaced apart from each other in a third lateral direction x1 of the semiconductor body 100. According to an example, the gate electrodes 31 are elongated electrodes extending longitudinally in a fourth lateral direction y1, which is at least approximately perpendicular to the third lateral direction x1.

[0048] As an example, the shielding electrodes 21 and the gate electrodes 31 have the same orientation. That is, the first lateral direction x in which the shielding electrodes 21 are spaced apart is equal to the third lateral direction x1 in which the gate electrodes 31 are spaced apart. Equivalently, the second lateral direction y in which the shielding electrodes 21 extend longitudinally is equal to the fourth lateral direction y1 in which the gate electrodes 31 extend longitudinally.

[0049] Fig. Figure 5 schematically illustrates a top view of a transistor device with elongated shielding electrodes 21 and elongated gate electrodes 31, which have the same orientation. More precisely, it shows Fig. Figure 5 shows a top view of the gate pad 41 and the source pad 42 of a transistor device according to an example. Furthermore, the position and orientation of some shielding electrodes 21, arranged in shielding trenches 22 in the semiconductor body 100 under the gate pad 41, and the position and orientation of some gate electrodes 31, arranged in gate trenches 32 in the semiconductor body 100 under the source pad 42, are illustrated by bold lines.

[0050] The in Fig. Figure 5 illustrates a transistor device comprising a gate runner 42 formed over the semiconductor body 100 and connected to the gate pad 41. In this example, the transistor cells 3 comprise a first group of transistor cells whose gate electrodes 31 are directly connected to the gate pad 41, and a second group of transistor cells 3 whose gate electrodes 31 are directly connected to the gate runner 43, such that the gate electrodes of the transistor cells 3 of the second group are connected to the gate pad 41 via the gate runner 43. Fig. 5. The gate electrodes of the transistor cells of the first group have the reference symbol 311 and the gate electrodes of the transistor cells of the second group have the reference symbol 312.

[0051] With reference to Fig. 5 The gate runner 43 is elongated and extends longitudinally in the first lateral direction x, which is the direction in which the shielding electrodes 21 and the gate electrodes 31 are spaced apart. In the Fig. In the 5 illustrated example, the gate pad 41 is arranged essentially over a corner region of the semiconductor body 100, and the transistor device includes only one gate runner 43. According to another example (not illustrated), the gate pad 41 is arranged essentially in the middle between two opposite sides of the semiconductor body 100, and the transistor device includes two gate runners, each extending in the first lateral direction x, but on opposite sides of the gate pad.

[0052] It should be noted that “first lateral direction x” and “second lateral direction y” as well as “third lateral direction x1” and “fourth lateral direction y1” denote lateral orientations, so that each of these directions represents a specific direction and the corresponding opposite direction.

[0053] The cross-sectional view of Gate Pad Region 120 and an adjacent section of the in Fig. The illustrated cell region 110 corresponds to a cross-sectional view in the Fig. Figure 5 illustrates the section plane A-A', which intersects the gate pad 41 and a section of the source pad 42 and regions of the semiconductor body 100. The cross-sectional views of the Fig. 3A and Fig. 4A illustrated transistor cells 3 correspond to cross-sectional views in the in Fig. 5 illustrated cutting plane BB' and C-C', where the cutting plane BB' cuts a section of the source pad 42 and transistor cells 3 of the first group and the cutting plane CC' cuts a section of the source pad 42 and transistor cells 3 of the second group.

[0054] Referring to the above, the gate electrodes 311 of the first group of transistor cells 3 are directly connected to the gate pad 41. For this purpose, the gate electrodes 311 extend longitudinally to below the gate pad 41. An example of connecting the gate electrodes 311 of the first group to the gate pad 41 is shown in Fig. Figure 6 illustrates this and is explained further below. Furthermore, the gate electrodes 312 of the second group of transistor cells 3 are directly connected to the gate runner 44. For this purpose, the gate electrodes 312 extend longitudinally to below the gate runner 44. An example of connecting the gate electrodes 312 of the second group to the gate pad 41 is shown in Figure 6. Fig. 7 is illustrated and explained further below.

[0055] Referring to the above, the shielding electrodes 21 are connected to the source pad 42. In the Fig. In the illustrated example 5, the transistor device further comprises a source runner 44 connected to the source pad 42. The source pad 42 and the source runner 44 define an opening in which the gate pad 41 and the gate runner 43 are arranged. The gate runner 44 is also positioned between the gate pad 41 and a first edge surface 103 of the semiconductor body 100. In this example, the shielding electrodes 21 are connected to the source runner 44, such that the shielding electrodes 21 are connected to the source pad 42 via the source runner 44. To connect the shielding electrodes 21 to the source runner 44, the shielding electrodes 21 extend longitudinally from below the gate pad 41, across the gate pad 41, and into the area below the source runner 44.

[0056] Fig. Figure 6 illustrates an example of connecting the gate pad 41 to the gate electrodes 311 of the first group and connecting the source runner 44 to the shielding electrodes 21. Fig. Figure 6 shows a vertical cross-sectional view in the Fig. The section plane D-D' is illustrated in Figure 5. The section plane DD' intersects a shielding electrode 21 and a section of an adjacent gate electrode 31 in the longitudinal directions of the gate electrode 21 and the shielding electrode 31. Furthermore, the section plane DD' intersects the gate pad 41, the source runner 44, a section of the source pad 42, and the semiconductor body 100.

[0057] With reference to Fig. 6 The shielding electrode 21 comprises a first longitudinal end 211 and a second longitudinal end 212, wherein the first longitudinal end terminates a section of the shielding electrode 21 that extends beyond the gate pad 41 in the longitudinal direction to below the source runner 44. A first end section, which is a section of the shielding electrode 21 adjacent to the first longitudinal end 211, is connected to the source runner 44 by a contact via 441 that extends in the vertical direction z from the source runner 44 through the dielectric layer 23, which is arranged above the shielding electrode 21, downwards to the shielding electrode 21. The second longitudinal end 212 of the shielding electrode 21 faces the adjacent gate electrode 31 and is spaced apart from the gate electrode 31. Furthermore, the second longitudinal end 212 is arranged below the gate pad 41.

[0058] With reference to Fig. In section 6, the gate electrode 31 has a first longitudinal end 311 that faces the second longitudinal end 212 of the adjacent shielding electrode 21. The first longitudinal end of the gate electrode 31 and an end section of the gate electrode 31, which is a section of the gate electrode 31 adjacent to the first longitudinal end 311, are arranged below the gate pad 41. The end section of the gate electrode 31 is connected to the gate pad 41 by an electrically conductive via 411. The via 411 extends in the vertical direction z from the gate pad 41 through the dielectric layer 23 downwards to the gate electrode 31. The dielectric layer 23 separates the shielding electrode 21 from the gate pad 41 and the gate electrode 31 from the gate pad 41.

[0059] Referring to the above, the source runner 44 can be arranged between the gate pad 41 and a first edge surface 103 of the semiconductor body 100. Optionally, as shown in Fig. As illustrated in dashed lines in Figure 6, the source runner 44 is connected to the semiconductor body 100 in the edge region of the semiconductor body 100. The edge region is a region of the semiconductor body 100 below the source runner 44. One or more contact pins 442 extend from the source runner 44 to an edge termination region 443 of the second doping type. The edge termination region 443 can be adjacent to the drift region 11 of the first doping type.

[0060] Referring to the above, the gate electrodes 312 of the second group of transistor cells 3 are connected to the gate runner 43. An example of connecting the gate runner 43 to the gate electrodes 312 of the transistor cells of the second group is shown in Fig. 7 illustrates.

[0061] Fig. Figure 7 shows a vertical cross-sectional view in the Fig. The section plane E-E' is illustrated in Figure 5. The section plane EE' intersects a section of a gate electrode 312, a section of the source pad 43, the gate runner 43, a shielding electrode 21, and a section of an adjacent gate electrode 31 in the longitudinal directions of the gate electrode 21 and the shielding electrode 31. With reference to Fig. 7 The gate electrode 312 comprises a first longitudinal end 311 and an end section adjoining the first longitudinal end 311. The end section is at least partially located below the gate runner 43 and is electrically connected to the gate runner 43 by an electrically conductive via 431, the via 431 extending through the dielectrically insulating layer 23 that separates the gate electrode 312 from the gate pad 41 (which is located in Fig. (not illustrated in Figure 7) and also separates from the gate runner 43. In the same way as adjacent to the gate pad 41, the source runner 44 can be connected to the edge termination region 443, which is located in the edge region of the semiconductor body 100.

[0062] As explained above, the shielding electrodes 21 are arranged in shielding trenches 22 at least partially beneath the gate pad 41, and the gate electrodes 31 can be arranged in gate trenches 32 at least partially beneath the source pad 42. Implementing both the shielding electrodes 21 and the gate electrode 31 as trench electrodes allows the transistor device to be fabricated efficiently, since the shielding electrodes 21 and the gate electrodes 31 can be formed by the same process sequence. An example of a method for fabricating the shielding electrodes 21 and the gate electrodes 31 is described below with reference to Fig. 8A-8D explained.

[0063] Each of the Fig. Figures 8A-8D show a vertical cross-sectional view of a section of the semiconductor body 100 in the transistor cell region 110 and the gate pad region 120. Only the drift region 11 is illustrated in the semiconductor body 100. Other doped regions, such as the source and body regions 34 and 35 of the transistor cells 3 or the shielding region 24 in the gate pad region 120, are not shown. These doped regions can be formed before or after the formation of the shielding electrodes 21 and the gate electrodes 31.

[0064] With reference to Fig. 8A The procedure includes forming the shielding trenches 22 and the gate trenches 32 by the same process steps. The formation of the trenches 22, 32 may include an anisotropic etching process using an etching mask (not illustrated) formed on the first surface 101.

[0065] With reference to Fig. 8B further comprises the formation of a dielectric layer 210 at least along the side walls and bottoms of the shielding trenches 22 and the gate trenches 32. Sections of the dielectric layer 210 in the gate trenches 32 form the gate dielectrics 33 of the transistor cells 3 in the finished device and sections of the dielectric layer 210 in the shielding trenches 22 form a section of the dielectric layer 23 that separates the shielding electrodes 21 from the semiconductor body 100 in the finished device.

[0066] The formation of the dielectric layer 210 can involve a deposition process in which the dielectric layer 210 is deposited on the sidewalls and bottoms of the trenches 22, 32 and the first surface 101 between the trenches. According to one example, the dielectric layer 210 is a homogeneous layer of only one dielectric material, such as silicon dioxide. According to another example, the dielectric layer 210 comprises two or more sublayers of different dielectric materials formed on top of each other.

[0067] According to one example, the dielectric layer 210 is designed to be thicker at the trench bottoms of the trenches 22 than at the trench sidewalls, so that in the finished device, the dielectric layer 23 in the trenches 22 is thicker at the trench bottoms than at the sidewalls. In this example, the dielectric layer 210 comprises, for example, an HDP (high-density plasma) oxide, which can be formed in a specific deposition process. Similar to the trench bottoms, the dielectric layer 210 can be thicker on the first surface 101 than on the trench sidewalls.

[0068] With reference to Fig. 8C further comprises the formation of an electrode layer 220 at least in the shielding trenches 22 and the gate trenches 32. According to a Fig. In the example illustrated in Figure 8C, the electrode layer 220 is formed such that it completely fills the shielding trenches 22 and the gate trenches 32 on the dielectric layer 210. Furthermore, the electrode layer 220 is formed over the first surface 101.

[0069] With reference to Fig. 8D further comprises the formation of the shielding electrodes 21 in the shielding trenches 22 and the gate electrodes 31 in the gate trenches 32 based on the electrode layer 220. This may include an etching process in which the electrode layer 220 is removed from above the first surface 101. According to one example (not illustrated), the etching process stops when the electrode layer 220 has been removed from above the first surface 101. According to another example (in Fig.(Illustrated in 8D) the etching process continues after the electrode layer 220 has been removed from above the first surface 101, so that the shielding electrodes 21 are recessed in the shielding trenches 22 and the gate electrodes 31 are recessed in the gate trenches 32 relative to the first surface 101.

[0070] After forming the shielding electrodes 21 and the gate electrodes 31, the remainder of the dielectric layer 23, which separates the shielding electrodes 21 from the gate pad 41 in the finished device, and the insulating layer 36, which separates the gate electrodes 31 from the source pad 42 in the finished device, can be formed. This can involve a deposition process in which a dielectric insulating layer is deposited, forming the dielectric layer 23 between the shielding electrodes 21 and the gate pad 41 and the insulating layer between the gate electrodes 31 and the source pad 42.

Claims

[1] Transistor device comprising: a semiconductor body (100); a drift region (11) of a first doping type in the semiconductor body (100); a gate pad (41) formed over a first surface (101) of the semiconductor body (100); a shielding structure (2) arranged between the gate pad (41) and the drift region (11) and comprising several shielding electrodes (21) each arranged in a respective shielding trench (22) and dielectrically insulated from the gate pad (41) and the semiconductor body (100); a source pad (42) formed above the first surface (101) of the semiconductor body (100) and connected to the shielding electrodes (21); and several transistor cells (3) each comprising a gate electrode (31) connected to the gate pad (41). [2] Transistor device according to claim 1, wherein the gate electrode (31) of each transistor cell is formed in a gate groove (22) extending from a first surface (101) of the semiconductor (100) into the semiconductor body (100). [3] Transistor device according to claim 1 or 2, further comprising: a source runner (44) formed above the first surface (101) of the semiconductor body (100) and connected to the source pad (42), wherein the shielding electrodes (21) are connected to the source pad (42) via the source runner (43). [4] Transistor device according to one of claims 1 to 3, wherein the shielding electrodes (21) are elongated electrodes spaced apart from each other in a first lateral direction (x) of the semiconductor body (100) and extending longitudinally in a second lateral direction (y). [5] Transistor device according to claim 4, wherein each of the shielding electrodes (21) comprises a first longitudinal end (211) and a second longitudinal end (212) opposite the first longitudinal end (211). [6] Transistor device according to claim 5, wherein an end section adjoining the first longitudinal end (211) of each shielding electrode (21) in the second lateral direction (y) projects from below the gate pad (41) and is connected to the source runner (44). [7] Transistor device according to one of claims 4 to 6, wherein the gate electrodes (31) are elongated electrodes spaced apart from each other in a third lateral direction (x1) and extending longitudinally in a fourth lateral direction (y1). [8] Transistor device according to claim 7, wherein the third lateral direction (x1) is equal to the first lateral direction (x), and wherein the fourth lateral direction (y1) is equal to the second lateral direction (x1). [9] Transistor device according to claim 8, wherein the gate electrodes (31) comprise a first group of gate electrodes spaced apart from the shielding electrodes (21) in the second lateral direction (y) and a second group of gate electrodes spaced apart from the shielding electrodes (21) in the first lateral direction (x), wherein the transistor device further comprises a gate runner (43) which is connected to the gate pad (41), wherein the gate electrodes (21) of the first group are directly connected to the gate pad (41), and wherein the gate electrodes (21) of the second group are connected to the gate pad (41) by a gate runner (43). [10] Transistor device according to any one of claims 1 to 9, further comprising: a shielding region (24) of the second doping type, adjacent to the drift region (11), wherein the shielding electrodes (21) are embedded in the shielding region (24). [11] Transistor device according to any one of claims 1 to 10, wherein each transistor cell (3) further comprises: a gate dielectric (33) that dielectrically insulates the gate electrode (31) from the semiconductor body (100); a source region (34) of the first doping type, which is connected to the source pad (42); and a body region (34) of the second doping type, adjacent to the gate dielectric (33) and the source region (34) and located between the source region (34) and the drift region (11). [12] Transistor device according to claim 11, wherein each transistor cell (3) further comprises: a cell shielding region (38) of the second doping type, which is connected to the source pad (42) and extends in a vertical direction (z) of the semiconductor body (100) into the drift region (11). [13] Transistor device according to claim 12, wherein the drift region (11) comprises a current propagation region (12) which is adjacent to the gate grooves (32) in the vertical direction (z) and has a higher doping concentration than the remainder of the drift region (11). [14] Transistor device according to claim 12 or 13, wherein the cell shielding region (38) is spaced apart from the gate trench (32) in the first lateral direction (x). [15] Transistor device according to claim 14, wherein the cell shielding region (38) is connected to the source pad (42) by a contact electrode (36) arranged in a trench extending from the first surface (101) into the semiconductor body (100). [16] Transistor device according to claim 12 or 13, wherein the cell shielding region (38) adjoins a side wall of the gate trench (32). [17] Transistor device according to any one of the preceding claims, further comprising: a drain region (13) of the first doping type coupled to the drift region (11). [18] Method for manufacturing a transistor device, the transistor device comprises: a semiconductor body (100); a drift region (11) of a first doping type in the semiconductor body (100); a gate pad (41) formed over a first surface (101) of the semiconductor body (100); a shielding structure (2) arranged between the gate pad (41) and the drift region (11) and comprising several shielding electrodes (21) each arranged in a respective shielding trench (22) and dielectrically insulated from the gate pad (41) and the semiconductor body (100); a source pad (42) formed above the first surface (101) of the semiconductor body (100) and connected to the shielding electrodes (21); and several transistor cells (3), each comprising a gate electrode (31) connected to the gate pad (41), and the procedure includes: Formation of the shielding electrodes (21) and the gate electrodes (31) by the same process sequence.

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