TIME-TO-DIGITAL CONVERSION DEVICE

Abstract

One embodiment of a time-to-digital conversion device comprises a first oscillator configured to output a first clock signal in response to a first event, and a second oscillator configured to output a second clock signal in response to a second event. The embodiment of the time-to-digital conversion device further comprises a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate a count based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal. The count indicates the time difference between the first and second events.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This patent application claims the benefits of provisional US patent application no. 63 / 703,789, filed on October 4, 2024, the entire disclosure of which is hereby incorporated by reference. BACKGROUND

[0002] A time-to-digital conversion device, such as a time-to-digital converter (TDC), is designed to convert time information into digital values. In some applications, a TDC can be used in conjunction with a voltage-to-timing converter (VTC) to capture a waveform on an integrated circuit (IC) to monitor the power integrity (PI) characteristic of the IC die. In some applications, a TDC can be used to measure the phase noise of a phase-locked loop (PLL). In some applications, a TDC can be used to measure the time of flight (ToF) of a wireless, acoustic, and / or optical signal.

[0003] In some applications requiring high-precision and flexible waveform measurement, a time-to-digital conversion device with a resolution of less than 100 femtoseconds (fs) and a large dynamic range can be used. However, in some applications, a limited range budget for implementing a time-to-digital conversion device may restrict its resolution and / or dynamic range. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this revelation are best understood from the following detailed description, when read in conjunction with the accompanying figures. It should be noted that various elements are not drawn to scale, as is common practice in the industry. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1A to 1B are block diagrams of application examples based on a time-to-digital conversion device according to some embodiments. Fig. Figure 2 is a block diagram of an exemplary time-to-digital conversion device according to some embodiments. Fig. Figure 3 is a process flow diagram of an exemplary process flow performed by a time-to-digital conversion device, according to some embodiments. Fig. 4A is a circuit diagram of an exemplary oscillator according to several embodiments. Fig. 4B is a circuit diagram of the NAND gate in the delay circuit in Fig. 4A according to some embodiments. Fig. Figure 5 is a circuit diagram of an exemplary phase detector according to some embodiments. Fig. 6A is a circuit diagram of an exemplary clock gate circuit according to several embodiments. Fig. 6B to 6C are circuit diagrams of variation examples based on the clock gate circuit in Fig. 6A according to some embodiments. Fig. Figure 7 is a block diagram of an exemplary counter according to some embodiments. Fig. Figures 8A to 8D are diagrams of signal waveforms and / or digital values ​​from an exemplary time-to-digital conversion session performed by a time-to-digital conversion device, based on the examples in Fig. 2 to 6A and 7, according to some embodiments. Fig. Figures 9A to 9B are diagrams of an exemplary delay circuit based on a phase interpolator according to some embodiments. Fig. Figures 10A to 10C are diagrams of an exemplary delay circuit based on an adjustable load resistance according to some embodiments. Fig. Figure 11 is a circuit diagram of oscillators arranged to correspond to different clock periods, according to some embodiments. Fig. Figure 12 is a flowchart of a method for generating a count value that indicates a time difference between a first event and a second event, according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various elements of the provided content. To simplify the presentation, specific examples of components and arrangements are described below. These are, of course, only examples and are not to be understood as limiting. For example, the formation of a first element or a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and it may also include embodiments in which further elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself establish a relationship between the various designs and / or devices discussed.

[0006] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass various orientations of the device during use or operation. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative terms used herein may be interpreted accordingly. Furthermore, the term "made of" may mean either "containing" or "consisting of."In this revelation, the phrase “one of A, B and C” means “A, B and / or C” (A, B, C, A and B, A and C, B and C or A, B and C) and not one element of A, one element of B and one element of C, unless otherwise described.

[0007] Recent advances in computer technology have led to an increased demand for computing power. For example, artificial intelligence (AI) is now more powerful than ever before, employing advanced large language models with numerous parameters. Training these large language models and / or performing inference operations based on them requires significant computing power, which has increased the need for high-performance computing (HPC) equipment. Processing circuitry and components, such as central processing units (CPUs), graphics processing units (GPUs), and / or tensor processing units (TPUs), within an HPC device face power integrity challenges due to high currents. These challenges can be addressed by monitoring the power impedance of the processing circuitry and components.

[0008] In some applications, power impedance monitoring includes monitoring on-chip waveforms or signal delays relative to a reference signal. For example, it shows Fig. Figure 1A is a block diagram 100A of a first application example for determining a clock offset within the digital logic 110 in an integrated circuit according to some embodiments. In Fig. In 1A, two clock signals CLK1 (e.g., a reference signal) and CLK2 (e.g., a monitored signal), output by the digital logic 110, are coupled to a time-to-digital conversion device 120 for comparison. In this example, the time-to-digital conversion device 120 is configured to generate an output signal TDC_OUT based on the clock signals CLK1 and CLK2, where the output signal TDC_OUT represents a value (e.g., multi-bit digital data) indicating a time difference between the clock signal CLK1 and the clock signal CLK2.

[0009] Furthermore, Fig. 1B a block diagram 100B of a second application example for detecting a voltage level of a waveform in an integrated circuit, according to some embodiments. In Fig. In 1B, a voltage signal VSENSE is acquired by a voltage-to-time converter (labeled "VTC") 130. Based on a reference clock signal CLK_REF, the voltage-to-time converter 130 generates a delay signal CLK_DELAY, so that the voltage level of the voltage signal VSENSE is converted into a time difference between the reference clock signal CLK_REF and the delay signal CLK_DELAY. In this example, a time-to-digital conversion device 140 is configured to generate an output signal TDC_OUT based on the reference clock signal CLK_REF and the delay signal CLK_DELAY, where the output signal TDC_OUT represents a value (e.g., multi-bit digital data) that indicates a time difference between the reference clock signal CLK_REF and the delay signal CLK_DELAY.

[0010] In some applications, a time-to-digital conversion device based on a Vernier delay line can achieve a fine resolution (e.g., below 100 femtoseconds (fs)), but at the cost of more delay levels, area, complexity, and therefore cost.

[0011] This disclosure describes, in one or more embodiments, a time-to-digital conversion device based on the clock period difference between two oscillators. In some embodiments, two oscillators are activated in response to two events, and a later activated clock signal lags an earlier activated clock signal by an increment of the clock period difference per clock cycle. In some embodiments, according to one or more of this application, the device still exhibits fine resolution in the time domain (e.g., a resolution of less than 80 femtoseconds) and a measurable range of 0 to 245 picoseconds without increasing the number of delay stages, which in turn improves the landscape efficiency in an integrated circuit, reduces the complexity of the circuit arrangement, and lowers manufacturing costs.

[0012] Fig. Figure 2 is a block diagram of a time-to-digital conversion device 200, according to some embodiments. The time-to-digital conversion device 200 in Fig. Figure 2 is illustrated as a non-restrictive example. In some embodiments, some components of the time-to-digital conversion device 200 are in Fig. 2 simplified or omitted.

[0013] In Fig. The time-to-digital conversion device 200 comprises a first oscillator 210, a second oscillator 220, a phase detector 230, and a clock counter 240. The first oscillator 210 is configured to receive a first reference signal START1 and a first deceleration control signal SLOW1. The first oscillator 210 is configured to output a first clock signal CKA_M in response to a first event. In some embodiments, the first oscillator 210 is further configured to output a first buffered clock signal CKA_OUT, which is derived from the first clock signal CKA_M passing through a buffer stage of the first oscillator 210. In some embodiments, the first clock signal CKA_M and the first buffered clock signal CKA_OUT have a first clock period T1.

[0014] In addition, the second oscillator 220 is configured to receive a second reference signal START2 and a second deceleration control signal SLOW2. The second oscillator 220 is configured to output a second clock signal CKB_M in response to a second event. In some embodiments, the second clock signal CKB_M has a second clock period T2. In some embodiments, the first event occurs before the second event. In some embodiments, the first clock period T1 is longer than the second clock period T2. In some embodiments, the second clock period T2 is at least 100 times the period difference ΔT between the first clock period T1 and the second clock period T2. In some embodiments, the second clock period T2 ranges from 2 nanoseconds (ns) to 6 ns. In some embodiments, the period difference ΔT is between 60 femtoseconds (fs) and 100 fs.

[0015] In some embodiments, the first event, as a non-limiting example, corresponds to the change or transition of the first reference signal START1 from a first logical state (e.g., logical LOW or LOW in this disclosure) to a second logical state (e.g., logical HIGH or HIGH in this disclosure). In some embodiments, the second event corresponds to the change or transition of the second reference signal START2 from the first logical state (e.g., LOW) to the second logical state (e.g., HIGH). In some embodiments, the first oscillator 210 is configured to be deactivated when the first reference signal START1 assumes the first logical state and to be activated when the first reference signal START1 assumes the second logical state.In some embodiments, the second oscillator 220 is configured to be deactivated when the second reference signal START2 assumes the first logical state, and to be activated when the second reference signal START2 assumes the second logical state.

[0016] In some embodiments, the first clock period T1 is adjustable based on the first deceleration control signal SLOW1, and the second clock period T2 is adjustable based on the second deceleration control signal SLOW2. In some embodiments, the first oscillator 210 and the second oscillator 220 are based on the same hardware arrangement. In some embodiments, the first oscillator 210 is a first ring oscillator comprising one or more first load capacitors, a first load resistor, or a first phase interpolator between two successive inverting stages of the first oscillator 210, and configured to set a first adjustable delay of the first oscillator 210.In some embodiments, the second oscillator 220 is a first ring oscillator comprising one or more second load capacitors, a second load resistor, or a second phase interpolator between two successive inverting stages of the second oscillator 220, and configured to set a second adjustable delay of the second oscillator 220. In some embodiments, the first clock period T1 is determined based on the first adjustable delay of the first oscillator 210, and the second clock period T2 is determined based on the second adjustable delay of the second oscillator 220.

[0017] During operation of the time-to-digital conversion device 200, the first clock period T1 and the second clock period T2 are set based on the first deceleration control signal SLOW1 and the second deceleration control signal SLOW2. For example, during operation, the first deceleration control signal SLOW1 is set to the second logic state (e.g., HIGH), indicating that the first clock period T1 corresponds to a slower clock setting of the first oscillator 210 (e.g., setting the first adjustable delay to a higher value), while the second deceleration control signal SLOW2 is set to the first logic state (e.g., LOW), indicating that the second clock period T2 corresponds to a faster clock setting of the second oscillator 220 (e.g., setting a second adjustable delay to a smaller value).

[0018] In some alternative embodiments, the first oscillator 210 and the second oscillator 220 are based on different hardware devices corresponding to the output of clock signals with first clock period T1 and second clock period T2, respectively. In some embodiments, due to the hardware devices of the first oscillator 210 and the second oscillator 220, no adjustable delays are available, and the first deceleration control signal SLOW1 and / or the second deceleration control signal SLOW2 are therefore omitted.

[0019] The phase detector 230 is configured to generate a detection signal HITB based on a phase relationship between the first clock signal CKA_M and the second clock signal CKB_M. In some embodiments, as a non-limiting example, the detection signal HITB has the first logical state (e.g., LOW), which indicates that the phase of the first clock signal CKA_M lags behind the phase of the second clock signal CKB_M, and has the second logical state (e.g., HIGH), which indicates that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M.

[0020] The clock counter 240 is configured to generate a count value TDC_OUT based on the first clock signal CKA_M in response to the detection signal HITB, which indicates that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M. In some embodiments, the count value TDC_OUT indicates the time difference between the first and second events. In some embodiments, the clock counter 240 is configured to receive and count the clock cycles of the first clock signal CKA_M. In some embodiments, the clock counter 240 is configured to receive and count the clock cycles of the first buffered clock signal CKA_OUT.In some other embodiments, the clock counter 240 is configured to generate the count value TDC_OUT based on the second clock signal CKB_M instead of the first clock signal CKA_M or the first buffered clock signal CKA_OUT when the detection signal HITB indicates that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M.

[0021] In Fig. 2. The clock counter 240 comprises a clock gate circuit 250 and a counter 260. In some embodiments, a clock gate circuit 250 is configured to generate a counting clock signal CKC based on the first clock signal CKA_M (or the first buffered clock signal CKA_OUT, which is derived from the first clock signal CKA_M) and the detection signal HITB. In some embodiments, the clock gate circuit 250 is configured to generate the counting clock signal CKC, which has the same frequency and period as the first clock signal CKA_M, in response to the detection signal HITB being in the second logic state (e.g., HIGH), which indicates that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M. In some embodiments, the clock gate circuit 250 is set up, the counting clock signal CKC is generated in response to the fact that the recognition signal HITB is in the first logical state (e.g.to set the signal from LOW to a logical state (e.g., the first logical state or LOW). In this example, the clock gate circuit 250 comprises a clock terminal (represented by a triangle sign) configured to receive the first clock signal CKA_M or the first buffered clock signal CKA_OUT, an enable terminal (labeled "EN") configured to receive the detection signal HITB, and an output terminal configured to output the count clock signal CKC.

[0022] In some embodiments, counter 260 is an N-bit counter, and TDC_OUT is a count value that is an unsigned N-bit integer. In some embodiments, N ranges from 6 to 12 or from 8 to 10. In this example, counter 260 includes a clock terminal (represented by a triangle) configured to receive the count clock signal CKC and an output terminal configured to output the count value TDC_OUT.

[0023] In some embodiments, an integrated circuit comprises one or more digital circuit blocks configured to output different reference signals (e.g., the first reference signal START1 and the second reference signal START2). In some embodiments, the integrated circuit further comprises a time-to-digital conversion device 200 configured to output a count value (e.g., count value TDC_OUT) indicating a time difference between a first event based on the first reference signal and a second event based on the second reference signal.

[0024] Fig. Figure 3 is a process flow diagram of a process 300 performed by a time-to-digital conversion device, according to some embodiments. In some embodiments, the process 300 is illustrated based on various operations performed by the time-to-digital conversion device 200 in Fig. 2 will be presented as a non-restrictive example. In Fig. The process flow 300 comprises stages 310 to 355.

[0025] In stage 310, various components of the time-to-digital conversion device are reset. For example, the phase detector 230, the clock gate circuit 250, and the counter 260 are reset to clear all data or logical states from a previous time-to-digital conversion. In stage 310, the detection signal HITB is set to deactivate the clock gate circuit 250, and the counter clock signal CKC is set to prevent any action from being taken at the counter 260.

[0026] In stage 315, a first reference signal (e.g., the first reference signal START1) transitions from a first logic state (e.g., LOW) to a second logic state (e.g., HIGH), and the transition of the logic state indicates the occurrence of a first event. In stage 320, a first oscillator (e.g., the first oscillator 210) outputs a first clock signal (e.g., the first clock signal CKA_M) as an oscillating signal in response to the first event. In some embodiments, the first clock signal CKA_M has a first clock period T1.

[0027] At stage 325, the phase detector 230, based on the presence of the first clock signal CKA_M (as an oscillating signal) and the absence of the second clock signal CKB_M (as an oscillating signal), begins to output the detection signal HITB on the first logic state (e.g., LOW), which indicates that one phase of the second clock signal CKB_M lags behind one phase of the first clock signal CKA_M, which in turn activates the clock gate circuit 250 and then the counter 260.

[0028] In stage 330, a second reference signal (e.g., the first reference signal START2) transitions from the first logic state (e.g., LOW) to the second logic state (e.g., HIGH), and the transition of the logic state indicates the occurrence of a second event. In some embodiments, the transition of the logic state of the second reference signal START2 from LOW to HIGH is delayed by a time difference Tsense relative to the transition of the logic state of the first reference signal START1 from LOW to HIGH. In stage 335, a second oscillator (e.g., the second oscillator 220) outputs a first clock signal (e.g., the second clock signal CKB_M) as an oscillating signal in response to the second event. In some embodiments, the second clock signal CKB_M has a second clock period T2, which is equal to (T1 - ΔT).In stage 335, the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M, and clock gate circuit 250 and counter 260 thus remain activated.

[0029] In stage 340, the phase of the second clock signal CKB_M catches up after Tsense / ΔT cycles and then leads the phase of the first clock signal CKA_M. In stage 345, in response to the updated phase relationship between the first clock signal CKA_M and the second clock signal CKB_M, the phase detector 230 outputs the detection signal HITB at the second logic state (e.g., HIGH), indicating that the phase of the first clock signal CKA_M lags behind the phase of the second clock signal CKB_M.

[0030] In stage 350, the detection signal HITB in the second logic state (e.g., HIGH) would again deactivate the clock gate circuit 250. In stage 350, the clock gate circuit 250 sets the counting clock signal CKC to a fixed logic state to prevent any action at the counter 260. In stage 355, the counter 260 stops. The counter output (e.g., the count value TDC_OUT) is read as the conversion result. In some embodiments, the count value TDC_OUT represents a ratio between the time difference Tsense and the period difference ΔT. In some embodiments, the time difference Tsense is determined based on TDC_OUT × ΔT. In some embodiments, ΔT also represents a time domain resolution of the time-to-digital conversion device, and the count value range of the counter 260 corresponds to a measurable range of the time-to-digital conversion device.

[0031] Fig. Figure 4A is a circuit diagram of an oscillator 400, which is a ring oscillator, according to some embodiments. In some embodiments, a hardware device of the oscillator 400 is a non-limiting example used to convert the first oscillator 210 and / or the second oscillator 220 into Fig. 2 can be used.

[0032] The oscillator 400 comprises a first NAND gate 412 as an input stage, a first set of inverters 414, a second set of inverters 415, a third set of inverters 416, a second NAND gate 417, and an inverter 418. The oscillator 400 further comprises a buffer circuit 420 after the third set of inverters 416 and a delay circuit 430 between the second set of inverters 415 and the third set of inverters 416. In some embodiments, the buffer circuit 420 comprises one or more inverters. In this example, the delay circuit 430 comprises a driver stage 432 (with one or more inverters, such as one inverter in this example) and a third NAND gate 434. Fig. In 4A, the first NAND gate 412, the first set of inverters 414, the second set of inverters 415, the driver stage 432 of the delay circuit 430, the third set of inverters 416, the second NAND gate 417, and the inverter 418 are electrically coupled sequentially as a loop of K inverting stages, where K is an odd, positive integer. In some embodiments, the signal at an output terminal of the first set of inverters 414 is output by the oscillator 400 as the clock signal CK_M.

[0033] In some embodiments, the first NAND gate 412 comprises a first input terminal configured to receive a feedback clock signal CK_F from the inverter 418, and a second input terminal configured to receive a reference signal START. In some embodiments, the first NAND gate 412 outputs the second logic state (e.g., HIGH) in response to the first logic state of the reference signal START (e.g., LOW), thus effectively disabling the oscillator 400. In some embodiments, the first NAND gate 412 outputs the inverse of the feedback clock signal CK_F at its output terminal when the reference signal START assumes the second logic state (e.g., HIGH).

[0034] In some embodiments, the second NAND gate 417 comprises a first input terminal electrically coupled to an output terminal of the third set of inverters 416, and a second input signal configured to receive an enable signal EN. In some embodiments, in response to the enable signal EN in the first logic state (e.g., LOW), the second NAND gate 417 outputs the second logic state (e.g., HIGH), effectively disabling the oscillator 400. In some embodiments, in response to the enable signal EN being in the second logic state (e.g., HIGH), the second NAND gate 417 outputs at its output terminal the inverted signal from the output terminal of the third set of inverters 416. In some embodiments, the second NAND gate 417 is replaced by an inverter, and the enable signal EN is omitted.

[0035] In some embodiments, the buffer circuit 420 is configured to output a buffered clock signal CK_OUT that has the same frequency and period as the clock signal CK_M. In some embodiments, the buffer circuit 420 provides the buffered clock signal CK_OUT with greater drive capability than the clock signal CK_M, while minimizing disturbance to the loop of the K-inverter stages of the oscillator 400.

[0036] In some embodiments, the delay circuit 430 is configured to introduce an adjustable delay into the loop of the K-inverter stages of the oscillator 400. In this example, the third NAND gate 434 is illustrated as a non-restrictive example. In some embodiments, a NOR gate is used instead of the third NAND gate 434.

[0037] In this example, the third NAND gate 434 comprises a first input terminal (labeled "LOAD") coupled to an output terminal of the driver stage 432, a second input terminal configured to receive a slowdown control signal SLOW, and an output terminal that is not electrically coupled to any other circuitry. In some embodiments, the first input terminal has a first equivalent load capacitance when the slowdown control signal SLOW assumes the first logic state (e.g., LOW). In some embodiments, the first input terminal has a second equivalent load capacitance, greater than the first equivalent load capacitance, in response to the slowdown control signal SLOW being in the second logic state (e.g., HIGH).

[0038] In an example where the first oscillator 210 is based on the oscillator 400, the reference signal START and the corresponding connection in Fig. 4A the first reference signal START1 and the corresponding connection in Fig. 2; the clock signal CK_M and the corresponding connection in Fig. 4A corresponds to the first clock signal CKA_M and the corresponding connection in Fig. 2, the buffered clock signal CK_OUT and the corresponding connection in Fig. 4A corresponds to the first buffered clock signal CKA_OUT and the corresponding connection in Fig. 2, and the deceleration control signal SLOW and the corresponding connection in Fig. 4A corresponds to the first deceleration control signal SLOW1 and the corresponding connection in Fig. 2.

[0039] Fig. 4B is a circuit diagram of the NAND gate 434 in the delay circuit 430 in Fig. 4A as a non-restrictive example according to some embodiments. In Fig. 4B includes the NAND gate 434 with a first input pin 442, which is connected in Fig. 4A is also labelled "LOAD". The NAND gate 434 includes a second input terminal 444, which is configured to receive the deceleration control signal SLOW, and an output terminal 446, which is not electrically coupled to any other circuit arrangements outside the NAND gate 434.

[0040] The NAND gate 434 comprises a first p-transistor 452, a second p-transistor 454, a first n-transistor 456, and a second n-transistor 458. A first drain / source terminal of the first p-transistor 452 and a first drain / source terminal of the second p-transistor 454 are electrically coupled to a first power supply node, which is configured to carry a first power supply voltage (e.g., VDD). A second drain / source terminal of the first p-transistor 452, a second drain / source terminal of the second p-transistor 454, and a first drain / source terminal of the first n-transistor 456 are electrically coupled to the output terminal 446 of the NAND gate 434. A second drain / source terminal of the first n-transistor 456 is electrically coupled to a first drain / source terminal of the second n-transistor 458.A second drain / source terminal of the second n-transistor 458 is electrically coupled to a second power supply node, which is configured to carry a second power supply voltage (e.g., VSS or ground). A gate terminal of the first p-transistor 452 and a gate terminal of the first n-transistor 456 are electrically coupled to the first input terminal 442 of the NAND gate 434. A gate terminal of the second p-transistor 454 and a gate terminal of the second n-transistor 458 are electrically coupled to the second input terminal 444 of the NAND gate 434.

[0041] In this example, in response to the slowdown control signal SLOW, which is in the first logic state (e.g., LOW), the second p-transistor 454 is turned on and the second n-transistor 458 is turned off. A load capacitance that can be observed at the first input terminal 442 is primarily due to the parasitic capacitance (represented by a capacitor with capacitance Cp) between the first input terminal 442 and the output terminal 446. In response to the slowdown control signal SLOW, which is in the second logic state (e.g., HIGH), the second p-transistor 454 is turned off and the second n-transistor 458 is turned on. A load capacitance that can be observed at the first input terminal 442 is due to the amplification of the parasitic capacitance (e.g.,the capacitance Cp) by the Miller effect, which is effectively (1+M) × Cp, where M is the gain from output terminal 446 to the first input terminal 442.

[0042] In this example, the load difference between the slowdown control signal SLOW, which is in the first logic state, and the second logic state is M × Cp. In some embodiments, one oscillator based on oscillator 400 with a load capacitance Cp and another oscillator based on oscillator 400 with a load capacitance (1+M) × Cp would have different clock periods, and the difference in clock periods can be determined based on the load difference M × Cp.

[0043] Fig. Figure 5 is a circuit diagram of a phase detector 500, according to some embodiments. In some embodiments, the phase detector 500 is a non-limiting example of the phase detector 230 in Fig. 2.

[0044] In Fig. In Figure 5, the phase detector 500 comprises a D flip-flop 510, a first buffer stage with series-coupled inverters 522 and 524, a second buffer stage with series-coupled inverters 532 and 534, and an output stage with an inverter 542. In some embodiments, the inverters 522 and 524 are configured to buffer a first clock signal (e.g., the first clock signal CKA_M) from a first oscillator (e.g., the first oscillator 210), and the inverters 532 and 534 are configured to buffer a second clock signal (e.g., the second clock signal CKB_M) from a second oscillator (e.g., the second oscillator 220).

[0045] In this example, the D flip-flop 510 comprises a D terminal, a CLK terminal, a Q terminal, and a CD terminal. In some embodiments, the D terminal of the D flip-flop 510 is configured to receive a first signal originating from the first buffer stage and corresponding to the first clock signal CKA_M. In some embodiments, the CLK terminal of the D flip-flop 510 is configured to receive a second signal, inverted based on the signal from the second buffer stage, corresponding to the inversion of the second clock signal CKB_M. In some embodiments, the Q terminal of the D flip-flop 510 is configured to output a third signal corresponding to the detection signal HITB. In this example, the inverter 542 receives the third signal from the Q terminal of the D flip-flop 510 and outputs the detection signal HITB.In some embodiments, the CD terminal of the D flip-flop 510 is configured to receive a reset signal RST, which has no effect on the operation of the D flip-flop 510 when the reset signal RST is in the first logic state (e.g., LOW), and which causes the D flip-flop 510 to reset the output at the Q terminal of the D flip-flop 510 when the reset signal RST is in the second logic state (e.g., HIGH).

[0046] Fig. Figure 6A is a circuit diagram of an exemplary clock gate circuit 600 according to some embodiments. In some embodiments, the clock gate circuit 600 is a non-limiting example of the clock gate circuit 250 in Fig. 2.

[0047] In Fig. Figure 6 of the clock gate circuit 600 comprises a first D flip-flop 610, a second D flip-flop 620, a first buffer stage comprising inverters 632 and 634 coupled in series, a second buffer stage comprising an inverter 642, and an output stage comprising a NAND gate 644. In this example, each of the first D flip-flop 610 and the second D flip-flop 620 comprises a D terminal, a CLK terminal, a Q terminal, and a CD terminal. In some embodiments, the D terminal of the first D flip-flop 610 is configured to accept a supply voltage (e.g., VDD) representing the second logic state (e.g., HIGH). In some embodiments, the CLK terminal of the first D flip-flop 610 is configured to receive a signal that is inverted based on the detection signal HITB.In some embodiments, the CD terminal of the first D flip-flop 610 is configured to receive a reset signal RST that has no effect on the operation of the first D flip-flop 610 when the reset signal RST is in the first logic state (e.g., LOW). It causes the first D flip-flop 610 to reset the output at its Q terminal in response to the reset signal RST being in the second logic state (e.g., HIGH). In some embodiments, inverters 632 and 634 are configured to buffer the output signal from the Q terminal of the first D flip-flop 610 and provide the buffered output signal (labeled "STOP") to the second D flip-flop 620.

[0048] In some embodiments, the D terminal of the second D flip-flop 620 is configured to receive the buffered output signal STOP from the inverter 634. In some embodiments, the CLK terminal of the second D flip-flop 620 is configured to receive the first buffered clock signal CKA_OUT from a first oscillator (e.g., the first oscillator 210). In some embodiments, the CD terminal of the second D flip-flop 620 is configured to receive the reset signal RST, which has no effect on the operation of the second D flip-flop 620 when the reset signal RST is in the first logic state (e.g., LOW), and causes the second D flip-flop 620 to reset the output at the Q terminal of the second D flip-flop 620 in response to the reset signal RST being in the second logic state (e.g., HIGH).In some embodiments, the Q terminal of the second D flip-flop 620 is configured to output a STOP_R signal based on the STOP signal and the first buffered clock signal CKA_OUT.

[0049] In this example, inverter 642 receives the STOP_R signal and outputs an inverted STOP_B signal. In some embodiments, NAND gate 644 includes a first input terminal configured to receive the first buffered clock signal CKA_OUT and a second input terminal configured to receive the STOP_B signal. In some embodiments, in response to the first logic state of the STOP_B signal (e.g., LOW), NAND gate 644 outputs the second logic state (e.g., HIGH) at its output terminal as a counter clock signal CKC (e.g., a non-oscillating signal). In some embodiments, the NAND gate 644 outputs the inverse of the first buffered clock signal CKA_OUT as a counter clock signal CKC (e.g., an oscillating signal) at its output terminal in response to the second logical state of the STOP_B signal (e.g., HIGH).

[0050] In some other embodiments, the first clock signal CKA_M, the second clock signal CKB_M, or a second buffered clock signal based on the second clock signal CKB_M can be used instead of the first buffered clock signal CKA_OUT.

[0051] Fig. 6B is a circuit diagram of a variation example 650A based on clock gate circuit 600 in Fig. 6A according to some embodiments. In some embodiments, the combination of second D flip-flop 620, inverter 642 and NAND gate 644 can be replaced by variation example 650A.

[0052] In Fig. Variation 6B comprises a D flip-flop 620A and an AND gate 646. In this example, the D flip-flop 620A includes a D terminal, a CLK terminal, and a Q terminal. In some embodiments, the D terminal of the D flip-flop 620A is configured to receive the STOP signal. In some embodiments, the clock terminal of the D flip-flop 620A is configured to receive the first buffered clock signal CKA_OUT from a first oscillator (e.g., the first oscillator 210). In some embodiments, the Q terminal of the D flip-flop 620A is configured to output a STOP_R signal based on the STOP signal and the first buffered clock signal CKA_OUT.

[0053] In Fig. 6B is the first input of the AND gate 646 configured to receive the STOP_R signal, and a second input of the AND gate 646 is configured to receive the first buffered clock signal CKA_OUT. In this example, an output of the AND gate 646 is configured to output the counter clock signal CKC.

[0054] Fig. 6C is a circuit diagram of a variation example 650B based on clock gate circuit 600 in Fig. 6A according to some embodiments. In some embodiments, the combination of second D flip-flop 620, inverter 642 and NAND gate 644 can be replaced by variation example 650A.

[0055] In Fig. Variation 6C comprises a D-flip module 620B and an AND gate 646. In this example, the D-flip module 620B includes a D terminal, an EN terminal, and a Q terminal. In some embodiments, the D terminal of the D-flip module 620B is configured to receive the STOP signal. In some embodiments, the EN terminal of the D-flip module 620B is configured to receive the first buffered clock signal CKA_OUT from a first oscillator (e.g., the first oscillator 210). In some embodiments, the Q terminal of the D-flip module 620B is configured to output a STOP_R signal based on the STOP signal and the first buffered clock signal CKA_OUT.

[0056] In Fig. 6C is the first input of the AND gate 646 configured to receive the STOP_R signal, and a second input of the AND gate 646 is configured to receive the first buffered clock signal CKA_OUT. In this example, an output of the AND gate 646 is configured to output the counter clock signal CKC.

[0057] Fig. Figure 7 is a block diagram of an exemplary counter 700 according to some embodiments. In some embodiments, the counter 700 is a non-limiting example of counter example 260 in Fig. 2.

[0058] In Fig. In embodiment 7, the counter 700 comprises an N-bit adder 710 and a clocked N-bit buffer 720. In some embodiments, the N-bit adder 710 corresponds to an N-bit carry-ripple adder and comprises a first N-bit input port Ain, a second N-bit input port Bin, a carry port Cin, and an N-bit output port S. In some embodiments, the clocked N-bit buffer 720 corresponds to a collection of N D flip-flops and comprises an N-bit input port D, an N-bit output port Q, a clock port (indicated by a triangle), and a CD port. In some embodiments, the CD port of the clocked N-bit buffer 720 is configured to reset the binary value at the N-bit output port Q based on a reset signal RST.In some embodiments, the clocked N-bit buffer 720 is configured to update the binary value at the N-bit output port Q with the binary value at the N-bit input port D in response to a counter clock signal CKC at the clock terminal.

[0059] In this example, the N-bit output port Q of the clocked N-bit buffer 720 is configured to carry the counter value TDC_OUT, and the first N-bit input port Ain of the N-bit adder 710 is configured to receive the counter value TDC_OUT from the N-bit output port Q of the clocked N-bit buffer 720. In this example, the second N-bit input port Bin is configured to receive a binary value 0001b, and the carry terminal Cin is coupled to a supply voltage (e.g., VSS or ground) representing a binary value ob. In some embodiments, the N-bit output port S is configured to output a binary value based on summing the binary values ​​at the first N-bit input port Ain, the second N-bit input port Bin, and the carry terminal Cin. The N-bit input port D of the clocked N-bit buffer 720 receives the binary value from the N-bit output port S of the N-bit adder 710.

[0060] During operation, the clocked N-bit buffer 720, in response to the push-pull signal CKC transitioning from the first logic state (e.g., LOW) to the second logic state (e.g., HIGH), updates the counter value TDC_OUT at the N-bit output port Q based on the output value of the N-bit adder 710. In response to the updated counter value TDC_OUT, the N-bit adder 710 updates the digital value at the N-bit output port S by adding the updated counter value TDC_OUT (the value at the first N-bit input port Ain) and 1 (the value at the second N-bit input port Bin). The updated digital value at the N-bit output port S is used to update the counter value TDC_OUT at the N-bit output port Q the next time the counter clock signal CKC transitions from the first logical state (e.g., LOW) to the second logical state (e.g., HIGH).

[0061] Fig. Figures 8A to 8D are diagrams of signal waveforms and / or digital values ​​from an exemplary time-to-digital conversion session performed by a time-to-digital conversion device, based on the examples in Fig. 2 to 6A and 7 according to some embodiments.

[0062] Fig. Section 8A comprises diagrams 801 to 808. In diagrams 801 to 807, time is represented by the horizontal axes and the voltage levels of the various signals by the vertical axes. In diagram 808, time is represented by the horizontal axis and the digital value by the vertical axes.

[0063] Diagram 801 includes a waveform 812, which corresponds to the waveform of the reset signal RST in Fig. 5, Fig. 6A and Fig. 7. Diagram 802 includes a waveform 822, which corresponds to the waveform of the first reference signal START1 in Fig. 2 and a waveform 824, which corresponds to the waveform of the second reference signal START2 in Fig. 2. Diagram 803 includes a waveform 832, which corresponds to the waveform of the first clock signal CKA_M in Fig. 2 and Fig. 5. Graph 804 includes a waveform 834, which corresponds to the waveform of the second clock signal CKB_M in Fig. 2 and Fig. 5. Diagram 805 includes a waveform 836, which corresponds to the waveform of the counting clock signal CKC in Fig. 2, Fig. 6A, and Fig. 7. Diagram 806 includes a waveform 842, which corresponds to the waveform of the HITB detection signal in Fig. 2, Fig. 5 and Fig. 6A. The graph 807 includes a waveform 844, which corresponds to the waveform of the buffered output signal STOP in Fig. 6A corresponds to diagram 808. The diagram includes a curve shape 850, which corresponds to the curve shape of the count value TDC_OUT in Fig. 2 and Fig. 7 corresponds.

[0064] In Fig. 8A oscillates the first clock signal CKA_M (waveform 832), the second clock signal CKB_M (waveform 834), and the counting clock signal CKC (waveform 836) in response to the first reference signal START1 (waveform 822) and the second reference signal START2 (waveform 824) transitioning from a low voltage level to a high voltage level, between a high voltage level (e.g., corresponding to a logic HIGH state) and a low voltage level (e.g., corresponding to a logic LOW state). Fig. At 8A, the count value TDC_OUT (waveform 850) increases, while one phase of the second reference signal START2 lags behind one phase of the first reference signal START1. Fig. At 8A, the count value TDC_OUT (waveform 850) does not increase further, and the first clock signal CKA_M (waveform 832), the second clock signal CKB_M (waveform 834) and the count clock signal CKC (waveform 836) remain in a fixed logical state (e.g. represented by the low voltage level) after the detection signal HITB (waveform 842) and the buffered output signal STOP (waveform 844) indicate that the phase of the first reference signal START1 lags behind the phase of the second reference signal START2.

[0065] Parts of diagrams 801 to 808 in Part A are in Fig. 8B, and parts of diagrams 801 to 808 in Part B are in Fig. 8C further shown.

[0066] Fig. 8B is an enlarged view of Part A in Fig. 8A. Fig. 8B comprises diagrams 801A to 808A, which correspond to sections of diagrams 801 to 808 in Part A. Fig. 8B obtains waveforms that resemble those in Fig. 8A corresponds to the same reference numbers.

[0067] In Fig. 8B is located before the time to the reset signal RST (waveform 812) at the high voltage level (e.g. HIGH) for resetting various components of a time-to-digital conversion device (e.g., time-to-digital conversion device 200), which is the stage 310 in Fig. 3 corresponds. At time to, the reset signal RST (waveform 812) transitions from the high voltage level (e.g. HIGH) to the low voltage level (e.g. LOW) so that the time-to-digital conversion device can operate in response to various other signals.

[0068] At time 11, the first reference signal START1 (waveform 822) transitions from the low voltage level (e.g., LOW) to the high voltage level (e.g., HIGH), which corresponds to stage 315 in Fig. 3 corresponds. In response to the transition and level 320 in Fig. Accordingly, after an inherent delay, a first oscillator (e.g., the first oscillator 210) begins outputting the first clock signal CKA_M (waveform 832) as an oscillating signal that alternates between the low and high voltage levels. Additionally, a clock counter (e.g., the clock counter 240) is activated by the first clock signal CKA_M, which is indicated by the counting clock signal CKC (waveform 836) and corresponds to stage 325 in Fig. 3 corresponds.

[0069] At time t2, the second reference signal START2 (waveform 824) transitions from the low voltage level (e.g., LOW) to the high voltage level (e.g., HIGH), which corresponds to stage 330 in Fig. 3 corresponds to the transition of the second reference signal START2. The transition of the second reference signal START2 is delayed by a time difference Tsense compared to the transition of the first reference signal START1 (e.g., t2 - t1 = Tsense). In response to the transition of the second reference signal START2 and stage 335 in Fig. 3 accordingly, a second oscillator (e.g. the second oscillator 220) begins, after an inherent delay, to output the second clock signal CKB_M (waveform 834) as an oscillating signal that alternates between the low voltage level and the high voltage level.

[0070] In some embodiments, the first clock signal CKA_M has a first clock period T1, and the second clock signal CKB_M has a second clock period T2, which is smaller than the first clock T1 by a period difference ΔT. Fig. 8B begins to lag one phase of the second clock signal CKB_M behind one phase of the first clock signal CKA_M. Fig. In step 8B, the phase difference between the second clock signal CKB_M and the first clock signal CKA_M is decreased by the period difference ΔT in each clock cycle of either the first clock signal CKA_M or the second clock signal CKB_M. In this example, the counting clock signal CKC (waveform 836) and the first clock signal CKA_M have the same frequency. Thus, the clock counter counts the clock cycles of the counting clock signal CKC, which represent a number of clock cycles of the first clock signal CKA_M that have elapsed.

[0071] Fig. 8C is an enlarged view of Part B in Fig. 8A. Fig. 8C comprises diagrams 801B to 808B, which correspond to sections of diagrams 801 to 808 in Part B. Fig. 8C obtains waveforms that resemble those in Fig. 8A corresponds to the same reference numbers.

[0072] In Fig. 8C catches up to the phase of the second clock signal CKB_M (waveform 834) at time t3 after Tsense / ΔT cycles from the time of activation of the first oscillator and begins to lead the phase of the first clock signal CKA_M (waveform 832), which corresponds to stage 340 in Fig. 3 corresponds. At time t4, a phase detector (e.g., phase detector 230) detects the change in the phase relationship between the first clock signal CKA_M and the second clock signal CKB_M and outputs a detection signal HITB (waveform 842), which transitions from the high voltage level (e.g., HIGH) to the low voltage level (e.g., LOW), which corresponds to stage 345 in Fig. 3 corresponds.

[0073] In response to the HITB detection signal (waveform 842), which transitions from the high voltage level to the low voltage level and reaches stage 350 in Fig. When the voltage corresponds to 3, the buffered output signal STOP (waveform 844) transitions from the low voltage level to the high voltage level, which in turn deactivates a clock gate circuit (e.g., clock gate circuit 250) that outputs the count clock signal CKC (waveform 836). The digital value of the count value TDC_OUT (waveform 850) is then read as the conversion result, which corresponds to stage 355 in Fig. 3 corresponds.

[0074] Fig. 8D is a diagram of the digital values ​​of the counter value TDC_OUT (waveform 850) as a function of the time difference (e.g., tsense) between the first reference signal START1 and the second reference signal START2, following the example in Fig. 8A according to some embodiments. In Fig. In 8D, the time difference Tsense is represented by the horizontal axis and the digital value by the vertical axis.

[0075] In this non-restrictive example, the time difference Tsense and the digital value have a linear, proportional relationship, as shown by curve 860. In this example, data point 862 represents the count value TDC_OUT with a digital value of 476 in response to a time difference Tsense of 45.2531 picoseconds (ps). In this example, data point 864 represents the count value TDC_OUT with a digital value of 2876 in response to a time difference Tsense of 235.4562 ps. Accordingly, in this non-restrictive example, the resolution for measuring the time difference Tsense is 79.4 fs (per digital unit).

[0076] Fig. Figure 9A is a circuit diagram of a delay circuit in Example 900, which is based on a phase interpolator, according to some embodiments. In some embodiments, the delay circuit 900 can be considered an alternative embodiment of the delay circuit 430 in Fig. 4A can be used. In Fig. 9A comprises the delay circuit 900, the inverters 912 and 914, the capacitors 922 and 924, and a phase interpolator 932. The input terminals of inverters 912 and 914 are suitable for connection to the second set of inverters 415 in Fig. 4A to be electrically coupled; and the output terminal of the phase interpolator 932 is suitable to be electrically coupled with the third set of inverters 416 in Fig. to be connected to 4A.

[0077] In Fig. In embodiment 9A, capacitor 922 has one terminal coupled to a power supply node configured to carry a power supply voltage (e.g., VSS or ground), and another terminal electrically coupled to an output terminal of inverter 912 and an input terminal of phase interpolator 932. Capacitor 924 also has one terminal coupled to a power supply node configured to carry a power supply voltage (e.g., VSS or ground), and another terminal electrically coupled to an output terminal of inverter 912 and an input terminal of phase interpolator 932. In some embodiments, capacitor 922 has a capacitance of C1. In some embodiments, capacitor 924 is in a first logic state (e.g.,LOW) a capacitance of C2 in response to a slowdown control signal SLOW in a second logic state (e.g., HIGH) and a capacitance of C2 + ΔC. In some embodiments, the capacitances C1 and C2 are set to be equal or within 10% of each other. In some embodiments, capacitor 922 is omitted, and capacitance C1 is assumed to be zero.

[0078] In Fig. 9A, the signal at one input terminal of the phase interpolator 932, which is coupled to the output terminal of the inverter 912, is designated PI_INo; and the signal at the other input terminal of the phase interpolator 932, which is coupled to the output terminal of the inverter 914, is designated PI_IN1. The signal at the output terminal of the phase interpolator 932 is labeled PI_OUT. In some embodiments, the phase interpolator 932 is configured to determine a first time delay of a signal transition of the signal PI_IN1 with respect to a signal transition of the signal PI_INo and outputs a signal PI_OUT that has a signal transition and a second time delay with respect to the signal transition of the signal PI_INo. In some embodiments, the second time delay is a fraction of the first time delay.

[0079] Fig. 9B is a diagram of various signals of the 900 delay circuit in Fig. 9A according to some embodiments. In Fig. In 9B, time is represented on the horizontal axis. Fig. 9B shows that a signal transition of the signal PI_IN1 has a first delay TD1 with respect to a signal transition of the signal PI_INo. Fig. 9B shows a signal transition of the signal PI_OUT with a second delay TD2 with respect to a signal transition of the signal PI_IN0.

[0080] Accordingly, the delay circuit 900 can be configured to further reduce the period difference ΔT between two oscillators without further reducing the difference in the corresponding load capacitance values ​​of the two oscillators. In some embodiments, the period difference ΔT based on the second delay TD2 is in the range of a few tens of fs, in order to achieve a finer resolution of the resulting time-to-digital conversion device than based on the first delay TD1.

[0081] Fig. 10A is a circuit diagram of a delay circuit in Example 1000 based on an adjustable load resistance according to some embodiments. In some embodiments, the delay circuit 1000 is a further alternative embodiment of the delay circuit 430 in Fig. 4A usable. In Fig. The 10A delay circuit 1000 comprises an inverter 1012, a capacitor 1014, and an adjustable resistor 1016. The input terminal of the inverter 1012 is suitable for connection to the second set of inverters 415 in Fig. 4A to be electrically coupled; and an output node 1018 of the delay circuit 1000 is suitable to be electrically coupled with the third set of inverters 416 in Fig. to be connected to 4A.

[0082] In Fig. In embodiment 10A, capacitor 1014 has one terminal connected to a power supply node configured to carry a power supply voltage (e.g., VSS or ground) and another terminal electrically connected to an output node 1018. Furthermore, adjustable resistor 1016 has one terminal electrically connected to an output terminal of inverter 1012 and another terminal electrically connected to output node 1018. In some embodiments, a time delay between the input terminal of inverter 1012 and output node 1018 can be determined based on the resistance of adjustable resistor 1016, with the larger the resistance value of adjustable resistor 1016, the greater the delay between the second set of inverters 415 and the third set of inverters 416.

[0083] Fig. 10B is a circuit diagram of a first adjustable resistor example 1016A, which is called adjustable resistor 1016 in Fig. 10A, usable according to some embodiments. The first adjustable resistor 1016A comprises a first terminal 1022 and a second terminal 1024, which correspond to the two terminals of the adjustable resistor 1016 in Fig. 10A. The first adjustable resistor 1016A comprises a p-transistor 1026, an n-transistor 1028, and a bias generator 1030. A first drain / source terminal of the p-transistor 1026 and a first drain / source terminal of the n-transistor 1028 are electrically coupled to the first terminal 1022; and a second drain / source terminal of the p-transistor 1026 and a second drain / source terminal of the n-transistor 1028 are electrically coupled to the second terminal 1024.

[0084] In some embodiments, the bias generator 1030 is configured to generate a first bias voltage Vbiasp, which is applied to a gate terminal of the p-transistor 1026, and a second bias voltage Vbiasn, which is applied to a gate terminal of the n-transistor 1028. In some embodiments, the bias generator 1030 is configured to output suitable voltage levels at the first bias voltage Vbiasp and the second bias voltage Vbiasn in response to the deceleration control signal SLOW, in order to set a resistance value between the first terminal 1022 and the second terminal 1024.

[0085] Fig. 10C is a circuit diagram of a second adjustable resistor example 1016B, which is known as adjustable resistor 1016 in Fig. 10A, according to some embodiments. The second adjustable resistor 1016B comprises a first terminal 1042 and a second terminal 1044, which correspond to the two terminals of the adjustable resistor 1016 in Fig. 10A. The second adjustable resistor 1016B comprises a first resistor 1046, a second resistor 1048, and a switch 1050. In this example, the second resistor 1048 is electrically coupled between the first terminal 1042 and the second terminal 1044, and the first resistor 1046 is electrically coupled at one end to the second terminal 1044 and at the other end to the switch 1050.

[0086] In Fig. In section 10C, switch 1050 is configured to electrically couple the first resistor 1046 to the first terminal 1042 or to electrically decouple the first resistor 1046 from the first terminal 1042 in response to an inverse deceleration control signal SLOW (labeled " / SLOW"). Accordingly, the resistance between the first terminal 1042 and the second terminal 1044 is adjustable based on the deceleration control signal SLOW.

[0087] Fig. Figure 11 is a circuit diagram of oscillators configured to correspond to different clock periods, according to some embodiments. In Fig. 11 corresponds to a first oscillator 1100A, which corresponds to the first oscillator 210 in Fig. 2, and a second oscillator 1100B corresponds to the second oscillator 220 in Fig. 2.

[0088] In some embodiments, the first oscillator 1100A is a ring oscillator and comprises a NAND gate 1102A, a first set of inverters 1104A, a second set of inverters 1106A, and a third set of inverters 1110. A first input terminal of the NAND gate 1102A is electrically coupled to an output terminal of the third set of inverters 1110. A second input terminal of the NAND gate 1102A is configured to receive a reference signal (e.g., the first reference signal START1). In some embodiments, the signal at an output terminal of the first set of inverters 1104A is used as the output clock signal (e.g., the first clock signal CKA_M).

[0089] In some embodiments, the second oscillator 1100B is a ring oscillator and comprises a NAND gate 1102B, a first set of inverters 1104B, and a second set of inverters 1106B. A first input terminal of the NAND gate 1102B is electrically coupled to an output terminal of the second set of inverters 1106B. A second input terminal of the NAND gate 1102B is configured to receive another reference signal (e.g., the second reference signal START2). In some embodiments, the signal at an output terminal of the first set of inverters 1104B is used as the output clock signal (e.g., the second clock signal CKB_M).

[0090] In some embodiments, the hardware arrangements of the NAND gate 1102A, the first set of inverters 1104A, and the second set of inverters 1106A correspond to the hardware arrangements of the NAND gate 1102B, the first set of inverters 1104B, and the second set of inverters 1106B. In some embodiments, the third set of inverters 1110M comprises inverting stages. In some embodiments, the NAND gate 1102A, the first set of inverters 1104A, the second set of inverters 1106A, and the third set of inverters 1110M are electrically coupled sequentially as a loop of K+M inverter stages. In some embodiments, the NAND gate 1102B, the first set of inverters 1104B, and the second set of inverters 1106B are also electrically coupled in series as a loop of K-inverter stages. In some embodiments, K is an odd, positive integer and M is an even, positive integer.

[0091] In this example, the additional delay introduced by the third set of inverters 1110 increases the duration of the first clock signal CKA_M relative to the second clock signal CKB_M. In some embodiments, because no adjustable delays are available based on the hardware features of the first oscillator 1100A and the second oscillator 1100B, the first deceleration control signal SLOW1 and / or the second deceleration control signal SLOW2 is, as shown in Fig. The section illustrated in point 2 is therefore omitted.

[0092] Fig. Figure 12 is a flowchart of a method 1200 for generating a count value indicating a time difference between a first event and a second event, according to some embodiments. In some embodiments, various operations of the method 1200 are performed by the time-to-digital conversion device 200. Fig. 2 with regard to the various embodiments in Fig. 3 to 11 executed. As in Fig. 12 comprises procedure 1200 blocks 1210 to 1240.

[0093] In block 1210, a first clock signal (e.g., the first clock signal CKA_M) is received. Fig. 2) from a first oscillator (e.g. the first oscillator 210 in Fig. 2) output in response to the first event. In some embodiments, the first clock signal has a first clock period. In some embodiments, block 1210 corresponds at least to the processes of stages 315 and 320 in Fig. 3.

[0094] In some embodiments, the method 1200 further comprises receiving a first reference signal by the first oscillator (e.g. the first reference signal START1 in Fig. 2), wherein the first event corresponds to a change of the first reference signal from a first logical state (e.g., LOW) to a second logical state (e.g., HIGH). In some embodiments, Method 1200 further comprises disabling the first oscillator based on the first reference signal being in the first logical state and / or enabling the first oscillator based on the first reference signal being in the second logical state.

[0095] In block 1220, a second clock signal (e.g., the second clock signal CKA_M) is used. Fig. 2) from a second oscillator (e.g. the second oscillator 220 in Fig. 2) output in response to the first event. In some embodiments, the second clock signal has a second clock period T2. In some embodiments, the first event occurs before the second event (e.g., by a time difference Tsense). In some embodiments, the first clock period is greater than the second clock period by a period difference ΔT. In some embodiments, block 1220 corresponds at least to the processes of stages 330 and 335 in Fig. 3.

[0096] In some embodiments, the method 1200 further comprises receiving a second reference signal by the first oscillator (e.g. the second reference signal START2 in Fig. 2), wherein the second event corresponds to a change of the second reference signal from a first logical state (e.g., LOW) to a second logical state (e.g., HIGH). In some embodiments, Method 1200 further comprises disabling the second oscillator based on the second reference signal being in the first logical state, and / or enabling the second oscillator based on the second reference signal being in the second logical state.

[0097] Block 1230 contains a detection signal (e.g., HITB detection signal). Fig. 2) from a phase detector (e.g. phase detector 230 in Fig. 2) generated on the basis of a phase relationship between the first clock signal and the second clock signal. In some embodiments, block 1230 corresponds at least to the processes of stages 340 and 345 in Fig. 3.

[0098] In block 1240 the counter value (e.g., counter value TDC_OUT) is stored. Fig. 2) generated by a clock counter (e.g. clock counter 240 in Fig. 2) generated on the basis of the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal. In some embodiments, block 1240 corresponds to at least one section of the operations of stages 325 to 345 in Fig. 3.

[0099] In some embodiments, the method 1200 for generating the count value by the clock counter further comprises generation by a clock gate circuit (e.g. the clock gate circuit 250 in Fig. 2) of the clock counter a counting clock signal (e.g. the counting clock signal CKC in Fig. 2) based on the first clock signal and the recognition signal. In some embodiments, the method 1200 further comprises generating a counter (e.g., counter 260 in Fig. 2) the count value based on the counting clock signal. In some embodiments, the counter is an N-bit counter, where N is in the range of 6 to 12 or 8 to 10. In some embodiments, the count value is an unsigned N-bit integer.

[0100] In some embodiments, Method 1200 further comprises adjusting the first oscillator, the second oscillator, or both such that the second clock period is at least 100 times the period difference ΔT between the first clock period and the second clock period. In some embodiments, the first oscillator is a first ring oscillator and the second oscillator is a second ring oscillator. In some embodiments, Method 1200 further comprises adjusting a first adjustable delay of the first oscillator based on the adjustment of one or more first load capacitances, a first load resistance, or a first phase interpolator between successive inverting stages of the first oscillator, as in the examples in the Fig. 4A, 4B, and 9A to 10C are illustrated. In some embodiments, Method 1200 further comprises setting a second adjustable delay of the first oscillator based on setting one or more second load capacitances, a second load resistance, or a second phase interpolator between successive inverting stages of the second oscillator, as illustrated in the examples in the Fig. 4A, 4B, and 9A to 10C are illustrated.

[0101] In some aspects, a time-to-digital conversion device comprises a first oscillator configured to output a first clock signal in response to a first event, and a second oscillator configured to output a second clock signal in response to a second event. The first event occurs before the second event. The first clock signal has a first clock period, the second clock signal has a second clock period, and the first clock period is longer than the second clock period.The time-to-digital conversion device further comprises a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate a count based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal. The count indicates the time difference between the first and second events.

[0102] In some aspects, a method for generating a count value indicating a time difference between a first event and a second event involves the output of a first clock signal by a first oscillator in response to the first event and the output of a second clock signal by a second oscillator in response to the second event. The first event occurs before the second event. The first clock signal has a first clock period, the second clock signal has a second clock period, and the first clock period is greater than the second clock period.The method further comprises generating a detection signal by a phase detector based on a phase relationship between the first clock signal and the second clock signal, and generating the count value by a clock counter based on the first clock signal in response to the detection signal, which indicates that a phase of the second clock signal lags behind a phase of the first clock signal.

[0103] In some aspects, an integrated circuit comprises one or more digital circuit blocks configured to output a first reference signal and a second reference signal, as well as a time-to-digital conversion device configured to output a count value indicating the time difference between a first event and a second event. The time-to-digital conversion device includes a first oscillator configured to output a first clock signal based on the first reference signal in response to the first event, and a second oscillator configured to output a second clock signal based on the second reference signal in response to the second event. The first event occurs before the second event.The first clock signal has a first clock period, the second clock signal has a second clock period, and the first clock period is longer than the second clock period. The time-to-digital conversion device further comprises a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate a count based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal.

[0104] The above describes elements of several embodiments so that those skilled in the field can better understand the aspects of this disclosure. Those skilled in the field should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments or examples introduced herein. Those skilled in the field should also recognize that such equivalent designs do not deviate from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without deviating from the spirit and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 703,789

[0001]

Claims

[1] Time-to-digital conversion device comprising: a first oscillator configured to output a first clock signal in response to a first event, the first clock signal having a first clock period; a second oscillator configured to output a second clock signal in response to a second event, wherein the second clock signal has a second clock period, the first event occurs before the second event, and the first clock period is greater than the second clock period; a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal; and a clock counter configured to generate a count based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal, the count indicating a time difference between the first event and the second event. [2] Time-to-digital conversion device according to claim 1, wherein the first event corresponds to a first reference signal that transitions from a first logical state to a second logical state, and The second event corresponds to a second reference signal that transitions from the first logical state to the second logical state. [3] Time-to-digital conversion device according to claim 2, wherein the first oscillator is configured to be deactivated based on the first reference signal that is in the first logical state and activated based on the first reference signal that is in the second logical state, and the second oscillator is set up so that it is deactivated when the second reference signal assumes the first logical state, and is activated when the second reference signal assumes the second logical state. [4] Time-to-digital conversion device according to claim 1, wherein the first oscillator is a first ring oscillator comprising one or more of a first load capacitance, a first load resistance, or a first phase interpolator between two successive inverting stages of the first oscillator and is configured to set a first tunable delay of the first oscillator, and The second oscillator is a second ring oscillator comprising one or more second load capacitors, a second load resistor, or a second phase interpolator between two successive inverting stages of the second oscillator, and is configured to set a second adjustable delay of the second oscillator. [5] Time-to-digital conversion device according to claim 4, wherein the first load capacity or the second load capacity is based on a NAND gate or a NOR gate. [6] Time-to-digital conversion device according to any one of claims 1 to 5, wherein the phase detector includes a D flip-flop, a D-terminal of the D flip-flop is configured to receive a first signal corresponding to the first clock signal, a clock pin of the D flip-flop is configured to receive a second signal that corresponds to the inversion of the second clock signal, and a Q terminal of the D flip-flop is configured to output a third signal that corresponds to the detection signal. [7] Time-to-digital conversion device according to any one of claims 1 to 6, wherein the clock counter comprises: a clock gate circuit configured to generate a counting clock signal based on the initial clock signal and the detection signal; and a counter that is set up to generate the count value based on the counting clock signal. [8] Time-to-digital conversion device according to claim 7, wherein the clock gate circuit is based on a D flip-flop or a D latch and a NAND gate or an AND gate. [9] The time-to-digital conversion device according to claim 7 or 8, wherein the counter is an N-bit counter and N ranges from 6 to 12. [10] Time-to-digital conversion device according to any one of claims 1 to 9, wherein the second clock period is at least 100 times the period difference between the first clock period and the second clock period. [11] Method for generating a count value indicating a time difference between a first event and a second event, comprising: Output of a first clock signal by a first oscillator in response to the first event, wherein the first clock signal has a first clock period; Output of a second clock signal by a second oscillator in response to the second event, wherein the second clock signal has a second clock period, the first event occurs before the second event, and the first clock period is greater than the second clock period; Generating a detection signal using a phase detector based on a phase relationship between the first clock signal and the second clock signal; and Generating the count value by a clock counter based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal. [12] The method of claim 11, further comprising: Receiving a first reference signal by the first oscillator, wherein the first event corresponds to the change of the first reference signal from a first logical state to a second logical state, and Receiving a second reference signal by the second oscillator, where the second event corresponds to the change of the second reference signal from the first logical state to the second logical state. [13] The method of claim 12, further comprising: Deactivating the first oscillator based on the first reference signal that exhibits the first logical state; Activating the first oscillator based on the first reference signal, which has the second logical state; Disabling the second oscillator based on the second reference signal, which has the first logical state; or Activating the second oscillator based on the second reference signal, which has the second logical state. [14] Method according to any one of claims 11 to 13, further comprising: Setting a first adjustable delay of the first oscillator based on setting one or more of a first load capacitance, a first load resistance, or a first phase interpolator between two successive inverting stages of the first oscillator, and Setting a second adjustable delay of the second oscillator based on the installation of one or more second load capacitors, a second load resistor, or a second phase interpolator between two successive inverting stages of the first oscillator, where the first oscillator is a first ring oscillator and the second oscillator is a second ring oscillator. [15] Method according to any one of claims 11 to 14, wherein generating the count value by the clock counter comprises: Generating a counting clock signal based on the first clock signal and the recognition signal by a clock gate circuit of the clock counter; and Generating the count value using a counter based on the counting clock signal. [16] Method according to claim 15, wherein the count value is an unsigned N-bit integer, and N from 6 to 12 is sufficient. [17] Method according to any one of claims 11 to 16, further comprising: Adjusting the first oscillator, the second oscillator, or both, so that the second clock period is at least 100 times the period difference between the first clock period and the second clock period. [18] Integrated circuit comprising: one or more digital circuit blocks configured to output a first reference signal and a second reference signal; and a time-to-digital conversion device configured to output a count value indicating a time difference between a first event and a second event, the time-to-digital conversion device comprising: a first oscillator, configured to output a first clock signal based on the first reference signal in response to the first event, the first clock signal having a first clock period; a second oscillator, configured to output a second clock signal in response to the second event based on the second reference signal, wherein the second clock signal has a second clock period, the first event occurs before the second event, and the first clock period is greater than the second clock period; a phase detector, configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal; and a clock counter, set up to generate a count value based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal. [19] Integrated circuit according to claim 18, wherein the first oscillator is a first ring oscillator comprising one or more of a first load capacitance, a first load resistance, or a first phase interpolator between two successive inverting stages of the first oscillator and is configured to set a first tunable delay of the first oscillator, and The second oscillator is a second ring oscillator comprising one or more second load capacitors, a second load resistor, or a second phase interpolator between two successive inverting stages of the second oscillator, and is configured to set a second adjustable delay of the second oscillator. [20] Integrated circuit according to claim 18 or 19 comprising a clock counter: a clock gate circuit configured to generate a counting clock signal based on the initial clock signal and the detection signal; and a counter that is set up to generate the count value based on the counting clock signal.

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